./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.13.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.13.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:49:00,658 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:49:00,750 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-13 13:49:00,759 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:49:00,762 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:49:00,799 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:49:00,800 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:49:00,800 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:49:00,801 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:49:00,801 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:49:00,802 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:49:00,802 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:49:00,802 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:49:00,803 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-13 13:49:00,803 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-13 13:49:00,803 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-13 13:49:00,804 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-13 13:49:00,804 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-13 13:49:00,805 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-13 13:49:00,805 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:49:00,805 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-13 13:49:00,805 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-13 13:49:00,805 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 13:49:00,805 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-13 13:49:00,805 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-13 13:49:00,806 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:49:00,807 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:49:00,807 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:49:00,807 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:49:00,807 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 13:49:00,807 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-13 13:49:00,808 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 [2024-11-13 13:49:01,131 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:49:01,145 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:49:01,149 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:49:01,150 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:49:01,151 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:49:01,153 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/systemc/transmitter.13.cil.c Unable to find full path for "g++" [2024-11-13 13:49:03,025 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:49:03,400 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:49:03,401 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/sv-benchmarks/c/systemc/transmitter.13.cil.c [2024-11-13 13:49:03,423 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/data/3dc1b0169/a50c11aff2e945b5825c36bf3212181c/FLAGa0cf37112 [2024-11-13 13:49:03,444 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/data/3dc1b0169/a50c11aff2e945b5825c36bf3212181c [2024-11-13 13:49:03,448 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:49:03,449 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:49:03,452 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:49:03,452 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:49:03,456 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:49:03,458 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:49:03" (1/1) ... [2024-11-13 13:49:03,458 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@635756d3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:03, skipping insertion in model container [2024-11-13 13:49:03,459 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:49:03" (1/1) ... [2024-11-13 13:49:03,525 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:49:03,909 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:49:03,922 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:49:04,010 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:49:04,031 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:49:04,032 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04 WrapperNode [2024-11-13 13:49:04,032 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:49:04,033 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:49:04,033 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:49:04,033 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:49:04,043 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,053 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,171 INFO L138 Inliner]: procedures = 54, calls = 70, calls flagged for inlining = 65, calls inlined = 287, statements flattened = 4424 [2024-11-13 13:49:04,171 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:49:04,172 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:49:04,172 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:49:04,172 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:49:04,181 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,182 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,197 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,228 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 13:49:04,228 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,228 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,280 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,338 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,347 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,361 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,378 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:49:04,379 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:49:04,380 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:49:04,380 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:49:04,381 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (1/1) ... [2024-11-13 13:49:04,388 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-13 13:49:04,402 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:49:04,416 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-13 13:49:04,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_db108f0f-8bdf-48c0-aee4-14ae45472fba/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-13 13:49:04,449 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 13:49:04,450 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 13:49:04,450 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:49:04,450 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:49:04,583 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:49:04,585 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:49:08,372 INFO L? ?]: Removed 948 outVars from TransFormulas that were not future-live. [2024-11-13 13:49:08,372 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:49:08,424 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:49:08,425 INFO L316 CfgBuilder]: Removed 17 assume(true) statements. [2024-11-13 13:49:08,425 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:49:08 BoogieIcfgContainer [2024-11-13 13:49:08,425 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:49:08,426 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-13 13:49:08,426 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-13 13:49:08,431 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-13 13:49:08,432 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:49:08,432 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 01:49:03" (1/3) ... [2024-11-13 13:49:08,433 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e54a893 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:49:08, skipping insertion in model container [2024-11-13 13:49:08,433 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:49:08,433 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:49:04" (2/3) ... [2024-11-13 13:49:08,433 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e54a893 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 01:49:08, skipping insertion in model container [2024-11-13 13:49:08,433 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-13 13:49:08,434 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:49:08" (3/3) ... [2024-11-13 13:49:08,435 INFO L333 chiAutomizerObserver]: Analyzing ICFG transmitter.13.cil.c [2024-11-13 13:49:08,515 INFO L299 stractBuchiCegarLoop]: Interprodecural is true [2024-11-13 13:49:08,515 INFO L300 stractBuchiCegarLoop]: Hoare is None [2024-11-13 13:49:08,515 INFO L301 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-13 13:49:08,515 INFO L302 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-13 13:49:08,515 INFO L303 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-13 13:49:08,515 INFO L304 stractBuchiCegarLoop]: Difference is false [2024-11-13 13:49:08,515 INFO L305 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-13 13:49:08,516 INFO L309 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-13 13:49:08,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1936 states, 1935 states have (on average 1.4945736434108527) internal successors, (2892), 1935 states have internal predecessors, (2892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:08,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1759 [2024-11-13 13:49:08,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:08,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:08,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:08,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:08,649 INFO L331 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-13 13:49:08,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1936 states, 1935 states have (on average 1.4945736434108527) internal successors, (2892), 1935 states have internal predecessors, (2892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:08,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1759 [2024-11-13 13:49:08,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:08,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:08,709 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:08,710 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:08,723 INFO L745 eck$LassoCheckResult]: Stem: 145#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1847#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 684#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1843#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1770#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1060#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1403#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 260#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1396#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 537#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 435#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 793#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 292#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 544#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 676#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 802#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 828#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 907#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 301#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1826#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1393#L1258-2true assume !(0 == ~T1_E~0); 484#L1263-1true assume !(0 == ~T2_E~0); 709#L1268-1true assume !(0 == ~T3_E~0); 1359#L1273-1true assume !(0 == ~T4_E~0); 1759#L1278-1true assume !(0 == ~T5_E~0); 1141#L1283-1true assume !(0 == ~T6_E~0); 1793#L1288-1true assume !(0 == ~T7_E~0); 1564#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1533#L1298-1true assume !(0 == ~T9_E~0); 1379#L1303-1true assume !(0 == ~T10_E~0); 195#L1308-1true assume !(0 == ~T11_E~0); 164#L1313-1true assume !(0 == ~T12_E~0); 1851#L1318-1true assume !(0 == ~T13_E~0); 167#L1323-1true assume !(0 == ~E_1~0); 265#L1328-1true assume !(0 == ~E_2~0); 1803#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 961#L1338-1true assume !(0 == ~E_4~0); 1101#L1343-1true assume !(0 == ~E_5~0); 1656#L1348-1true assume !(0 == ~E_6~0); 1672#L1353-1true assume !(0 == ~E_7~0); 725#L1358-1true assume !(0 == ~E_8~0); 990#L1363-1true assume !(0 == ~E_9~0); 1051#L1368-1true assume !(0 == ~E_10~0); 91#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 483#L1378-1true assume !(0 == ~E_12~0); 235#L1383-1true assume !(0 == ~E_13~0); 1089#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 727#L607true assume 1 == ~m_pc~0; 998#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1096#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 581#is_master_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 658#L1560true assume !(0 != activate_threads_~tmp~1#1); 1737#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 175#L626true assume !(1 == ~t1_pc~0); 1260#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 324#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 971#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1923#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 128#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1329#L645true assume 1 == ~t2_pc~0; 184#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1293#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 220#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1915#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 643#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1718#L664true assume 1 == ~t3_pc~0; 1636#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 952#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 410#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1411#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1629#L683true assume !(1 == ~t4_pc~0); 973#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 780#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1705#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 918#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 598#L702true assume 1 == ~t5_pc~0; 1694#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 910#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1561#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1386#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1229#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74#L721true assume !(1 == ~t6_pc~0); 65#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 141#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 418#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1517#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 856#L740true assume 1 == ~t7_pc~0; 100#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1867#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 760#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 375#L759true assume !(1 == ~t8_pc~0); 1370#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1856#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1508#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1067#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1678#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1562#L778true assume 1 == ~t9_pc~0; 1334#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1266#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 246#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 731#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 182#L797true assume !(1 == ~t10_pc~0); 252#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1300#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1299#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 481#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 694#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1385#L816true assume 1 == ~t11_pc~0; 47#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 574#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1423#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 422#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1503#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 801#L835true assume 1 == ~t12_pc~0; 704#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 132#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1797#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 518#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1435#L854true assume !(1 == ~t13_pc~0); 293#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 321#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1355#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 140#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1221#L1664-2true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1804#L1401true assume !(1 == ~M_E~0); 414#L1401-2true assume !(1 == ~T1_E~0); 1232#L1406-1true assume !(1 == ~T2_E~0); 848#L1411-1true assume !(1 == ~T3_E~0); 1613#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 580#L1421-1true assume !(1 == ~T5_E~0); 291#L1426-1true assume !(1 == ~T6_E~0); 1004#L1431-1true assume !(1 == ~T7_E~0); 64#L1436-1true assume !(1 == ~T8_E~0); 745#L1441-1true assume !(1 == ~T9_E~0); 477#L1446-1true assume !(1 == ~T10_E~0); 1784#L1451-1true assume !(1 == ~T11_E~0); 1095#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 743#L1461-1true assume !(1 == ~T13_E~0); 432#L1466-1true assume !(1 == ~E_1~0); 1777#L1471-1true assume !(1 == ~E_2~0); 1066#L1476-1true assume !(1 == ~E_3~0); 1306#L1481-1true assume !(1 == ~E_4~0); 1592#L1486-1true assume !(1 == ~E_5~0); 203#L1491-1true assume !(1 == ~E_6~0); 35#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 756#L1501-1true assume !(1 == ~E_8~0); 474#L1506-1true assume !(1 == ~E_9~0); 1027#L1511-1true assume !(1 == ~E_10~0); 447#L1516-1true assume !(1 == ~E_11~0); 12#L1521-1true assume !(1 == ~E_12~0); 34#L1526-1true assume !(1 == ~E_13~0); 305#L1531-1true assume { :end_inline_reset_delta_events } true; 1161#L1892-2true [2024-11-13 13:49:08,728 INFO L747 eck$LassoCheckResult]: Loop: 1161#L1892-2true assume !false; 1879#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1767#L1233-1true assume !true; 536#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 330#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1632#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1914#L1258-5true assume !(0 == ~T1_E~0); 135#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1603#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1622#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1921#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1623#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 254#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1802#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1158#L1298-3true assume !(0 == ~T9_E~0); 1704#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1420#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1157#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 649#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 136#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1294#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1681#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 210#L1338-3true assume !(0 == ~E_4~0); 1045#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1534#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1303#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1343#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 610#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 325#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1898#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 873#L1378-3true assume !(0 == ~E_12~0); 1452#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1087#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1776#L607-42true assume !(1 == ~m_pc~0); 898#L607-44true is_master_triggered_~__retres1~0#1 := 0; 503#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 405#is_master_triggered_returnLabel#15true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 337#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 695#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1211#L626-42true assume 1 == ~t1_pc~0; 390#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1463#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1761#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1118#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 152#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1569#L645-42true assume 1 == ~t2_pc~0; 1407#L646-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1706#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 266#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1666#L664-42true assume 1 == ~t3_pc~0; 451#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1626#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 940#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 827#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1005#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1801#L683-42true assume !(1 == ~t4_pc~0); 729#L683-44true is_transmit4_triggered_~__retres1~4#1 := 0; 833#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1008#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1404#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1919#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1152#L702-42true assume 1 == ~t5_pc~0; 634#L703-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 576#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 655#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1280#L1600-42true assume !(0 != activate_threads_~tmp___4~0#1); 26#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98#L721-42true assume !(1 == ~t6_pc~0); 1577#L721-44true is_transmit6_triggered_~__retres1~6#1 := 0; 357#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1585#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 463#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 368#L740-42true assume 1 == ~t7_pc~0; 1310#L741-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 550#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 670#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 453#L1616-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 638#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1911#L759-42true assume !(1 == ~t8_pc~0); 1348#L759-44true is_transmit8_triggered_~__retres1~8#1 := 0; 487#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 797#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 538#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 600#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1164#L778-42true assume !(1 == ~t9_pc~0); 603#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 804#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1781#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 730#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1614#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 775#L797-42true assume !(1 == ~t10_pc~0); 1034#L797-44true is_transmit10_triggered_~__retres1~10#1 := 0; 924#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 790#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1890#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 805#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1722#L816-42true assume 1 == ~t11_pc~0; 9#L817-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1865#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1483#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 479#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 314#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 573#L835-42true assume 1 == ~t12_pc~0; 837#L836-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1235#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 641#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1850#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1228#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 938#L854-42true assume 1 == ~t13_pc~0; 1794#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 475#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 364#is_transmit13_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 508#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 430#L1664-44true havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1869#L1401-3true assume !(1 == ~M_E~0); 1079#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 183#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 119#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1687#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 457#L1421-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1041#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 207#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 281#L1436-3true assume !(1 == ~T8_E~0); 14#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1134#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1123#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 513#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 295#L1461-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1612#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1828#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 267#L1476-3true assume !(1 == ~E_3~0); 1696#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 507#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 280#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1471#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 535#L1501-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1594#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 869#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 861#L1516-3true assume !(1 == ~E_11~0); 1730#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 613#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 957#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1854#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1893#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 194#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 489#L1911true assume !(0 == start_simulation_~tmp~3#1); 1297#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 892#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1016#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 94#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 511#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1325#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1339#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1161#L1892-2true [2024-11-13 13:49:08,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:08,739 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2024-11-13 13:49:08,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:08,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542385525] [2024-11-13 13:49:08,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:08,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:08,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:09,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:09,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:09,211 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542385525] [2024-11-13 13:49:09,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542385525] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:09,211 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:09,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:09,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870829153] [2024-11-13 13:49:09,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:09,218 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:09,220 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:09,220 INFO L85 PathProgramCache]: Analyzing trace with hash -1868176179, now seen corresponding path program 1 times [2024-11-13 13:49:09,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:09,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017699719] [2024-11-13 13:49:09,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:09,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:09,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:09,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:09,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:09,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2017699719] [2024-11-13 13:49:09,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2017699719] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:09,349 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:09,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:49:09,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572119139] [2024-11-13 13:49:09,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:09,351 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:09,352 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:09,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-13 13:49:09,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 13:49:09,384 INFO L87 Difference]: Start difference. First operand has 1936 states, 1935 states have (on average 1.4945736434108527) internal successors, (2892), 1935 states have internal predecessors, (2892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:09,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:09,483 INFO L93 Difference]: Finished difference Result 1934 states and 2855 transitions. [2024-11-13 13:49:09,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1934 states and 2855 transitions. [2024-11-13 13:49:09,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:09,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1934 states to 1928 states and 2849 transitions. [2024-11-13 13:49:09,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:09,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:09,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2849 transitions. [2024-11-13 13:49:09,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:09,548 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2024-11-13 13:49:09,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2849 transitions. [2024-11-13 13:49:09,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:09,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4776970954356847) internal successors, (2849), 1927 states have internal predecessors, (2849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:09,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2849 transitions. [2024-11-13 13:49:09,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2024-11-13 13:49:09,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-13 13:49:09,666 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2849 transitions. [2024-11-13 13:49:09,666 INFO L331 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-13 13:49:09,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2849 transitions. [2024-11-13 13:49:09,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:09,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:09,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:09,684 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:09,684 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:09,685 INFO L745 eck$LassoCheckResult]: Stem: 4170#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5070#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5071#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5796#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5467#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5468#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4391#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4392#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4869#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4706#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4707#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4455#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4456#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4877#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5061#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5229#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5262#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4471#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4472#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5687#L1258-2 assume !(0 == ~T1_E~0); 4789#L1263-1 assume !(0 == ~T2_E~0); 4790#L1268-1 assume !(0 == ~T3_E~0); 5107#L1273-1 assume !(0 == ~T4_E~0); 5666#L1278-1 assume !(0 == ~T5_E~0); 5524#L1283-1 assume !(0 == ~T6_E~0); 5525#L1288-1 assume !(0 == ~T7_E~0); 5762#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5751#L1298-1 assume !(0 == ~T9_E~0); 5682#L1303-1 assume !(0 == ~T10_E~0); 4269#L1308-1 assume !(0 == ~T11_E~0); 4209#L1313-1 assume !(0 == ~T12_E~0); 4210#L1318-1 assume !(0 == ~T13_E~0); 4215#L1323-1 assume !(0 == ~E_1~0); 4216#L1328-1 assume !(0 == ~E_2~0); 4401#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5395#L1338-1 assume !(0 == ~E_4~0); 5396#L1343-1 assume !(0 == ~E_5~0); 5501#L1348-1 assume !(0 == ~E_6~0); 5781#L1353-1 assume !(0 == ~E_7~0); 5130#L1358-1 assume !(0 == ~E_8~0); 5131#L1363-1 assume !(0 == ~E_9~0); 5417#L1368-1 assume !(0 == ~E_10~0); 4063#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4064#L1378-1 assume !(0 == ~E_12~0); 4344#L1383-1 assume !(0 == ~E_13~0); 4345#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5135#L607 assume 1 == ~m_pc~0; 5136#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4419#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4932#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4933#L1560 assume !(0 != activate_threads_~tmp~1#1); 5042#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4230#L626 assume !(1 == ~t1_pc~0); 4231#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4512#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4513#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5403#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4138#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4139#L645 assume 1 == ~t2_pc~0; 4246#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4203#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4312#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4313#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 5016#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5017#L664 assume 1 == ~t3_pc~0; 5779#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3997#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3998#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4661#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4662#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5695#L683 assume !(1 == ~t4_pc~0); 5246#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5200#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4021#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4022#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5353#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4956#L702 assume 1 == ~t5_pc~0; 4957#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4892#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5348#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5685#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5593#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4033#L721 assume !(1 == ~t6_pc~0); 4014#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4015#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4162#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4297#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4677#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5293#L740 assume 1 == ~t7_pc~0; 4079#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3914#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3915#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3904#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3905#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4601#L759 assume !(1 == ~t8_pc~0); 4602#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4633#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5739#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5478#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5479#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5761#L778 assume 1 == ~t9_pc~0; 5651#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4062#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4367#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3940#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3941#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4242#L797 assume !(1 == ~t10_pc~0); 4243#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4377#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5628#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4785#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4786#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5087#L816 assume 1 == ~t11_pc~0; 3975#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3976#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4921#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4683#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4684#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5228#L835 assume 1 == ~t12_pc~0; 5102#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4126#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3965#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3966#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4841#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4842#L854 assume !(1 == ~t13_pc~0); 4457#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4458#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4507#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4160#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4161#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5589#L1401 assume !(1 == ~M_E~0); 4670#L1401-2 assume !(1 == ~T1_E~0); 4671#L1406-1 assume !(1 == ~T2_E~0); 5282#L1411-1 assume !(1 == ~T3_E~0); 5283#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4931#L1421-1 assume !(1 == ~T5_E~0); 4453#L1426-1 assume !(1 == ~T6_E~0); 4454#L1431-1 assume !(1 == ~T7_E~0); 4012#L1436-1 assume !(1 == ~T8_E~0); 4013#L1441-1 assume !(1 == ~T9_E~0); 4778#L1446-1 assume !(1 == ~T10_E~0); 4779#L1451-1 assume !(1 == ~T11_E~0); 5497#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5155#L1461-1 assume !(1 == ~T13_E~0); 4699#L1466-1 assume !(1 == ~E_1~0); 4700#L1471-1 assume !(1 == ~E_2~0); 5476#L1476-1 assume !(1 == ~E_3~0); 5477#L1481-1 assume !(1 == ~E_4~0); 5634#L1486-1 assume !(1 == ~E_5~0); 4282#L1491-1 assume !(1 == ~E_6~0); 3950#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3951#L1501-1 assume !(1 == ~E_8~0); 4774#L1506-1 assume !(1 == ~E_9~0); 4775#L1511-1 assume !(1 == ~E_10~0); 4729#L1516-1 assume !(1 == ~E_11~0); 3902#L1521-1 assume !(1 == ~E_12~0); 3903#L1526-1 assume !(1 == ~E_13~0); 3949#L1531-1 assume { :end_inline_reset_delta_events } true; 4479#L1892-2 [2024-11-13 13:49:09,686 INFO L747 eck$LassoCheckResult]: Loop: 4479#L1892-2 assume !false; 5542#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5795#L1233-1 assume !false; 5722#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5043#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 5022#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5571#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3991#L1046 assume !(0 != eval_~tmp~0#1); 3993#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4524#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4525#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5778#L1258-5 assume !(0 == ~T1_E~0); 4150#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4151#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5770#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5774#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5775#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4382#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4383#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5539#L1298-3 assume !(0 == ~T9_E~0); 5540#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5702#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5538#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5027#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4152#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4153#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5626#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4293#L1338-3 assume !(0 == ~E_4~0); 4294#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5453#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5631#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5632#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4972#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4514#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4515#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5313#L1378-3 assume !(0 == ~E_12~0); 5314#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5494#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5495#L607-42 assume 1 == ~m_pc~0; 5112#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4822#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4654#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4534#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4535#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5088#L626-42 assume 1 == ~t1_pc~0; 4625#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4626#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5726#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5511#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4185#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4186#L645-42 assume !(1 == ~t2_pc~0); 5431#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5432#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4970#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4402#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3922#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3923#L664-42 assume !(1 == ~t3_pc~0); 4438#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 4439#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5372#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5260#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5261#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5424#L683-42 assume !(1 == ~t4_pc~0); 5138#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 5139#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5267#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5427#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5692#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5533#L702-42 assume !(1 == ~t5_pc~0); 4615#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4616#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4924#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5037#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 3934#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3935#L721-42 assume 1 == ~t6_pc~0; 4074#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4095#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4273#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4274#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4755#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4589#L740-42 assume !(1 == ~t7_pc~0); 4308#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4309#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4885#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4738#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4739#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5010#L759-42 assume 1 == ~t8_pc~0; 4861#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4795#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4796#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4870#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4871#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4961#L778-42 assume 1 == ~t9_pc~0; 4807#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4809#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5232#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5140#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5141#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5195#L797-42 assume 1 == ~t10_pc~0; 4316#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4317#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5213#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5214#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5233#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5234#L816-42 assume 1 == ~t11_pc~0; 3894#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3895#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5732#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4782#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4493#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4494#L835-42 assume !(1 == ~t12_pc~0); 4818#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4819#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5013#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5014#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5592#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5370#L854-42 assume 1 == ~t13_pc~0; 5371#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4415#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4581#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4582#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4695#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4696#L1401-3 assume !(1 == ~M_E~0); 5487#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4245#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4121#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4122#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4745#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4746#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4287#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4288#L1436-3 assume !(1 == ~T8_E~0); 3906#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3907#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5515#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4833#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4461#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4462#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5772#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4403#L1476-3 assume !(1 == ~E_3~0); 4404#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4827#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4431#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4432#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4867#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4868#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5309#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5297#L1516-3 assume !(1 == ~E_11~0); 5298#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4975#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4976#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5391#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4220#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4267#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4268#L1911 assume !(0 == start_simulation_~tmp~3#1); 4799#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5330#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4359#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3944#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3945#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4068#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4831#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 5645#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4479#L1892-2 [2024-11-13 13:49:09,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:09,686 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2024-11-13 13:49:09,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:09,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1746137235] [2024-11-13 13:49:09,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:09,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:09,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:09,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:09,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:09,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1746137235] [2024-11-13 13:49:09,895 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1746137235] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:09,895 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:09,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:09,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [924179215] [2024-11-13 13:49:09,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:09,896 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:09,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:09,896 INFO L85 PathProgramCache]: Analyzing trace with hash 1541090671, now seen corresponding path program 1 times [2024-11-13 13:49:09,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:09,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904600267] [2024-11-13 13:49:09,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:09,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:09,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:10,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:10,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:10,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904600267] [2024-11-13 13:49:10,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [904600267] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:10,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:10,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:10,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297566181] [2024-11-13 13:49:10,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:10,104 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:10,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:10,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:10,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:10,109 INFO L87 Difference]: Start difference. First operand 1928 states and 2849 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:10,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:10,184 INFO L93 Difference]: Finished difference Result 1928 states and 2848 transitions. [2024-11-13 13:49:10,186 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2848 transitions. [2024-11-13 13:49:10,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:10,215 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2848 transitions. [2024-11-13 13:49:10,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:10,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:10,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2848 transitions. [2024-11-13 13:49:10,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:10,227 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2024-11-13 13:49:10,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2848 transitions. [2024-11-13 13:49:10,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:10,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4771784232365146) internal successors, (2848), 1927 states have internal predecessors, (2848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:10,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2848 transitions. [2024-11-13 13:49:10,280 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2024-11-13 13:49:10,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:10,281 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2848 transitions. [2024-11-13 13:49:10,281 INFO L331 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-13 13:49:10,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2848 transitions. [2024-11-13 13:49:10,292 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:10,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:10,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:10,297 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:10,297 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:10,297 INFO L745 eck$LassoCheckResult]: Stem: 8033#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8933#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8934#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9659#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 9330#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9331#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8254#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8255#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8732#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8569#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8570#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8318#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8319#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8740#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8924#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9092#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9125#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8334#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8335#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 9550#L1258-2 assume !(0 == ~T1_E~0); 8652#L1263-1 assume !(0 == ~T2_E~0); 8653#L1268-1 assume !(0 == ~T3_E~0); 8970#L1273-1 assume !(0 == ~T4_E~0); 9529#L1278-1 assume !(0 == ~T5_E~0); 9387#L1283-1 assume !(0 == ~T6_E~0); 9388#L1288-1 assume !(0 == ~T7_E~0); 9625#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9614#L1298-1 assume !(0 == ~T9_E~0); 9545#L1303-1 assume !(0 == ~T10_E~0); 8132#L1308-1 assume !(0 == ~T11_E~0); 8072#L1313-1 assume !(0 == ~T12_E~0); 8073#L1318-1 assume !(0 == ~T13_E~0); 8078#L1323-1 assume !(0 == ~E_1~0); 8079#L1328-1 assume !(0 == ~E_2~0); 8264#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9258#L1338-1 assume !(0 == ~E_4~0); 9259#L1343-1 assume !(0 == ~E_5~0); 9364#L1348-1 assume !(0 == ~E_6~0); 9644#L1353-1 assume !(0 == ~E_7~0); 8993#L1358-1 assume !(0 == ~E_8~0); 8994#L1363-1 assume !(0 == ~E_9~0); 9280#L1368-1 assume !(0 == ~E_10~0); 7926#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 7927#L1378-1 assume !(0 == ~E_12~0); 8207#L1383-1 assume !(0 == ~E_13~0); 8208#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8998#L607 assume 1 == ~m_pc~0; 8999#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8282#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8795#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8796#L1560 assume !(0 != activate_threads_~tmp~1#1); 8905#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8093#L626 assume !(1 == ~t1_pc~0); 8094#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8375#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8376#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9266#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 8001#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8002#L645 assume 1 == ~t2_pc~0; 8109#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8066#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8175#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8176#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 8879#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8880#L664 assume 1 == ~t3_pc~0; 9642#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7860#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7861#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8524#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 8525#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9558#L683 assume !(1 == ~t4_pc~0); 9109#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9063#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7884#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7885#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9216#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8819#L702 assume 1 == ~t5_pc~0; 8820#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8755#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9211#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9548#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 9456#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7896#L721 assume !(1 == ~t6_pc~0); 7877#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7878#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8025#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8160#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 8540#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9156#L740 assume 1 == ~t7_pc~0; 7942#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7777#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7778#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7767#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 7768#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8464#L759 assume !(1 == ~t8_pc~0); 8465#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8496#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9602#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9341#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 9342#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9624#L778 assume 1 == ~t9_pc~0; 9514#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7925#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8230#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7803#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 7804#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8105#L797 assume !(1 == ~t10_pc~0); 8106#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8240#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9491#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8648#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 8649#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8950#L816 assume 1 == ~t11_pc~0; 7838#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7839#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8784#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8546#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 8547#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9091#L835 assume 1 == ~t12_pc~0; 8965#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7989#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7828#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7829#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 8704#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8705#L854 assume !(1 == ~t13_pc~0); 8320#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8321#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8370#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8023#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8024#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9452#L1401 assume !(1 == ~M_E~0); 8533#L1401-2 assume !(1 == ~T1_E~0); 8534#L1406-1 assume !(1 == ~T2_E~0); 9145#L1411-1 assume !(1 == ~T3_E~0); 9146#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8794#L1421-1 assume !(1 == ~T5_E~0); 8316#L1426-1 assume !(1 == ~T6_E~0); 8317#L1431-1 assume !(1 == ~T7_E~0); 7875#L1436-1 assume !(1 == ~T8_E~0); 7876#L1441-1 assume !(1 == ~T9_E~0); 8641#L1446-1 assume !(1 == ~T10_E~0); 8642#L1451-1 assume !(1 == ~T11_E~0); 9360#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9018#L1461-1 assume !(1 == ~T13_E~0); 8562#L1466-1 assume !(1 == ~E_1~0); 8563#L1471-1 assume !(1 == ~E_2~0); 9339#L1476-1 assume !(1 == ~E_3~0); 9340#L1481-1 assume !(1 == ~E_4~0); 9497#L1486-1 assume !(1 == ~E_5~0); 8145#L1491-1 assume !(1 == ~E_6~0); 7813#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7814#L1501-1 assume !(1 == ~E_8~0); 8637#L1506-1 assume !(1 == ~E_9~0); 8638#L1511-1 assume !(1 == ~E_10~0); 8592#L1516-1 assume !(1 == ~E_11~0); 7765#L1521-1 assume !(1 == ~E_12~0); 7766#L1526-1 assume !(1 == ~E_13~0); 7812#L1531-1 assume { :end_inline_reset_delta_events } true; 8342#L1892-2 [2024-11-13 13:49:10,298 INFO L747 eck$LassoCheckResult]: Loop: 8342#L1892-2 assume !false; 9405#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9658#L1233-1 assume !false; 9585#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8906#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8885#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9434#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7854#L1046 assume !(0 != eval_~tmp~0#1); 7856#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8387#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8388#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9641#L1258-5 assume !(0 == ~T1_E~0); 8013#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8014#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9633#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9637#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9638#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8245#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8246#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9402#L1298-3 assume !(0 == ~T9_E~0); 9403#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9565#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9401#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8890#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8015#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8016#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9489#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8156#L1338-3 assume !(0 == ~E_4~0); 8157#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9316#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9494#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9495#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8835#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8377#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8378#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9176#L1378-3 assume !(0 == ~E_12~0); 9177#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9357#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9358#L607-42 assume !(1 == ~m_pc~0); 8976#L607-44 is_master_triggered_~__retres1~0#1 := 0; 8685#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8517#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8397#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8398#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8951#L626-42 assume 1 == ~t1_pc~0; 8488#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8489#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9589#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9374#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8048#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8049#L645-42 assume 1 == ~t2_pc~0; 9557#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9295#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8833#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8265#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7785#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7786#L664-42 assume 1 == ~t3_pc~0; 8598#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8302#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9235#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9123#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9124#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9287#L683-42 assume 1 == ~t4_pc~0; 9650#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9002#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9130#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9290#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9555#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9396#L702-42 assume 1 == ~t5_pc~0; 8867#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8479#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8787#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8900#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 7797#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7798#L721-42 assume 1 == ~t6_pc~0; 7937#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7958#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8136#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8137#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8618#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8452#L740-42 assume 1 == ~t7_pc~0; 8453#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8172#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8748#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8601#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8602#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8873#L759-42 assume 1 == ~t8_pc~0; 8724#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8658#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8659#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8733#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8734#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8824#L778-42 assume 1 == ~t9_pc~0; 8670#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8672#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9095#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9003#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9004#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9058#L797-42 assume 1 == ~t10_pc~0; 8179#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8180#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9076#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9077#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9096#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9097#L816-42 assume 1 == ~t11_pc~0; 7757#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7758#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9595#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8645#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8356#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8357#L835-42 assume !(1 == ~t12_pc~0); 8681#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 8682#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8876#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8877#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9455#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9233#L854-42 assume 1 == ~t13_pc~0; 9234#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8278#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8444#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8445#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8558#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8559#L1401-3 assume !(1 == ~M_E~0); 9350#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8108#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7984#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7985#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8608#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8609#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8150#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8151#L1436-3 assume !(1 == ~T8_E~0); 7769#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7770#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9378#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8696#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8324#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8325#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9635#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8266#L1476-3 assume !(1 == ~E_3~0); 8267#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8690#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8294#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8295#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8730#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8731#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9172#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9160#L1516-3 assume !(1 == ~E_11~0); 9161#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8838#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8839#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9254#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8083#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8130#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8131#L1911 assume !(0 == start_simulation_~tmp~3#1); 8662#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9193#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8222#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 7807#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7808#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7931#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8694#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 9508#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8342#L1892-2 [2024-11-13 13:49:10,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:10,302 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2024-11-13 13:49:10,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:10,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967640929] [2024-11-13 13:49:10,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:10,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:10,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:10,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:10,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:10,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967640929] [2024-11-13 13:49:10,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967640929] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:10,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:10,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:10,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175610354] [2024-11-13 13:49:10,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:10,440 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:10,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:10,441 INFO L85 PathProgramCache]: Analyzing trace with hash 242231475, now seen corresponding path program 1 times [2024-11-13 13:49:10,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:10,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131097738] [2024-11-13 13:49:10,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:10,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:10,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:10,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:10,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:10,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131097738] [2024-11-13 13:49:10,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131097738] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:10,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:10,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:10,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413392838] [2024-11-13 13:49:10,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:10,625 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:10,625 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:10,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:10,625 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:10,626 INFO L87 Difference]: Start difference. First operand 1928 states and 2848 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:10,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:10,678 INFO L93 Difference]: Finished difference Result 1928 states and 2847 transitions. [2024-11-13 13:49:10,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2847 transitions. [2024-11-13 13:49:10,691 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:10,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2847 transitions. [2024-11-13 13:49:10,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:10,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:10,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2847 transitions. [2024-11-13 13:49:10,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:10,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2024-11-13 13:49:10,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2847 transitions. [2024-11-13 13:49:10,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:10,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4766597510373445) internal successors, (2847), 1927 states have internal predecessors, (2847), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:10,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2847 transitions. [2024-11-13 13:49:10,745 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2024-11-13 13:49:10,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:10,748 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2847 transitions. [2024-11-13 13:49:10,748 INFO L331 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-13 13:49:10,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2847 transitions. [2024-11-13 13:49:10,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:10,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:10,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:10,761 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:10,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:10,762 INFO L745 eck$LassoCheckResult]: Stem: 11896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 11897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12796#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12797#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13522#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13193#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13194#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12117#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12118#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12595#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12432#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12433#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12181#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12182#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12603#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12787#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12955#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12988#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12197#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12198#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13413#L1258-2 assume !(0 == ~T1_E~0); 12515#L1263-1 assume !(0 == ~T2_E~0); 12516#L1268-1 assume !(0 == ~T3_E~0); 12833#L1273-1 assume !(0 == ~T4_E~0); 13392#L1278-1 assume !(0 == ~T5_E~0); 13250#L1283-1 assume !(0 == ~T6_E~0); 13251#L1288-1 assume !(0 == ~T7_E~0); 13488#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13477#L1298-1 assume !(0 == ~T9_E~0); 13408#L1303-1 assume !(0 == ~T10_E~0); 11995#L1308-1 assume !(0 == ~T11_E~0); 11935#L1313-1 assume !(0 == ~T12_E~0); 11936#L1318-1 assume !(0 == ~T13_E~0); 11941#L1323-1 assume !(0 == ~E_1~0); 11942#L1328-1 assume !(0 == ~E_2~0); 12127#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13121#L1338-1 assume !(0 == ~E_4~0); 13122#L1343-1 assume !(0 == ~E_5~0); 13227#L1348-1 assume !(0 == ~E_6~0); 13507#L1353-1 assume !(0 == ~E_7~0); 12856#L1358-1 assume !(0 == ~E_8~0); 12857#L1363-1 assume !(0 == ~E_9~0); 13143#L1368-1 assume !(0 == ~E_10~0); 11789#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11790#L1378-1 assume !(0 == ~E_12~0); 12070#L1383-1 assume !(0 == ~E_13~0); 12071#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12861#L607 assume 1 == ~m_pc~0; 12862#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12145#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12658#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12659#L1560 assume !(0 != activate_threads_~tmp~1#1); 12768#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11956#L626 assume !(1 == ~t1_pc~0); 11957#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12238#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12239#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13129#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11864#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11865#L645 assume 1 == ~t2_pc~0; 11972#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11929#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12038#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12039#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12742#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12743#L664 assume 1 == ~t3_pc~0; 13505#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11723#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11724#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12387#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12388#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13421#L683 assume !(1 == ~t4_pc~0); 12972#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12926#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11748#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13079#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12682#L702 assume 1 == ~t5_pc~0; 12683#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12618#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13074#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13411#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13319#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11759#L721 assume !(1 == ~t6_pc~0); 11740#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11741#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11888#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12023#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12403#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13019#L740 assume 1 == ~t7_pc~0; 11805#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11640#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11641#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11630#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11631#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12327#L759 assume !(1 == ~t8_pc~0); 12328#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12359#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13465#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13204#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13205#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13487#L778 assume 1 == ~t9_pc~0; 13377#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11788#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12093#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11666#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11667#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11968#L797 assume !(1 == ~t10_pc~0); 11969#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12103#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13354#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12511#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12512#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12813#L816 assume 1 == ~t11_pc~0; 11701#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11702#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12647#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12409#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12410#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12954#L835 assume 1 == ~t12_pc~0; 12828#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11852#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11691#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11692#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12567#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12568#L854 assume !(1 == ~t13_pc~0); 12183#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12184#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12233#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11886#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11887#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13315#L1401 assume !(1 == ~M_E~0); 12396#L1401-2 assume !(1 == ~T1_E~0); 12397#L1406-1 assume !(1 == ~T2_E~0); 13008#L1411-1 assume !(1 == ~T3_E~0); 13009#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12657#L1421-1 assume !(1 == ~T5_E~0); 12179#L1426-1 assume !(1 == ~T6_E~0); 12180#L1431-1 assume !(1 == ~T7_E~0); 11738#L1436-1 assume !(1 == ~T8_E~0); 11739#L1441-1 assume !(1 == ~T9_E~0); 12504#L1446-1 assume !(1 == ~T10_E~0); 12505#L1451-1 assume !(1 == ~T11_E~0); 13223#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12881#L1461-1 assume !(1 == ~T13_E~0); 12425#L1466-1 assume !(1 == ~E_1~0); 12426#L1471-1 assume !(1 == ~E_2~0); 13202#L1476-1 assume !(1 == ~E_3~0); 13203#L1481-1 assume !(1 == ~E_4~0); 13360#L1486-1 assume !(1 == ~E_5~0); 12008#L1491-1 assume !(1 == ~E_6~0); 11676#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11677#L1501-1 assume !(1 == ~E_8~0); 12500#L1506-1 assume !(1 == ~E_9~0); 12501#L1511-1 assume !(1 == ~E_10~0); 12455#L1516-1 assume !(1 == ~E_11~0); 11628#L1521-1 assume !(1 == ~E_12~0); 11629#L1526-1 assume !(1 == ~E_13~0); 11675#L1531-1 assume { :end_inline_reset_delta_events } true; 12205#L1892-2 [2024-11-13 13:49:10,762 INFO L747 eck$LassoCheckResult]: Loop: 12205#L1892-2 assume !false; 13268#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13521#L1233-1 assume !false; 13448#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12769#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12748#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13297#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11717#L1046 assume !(0 != eval_~tmp~0#1); 11719#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12250#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12251#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13504#L1258-5 assume !(0 == ~T1_E~0); 11876#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11877#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13496#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13500#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13501#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12108#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12109#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13265#L1298-3 assume !(0 == ~T9_E~0); 13266#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13428#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13264#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12753#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11878#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11879#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13352#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12019#L1338-3 assume !(0 == ~E_4~0); 12020#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13179#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13357#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13358#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12698#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12240#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12241#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13039#L1378-3 assume !(0 == ~E_12~0); 13040#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13220#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13221#L607-42 assume 1 == ~m_pc~0; 12838#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12548#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12380#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12260#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12261#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12814#L626-42 assume !(1 == ~t1_pc~0); 12353#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12352#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13452#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13237#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11911#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11912#L645-42 assume !(1 == ~t2_pc~0); 13157#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13158#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12696#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12128#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11648#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11649#L664-42 assume !(1 == ~t3_pc~0); 12164#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 12165#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13098#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12986#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12987#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13150#L683-42 assume !(1 == ~t4_pc~0); 12864#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12865#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12993#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13153#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13418#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13259#L702-42 assume !(1 == ~t5_pc~0); 12341#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 12342#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12650#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12763#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 11660#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11661#L721-42 assume 1 == ~t6_pc~0; 11800#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11821#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11999#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12000#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12481#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12315#L740-42 assume !(1 == ~t7_pc~0); 12034#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 12035#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12611#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12464#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12465#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12736#L759-42 assume 1 == ~t8_pc~0; 12587#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12521#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12522#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12596#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12597#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12687#L778-42 assume 1 == ~t9_pc~0; 12533#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12535#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12958#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12866#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12867#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12921#L797-42 assume 1 == ~t10_pc~0; 12042#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12043#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12939#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12940#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12959#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12960#L816-42 assume 1 == ~t11_pc~0; 11620#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11621#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13458#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12508#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12219#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12220#L835-42 assume !(1 == ~t12_pc~0); 12544#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 12545#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12739#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12740#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13318#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13096#L854-42 assume 1 == ~t13_pc~0; 13097#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12141#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12307#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12308#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12421#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12422#L1401-3 assume !(1 == ~M_E~0); 13213#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11971#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11847#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11848#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12471#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12472#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12013#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12014#L1436-3 assume !(1 == ~T8_E~0); 11632#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11633#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13241#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12559#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12187#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12188#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13498#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12129#L1476-3 assume !(1 == ~E_3~0); 12130#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12553#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12157#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12158#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12593#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12594#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13035#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13023#L1516-3 assume !(1 == ~E_11~0); 13024#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12701#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12702#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13117#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11946#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11993#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11994#L1911 assume !(0 == start_simulation_~tmp~3#1); 12525#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13056#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12085#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11670#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11671#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11794#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12557#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 13371#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12205#L1892-2 [2024-11-13 13:49:10,763 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:10,763 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2024-11-13 13:49:10,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:10,763 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36941324] [2024-11-13 13:49:10,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:10,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:10,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:10,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:10,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:10,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36941324] [2024-11-13 13:49:10,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36941324] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:10,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:10,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:10,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414574725] [2024-11-13 13:49:10,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:10,867 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:10,867 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:10,867 INFO L85 PathProgramCache]: Analyzing trace with hash 663835854, now seen corresponding path program 1 times [2024-11-13 13:49:10,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:10,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807662729] [2024-11-13 13:49:10,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:10,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:10,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:10,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:10,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:10,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807662729] [2024-11-13 13:49:10,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807662729] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:10,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:10,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:10,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023285475] [2024-11-13 13:49:10,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:10,988 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:10,988 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:10,988 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:10,988 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:10,988 INFO L87 Difference]: Start difference. First operand 1928 states and 2847 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:11,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:11,039 INFO L93 Difference]: Finished difference Result 1928 states and 2846 transitions. [2024-11-13 13:49:11,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2846 transitions. [2024-11-13 13:49:11,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:11,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2846 transitions. [2024-11-13 13:49:11,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:11,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:11,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2846 transitions. [2024-11-13 13:49:11,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:11,089 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2024-11-13 13:49:11,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2846 transitions. [2024-11-13 13:49:11,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:11,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4761410788381744) internal successors, (2846), 1927 states have internal predecessors, (2846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:11,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2846 transitions. [2024-11-13 13:49:11,137 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2024-11-13 13:49:11,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:11,139 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2846 transitions. [2024-11-13 13:49:11,139 INFO L331 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-13 13:49:11,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2846 transitions. [2024-11-13 13:49:11,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:11,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:11,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:11,158 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:11,158 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:11,158 INFO L745 eck$LassoCheckResult]: Stem: 15759#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 15760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16659#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16660#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17385#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 17056#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17057#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15980#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15981#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16458#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16295#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16296#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16044#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16045#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16466#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16650#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16818#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16851#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 16060#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16061#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 17276#L1258-2 assume !(0 == ~T1_E~0); 16378#L1263-1 assume !(0 == ~T2_E~0); 16379#L1268-1 assume !(0 == ~T3_E~0); 16696#L1273-1 assume !(0 == ~T4_E~0); 17255#L1278-1 assume !(0 == ~T5_E~0); 17113#L1283-1 assume !(0 == ~T6_E~0); 17114#L1288-1 assume !(0 == ~T7_E~0); 17351#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17340#L1298-1 assume !(0 == ~T9_E~0); 17271#L1303-1 assume !(0 == ~T10_E~0); 15858#L1308-1 assume !(0 == ~T11_E~0); 15798#L1313-1 assume !(0 == ~T12_E~0); 15799#L1318-1 assume !(0 == ~T13_E~0); 15804#L1323-1 assume !(0 == ~E_1~0); 15805#L1328-1 assume !(0 == ~E_2~0); 15990#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16984#L1338-1 assume !(0 == ~E_4~0); 16985#L1343-1 assume !(0 == ~E_5~0); 17090#L1348-1 assume !(0 == ~E_6~0); 17370#L1353-1 assume !(0 == ~E_7~0); 16719#L1358-1 assume !(0 == ~E_8~0); 16720#L1363-1 assume !(0 == ~E_9~0); 17006#L1368-1 assume !(0 == ~E_10~0); 15652#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 15653#L1378-1 assume !(0 == ~E_12~0); 15933#L1383-1 assume !(0 == ~E_13~0); 15934#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16724#L607 assume 1 == ~m_pc~0; 16725#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16008#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16521#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16522#L1560 assume !(0 != activate_threads_~tmp~1#1); 16631#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15819#L626 assume !(1 == ~t1_pc~0); 15820#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16101#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16102#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16992#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 15727#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15728#L645 assume 1 == ~t2_pc~0; 15835#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15792#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15901#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15902#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 16605#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16606#L664 assume 1 == ~t3_pc~0; 17368#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15586#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15587#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16250#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 16251#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17284#L683 assume !(1 == ~t4_pc~0); 16835#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 16789#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15610#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15611#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16942#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16545#L702 assume 1 == ~t5_pc~0; 16546#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16481#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16937#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17274#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 17182#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15622#L721 assume !(1 == ~t6_pc~0); 15603#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 15604#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15751#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15886#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 16266#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16882#L740 assume 1 == ~t7_pc~0; 15668#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15503#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15504#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15493#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 15494#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16190#L759 assume !(1 == ~t8_pc~0); 16191#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16222#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17328#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17067#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 17068#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17350#L778 assume 1 == ~t9_pc~0; 17240#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15651#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15956#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15529#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 15530#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15831#L797 assume !(1 == ~t10_pc~0); 15832#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 15966#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17217#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16374#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 16375#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16676#L816 assume 1 == ~t11_pc~0; 15564#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15565#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16510#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16272#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 16273#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16817#L835 assume 1 == ~t12_pc~0; 16691#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15715#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15554#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15555#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 16430#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16431#L854 assume !(1 == ~t13_pc~0); 16046#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 16047#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16096#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15749#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 15750#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17178#L1401 assume !(1 == ~M_E~0); 16259#L1401-2 assume !(1 == ~T1_E~0); 16260#L1406-1 assume !(1 == ~T2_E~0); 16871#L1411-1 assume !(1 == ~T3_E~0); 16872#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16520#L1421-1 assume !(1 == ~T5_E~0); 16042#L1426-1 assume !(1 == ~T6_E~0); 16043#L1431-1 assume !(1 == ~T7_E~0); 15601#L1436-1 assume !(1 == ~T8_E~0); 15602#L1441-1 assume !(1 == ~T9_E~0); 16367#L1446-1 assume !(1 == ~T10_E~0); 16368#L1451-1 assume !(1 == ~T11_E~0); 17086#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16744#L1461-1 assume !(1 == ~T13_E~0); 16288#L1466-1 assume !(1 == ~E_1~0); 16289#L1471-1 assume !(1 == ~E_2~0); 17065#L1476-1 assume !(1 == ~E_3~0); 17066#L1481-1 assume !(1 == ~E_4~0); 17223#L1486-1 assume !(1 == ~E_5~0); 15871#L1491-1 assume !(1 == ~E_6~0); 15539#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 15540#L1501-1 assume !(1 == ~E_8~0); 16363#L1506-1 assume !(1 == ~E_9~0); 16364#L1511-1 assume !(1 == ~E_10~0); 16318#L1516-1 assume !(1 == ~E_11~0); 15491#L1521-1 assume !(1 == ~E_12~0); 15492#L1526-1 assume !(1 == ~E_13~0); 15538#L1531-1 assume { :end_inline_reset_delta_events } true; 16068#L1892-2 [2024-11-13 13:49:11,162 INFO L747 eck$LassoCheckResult]: Loop: 16068#L1892-2 assume !false; 17131#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17384#L1233-1 assume !false; 17311#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16632#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16611#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17160#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15580#L1046 assume !(0 != eval_~tmp~0#1); 15582#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16113#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16114#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17367#L1258-5 assume !(0 == ~T1_E~0); 15739#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15740#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17359#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17363#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17364#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15971#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15972#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17128#L1298-3 assume !(0 == ~T9_E~0); 17129#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17291#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17127#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16616#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15741#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15742#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17215#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15882#L1338-3 assume !(0 == ~E_4~0); 15883#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17042#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17220#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17221#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16561#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16103#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16104#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16902#L1378-3 assume !(0 == ~E_12~0); 16903#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17083#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17084#L607-42 assume 1 == ~m_pc~0; 16701#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16411#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16243#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16123#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16124#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16677#L626-42 assume 1 == ~t1_pc~0; 16214#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16215#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17315#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17100#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15774#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15775#L645-42 assume 1 == ~t2_pc~0; 17283#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17021#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16559#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15991#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15511#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15512#L664-42 assume 1 == ~t3_pc~0; 16324#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16028#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16961#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16849#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16850#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17013#L683-42 assume 1 == ~t4_pc~0; 17376#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16728#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16856#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17016#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17281#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17122#L702-42 assume 1 == ~t5_pc~0; 16593#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16205#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16513#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16626#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 15523#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15524#L721-42 assume !(1 == ~t6_pc~0); 15664#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 15684#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15862#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15863#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16344#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16178#L740-42 assume 1 == ~t7_pc~0; 16179#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15898#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16474#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16327#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16328#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16599#L759-42 assume 1 == ~t8_pc~0; 16450#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16384#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16385#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16459#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16460#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16550#L778-42 assume 1 == ~t9_pc~0; 16396#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16398#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16821#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16729#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16730#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16784#L797-42 assume 1 == ~t10_pc~0; 15905#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15906#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16802#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16803#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16822#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16823#L816-42 assume 1 == ~t11_pc~0; 15483#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15484#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17321#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16371#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16082#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16083#L835-42 assume !(1 == ~t12_pc~0); 16407#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 16408#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16602#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16603#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17181#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16959#L854-42 assume 1 == ~t13_pc~0; 16960#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16004#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16170#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16171#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16284#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16285#L1401-3 assume !(1 == ~M_E~0); 17076#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15834#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15710#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15711#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16334#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16335#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15876#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15877#L1436-3 assume !(1 == ~T8_E~0); 15495#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15496#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17104#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16422#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16050#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16051#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17361#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15992#L1476-3 assume !(1 == ~E_3~0); 15993#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16416#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16020#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16021#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16456#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16457#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16898#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16886#L1516-3 assume !(1 == ~E_11~0); 16887#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16564#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16565#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16980#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15809#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15856#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15857#L1911 assume !(0 == start_simulation_~tmp~3#1); 16388#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16919#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 15948#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 15533#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15534#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15657#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16420#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 17234#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 16068#L1892-2 [2024-11-13 13:49:11,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:11,163 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2024-11-13 13:49:11,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:11,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949507961] [2024-11-13 13:49:11,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:11,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:11,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:11,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:11,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:11,288 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949507961] [2024-11-13 13:49:11,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1949507961] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:11,289 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:11,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:11,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130699227] [2024-11-13 13:49:11,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:11,289 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:11,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:11,290 INFO L85 PathProgramCache]: Analyzing trace with hash -160740301, now seen corresponding path program 1 times [2024-11-13 13:49:11,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:11,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685633143] [2024-11-13 13:49:11,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:11,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:11,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:11,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:11,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:11,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685633143] [2024-11-13 13:49:11,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685633143] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:11,413 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:11,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:11,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230215407] [2024-11-13 13:49:11,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:11,414 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:11,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:11,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:11,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:11,415 INFO L87 Difference]: Start difference. First operand 1928 states and 2846 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:11,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:11,465 INFO L93 Difference]: Finished difference Result 1928 states and 2845 transitions. [2024-11-13 13:49:11,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2845 transitions. [2024-11-13 13:49:11,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:11,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2845 transitions. [2024-11-13 13:49:11,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:11,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:11,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2845 transitions. [2024-11-13 13:49:11,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:11,498 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2024-11-13 13:49:11,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2845 transitions. [2024-11-13 13:49:11,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:11,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4756224066390042) internal successors, (2845), 1927 states have internal predecessors, (2845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:11,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2845 transitions. [2024-11-13 13:49:11,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2024-11-13 13:49:11,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:11,543 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2845 transitions. [2024-11-13 13:49:11,543 INFO L331 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-13 13:49:11,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2845 transitions. [2024-11-13 13:49:11,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:11,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:11,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:11,558 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:11,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:11,558 INFO L745 eck$LassoCheckResult]: Stem: 19622#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 19623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20522#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20523#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21248#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20919#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20920#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19843#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19844#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20321#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20158#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20159#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19907#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19908#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20329#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20513#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20681#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20714#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19923#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19924#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 21139#L1258-2 assume !(0 == ~T1_E~0); 20241#L1263-1 assume !(0 == ~T2_E~0); 20242#L1268-1 assume !(0 == ~T3_E~0); 20559#L1273-1 assume !(0 == ~T4_E~0); 21118#L1278-1 assume !(0 == ~T5_E~0); 20976#L1283-1 assume !(0 == ~T6_E~0); 20977#L1288-1 assume !(0 == ~T7_E~0); 21214#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21203#L1298-1 assume !(0 == ~T9_E~0); 21134#L1303-1 assume !(0 == ~T10_E~0); 19721#L1308-1 assume !(0 == ~T11_E~0); 19661#L1313-1 assume !(0 == ~T12_E~0); 19662#L1318-1 assume !(0 == ~T13_E~0); 19667#L1323-1 assume !(0 == ~E_1~0); 19668#L1328-1 assume !(0 == ~E_2~0); 19853#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20847#L1338-1 assume !(0 == ~E_4~0); 20848#L1343-1 assume !(0 == ~E_5~0); 20953#L1348-1 assume !(0 == ~E_6~0); 21233#L1353-1 assume !(0 == ~E_7~0); 20582#L1358-1 assume !(0 == ~E_8~0); 20583#L1363-1 assume !(0 == ~E_9~0); 20869#L1368-1 assume !(0 == ~E_10~0); 19515#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19516#L1378-1 assume !(0 == ~E_12~0); 19796#L1383-1 assume !(0 == ~E_13~0); 19797#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20587#L607 assume 1 == ~m_pc~0; 20588#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19871#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20384#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20385#L1560 assume !(0 != activate_threads_~tmp~1#1); 20494#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19682#L626 assume !(1 == ~t1_pc~0); 19683#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19964#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19965#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20855#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19590#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19591#L645 assume 1 == ~t2_pc~0; 19698#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19655#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19764#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19765#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20468#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20469#L664 assume 1 == ~t3_pc~0; 21231#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19449#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19450#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20113#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 20114#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21147#L683 assume !(1 == ~t4_pc~0); 20698#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20652#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19473#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19474#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20805#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20408#L702 assume 1 == ~t5_pc~0; 20409#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20344#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20800#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21137#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 21045#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19485#L721 assume !(1 == ~t6_pc~0); 19466#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19467#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19614#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19749#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 20129#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20745#L740 assume 1 == ~t7_pc~0; 19531#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19366#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19367#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19356#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19357#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20053#L759 assume !(1 == ~t8_pc~0); 20054#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20085#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21191#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20930#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20931#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21213#L778 assume 1 == ~t9_pc~0; 21103#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19514#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19819#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19392#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19393#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19694#L797 assume !(1 == ~t10_pc~0); 19695#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19829#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21080#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20237#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20238#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20539#L816 assume 1 == ~t11_pc~0; 19427#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19428#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20373#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20135#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 20136#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20680#L835 assume 1 == ~t12_pc~0; 20554#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19578#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19417#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19418#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20293#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20294#L854 assume !(1 == ~t13_pc~0); 19909#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19910#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19959#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19612#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19613#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21041#L1401 assume !(1 == ~M_E~0); 20122#L1401-2 assume !(1 == ~T1_E~0); 20123#L1406-1 assume !(1 == ~T2_E~0); 20734#L1411-1 assume !(1 == ~T3_E~0); 20735#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20383#L1421-1 assume !(1 == ~T5_E~0); 19905#L1426-1 assume !(1 == ~T6_E~0); 19906#L1431-1 assume !(1 == ~T7_E~0); 19464#L1436-1 assume !(1 == ~T8_E~0); 19465#L1441-1 assume !(1 == ~T9_E~0); 20230#L1446-1 assume !(1 == ~T10_E~0); 20231#L1451-1 assume !(1 == ~T11_E~0); 20949#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20607#L1461-1 assume !(1 == ~T13_E~0); 20151#L1466-1 assume !(1 == ~E_1~0); 20152#L1471-1 assume !(1 == ~E_2~0); 20928#L1476-1 assume !(1 == ~E_3~0); 20929#L1481-1 assume !(1 == ~E_4~0); 21086#L1486-1 assume !(1 == ~E_5~0); 19734#L1491-1 assume !(1 == ~E_6~0); 19402#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19403#L1501-1 assume !(1 == ~E_8~0); 20226#L1506-1 assume !(1 == ~E_9~0); 20227#L1511-1 assume !(1 == ~E_10~0); 20181#L1516-1 assume !(1 == ~E_11~0); 19354#L1521-1 assume !(1 == ~E_12~0); 19355#L1526-1 assume !(1 == ~E_13~0); 19401#L1531-1 assume { :end_inline_reset_delta_events } true; 19931#L1892-2 [2024-11-13 13:49:11,558 INFO L747 eck$LassoCheckResult]: Loop: 19931#L1892-2 assume !false; 20994#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21247#L1233-1 assume !false; 21174#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20495#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20474#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21023#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19443#L1046 assume !(0 != eval_~tmp~0#1); 19445#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19976#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19977#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21230#L1258-5 assume !(0 == ~T1_E~0); 19602#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19603#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21222#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21226#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21227#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19834#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19835#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20991#L1298-3 assume !(0 == ~T9_E~0); 20992#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21154#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20990#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20479#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19604#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19605#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21078#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19745#L1338-3 assume !(0 == ~E_4~0); 19746#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20905#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21083#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21084#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20424#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19966#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19967#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20765#L1378-3 assume !(0 == ~E_12~0); 20766#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20946#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20947#L607-42 assume 1 == ~m_pc~0; 20564#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20274#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20106#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19986#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19987#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20540#L626-42 assume 1 == ~t1_pc~0; 20077#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20078#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21178#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20963#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19637#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19638#L645-42 assume !(1 == ~t2_pc~0); 20883#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 20884#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20422#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19854#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19374#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19375#L664-42 assume !(1 == ~t3_pc~0); 19890#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 19891#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20824#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20712#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20713#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20876#L683-42 assume 1 == ~t4_pc~0; 21239#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20591#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20719#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20879#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21144#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20985#L702-42 assume !(1 == ~t5_pc~0); 20067#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 20068#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20376#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20489#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 19386#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19387#L721-42 assume 1 == ~t6_pc~0; 19526#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19547#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19725#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19726#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20207#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20041#L740-42 assume !(1 == ~t7_pc~0); 19760#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 19761#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20337#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20190#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20191#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20462#L759-42 assume 1 == ~t8_pc~0; 20313#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20247#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20248#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20322#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20323#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20413#L778-42 assume 1 == ~t9_pc~0; 20259#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20261#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20684#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20592#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20593#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20647#L797-42 assume 1 == ~t10_pc~0; 19768#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19769#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20665#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20666#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20685#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20686#L816-42 assume 1 == ~t11_pc~0; 19346#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19347#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21184#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20234#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19945#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19946#L835-42 assume 1 == ~t12_pc~0; 20372#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20271#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20465#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20466#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21044#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20822#L854-42 assume 1 == ~t13_pc~0; 20823#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 19867#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20033#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20034#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20147#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20148#L1401-3 assume !(1 == ~M_E~0); 20939#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19697#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19573#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19574#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20197#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20198#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19739#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19740#L1436-3 assume !(1 == ~T8_E~0); 19358#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19359#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20967#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20285#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19913#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 19914#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21224#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19855#L1476-3 assume !(1 == ~E_3~0); 19856#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20279#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19883#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19884#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20319#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20320#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20761#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20749#L1516-3 assume !(1 == ~E_11~0); 20750#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20427#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20428#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20843#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19672#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19719#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19720#L1911 assume !(0 == start_simulation_~tmp~3#1); 20251#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20782#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19811#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 19396#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19397#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19520#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20283#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 21097#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19931#L1892-2 [2024-11-13 13:49:11,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:11,559 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2024-11-13 13:49:11,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:11,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436664529] [2024-11-13 13:49:11,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:11,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:11,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:11,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:11,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:11,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1436664529] [2024-11-13 13:49:11,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1436664529] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:11,631 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:11,631 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:11,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167771052] [2024-11-13 13:49:11,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:11,632 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:11,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:11,632 INFO L85 PathProgramCache]: Analyzing trace with hash -1049251535, now seen corresponding path program 1 times [2024-11-13 13:49:11,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:11,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888533487] [2024-11-13 13:49:11,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:11,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:11,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:11,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:11,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:11,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888533487] [2024-11-13 13:49:11,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888533487] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:11,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:11,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:11,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [346294045] [2024-11-13 13:49:11,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:11,755 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:11,755 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:11,756 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:11,756 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:11,756 INFO L87 Difference]: Start difference. First operand 1928 states and 2845 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:11,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:11,801 INFO L93 Difference]: Finished difference Result 1928 states and 2844 transitions. [2024-11-13 13:49:11,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2844 transitions. [2024-11-13 13:49:11,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:11,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2844 transitions. [2024-11-13 13:49:11,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:11,824 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:11,825 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2844 transitions. [2024-11-13 13:49:11,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:11,828 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2024-11-13 13:49:11,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2844 transitions. [2024-11-13 13:49:11,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:11,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4751037344398341) internal successors, (2844), 1927 states have internal predecessors, (2844), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:11,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2844 transitions. [2024-11-13 13:49:11,866 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2024-11-13 13:49:11,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:11,868 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2844 transitions. [2024-11-13 13:49:11,868 INFO L331 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-13 13:49:11,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2844 transitions. [2024-11-13 13:49:11,878 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:11,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:11,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:11,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:11,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:11,883 INFO L745 eck$LassoCheckResult]: Stem: 23485#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25111#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24782#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24783#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23706#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23707#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24184#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24021#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 24022#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23770#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23771#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24192#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24376#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24544#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24577#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23786#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23787#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 25002#L1258-2 assume !(0 == ~T1_E~0); 24104#L1263-1 assume !(0 == ~T2_E~0); 24105#L1268-1 assume !(0 == ~T3_E~0); 24422#L1273-1 assume !(0 == ~T4_E~0); 24981#L1278-1 assume !(0 == ~T5_E~0); 24839#L1283-1 assume !(0 == ~T6_E~0); 24840#L1288-1 assume !(0 == ~T7_E~0); 25077#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25066#L1298-1 assume !(0 == ~T9_E~0); 24997#L1303-1 assume !(0 == ~T10_E~0); 23584#L1308-1 assume !(0 == ~T11_E~0); 23524#L1313-1 assume !(0 == ~T12_E~0); 23525#L1318-1 assume !(0 == ~T13_E~0); 23530#L1323-1 assume !(0 == ~E_1~0); 23531#L1328-1 assume !(0 == ~E_2~0); 23716#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 24710#L1338-1 assume !(0 == ~E_4~0); 24711#L1343-1 assume !(0 == ~E_5~0); 24816#L1348-1 assume !(0 == ~E_6~0); 25096#L1353-1 assume !(0 == ~E_7~0); 24445#L1358-1 assume !(0 == ~E_8~0); 24446#L1363-1 assume !(0 == ~E_9~0); 24732#L1368-1 assume !(0 == ~E_10~0); 23378#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 23379#L1378-1 assume !(0 == ~E_12~0); 23659#L1383-1 assume !(0 == ~E_13~0); 23660#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24450#L607 assume 1 == ~m_pc~0; 24451#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23734#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24247#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24248#L1560 assume !(0 != activate_threads_~tmp~1#1); 24357#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23545#L626 assume !(1 == ~t1_pc~0); 23546#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23827#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23828#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24718#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 23453#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23454#L645 assume 1 == ~t2_pc~0; 23561#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23518#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23627#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23628#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 24331#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24332#L664 assume 1 == ~t3_pc~0; 25094#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23312#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23313#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23976#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 23977#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25010#L683 assume !(1 == ~t4_pc~0); 24561#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24515#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23336#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23337#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24668#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24271#L702 assume 1 == ~t5_pc~0; 24272#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24207#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24663#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25000#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 24908#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23348#L721 assume !(1 == ~t6_pc~0); 23329#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 23330#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23477#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23612#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 23992#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24608#L740 assume 1 == ~t7_pc~0; 23394#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23229#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23230#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23219#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 23220#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23916#L759 assume !(1 == ~t8_pc~0); 23917#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23948#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25054#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24793#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 24794#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25076#L778 assume 1 == ~t9_pc~0; 24966#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23377#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23682#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23255#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 23256#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23557#L797 assume !(1 == ~t10_pc~0); 23558#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23692#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24943#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24100#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 24101#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24402#L816 assume 1 == ~t11_pc~0; 23290#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23291#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24236#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23998#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 23999#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24543#L835 assume 1 == ~t12_pc~0; 24417#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23441#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23280#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23281#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 24156#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24157#L854 assume !(1 == ~t13_pc~0); 23772#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 23773#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23822#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23475#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23476#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24904#L1401 assume !(1 == ~M_E~0); 23985#L1401-2 assume !(1 == ~T1_E~0); 23986#L1406-1 assume !(1 == ~T2_E~0); 24597#L1411-1 assume !(1 == ~T3_E~0); 24598#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24246#L1421-1 assume !(1 == ~T5_E~0); 23768#L1426-1 assume !(1 == ~T6_E~0); 23769#L1431-1 assume !(1 == ~T7_E~0); 23327#L1436-1 assume !(1 == ~T8_E~0); 23328#L1441-1 assume !(1 == ~T9_E~0); 24093#L1446-1 assume !(1 == ~T10_E~0); 24094#L1451-1 assume !(1 == ~T11_E~0); 24812#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24470#L1461-1 assume !(1 == ~T13_E~0); 24014#L1466-1 assume !(1 == ~E_1~0); 24015#L1471-1 assume !(1 == ~E_2~0); 24791#L1476-1 assume !(1 == ~E_3~0); 24792#L1481-1 assume !(1 == ~E_4~0); 24949#L1486-1 assume !(1 == ~E_5~0); 23597#L1491-1 assume !(1 == ~E_6~0); 23265#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 23266#L1501-1 assume !(1 == ~E_8~0); 24089#L1506-1 assume !(1 == ~E_9~0); 24090#L1511-1 assume !(1 == ~E_10~0); 24044#L1516-1 assume !(1 == ~E_11~0); 23217#L1521-1 assume !(1 == ~E_12~0); 23218#L1526-1 assume !(1 == ~E_13~0); 23264#L1531-1 assume { :end_inline_reset_delta_events } true; 23794#L1892-2 [2024-11-13 13:49:11,884 INFO L747 eck$LassoCheckResult]: Loop: 23794#L1892-2 assume !false; 24857#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25110#L1233-1 assume !false; 25037#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24358#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24337#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24886#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23306#L1046 assume !(0 != eval_~tmp~0#1); 23308#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23839#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23840#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25093#L1258-5 assume !(0 == ~T1_E~0); 23465#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23466#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25085#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25089#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25090#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23697#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23698#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24854#L1298-3 assume !(0 == ~T9_E~0); 24855#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25017#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24853#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24342#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 23467#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23468#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24941#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23608#L1338-3 assume !(0 == ~E_4~0); 23609#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24768#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24946#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24947#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24287#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23829#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23830#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24628#L1378-3 assume !(0 == ~E_12~0); 24629#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24809#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24810#L607-42 assume 1 == ~m_pc~0; 24427#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24137#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23969#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23849#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23850#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24403#L626-42 assume 1 == ~t1_pc~0; 23940#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23941#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25041#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24826#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23500#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23501#L645-42 assume 1 == ~t2_pc~0; 25009#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24747#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24285#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23717#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23237#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23238#L664-42 assume 1 == ~t3_pc~0; 24050#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23754#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24687#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24575#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24576#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24739#L683-42 assume !(1 == ~t4_pc~0); 24453#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 24454#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24582#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24742#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25007#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24848#L702-42 assume !(1 == ~t5_pc~0); 23930#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 23931#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24239#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24352#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 23249#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23250#L721-42 assume 1 == ~t6_pc~0; 23389#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23410#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23588#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23589#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24070#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23904#L740-42 assume 1 == ~t7_pc~0; 23905#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23624#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24200#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24053#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24054#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24325#L759-42 assume 1 == ~t8_pc~0; 24176#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24110#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24111#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24185#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24186#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24276#L778-42 assume 1 == ~t9_pc~0; 24122#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24124#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24547#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24455#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24456#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24510#L797-42 assume !(1 == ~t10_pc~0); 23633#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 23632#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24528#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24529#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24548#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24549#L816-42 assume 1 == ~t11_pc~0; 23209#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23210#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25047#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24097#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23808#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23809#L835-42 assume !(1 == ~t12_pc~0); 24133#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 24134#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24328#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24329#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24907#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24685#L854-42 assume !(1 == ~t13_pc~0); 23729#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 23730#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 23896#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23897#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 24010#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24011#L1401-3 assume !(1 == ~M_E~0); 24802#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23560#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23436#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23437#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24060#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24061#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23602#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23603#L1436-3 assume !(1 == ~T8_E~0); 23221#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23222#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24830#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24148#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23776#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 23777#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25087#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23718#L1476-3 assume !(1 == ~E_3~0); 23719#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24142#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23746#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23747#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24182#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24183#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24624#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24612#L1516-3 assume !(1 == ~E_11~0); 24613#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24290#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 24291#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24706#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23535#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23582#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23583#L1911 assume !(0 == start_simulation_~tmp~3#1); 24114#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24645#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 23674#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 23259#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23260#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23383#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24146#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24960#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23794#L1892-2 [2024-11-13 13:49:11,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:11,884 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2024-11-13 13:49:11,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:11,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406717131] [2024-11-13 13:49:11,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:11,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:11,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:11,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:11,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:11,961 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406717131] [2024-11-13 13:49:11,961 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [406717131] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:11,961 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:11,961 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:11,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030228991] [2024-11-13 13:49:11,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:11,961 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:11,962 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:11,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1598885136, now seen corresponding path program 1 times [2024-11-13 13:49:11,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:11,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482753625] [2024-11-13 13:49:11,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:11,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:11,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:12,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:12,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:12,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482753625] [2024-11-13 13:49:12,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482753625] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:12,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:12,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:12,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1608876164] [2024-11-13 13:49:12,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:12,057 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:12,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:12,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:12,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:12,057 INFO L87 Difference]: Start difference. First operand 1928 states and 2844 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:12,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:12,108 INFO L93 Difference]: Finished difference Result 1928 states and 2843 transitions. [2024-11-13 13:49:12,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2843 transitions. [2024-11-13 13:49:12,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:12,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2843 transitions. [2024-11-13 13:49:12,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:12,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:12,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2843 transitions. [2024-11-13 13:49:12,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:12,134 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2024-11-13 13:49:12,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2843 transitions. [2024-11-13 13:49:12,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:12,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.474585062240664) internal successors, (2843), 1927 states have internal predecessors, (2843), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:12,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2843 transitions. [2024-11-13 13:49:12,172 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2024-11-13 13:49:12,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:12,174 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2843 transitions. [2024-11-13 13:49:12,174 INFO L331 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-13 13:49:12,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2843 transitions. [2024-11-13 13:49:12,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:12,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:12,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:12,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:12,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:12,186 INFO L745 eck$LassoCheckResult]: Stem: 27348#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27349#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28248#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28249#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28974#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28645#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28646#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27569#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27570#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28047#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27884#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27885#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27633#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27634#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28055#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28239#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28407#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28440#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27649#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27650#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28865#L1258-2 assume !(0 == ~T1_E~0); 27967#L1263-1 assume !(0 == ~T2_E~0); 27968#L1268-1 assume !(0 == ~T3_E~0); 28285#L1273-1 assume !(0 == ~T4_E~0); 28844#L1278-1 assume !(0 == ~T5_E~0); 28702#L1283-1 assume !(0 == ~T6_E~0); 28703#L1288-1 assume !(0 == ~T7_E~0); 28940#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28929#L1298-1 assume !(0 == ~T9_E~0); 28860#L1303-1 assume !(0 == ~T10_E~0); 27447#L1308-1 assume !(0 == ~T11_E~0); 27387#L1313-1 assume !(0 == ~T12_E~0); 27388#L1318-1 assume !(0 == ~T13_E~0); 27393#L1323-1 assume !(0 == ~E_1~0); 27394#L1328-1 assume !(0 == ~E_2~0); 27579#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28573#L1338-1 assume !(0 == ~E_4~0); 28574#L1343-1 assume !(0 == ~E_5~0); 28679#L1348-1 assume !(0 == ~E_6~0); 28959#L1353-1 assume !(0 == ~E_7~0); 28308#L1358-1 assume !(0 == ~E_8~0); 28309#L1363-1 assume !(0 == ~E_9~0); 28595#L1368-1 assume !(0 == ~E_10~0); 27241#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27242#L1378-1 assume !(0 == ~E_12~0); 27522#L1383-1 assume !(0 == ~E_13~0); 27523#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28313#L607 assume 1 == ~m_pc~0; 28314#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27597#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28110#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28111#L1560 assume !(0 != activate_threads_~tmp~1#1); 28220#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27408#L626 assume !(1 == ~t1_pc~0); 27409#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27690#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27691#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28581#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27316#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27317#L645 assume 1 == ~t2_pc~0; 27424#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27381#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27490#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27491#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 28194#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28195#L664 assume 1 == ~t3_pc~0; 28957#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27175#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27176#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27839#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27840#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28873#L683 assume !(1 == ~t4_pc~0); 28424#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28378#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27199#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27200#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28531#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28134#L702 assume 1 == ~t5_pc~0; 28135#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28070#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28526#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28863#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28771#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27211#L721 assume !(1 == ~t6_pc~0); 27192#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 27193#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27475#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27855#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28471#L740 assume 1 == ~t7_pc~0; 27257#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27092#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27093#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27082#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 27083#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27779#L759 assume !(1 == ~t8_pc~0); 27780#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27811#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28917#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28656#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28657#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28939#L778 assume 1 == ~t9_pc~0; 28829#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27240#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27545#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27118#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 27119#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27420#L797 assume !(1 == ~t10_pc~0); 27421#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27555#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28806#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27963#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27964#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28265#L816 assume 1 == ~t11_pc~0; 27153#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27154#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28099#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27861#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27862#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28406#L835 assume 1 == ~t12_pc~0; 28280#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27304#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27143#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27144#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 28019#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28020#L854 assume !(1 == ~t13_pc~0); 27635#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27636#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27685#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27338#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27339#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28767#L1401 assume !(1 == ~M_E~0); 27848#L1401-2 assume !(1 == ~T1_E~0); 27849#L1406-1 assume !(1 == ~T2_E~0); 28460#L1411-1 assume !(1 == ~T3_E~0); 28461#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28109#L1421-1 assume !(1 == ~T5_E~0); 27631#L1426-1 assume !(1 == ~T6_E~0); 27632#L1431-1 assume !(1 == ~T7_E~0); 27190#L1436-1 assume !(1 == ~T8_E~0); 27191#L1441-1 assume !(1 == ~T9_E~0); 27956#L1446-1 assume !(1 == ~T10_E~0); 27957#L1451-1 assume !(1 == ~T11_E~0); 28675#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28333#L1461-1 assume !(1 == ~T13_E~0); 27877#L1466-1 assume !(1 == ~E_1~0); 27878#L1471-1 assume !(1 == ~E_2~0); 28654#L1476-1 assume !(1 == ~E_3~0); 28655#L1481-1 assume !(1 == ~E_4~0); 28812#L1486-1 assume !(1 == ~E_5~0); 27460#L1491-1 assume !(1 == ~E_6~0); 27128#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27129#L1501-1 assume !(1 == ~E_8~0); 27952#L1506-1 assume !(1 == ~E_9~0); 27953#L1511-1 assume !(1 == ~E_10~0); 27907#L1516-1 assume !(1 == ~E_11~0); 27080#L1521-1 assume !(1 == ~E_12~0); 27081#L1526-1 assume !(1 == ~E_13~0); 27127#L1531-1 assume { :end_inline_reset_delta_events } true; 27657#L1892-2 [2024-11-13 13:49:12,186 INFO L747 eck$LassoCheckResult]: Loop: 27657#L1892-2 assume !false; 28720#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28973#L1233-1 assume !false; 28900#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28221#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28200#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28749#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27169#L1046 assume !(0 != eval_~tmp~0#1); 27171#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27702#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27703#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28956#L1258-5 assume !(0 == ~T1_E~0); 27328#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27329#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28948#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28952#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28953#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27560#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27561#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28717#L1298-3 assume !(0 == ~T9_E~0); 28718#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28880#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28716#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28205#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27330#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27331#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28804#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27471#L1338-3 assume !(0 == ~E_4~0); 27472#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28631#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28809#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28810#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28150#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27692#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27693#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28491#L1378-3 assume !(0 == ~E_12~0); 28492#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28672#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28673#L607-42 assume 1 == ~m_pc~0; 28290#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28000#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27832#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27712#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27713#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28266#L626-42 assume 1 == ~t1_pc~0; 27803#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27804#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28904#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28689#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27363#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27364#L645-42 assume !(1 == ~t2_pc~0); 28609#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 28610#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28148#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27580#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27100#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27101#L664-42 assume !(1 == ~t3_pc~0); 27616#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 27617#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28550#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28438#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28439#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28602#L683-42 assume 1 == ~t4_pc~0; 28965#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28317#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28445#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28605#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28870#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28711#L702-42 assume !(1 == ~t5_pc~0); 27793#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 27794#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28102#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28215#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 27112#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27113#L721-42 assume 1 == ~t6_pc~0; 27252#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27273#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27451#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27452#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27933#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27767#L740-42 assume 1 == ~t7_pc~0; 27768#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27487#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28063#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27916#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27917#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28188#L759-42 assume 1 == ~t8_pc~0; 28039#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27973#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27974#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28048#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28049#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28139#L778-42 assume 1 == ~t9_pc~0; 27985#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27987#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28410#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28318#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28319#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28373#L797-42 assume 1 == ~t10_pc~0; 27494#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27495#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28391#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28392#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28411#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28412#L816-42 assume 1 == ~t11_pc~0; 27072#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 27073#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28910#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27960#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27671#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27672#L835-42 assume 1 == ~t12_pc~0; 28098#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27997#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28191#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28192#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28770#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28548#L854-42 assume 1 == ~t13_pc~0; 28549#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27593#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27759#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27760#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27873#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27874#L1401-3 assume !(1 == ~M_E~0); 28665#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27423#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27299#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27300#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27923#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27924#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27465#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27466#L1436-3 assume !(1 == ~T8_E~0); 27084#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27085#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28693#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28011#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27639#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 27640#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28950#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27581#L1476-3 assume !(1 == ~E_3~0); 27582#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28005#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27609#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27610#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28045#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28046#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28487#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28475#L1516-3 assume !(1 == ~E_11~0); 28476#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28153#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 28154#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28569#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27398#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27445#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27446#L1911 assume !(0 == start_simulation_~tmp~3#1); 27977#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28508#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27537#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 27122#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27123#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27246#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28009#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28823#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27657#L1892-2 [2024-11-13 13:49:12,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:12,186 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2024-11-13 13:49:12,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:12,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1890496845] [2024-11-13 13:49:12,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:12,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:12,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:12,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:12,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:12,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1890496845] [2024-11-13 13:49:12,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1890496845] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:12,261 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:12,261 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:12,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64818473] [2024-11-13 13:49:12,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:12,262 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:12,262 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:12,262 INFO L85 PathProgramCache]: Analyzing trace with hash 935577170, now seen corresponding path program 1 times [2024-11-13 13:49:12,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:12,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639241100] [2024-11-13 13:49:12,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:12,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:12,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:12,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:12,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:12,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639241100] [2024-11-13 13:49:12,386 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [639241100] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:12,386 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:12,386 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:12,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261671282] [2024-11-13 13:49:12,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:12,386 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:12,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:12,387 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:12,387 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:12,387 INFO L87 Difference]: Start difference. First operand 1928 states and 2843 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:12,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:12,431 INFO L93 Difference]: Finished difference Result 1928 states and 2842 transitions. [2024-11-13 13:49:12,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2842 transitions. [2024-11-13 13:49:12,445 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:12,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2842 transitions. [2024-11-13 13:49:12,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:12,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:12,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2842 transitions. [2024-11-13 13:49:12,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:12,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2024-11-13 13:49:12,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2842 transitions. [2024-11-13 13:49:12,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:12,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4740663900414939) internal successors, (2842), 1927 states have internal predecessors, (2842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:12,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2842 transitions. [2024-11-13 13:49:12,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2024-11-13 13:49:12,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:12,497 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2842 transitions. [2024-11-13 13:49:12,497 INFO L331 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-13 13:49:12,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2842 transitions. [2024-11-13 13:49:12,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:12,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:12,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:12,508 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:12,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:12,509 INFO L745 eck$LassoCheckResult]: Stem: 31211#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 32111#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32112#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32837#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32508#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32509#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31432#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31433#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31910#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31747#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31748#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31496#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31497#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31918#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32102#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32270#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32303#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31512#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31513#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32728#L1258-2 assume !(0 == ~T1_E~0); 31830#L1263-1 assume !(0 == ~T2_E~0); 31831#L1268-1 assume !(0 == ~T3_E~0); 32148#L1273-1 assume !(0 == ~T4_E~0); 32707#L1278-1 assume !(0 == ~T5_E~0); 32565#L1283-1 assume !(0 == ~T6_E~0); 32566#L1288-1 assume !(0 == ~T7_E~0); 32803#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32792#L1298-1 assume !(0 == ~T9_E~0); 32723#L1303-1 assume !(0 == ~T10_E~0); 31310#L1308-1 assume !(0 == ~T11_E~0); 31250#L1313-1 assume !(0 == ~T12_E~0); 31251#L1318-1 assume !(0 == ~T13_E~0); 31256#L1323-1 assume !(0 == ~E_1~0); 31257#L1328-1 assume !(0 == ~E_2~0); 31442#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 32436#L1338-1 assume !(0 == ~E_4~0); 32437#L1343-1 assume !(0 == ~E_5~0); 32542#L1348-1 assume !(0 == ~E_6~0); 32822#L1353-1 assume !(0 == ~E_7~0); 32171#L1358-1 assume !(0 == ~E_8~0); 32172#L1363-1 assume !(0 == ~E_9~0); 32458#L1368-1 assume !(0 == ~E_10~0); 31104#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 31105#L1378-1 assume !(0 == ~E_12~0); 31385#L1383-1 assume !(0 == ~E_13~0); 31386#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32176#L607 assume 1 == ~m_pc~0; 32177#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31460#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31973#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31974#L1560 assume !(0 != activate_threads_~tmp~1#1); 32083#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31271#L626 assume !(1 == ~t1_pc~0); 31272#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31553#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31554#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32444#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 31179#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31180#L645 assume 1 == ~t2_pc~0; 31287#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31244#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31353#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31354#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 32057#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32058#L664 assume 1 == ~t3_pc~0; 32820#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31038#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31039#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31702#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 31703#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32736#L683 assume !(1 == ~t4_pc~0); 32287#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 32241#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31062#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31063#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32394#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31997#L702 assume 1 == ~t5_pc~0; 31998#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31933#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32389#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32726#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 32634#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31074#L721 assume !(1 == ~t6_pc~0); 31055#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31056#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31203#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31338#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 31718#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32334#L740 assume 1 == ~t7_pc~0; 31120#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30955#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30956#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30945#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 30946#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31642#L759 assume !(1 == ~t8_pc~0); 31643#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31674#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32780#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32519#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 32520#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32802#L778 assume 1 == ~t9_pc~0; 32692#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31103#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31408#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30981#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 30982#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31283#L797 assume !(1 == ~t10_pc~0); 31284#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31418#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32669#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31826#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 31827#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32128#L816 assume 1 == ~t11_pc~0; 31016#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31017#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31962#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31724#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 31725#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32269#L835 assume 1 == ~t12_pc~0; 32143#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31167#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31006#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31007#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 31882#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31883#L854 assume !(1 == ~t13_pc~0); 31498#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 31499#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31548#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31201#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31202#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32630#L1401 assume !(1 == ~M_E~0); 31711#L1401-2 assume !(1 == ~T1_E~0); 31712#L1406-1 assume !(1 == ~T2_E~0); 32323#L1411-1 assume !(1 == ~T3_E~0); 32324#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31972#L1421-1 assume !(1 == ~T5_E~0); 31494#L1426-1 assume !(1 == ~T6_E~0); 31495#L1431-1 assume !(1 == ~T7_E~0); 31053#L1436-1 assume !(1 == ~T8_E~0); 31054#L1441-1 assume !(1 == ~T9_E~0); 31819#L1446-1 assume !(1 == ~T10_E~0); 31820#L1451-1 assume !(1 == ~T11_E~0); 32538#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32196#L1461-1 assume !(1 == ~T13_E~0); 31740#L1466-1 assume !(1 == ~E_1~0); 31741#L1471-1 assume !(1 == ~E_2~0); 32517#L1476-1 assume !(1 == ~E_3~0); 32518#L1481-1 assume !(1 == ~E_4~0); 32675#L1486-1 assume !(1 == ~E_5~0); 31323#L1491-1 assume !(1 == ~E_6~0); 30991#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 30992#L1501-1 assume !(1 == ~E_8~0); 31815#L1506-1 assume !(1 == ~E_9~0); 31816#L1511-1 assume !(1 == ~E_10~0); 31770#L1516-1 assume !(1 == ~E_11~0); 30943#L1521-1 assume !(1 == ~E_12~0); 30944#L1526-1 assume !(1 == ~E_13~0); 30990#L1531-1 assume { :end_inline_reset_delta_events } true; 31520#L1892-2 [2024-11-13 13:49:12,509 INFO L747 eck$LassoCheckResult]: Loop: 31520#L1892-2 assume !false; 32583#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32836#L1233-1 assume !false; 32763#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32084#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32063#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32612#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31032#L1046 assume !(0 != eval_~tmp~0#1); 31034#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31565#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31566#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32819#L1258-5 assume !(0 == ~T1_E~0); 31191#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31192#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32811#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32815#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32816#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31423#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31424#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32580#L1298-3 assume !(0 == ~T9_E~0); 32581#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32743#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32579#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32068#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 31193#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31194#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32667#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31334#L1338-3 assume !(0 == ~E_4~0); 31335#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32494#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32672#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32673#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32013#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31555#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31556#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32354#L1378-3 assume !(0 == ~E_12~0); 32355#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32535#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32536#L607-42 assume 1 == ~m_pc~0; 32153#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31863#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31695#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31575#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31576#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32129#L626-42 assume 1 == ~t1_pc~0; 31666#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31667#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32767#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32552#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31226#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31227#L645-42 assume !(1 == ~t2_pc~0); 32472#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 32473#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32011#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31443#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30963#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30964#L664-42 assume 1 == ~t3_pc~0; 31776#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31480#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32413#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32301#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32302#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32465#L683-42 assume !(1 == ~t4_pc~0); 32179#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 32180#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32308#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32468#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32733#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32574#L702-42 assume !(1 == ~t5_pc~0); 31656#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 31657#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31965#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32078#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 30975#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30976#L721-42 assume 1 == ~t6_pc~0; 31115#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31136#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31314#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31315#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31796#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31630#L740-42 assume !(1 == ~t7_pc~0); 31349#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 31350#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31926#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31779#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31780#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32051#L759-42 assume 1 == ~t8_pc~0; 31902#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31836#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31837#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31911#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31912#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32002#L778-42 assume 1 == ~t9_pc~0; 31848#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31850#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32273#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32181#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32182#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32236#L797-42 assume 1 == ~t10_pc~0; 31357#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31358#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32254#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32255#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32274#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32275#L816-42 assume 1 == ~t11_pc~0; 30935#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30936#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32773#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31823#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31534#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31535#L835-42 assume !(1 == ~t12_pc~0); 31859#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 31860#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32054#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32055#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32633#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32411#L854-42 assume 1 == ~t13_pc~0; 32412#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 31456#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31622#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 31623#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31736#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31737#L1401-3 assume !(1 == ~M_E~0); 32528#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31286#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31162#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31163#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31786#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31787#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31328#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31329#L1436-3 assume !(1 == ~T8_E~0); 30947#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30948#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32556#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31874#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 31502#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 31503#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32813#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31444#L1476-3 assume !(1 == ~E_3~0); 31445#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31868#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31472#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31473#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31908#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31909#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32350#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32338#L1516-3 assume !(1 == ~E_11~0); 32339#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32016#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 32017#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32432#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31261#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31308#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 31309#L1911 assume !(0 == start_simulation_~tmp~3#1); 31840#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32371#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31400#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30985#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30986#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31109#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31872#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32686#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31520#L1892-2 [2024-11-13 13:49:12,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:12,510 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2024-11-13 13:49:12,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:12,510 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933085266] [2024-11-13 13:49:12,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:12,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:12,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:12,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:12,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:12,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933085266] [2024-11-13 13:49:12,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [933085266] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:12,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:12,575 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:12,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861246193] [2024-11-13 13:49:12,575 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:12,575 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:12,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:12,576 INFO L85 PathProgramCache]: Analyzing trace with hash 1219768208, now seen corresponding path program 1 times [2024-11-13 13:49:12,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:12,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982932243] [2024-11-13 13:49:12,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:12,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:12,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:12,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:12,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:12,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982932243] [2024-11-13 13:49:12,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982932243] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:12,665 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:12,665 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:12,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1978574949] [2024-11-13 13:49:12,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:12,665 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:12,666 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:12,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:12,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:12,666 INFO L87 Difference]: Start difference. First operand 1928 states and 2842 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:12,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:12,713 INFO L93 Difference]: Finished difference Result 1928 states and 2841 transitions. [2024-11-13 13:49:12,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2841 transitions. [2024-11-13 13:49:12,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:12,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2841 transitions. [2024-11-13 13:49:12,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:12,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:12,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2841 transitions. [2024-11-13 13:49:12,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:12,736 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2024-11-13 13:49:12,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2841 transitions. [2024-11-13 13:49:12,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:12,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4735477178423237) internal successors, (2841), 1927 states have internal predecessors, (2841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:12,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2841 transitions. [2024-11-13 13:49:12,771 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2024-11-13 13:49:12,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:12,773 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2841 transitions. [2024-11-13 13:49:12,773 INFO L331 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-13 13:49:12,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2841 transitions. [2024-11-13 13:49:12,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:12,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:12,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:12,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:12,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:12,785 INFO L745 eck$LassoCheckResult]: Stem: 35074#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35075#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35974#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35975#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36700#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36371#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36372#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35295#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35296#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35773#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35610#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35611#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35359#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35360#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35781#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35965#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36133#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36166#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35375#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35376#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36591#L1258-2 assume !(0 == ~T1_E~0); 35693#L1263-1 assume !(0 == ~T2_E~0); 35694#L1268-1 assume !(0 == ~T3_E~0); 36011#L1273-1 assume !(0 == ~T4_E~0); 36570#L1278-1 assume !(0 == ~T5_E~0); 36428#L1283-1 assume !(0 == ~T6_E~0); 36429#L1288-1 assume !(0 == ~T7_E~0); 36666#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36655#L1298-1 assume !(0 == ~T9_E~0); 36586#L1303-1 assume !(0 == ~T10_E~0); 35173#L1308-1 assume !(0 == ~T11_E~0); 35113#L1313-1 assume !(0 == ~T12_E~0); 35114#L1318-1 assume !(0 == ~T13_E~0); 35119#L1323-1 assume !(0 == ~E_1~0); 35120#L1328-1 assume !(0 == ~E_2~0); 35305#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36299#L1338-1 assume !(0 == ~E_4~0); 36300#L1343-1 assume !(0 == ~E_5~0); 36405#L1348-1 assume !(0 == ~E_6~0); 36685#L1353-1 assume !(0 == ~E_7~0); 36034#L1358-1 assume !(0 == ~E_8~0); 36035#L1363-1 assume !(0 == ~E_9~0); 36321#L1368-1 assume !(0 == ~E_10~0); 34967#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34968#L1378-1 assume !(0 == ~E_12~0); 35248#L1383-1 assume !(0 == ~E_13~0); 35249#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36039#L607 assume 1 == ~m_pc~0; 36040#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35323#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35836#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35837#L1560 assume !(0 != activate_threads_~tmp~1#1); 35946#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35134#L626 assume !(1 == ~t1_pc~0); 35135#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35416#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35417#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36307#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 35042#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35043#L645 assume 1 == ~t2_pc~0; 35150#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35107#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35216#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35217#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35920#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35921#L664 assume 1 == ~t3_pc~0; 36683#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34901#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34902#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35565#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35566#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36599#L683 assume !(1 == ~t4_pc~0); 36150#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 36104#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34925#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34926#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36257#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35860#L702 assume 1 == ~t5_pc~0; 35861#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35796#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36252#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36589#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36497#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34937#L721 assume !(1 == ~t6_pc~0); 34918#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34919#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35066#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35201#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35581#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36197#L740 assume 1 == ~t7_pc~0; 34983#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34818#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34819#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34808#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34809#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35505#L759 assume !(1 == ~t8_pc~0); 35506#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35537#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36643#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36382#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36383#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36665#L778 assume 1 == ~t9_pc~0; 36555#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34966#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35271#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34844#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34845#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35146#L797 assume !(1 == ~t10_pc~0); 35147#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35281#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36532#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35689#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35690#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35991#L816 assume 1 == ~t11_pc~0; 34879#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34880#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35825#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35587#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35588#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36132#L835 assume 1 == ~t12_pc~0; 36006#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35030#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34869#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34870#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35745#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35746#L854 assume !(1 == ~t13_pc~0); 35361#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35362#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35411#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35064#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35065#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36493#L1401 assume !(1 == ~M_E~0); 35574#L1401-2 assume !(1 == ~T1_E~0); 35575#L1406-1 assume !(1 == ~T2_E~0); 36186#L1411-1 assume !(1 == ~T3_E~0); 36187#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35835#L1421-1 assume !(1 == ~T5_E~0); 35357#L1426-1 assume !(1 == ~T6_E~0); 35358#L1431-1 assume !(1 == ~T7_E~0); 34916#L1436-1 assume !(1 == ~T8_E~0); 34917#L1441-1 assume !(1 == ~T9_E~0); 35682#L1446-1 assume !(1 == ~T10_E~0); 35683#L1451-1 assume !(1 == ~T11_E~0); 36401#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36059#L1461-1 assume !(1 == ~T13_E~0); 35603#L1466-1 assume !(1 == ~E_1~0); 35604#L1471-1 assume !(1 == ~E_2~0); 36380#L1476-1 assume !(1 == ~E_3~0); 36381#L1481-1 assume !(1 == ~E_4~0); 36538#L1486-1 assume !(1 == ~E_5~0); 35186#L1491-1 assume !(1 == ~E_6~0); 34854#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34855#L1501-1 assume !(1 == ~E_8~0); 35678#L1506-1 assume !(1 == ~E_9~0); 35679#L1511-1 assume !(1 == ~E_10~0); 35633#L1516-1 assume !(1 == ~E_11~0); 34806#L1521-1 assume !(1 == ~E_12~0); 34807#L1526-1 assume !(1 == ~E_13~0); 34853#L1531-1 assume { :end_inline_reset_delta_events } true; 35383#L1892-2 [2024-11-13 13:49:12,786 INFO L747 eck$LassoCheckResult]: Loop: 35383#L1892-2 assume !false; 36446#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36699#L1233-1 assume !false; 36626#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35947#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35926#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36475#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34895#L1046 assume !(0 != eval_~tmp~0#1); 34897#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35429#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36682#L1258-5 assume !(0 == ~T1_E~0); 35054#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35055#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36674#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36678#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36679#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35286#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35287#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36443#L1298-3 assume !(0 == ~T9_E~0); 36444#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36606#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36442#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35931#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 35056#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35057#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36530#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35197#L1338-3 assume !(0 == ~E_4~0); 35198#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36357#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36535#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36536#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35876#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35418#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35419#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36217#L1378-3 assume !(0 == ~E_12~0); 36218#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36398#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36399#L607-42 assume 1 == ~m_pc~0; 36016#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35726#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35558#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35438#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35439#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35992#L626-42 assume 1 == ~t1_pc~0; 35529#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35530#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36630#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36415#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35089#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35090#L645-42 assume 1 == ~t2_pc~0; 36598#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36336#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35874#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35306#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34826#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34827#L664-42 assume 1 == ~t3_pc~0; 35639#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35343#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36276#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36164#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36165#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36328#L683-42 assume 1 == ~t4_pc~0; 36691#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36043#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36171#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36331#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36596#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36437#L702-42 assume 1 == ~t5_pc~0; 35908#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35520#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35828#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35941#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 34838#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34839#L721-42 assume 1 == ~t6_pc~0; 34978#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34999#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35177#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35178#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35659#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35493#L740-42 assume 1 == ~t7_pc~0; 35494#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35213#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35789#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35642#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35643#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35914#L759-42 assume 1 == ~t8_pc~0; 35765#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35699#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35700#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35774#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35775#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35865#L778-42 assume !(1 == ~t9_pc~0); 35712#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 35713#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36136#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36044#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36045#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36099#L797-42 assume 1 == ~t10_pc~0; 35220#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35221#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36117#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36118#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36137#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36138#L816-42 assume !(1 == ~t11_pc~0); 34800#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 34799#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36636#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35686#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35397#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35398#L835-42 assume 1 == ~t12_pc~0; 35824#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35723#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35917#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35918#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36496#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36274#L854-42 assume 1 == ~t13_pc~0; 36275#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35319#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35485#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35486#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35599#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35600#L1401-3 assume !(1 == ~M_E~0); 36391#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35149#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35025#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35026#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35649#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35650#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35191#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35192#L1436-3 assume !(1 == ~T8_E~0); 34810#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34811#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36419#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35737#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35365#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 35366#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36676#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35307#L1476-3 assume !(1 == ~E_3~0); 35308#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35731#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35335#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35336#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35771#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35772#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36213#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36201#L1516-3 assume !(1 == ~E_11~0); 36202#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35879#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35880#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36295#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35124#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35171#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35172#L1911 assume !(0 == start_simulation_~tmp~3#1); 35703#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36234#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35263#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34848#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34849#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34972#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35735#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36549#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35383#L1892-2 [2024-11-13 13:49:12,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:12,786 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2024-11-13 13:49:12,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:12,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377702431] [2024-11-13 13:49:12,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:12,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:12,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:12,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:12,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:12,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1377702431] [2024-11-13 13:49:12,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1377702431] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:12,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:12,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:12,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389806482] [2024-11-13 13:49:12,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:12,872 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:12,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:12,873 INFO L85 PathProgramCache]: Analyzing trace with hash -896257357, now seen corresponding path program 1 times [2024-11-13 13:49:12,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:12,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634218086] [2024-11-13 13:49:12,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:12,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:12,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:12,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:12,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:12,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634218086] [2024-11-13 13:49:12,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [634218086] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:12,952 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:12,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:12,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871325211] [2024-11-13 13:49:12,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:12,953 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:12,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:12,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:12,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:12,953 INFO L87 Difference]: Start difference. First operand 1928 states and 2841 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:12,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:12,997 INFO L93 Difference]: Finished difference Result 1928 states and 2840 transitions. [2024-11-13 13:49:12,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2840 transitions. [2024-11-13 13:49:13,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:13,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2840 transitions. [2024-11-13 13:49:13,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:13,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:13,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2840 transitions. [2024-11-13 13:49:13,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:13,025 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2024-11-13 13:49:13,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2840 transitions. [2024-11-13 13:49:13,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:13,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4730290456431536) internal successors, (2840), 1927 states have internal predecessors, (2840), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:13,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2840 transitions. [2024-11-13 13:49:13,067 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2024-11-13 13:49:13,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:13,068 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2840 transitions. [2024-11-13 13:49:13,068 INFO L331 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-13 13:49:13,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2840 transitions. [2024-11-13 13:49:13,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:13,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:13,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:13,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:13,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:13,080 INFO L745 eck$LassoCheckResult]: Stem: 38937#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 38938#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39838#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39839#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40563#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 40234#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40235#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39158#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39159#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39638#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39473#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39474#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39222#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39223#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39644#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39828#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39996#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40030#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 39238#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39239#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40454#L1258-2 assume !(0 == ~T1_E~0); 39556#L1263-1 assume !(0 == ~T2_E~0); 39557#L1268-1 assume !(0 == ~T3_E~0); 39874#L1273-1 assume !(0 == ~T4_E~0); 40433#L1278-1 assume !(0 == ~T5_E~0); 40291#L1283-1 assume !(0 == ~T6_E~0); 40292#L1288-1 assume !(0 == ~T7_E~0); 40530#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40518#L1298-1 assume !(0 == ~T9_E~0); 40449#L1303-1 assume !(0 == ~T10_E~0); 39036#L1308-1 assume !(0 == ~T11_E~0); 38979#L1313-1 assume !(0 == ~T12_E~0); 38980#L1318-1 assume !(0 == ~T13_E~0); 38984#L1323-1 assume !(0 == ~E_1~0); 38985#L1328-1 assume !(0 == ~E_2~0); 39168#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 40162#L1338-1 assume !(0 == ~E_4~0); 40163#L1343-1 assume !(0 == ~E_5~0); 40268#L1348-1 assume !(0 == ~E_6~0); 40548#L1353-1 assume !(0 == ~E_7~0); 39897#L1358-1 assume !(0 == ~E_8~0); 39898#L1363-1 assume !(0 == ~E_9~0); 40184#L1368-1 assume !(0 == ~E_10~0); 38830#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 38831#L1378-1 assume !(0 == ~E_12~0); 39113#L1383-1 assume !(0 == ~E_13~0); 39114#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39902#L607 assume 1 == ~m_pc~0; 39903#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39188#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39702#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39703#L1560 assume !(0 != activate_threads_~tmp~1#1); 39809#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38997#L626 assume !(1 == ~t1_pc~0); 38998#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39281#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40170#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 38906#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38907#L645 assume 1 == ~t2_pc~0; 39015#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38970#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39082#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 39783#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39784#L664 assume 1 == ~t3_pc~0; 40546#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38768#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38769#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39428#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 39429#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40462#L683 assume !(1 == ~t4_pc~0); 40013#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39967#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38788#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38789#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40120#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39727#L702 assume 1 == ~t5_pc~0; 39728#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39660#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40115#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40452#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 40361#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38804#L721 assume !(1 == ~t6_pc~0); 38781#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38782#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38929#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39064#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 39444#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40060#L740 assume 1 == ~t7_pc~0; 38846#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38681#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38682#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38671#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 38672#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39369#L759 assume !(1 == ~t8_pc~0); 39370#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39400#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40509#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40245#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 40246#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40528#L778 assume 1 == ~t9_pc~0; 40420#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38829#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39134#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38707#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 38708#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39010#L797 assume !(1 == ~t10_pc~0); 39011#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39144#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40395#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39552#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 39553#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39854#L816 assume 1 == ~t11_pc~0; 38744#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38745#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39690#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39450#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 39451#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39995#L835 assume 1 == ~t12_pc~0; 39869#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38893#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38732#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38733#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 39608#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39609#L854 assume !(1 == ~t13_pc~0); 39224#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 39225#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39276#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38927#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38928#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40356#L1401 assume !(1 == ~M_E~0); 39437#L1401-2 assume !(1 == ~T1_E~0); 39438#L1406-1 assume !(1 == ~T2_E~0); 40049#L1411-1 assume !(1 == ~T3_E~0); 40050#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39698#L1421-1 assume !(1 == ~T5_E~0); 39220#L1426-1 assume !(1 == ~T6_E~0); 39221#L1431-1 assume !(1 == ~T7_E~0); 38779#L1436-1 assume !(1 == ~T8_E~0); 38780#L1441-1 assume !(1 == ~T9_E~0); 39545#L1446-1 assume !(1 == ~T10_E~0); 39546#L1451-1 assume !(1 == ~T11_E~0); 40264#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39922#L1461-1 assume !(1 == ~T13_E~0); 39466#L1466-1 assume !(1 == ~E_1~0); 39467#L1471-1 assume !(1 == ~E_2~0); 40243#L1476-1 assume !(1 == ~E_3~0); 40244#L1481-1 assume !(1 == ~E_4~0); 40401#L1486-1 assume !(1 == ~E_5~0); 39049#L1491-1 assume !(1 == ~E_6~0); 38717#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38718#L1501-1 assume !(1 == ~E_8~0); 39541#L1506-1 assume !(1 == ~E_9~0); 39542#L1511-1 assume !(1 == ~E_10~0); 39496#L1516-1 assume !(1 == ~E_11~0); 38669#L1521-1 assume !(1 == ~E_12~0); 38670#L1526-1 assume !(1 == ~E_13~0); 38716#L1531-1 assume { :end_inline_reset_delta_events } true; 39246#L1892-2 [2024-11-13 13:49:13,081 INFO L747 eck$LassoCheckResult]: Loop: 39246#L1892-2 assume !false; 40309#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40562#L1233-1 assume !false; 40489#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39810#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39789#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40338#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38758#L1046 assume !(0 != eval_~tmp~0#1); 38760#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39291#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39292#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40545#L1258-5 assume !(0 == ~T1_E~0); 38917#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38918#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40537#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40541#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40542#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39149#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39150#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40306#L1298-3 assume !(0 == ~T9_E~0); 40307#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40469#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40305#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 39794#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38919#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38920#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40393#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39060#L1338-3 assume !(0 == ~E_4~0); 39061#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40220#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 40398#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 40399#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39739#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39279#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39280#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40080#L1378-3 assume !(0 == ~E_12~0); 40081#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 40261#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40262#L607-42 assume 1 == ~m_pc~0; 39879#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39589#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39421#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39301#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39302#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39855#L626-42 assume 1 == ~t1_pc~0; 39392#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39393#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40493#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40278#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38952#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38953#L645-42 assume !(1 == ~t2_pc~0); 40198#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 40199#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39737#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39169#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38689#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38690#L664-42 assume !(1 == ~t3_pc~0); 39205#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 39206#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40139#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40027#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40028#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40191#L683-42 assume !(1 == ~t4_pc~0); 39905#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 39906#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40034#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40194#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40459#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40300#L702-42 assume !(1 == ~t5_pc~0); 39382#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 39383#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39691#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39804#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 38701#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38702#L721-42 assume 1 == ~t6_pc~0; 38841#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38862#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39040#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39041#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39522#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39356#L740-42 assume !(1 == ~t7_pc~0); 39075#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 39076#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39652#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39505#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39506#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39777#L759-42 assume 1 == ~t8_pc~0; 39628#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39562#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39563#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39636#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39637#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39726#L778-42 assume 1 == ~t9_pc~0; 39574#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39576#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39999#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39907#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39908#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39962#L797-42 assume 1 == ~t10_pc~0; 39083#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39084#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39980#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39981#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40000#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40001#L816-42 assume 1 == ~t11_pc~0; 38661#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38662#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40499#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39549#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39260#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39261#L835-42 assume !(1 == ~t12_pc~0); 39585#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 39586#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39780#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39781#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40359#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 40137#L854-42 assume 1 == ~t13_pc~0; 40138#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 39182#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39348#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39349#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 39462#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39463#L1401-3 assume !(1 == ~M_E~0); 40254#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39009#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38888#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38889#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39512#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39513#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39054#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39055#L1436-3 assume !(1 == ~T8_E~0); 38673#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38674#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40282#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39600#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39228#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 39229#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40539#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39170#L1476-3 assume !(1 == ~E_3~0); 39171#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39594#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39198#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39199#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39634#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39635#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40076#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40064#L1516-3 assume !(1 == ~E_11~0); 40065#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 39742#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 39743#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40158#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 38987#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39034#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 39035#L1911 assume !(0 == start_simulation_~tmp~3#1); 39566#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40097#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39126#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38712#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38835#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39598#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40412#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 39246#L1892-2 [2024-11-13 13:49:13,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:13,081 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2024-11-13 13:49:13,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:13,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158142817] [2024-11-13 13:49:13,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:13,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:13,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:13,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:13,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:13,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158142817] [2024-11-13 13:49:13,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158142817] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:13,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:13,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:13,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1117407167] [2024-11-13 13:49:13,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:13,150 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:13,150 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:13,150 INFO L85 PathProgramCache]: Analyzing trace with hash 1541090671, now seen corresponding path program 2 times [2024-11-13 13:49:13,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:13,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585631963] [2024-11-13 13:49:13,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:13,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:13,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:13,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:13,256 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:13,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585631963] [2024-11-13 13:49:13,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585631963] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:13,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:13,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:13,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199230824] [2024-11-13 13:49:13,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:13,257 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:13,257 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:13,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:13,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:13,259 INFO L87 Difference]: Start difference. First operand 1928 states and 2840 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:13,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:13,310 INFO L93 Difference]: Finished difference Result 1928 states and 2839 transitions. [2024-11-13 13:49:13,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2839 transitions. [2024-11-13 13:49:13,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:13,335 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2839 transitions. [2024-11-13 13:49:13,335 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:13,337 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:13,337 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2839 transitions. [2024-11-13 13:49:13,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:13,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2024-11-13 13:49:13,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2839 transitions. [2024-11-13 13:49:13,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:13,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4725103734439835) internal successors, (2839), 1927 states have internal predecessors, (2839), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:13,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2839 transitions. [2024-11-13 13:49:13,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2024-11-13 13:49:13,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:13,433 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2839 transitions. [2024-11-13 13:49:13,433 INFO L331 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-13 13:49:13,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2839 transitions. [2024-11-13 13:49:13,443 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:13,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:13,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:13,449 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:13,449 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:13,450 INFO L745 eck$LassoCheckResult]: Stem: 42800#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 42801#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 43701#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43702#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44426#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 44097#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44098#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43021#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43022#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43501#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43336#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43337#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43085#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43086#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43507#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43691#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43859#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43893#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 43101#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43102#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 44317#L1258-2 assume !(0 == ~T1_E~0); 43419#L1263-1 assume !(0 == ~T2_E~0); 43420#L1268-1 assume !(0 == ~T3_E~0); 43737#L1273-1 assume !(0 == ~T4_E~0); 44296#L1278-1 assume !(0 == ~T5_E~0); 44154#L1283-1 assume !(0 == ~T6_E~0); 44155#L1288-1 assume !(0 == ~T7_E~0); 44393#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44381#L1298-1 assume !(0 == ~T9_E~0); 44312#L1303-1 assume !(0 == ~T10_E~0); 42899#L1308-1 assume !(0 == ~T11_E~0); 42839#L1313-1 assume !(0 == ~T12_E~0); 42840#L1318-1 assume !(0 == ~T13_E~0); 42847#L1323-1 assume !(0 == ~E_1~0); 42848#L1328-1 assume !(0 == ~E_2~0); 43031#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 44025#L1338-1 assume !(0 == ~E_4~0); 44026#L1343-1 assume !(0 == ~E_5~0); 44131#L1348-1 assume !(0 == ~E_6~0); 44411#L1353-1 assume !(0 == ~E_7~0); 43760#L1358-1 assume !(0 == ~E_8~0); 43761#L1363-1 assume !(0 == ~E_9~0); 44047#L1368-1 assume !(0 == ~E_10~0); 42693#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42694#L1378-1 assume !(0 == ~E_12~0); 42976#L1383-1 assume !(0 == ~E_13~0); 42977#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43765#L607 assume 1 == ~m_pc~0; 43766#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43051#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43565#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43566#L1560 assume !(0 != activate_threads_~tmp~1#1); 43672#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42860#L626 assume !(1 == ~t1_pc~0); 42861#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43144#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43145#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44033#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42769#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42770#L645 assume 1 == ~t2_pc~0; 42878#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42833#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42945#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43646#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43647#L664 assume 1 == ~t3_pc~0; 44409#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42631#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42632#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43291#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 43292#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44325#L683 assume !(1 == ~t4_pc~0); 43876#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43830#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42651#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42652#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43983#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43590#L702 assume 1 == ~t5_pc~0; 43591#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43523#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44315#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 44224#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42667#L721 assume !(1 == ~t6_pc~0); 42644#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42645#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42792#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42927#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 43307#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43923#L740 assume 1 == ~t7_pc~0; 42709#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42544#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42545#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42534#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42535#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43232#L759 assume !(1 == ~t8_pc~0); 43233#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43263#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44371#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44108#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 44109#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44391#L778 assume 1 == ~t9_pc~0; 44283#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42692#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42997#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42570#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42571#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42873#L797 assume !(1 == ~t10_pc~0); 42874#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43007#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44258#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43415#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43416#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43717#L816 assume 1 == ~t11_pc~0; 42607#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42608#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43553#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43313#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 43314#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43858#L835 assume 1 == ~t12_pc~0; 43732#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42756#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42595#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42596#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43471#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43472#L854 assume !(1 == ~t13_pc~0); 43087#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 43088#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43139#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42790#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42791#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44219#L1401 assume !(1 == ~M_E~0); 43300#L1401-2 assume !(1 == ~T1_E~0); 43301#L1406-1 assume !(1 == ~T2_E~0); 43912#L1411-1 assume !(1 == ~T3_E~0); 43913#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43561#L1421-1 assume !(1 == ~T5_E~0); 43083#L1426-1 assume !(1 == ~T6_E~0); 43084#L1431-1 assume !(1 == ~T7_E~0); 42642#L1436-1 assume !(1 == ~T8_E~0); 42643#L1441-1 assume !(1 == ~T9_E~0); 43410#L1446-1 assume !(1 == ~T10_E~0); 43411#L1451-1 assume !(1 == ~T11_E~0); 44127#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43785#L1461-1 assume !(1 == ~T13_E~0); 43329#L1466-1 assume !(1 == ~E_1~0); 43330#L1471-1 assume !(1 == ~E_2~0); 44106#L1476-1 assume !(1 == ~E_3~0); 44107#L1481-1 assume !(1 == ~E_4~0); 44264#L1486-1 assume !(1 == ~E_5~0); 42912#L1491-1 assume !(1 == ~E_6~0); 42580#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42581#L1501-1 assume !(1 == ~E_8~0); 43404#L1506-1 assume !(1 == ~E_9~0); 43405#L1511-1 assume !(1 == ~E_10~0); 43359#L1516-1 assume !(1 == ~E_11~0); 42532#L1521-1 assume !(1 == ~E_12~0); 42533#L1526-1 assume !(1 == ~E_13~0); 42579#L1531-1 assume { :end_inline_reset_delta_events } true; 43109#L1892-2 [2024-11-13 13:49:13,450 INFO L747 eck$LassoCheckResult]: Loop: 43109#L1892-2 assume !false; 44172#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44425#L1233-1 assume !false; 44352#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43673#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43652#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44201#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42621#L1046 assume !(0 != eval_~tmp~0#1); 42623#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43155#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43156#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44408#L1258-5 assume !(0 == ~T1_E~0); 42784#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42785#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44400#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44404#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44405#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43012#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43013#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44169#L1298-3 assume !(0 == ~T9_E~0); 44170#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44332#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44168#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43657#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42780#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42781#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44256#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42921#L1338-3 assume !(0 == ~E_4~0); 42922#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44083#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44261#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44262#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43602#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43142#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43143#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43943#L1378-3 assume !(0 == ~E_12~0); 43944#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 44124#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44125#L607-42 assume 1 == ~m_pc~0; 43742#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43452#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43284#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43164#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43165#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43718#L626-42 assume 1 == ~t1_pc~0; 43255#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43256#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44356#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44141#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42813#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42814#L645-42 assume 1 == ~t2_pc~0; 44324#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44062#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43600#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43032#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42552#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42553#L664-42 assume 1 == ~t3_pc~0; 43365#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43069#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44002#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43890#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43891#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44054#L683-42 assume 1 == ~t4_pc~0; 44417#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43769#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43897#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44057#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44322#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44163#L702-42 assume 1 == ~t5_pc~0; 43634#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43246#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43554#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43667#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 42564#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42565#L721-42 assume 1 == ~t6_pc~0; 42704#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42725#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42903#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42904#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43385#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43219#L740-42 assume 1 == ~t7_pc~0; 43220#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42939#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43515#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43368#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43369#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43640#L759-42 assume 1 == ~t8_pc~0; 43491#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43425#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43426#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43499#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43500#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43589#L778-42 assume 1 == ~t9_pc~0; 43437#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43439#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43862#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43770#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43771#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43825#L797-42 assume 1 == ~t10_pc~0; 42946#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42947#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43843#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43844#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43863#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43864#L816-42 assume 1 == ~t11_pc~0; 42524#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42525#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44362#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43412#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43123#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43124#L835-42 assume !(1 == ~t12_pc~0); 43448#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 43449#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43642#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43643#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44222#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 44000#L854-42 assume 1 == ~t13_pc~0; 44001#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 43043#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43211#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43212#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 43325#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43326#L1401-3 assume !(1 == ~M_E~0); 44117#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42872#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42751#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42752#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43375#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43376#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42917#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42918#L1436-3 assume !(1 == ~T8_E~0); 42536#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42537#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44145#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43463#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43091#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 43092#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44402#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43033#L1476-3 assume !(1 == ~E_3~0); 43034#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43457#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43061#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43062#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43497#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 43498#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43939#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43927#L1516-3 assume !(1 == ~E_11~0); 43928#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43605#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43606#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44021#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42850#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42897#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 42898#L1911 assume !(0 == start_simulation_~tmp~3#1); 43429#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43960#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42989#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42574#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42575#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42698#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43461#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 44275#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 43109#L1892-2 [2024-11-13 13:49:13,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:13,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2024-11-13 13:49:13,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:13,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672205097] [2024-11-13 13:49:13,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:13,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:13,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:13,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:13,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:13,547 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672205097] [2024-11-13 13:49:13,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672205097] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:13,548 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:13,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:13,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100126215] [2024-11-13 13:49:13,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:13,548 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:13,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:13,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1362934636, now seen corresponding path program 1 times [2024-11-13 13:49:13,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:13,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572492653] [2024-11-13 13:49:13,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:13,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:13,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:13,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:13,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:13,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572492653] [2024-11-13 13:49:13,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572492653] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:13,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:13,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:13,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078917428] [2024-11-13 13:49:13,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:13,674 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:13,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:13,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:13,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:13,675 INFO L87 Difference]: Start difference. First operand 1928 states and 2839 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:13,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:13,749 INFO L93 Difference]: Finished difference Result 1928 states and 2838 transitions. [2024-11-13 13:49:13,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2838 transitions. [2024-11-13 13:49:13,766 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:13,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2838 transitions. [2024-11-13 13:49:13,779 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:13,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:13,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2838 transitions. [2024-11-13 13:49:13,786 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:13,786 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2024-11-13 13:49:13,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2838 transitions. [2024-11-13 13:49:13,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:13,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4719917012448134) internal successors, (2838), 1927 states have internal predecessors, (2838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:13,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2838 transitions. [2024-11-13 13:49:13,847 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2024-11-13 13:49:13,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:13,848 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2838 transitions. [2024-11-13 13:49:13,848 INFO L331 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-13 13:49:13,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2838 transitions. [2024-11-13 13:49:13,862 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:13,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:13,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:13,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:13,867 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:13,867 INFO L745 eck$LassoCheckResult]: Stem: 46663#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46664#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 47563#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48289#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 47960#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47961#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46884#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46885#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47364#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47199#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 47200#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46948#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46949#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47370#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47554#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 47722#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 47755#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46964#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46965#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 48180#L1258-2 assume !(0 == ~T1_E~0); 47282#L1263-1 assume !(0 == ~T2_E~0); 47283#L1268-1 assume !(0 == ~T3_E~0); 47600#L1273-1 assume !(0 == ~T4_E~0); 48159#L1278-1 assume !(0 == ~T5_E~0); 48017#L1283-1 assume !(0 == ~T6_E~0); 48018#L1288-1 assume !(0 == ~T7_E~0); 48256#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48244#L1298-1 assume !(0 == ~T9_E~0); 48175#L1303-1 assume !(0 == ~T10_E~0); 46762#L1308-1 assume !(0 == ~T11_E~0); 46702#L1313-1 assume !(0 == ~T12_E~0); 46703#L1318-1 assume !(0 == ~T13_E~0); 46710#L1323-1 assume !(0 == ~E_1~0); 46711#L1328-1 assume !(0 == ~E_2~0); 46894#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 47888#L1338-1 assume !(0 == ~E_4~0); 47889#L1343-1 assume !(0 == ~E_5~0); 47994#L1348-1 assume !(0 == ~E_6~0); 48274#L1353-1 assume !(0 == ~E_7~0); 47623#L1358-1 assume !(0 == ~E_8~0); 47624#L1363-1 assume !(0 == ~E_9~0); 47910#L1368-1 assume !(0 == ~E_10~0); 46556#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 46557#L1378-1 assume !(0 == ~E_12~0); 46839#L1383-1 assume !(0 == ~E_13~0); 46840#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47628#L607 assume 1 == ~m_pc~0; 47629#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 46912#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47428#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47429#L1560 assume !(0 != activate_threads_~tmp~1#1); 47535#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46723#L626 assume !(1 == ~t1_pc~0); 46724#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47005#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47006#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47896#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 46631#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46632#L645 assume 1 == ~t2_pc~0; 46741#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46696#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46807#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46808#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 47509#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47510#L664 assume 1 == ~t3_pc~0; 48272#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46494#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46495#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47154#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 47155#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48188#L683 assume !(1 == ~t4_pc~0); 47739#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47693#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46514#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46515#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47846#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47453#L702 assume 1 == ~t5_pc~0; 47454#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47386#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47841#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48178#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 48087#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46530#L721 assume !(1 == ~t6_pc~0); 46507#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46508#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46655#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46790#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 47170#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47786#L740 assume 1 == ~t7_pc~0; 46572#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46407#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46408#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46397#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 46398#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47095#L759 assume !(1 == ~t8_pc~0); 47096#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47126#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48234#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47971#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 47972#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48254#L778 assume 1 == ~t9_pc~0; 48144#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46555#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46860#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46433#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 46434#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46736#L797 assume !(1 == ~t10_pc~0); 46737#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46870#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48121#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47278#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 47279#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47580#L816 assume 1 == ~t11_pc~0; 46470#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46471#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47416#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47176#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 47177#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47721#L835 assume 1 == ~t12_pc~0; 47595#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46619#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46458#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46459#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 47334#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47335#L854 assume !(1 == ~t13_pc~0); 46950#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 46951#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 47002#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46653#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46654#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48082#L1401 assume !(1 == ~M_E~0); 47163#L1401-2 assume !(1 == ~T1_E~0); 47164#L1406-1 assume !(1 == ~T2_E~0); 47775#L1411-1 assume !(1 == ~T3_E~0); 47776#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47424#L1421-1 assume !(1 == ~T5_E~0); 46946#L1426-1 assume !(1 == ~T6_E~0); 46947#L1431-1 assume !(1 == ~T7_E~0); 46505#L1436-1 assume !(1 == ~T8_E~0); 46506#L1441-1 assume !(1 == ~T9_E~0); 47273#L1446-1 assume !(1 == ~T10_E~0); 47274#L1451-1 assume !(1 == ~T11_E~0); 47990#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47648#L1461-1 assume !(1 == ~T13_E~0); 47192#L1466-1 assume !(1 == ~E_1~0); 47193#L1471-1 assume !(1 == ~E_2~0); 47969#L1476-1 assume !(1 == ~E_3~0); 47970#L1481-1 assume !(1 == ~E_4~0); 48127#L1486-1 assume !(1 == ~E_5~0); 46775#L1491-1 assume !(1 == ~E_6~0); 46443#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 46444#L1501-1 assume !(1 == ~E_8~0); 47267#L1506-1 assume !(1 == ~E_9~0); 47268#L1511-1 assume !(1 == ~E_10~0); 47222#L1516-1 assume !(1 == ~E_11~0); 46395#L1521-1 assume !(1 == ~E_12~0); 46396#L1526-1 assume !(1 == ~E_13~0); 46442#L1531-1 assume { :end_inline_reset_delta_events } true; 46972#L1892-2 [2024-11-13 13:49:13,868 INFO L747 eck$LassoCheckResult]: Loop: 46972#L1892-2 assume !false; 48035#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48288#L1233-1 assume !false; 48215#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47536#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47515#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48064#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46484#L1046 assume !(0 != eval_~tmp~0#1); 46486#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47018#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47019#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48271#L1258-5 assume !(0 == ~T1_E~0); 46645#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46646#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48263#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48267#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48268#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46875#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46876#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48032#L1298-3 assume !(0 == ~T9_E~0); 48033#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48195#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48031#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 47520#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46647#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46648#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48119#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46786#L1338-3 assume !(0 == ~E_4~0); 46787#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47946#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48125#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 48126#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47465#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47007#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47008#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47806#L1378-3 assume !(0 == ~E_12~0); 47807#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 47987#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47988#L607-42 assume 1 == ~m_pc~0; 47605#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47315#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47147#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47027#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47028#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47581#L626-42 assume !(1 == ~t1_pc~0); 47120#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 47119#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48219#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48004#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46676#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46677#L645-42 assume !(1 == ~t2_pc~0); 47924#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 47925#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47463#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46895#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46415#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46416#L664-42 assume !(1 == ~t3_pc~0); 46931#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46932#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47865#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47753#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47754#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47917#L683-42 assume 1 == ~t4_pc~0; 48280#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47632#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47760#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47920#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48185#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48026#L702-42 assume !(1 == ~t5_pc~0); 47108#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 47109#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47417#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47530#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 46427#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46428#L721-42 assume 1 == ~t6_pc~0; 46567#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46588#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46766#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46767#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47248#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47082#L740-42 assume !(1 == ~t7_pc~0); 46801#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 46802#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47378#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47231#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47232#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47503#L759-42 assume 1 == ~t8_pc~0; 47354#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47288#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47289#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47362#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47363#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47452#L778-42 assume 1 == ~t9_pc~0; 47300#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47302#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47725#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47633#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47634#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47688#L797-42 assume 1 == ~t10_pc~0; 46809#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46810#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47706#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47707#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47726#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47727#L816-42 assume 1 == ~t11_pc~0; 46387#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46388#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48225#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47275#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46986#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46987#L835-42 assume 1 == ~t12_pc~0; 47413#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 47311#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47505#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47506#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48085#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47863#L854-42 assume 1 == ~t13_pc~0; 47864#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46906#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 47074#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47075#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 47188#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47189#L1401-3 assume !(1 == ~M_E~0); 47980#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46735#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46614#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46615#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47238#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47239#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46780#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46781#L1436-3 assume !(1 == ~T8_E~0); 46399#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46400#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48008#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47326#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46954#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46955#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48265#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46896#L1476-3 assume !(1 == ~E_3~0); 46897#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47320#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46924#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46925#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47359#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47360#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47802#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47790#L1516-3 assume !(1 == ~E_11~0); 47791#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 47468#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 47469#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47884#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46713#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46760#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 46761#L1911 assume !(0 == start_simulation_~tmp~3#1); 47292#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47823#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46852#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46437#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 46438#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46561#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47324#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48138#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 46972#L1892-2 [2024-11-13 13:49:13,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:13,869 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2024-11-13 13:49:13,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:13,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764361564] [2024-11-13 13:49:13,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:13,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:13,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:13,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:13,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:13,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764361564] [2024-11-13 13:49:13,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764361564] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:13,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:13,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:13,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176039375] [2024-11-13 13:49:13,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:13,957 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:13,957 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:13,957 INFO L85 PathProgramCache]: Analyzing trace with hash -1926506352, now seen corresponding path program 1 times [2024-11-13 13:49:13,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:13,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633561445] [2024-11-13 13:49:13,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:13,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:13,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:14,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:14,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:14,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633561445] [2024-11-13 13:49:14,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [633561445] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:14,051 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:14,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:14,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065287774] [2024-11-13 13:49:14,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:14,052 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:14,052 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:14,052 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:14,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:14,053 INFO L87 Difference]: Start difference. First operand 1928 states and 2838 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:14,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:14,111 INFO L93 Difference]: Finished difference Result 1928 states and 2837 transitions. [2024-11-13 13:49:14,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1928 states and 2837 transitions. [2024-11-13 13:49:14,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:14,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1928 states to 1928 states and 2837 transitions. [2024-11-13 13:49:14,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1928 [2024-11-13 13:49:14,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1928 [2024-11-13 13:49:14,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1928 states and 2837 transitions. [2024-11-13 13:49:14,144 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:14,145 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2024-11-13 13:49:14,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1928 states and 2837 transitions. [2024-11-13 13:49:14,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1928 to 1928. [2024-11-13 13:49:14,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1928 states, 1928 states have (on average 1.4714730290456433) internal successors, (2837), 1927 states have internal predecessors, (2837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:14,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1928 states to 1928 states and 2837 transitions. [2024-11-13 13:49:14,188 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2024-11-13 13:49:14,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:14,190 INFO L424 stractBuchiCegarLoop]: Abstraction has 1928 states and 2837 transitions. [2024-11-13 13:49:14,190 INFO L331 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-13 13:49:14,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1928 states and 2837 transitions. [2024-11-13 13:49:14,202 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1755 [2024-11-13 13:49:14,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:14,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:14,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:14,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:14,209 INFO L745 eck$LassoCheckResult]: Stem: 50526#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 51426#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51427#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52152#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51823#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51824#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50747#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50748#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51227#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51062#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51063#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50811#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50812#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51233#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51417#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 51585#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 51618#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 50827#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50828#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 52043#L1258-2 assume !(0 == ~T1_E~0); 51145#L1263-1 assume !(0 == ~T2_E~0); 51146#L1268-1 assume !(0 == ~T3_E~0); 51463#L1273-1 assume !(0 == ~T4_E~0); 52022#L1278-1 assume !(0 == ~T5_E~0); 51880#L1283-1 assume !(0 == ~T6_E~0); 51881#L1288-1 assume !(0 == ~T7_E~0); 52118#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52107#L1298-1 assume !(0 == ~T9_E~0); 52038#L1303-1 assume !(0 == ~T10_E~0); 50625#L1308-1 assume !(0 == ~T11_E~0); 50565#L1313-1 assume !(0 == ~T12_E~0); 50566#L1318-1 assume !(0 == ~T13_E~0); 50573#L1323-1 assume !(0 == ~E_1~0); 50574#L1328-1 assume !(0 == ~E_2~0); 50757#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51751#L1338-1 assume !(0 == ~E_4~0); 51752#L1343-1 assume !(0 == ~E_5~0); 51857#L1348-1 assume !(0 == ~E_6~0); 52137#L1353-1 assume !(0 == ~E_7~0); 51486#L1358-1 assume !(0 == ~E_8~0); 51487#L1363-1 assume !(0 == ~E_9~0); 51773#L1368-1 assume !(0 == ~E_10~0); 50419#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50420#L1378-1 assume !(0 == ~E_12~0); 50702#L1383-1 assume !(0 == ~E_13~0); 50703#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51491#L607 assume 1 == ~m_pc~0; 51492#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50775#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51291#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51292#L1560 assume !(0 != activate_threads_~tmp~1#1); 51398#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50586#L626 assume !(1 == ~t1_pc~0); 50587#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50868#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50869#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51759#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50494#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50495#L645 assume 1 == ~t2_pc~0; 50604#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50559#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50670#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50671#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 51372#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51373#L664 assume 1 == ~t3_pc~0; 52135#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50355#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50356#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51017#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 51018#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52051#L683 assume !(1 == ~t4_pc~0); 51602#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51556#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50377#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50378#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51709#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51316#L702 assume 1 == ~t5_pc~0; 51317#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51249#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51704#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52041#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51950#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50393#L721 assume !(1 == ~t6_pc~0); 50370#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50371#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50518#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50653#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 51033#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51649#L740 assume 1 == ~t7_pc~0; 50435#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50270#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50271#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50260#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 50261#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50958#L759 assume !(1 == ~t8_pc~0); 50959#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50989#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52097#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51834#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51835#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52117#L778 assume 1 == ~t9_pc~0; 52007#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50418#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50723#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50296#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 50297#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50599#L797 assume !(1 == ~t10_pc~0); 50600#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50733#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51984#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51141#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 51142#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51443#L816 assume 1 == ~t11_pc~0; 50333#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50334#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51277#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51039#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 51040#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51584#L835 assume 1 == ~t12_pc~0; 51458#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50482#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50321#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50322#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 51197#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51198#L854 assume !(1 == ~t13_pc~0); 50813#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50814#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50863#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50516#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50517#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51945#L1401 assume !(1 == ~M_E~0); 51026#L1401-2 assume !(1 == ~T1_E~0); 51027#L1406-1 assume !(1 == ~T2_E~0); 51638#L1411-1 assume !(1 == ~T3_E~0); 51639#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51287#L1421-1 assume !(1 == ~T5_E~0); 50809#L1426-1 assume !(1 == ~T6_E~0); 50810#L1431-1 assume !(1 == ~T7_E~0); 50368#L1436-1 assume !(1 == ~T8_E~0); 50369#L1441-1 assume !(1 == ~T9_E~0); 51136#L1446-1 assume !(1 == ~T10_E~0); 51137#L1451-1 assume !(1 == ~T11_E~0); 51853#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51511#L1461-1 assume !(1 == ~T13_E~0); 51055#L1466-1 assume !(1 == ~E_1~0); 51056#L1471-1 assume !(1 == ~E_2~0); 51832#L1476-1 assume !(1 == ~E_3~0); 51833#L1481-1 assume !(1 == ~E_4~0); 51990#L1486-1 assume !(1 == ~E_5~0); 50638#L1491-1 assume !(1 == ~E_6~0); 50306#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50307#L1501-1 assume !(1 == ~E_8~0); 51130#L1506-1 assume !(1 == ~E_9~0); 51131#L1511-1 assume !(1 == ~E_10~0); 51085#L1516-1 assume !(1 == ~E_11~0); 50258#L1521-1 assume !(1 == ~E_12~0); 50259#L1526-1 assume !(1 == ~E_13~0); 50305#L1531-1 assume { :end_inline_reset_delta_events } true; 50835#L1892-2 [2024-11-13 13:49:14,210 INFO L747 eck$LassoCheckResult]: Loop: 50835#L1892-2 assume !false; 51898#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52151#L1233-1 assume !false; 52078#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51399#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51378#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51927#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 50347#L1046 assume !(0 != eval_~tmp~0#1); 50349#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50881#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50882#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 52134#L1258-5 assume !(0 == ~T1_E~0); 50508#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50509#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52126#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52130#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52131#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50738#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50739#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51895#L1298-3 assume !(0 == ~T9_E~0); 51896#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 52058#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51894#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51383#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50510#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50511#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51982#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50649#L1338-3 assume !(0 == ~E_4~0); 50650#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51809#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51988#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51989#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 51328#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50870#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50871#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51669#L1378-3 assume !(0 == ~E_12~0); 51670#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51850#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51851#L607-42 assume !(1 == ~m_pc~0); 51472#L607-44 is_master_triggered_~__retres1~0#1 := 0; 51178#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51012#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50890#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50891#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51447#L626-42 assume 1 == ~t1_pc~0; 50984#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50985#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52082#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51867#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50541#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50542#L645-42 assume 1 == ~t2_pc~0; 52050#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51787#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51326#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50758#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50278#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50279#L664-42 assume 1 == ~t3_pc~0; 51091#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50792#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51728#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51616#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51617#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51780#L683-42 assume !(1 == ~t4_pc~0); 51493#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 51494#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51622#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51783#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52048#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51889#L702-42 assume 1 == ~t5_pc~0; 51360#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50972#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51280#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51393#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 50290#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50291#L721-42 assume 1 == ~t6_pc~0; 50430#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50451#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50629#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50630#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51111#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50945#L740-42 assume 1 == ~t7_pc~0; 50946#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50665#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51241#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51094#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51095#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51366#L759-42 assume 1 == ~t8_pc~0; 51217#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51151#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51152#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51225#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51226#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51315#L778-42 assume 1 == ~t9_pc~0; 51163#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51165#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51588#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51495#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51496#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51551#L797-42 assume 1 == ~t10_pc~0; 50672#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50673#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51569#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51570#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51589#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51590#L816-42 assume 1 == ~t11_pc~0; 50250#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50251#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52088#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51138#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50849#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50850#L835-42 assume !(1 == ~t12_pc~0); 51171#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 51172#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 51368#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51369#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51948#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51726#L854-42 assume !(1 == ~t13_pc~0); 50768#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 50769#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50937#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50938#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 51051#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51052#L1401-3 assume !(1 == ~M_E~0); 51843#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50598#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50477#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50478#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51101#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51102#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50643#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50644#L1436-3 assume !(1 == ~T8_E~0); 50262#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50263#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51871#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51189#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50817#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50818#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52128#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50759#L1476-3 assume !(1 == ~E_3~0); 50760#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51183#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50787#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50788#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51222#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51223#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51665#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51653#L1516-3 assume !(1 == ~E_11~0); 51654#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 51331#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 51332#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51747#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50576#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50623#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50624#L1911 assume !(0 == start_simulation_~tmp~3#1); 51155#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51686#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50715#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50300#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50301#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50424#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51187#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 52001#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50835#L1892-2 [2024-11-13 13:49:14,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:14,210 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2024-11-13 13:49:14,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:14,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [832118281] [2024-11-13 13:49:14,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:14,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:14,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:14,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:14,355 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:14,355 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [832118281] [2024-11-13 13:49:14,355 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [832118281] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:14,355 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:14,355 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:49:14,355 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109345259] [2024-11-13 13:49:14,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:14,357 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:14,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:14,358 INFO L85 PathProgramCache]: Analyzing trace with hash -2068830159, now seen corresponding path program 1 times [2024-11-13 13:49:14,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:14,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607142472] [2024-11-13 13:49:14,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:14,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:14,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:14,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:14,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:14,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607142472] [2024-11-13 13:49:14,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607142472] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:14,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:14,463 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:14,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687291986] [2024-11-13 13:49:14,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:14,464 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:14,465 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:14,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:14,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:14,465 INFO L87 Difference]: Start difference. First operand 1928 states and 2837 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:14,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:14,686 INFO L93 Difference]: Finished difference Result 3583 states and 5241 transitions. [2024-11-13 13:49:14,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3583 states and 5241 transitions. [2024-11-13 13:49:14,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3410 [2024-11-13 13:49:14,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3583 states to 3583 states and 5241 transitions. [2024-11-13 13:49:14,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3583 [2024-11-13 13:49:14,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3583 [2024-11-13 13:49:14,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3583 states and 5241 transitions. [2024-11-13 13:49:14,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:14,733 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2024-11-13 13:49:14,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3583 states and 5241 transitions. [2024-11-13 13:49:14,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3583 to 3583. [2024-11-13 13:49:14,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3583 states, 3583 states have (on average 1.462740720066983) internal successors, (5241), 3582 states have internal predecessors, (5241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:14,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3583 states to 3583 states and 5241 transitions. [2024-11-13 13:49:14,820 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2024-11-13 13:49:14,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:14,821 INFO L424 stractBuchiCegarLoop]: Abstraction has 3583 states and 5241 transitions. [2024-11-13 13:49:14,821 INFO L331 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-13 13:49:14,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3583 states and 5241 transitions. [2024-11-13 13:49:14,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3410 [2024-11-13 13:49:14,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:14,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:14,847 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:14,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:14,848 INFO L745 eck$LassoCheckResult]: Stem: 56043#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56044#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56954#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56955#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57737#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 57355#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57356#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56266#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56267#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56747#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56582#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56583#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 56330#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 56331#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56755#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56943#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57112#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 57145#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 56346#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56347#L1258 assume !(0 == ~M_E~0); 57595#L1258-2 assume !(0 == ~T1_E~0); 56666#L1263-1 assume !(0 == ~T2_E~0); 56667#L1268-1 assume !(0 == ~T3_E~0); 56991#L1273-1 assume !(0 == ~T4_E~0); 57569#L1278-1 assume !(0 == ~T5_E~0); 57414#L1283-1 assume !(0 == ~T6_E~0); 57415#L1288-1 assume !(0 == ~T7_E~0); 57689#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57672#L1298-1 assume !(0 == ~T9_E~0); 57586#L1303-1 assume !(0 == ~T10_E~0); 56142#L1308-1 assume !(0 == ~T11_E~0); 56082#L1313-1 assume !(0 == ~T12_E~0); 56083#L1318-1 assume !(0 == ~T13_E~0); 56088#L1323-1 assume !(0 == ~E_1~0); 56089#L1328-1 assume !(0 == ~E_2~0); 56276#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 57281#L1338-1 assume !(0 == ~E_4~0); 57282#L1343-1 assume !(0 == ~E_5~0); 57391#L1348-1 assume !(0 == ~E_6~0); 57718#L1353-1 assume !(0 == ~E_7~0); 57014#L1358-1 assume !(0 == ~E_8~0); 57015#L1363-1 assume !(0 == ~E_9~0); 57305#L1368-1 assume !(0 == ~E_10~0); 55936#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 55937#L1378-1 assume !(0 == ~E_12~0); 56219#L1383-1 assume !(0 == ~E_13~0); 56220#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57018#L607 assume !(1 == ~m_pc~0); 56293#L607-2 is_master_triggered_~__retres1~0#1 := 0; 56294#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56811#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56812#L1560 assume !(0 != activate_threads_~tmp~1#1); 56921#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56103#L626 assume !(1 == ~t1_pc~0); 56104#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56387#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56388#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57289#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 56011#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56012#L645 assume 1 == ~t2_pc~0; 56119#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56076#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56186#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56187#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 56895#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56896#L664 assume 1 == ~t3_pc~0; 57712#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55871#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55872#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56536#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 56537#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57603#L683 assume !(1 == ~t4_pc~0); 57129#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 57083#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55896#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57239#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56835#L702 assume 1 == ~t5_pc~0; 56836#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56771#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57234#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57592#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 57486#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55906#L721 assume !(1 == ~t6_pc~0); 55888#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 55889#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56035#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56171#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 56552#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57178#L740 assume 1 == ~t7_pc~0; 55952#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55788#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55789#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55778#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 55779#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56476#L759 assume !(1 == ~t8_pc~0); 56477#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 56508#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57659#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57366#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 57367#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57688#L778 assume 1 == ~t9_pc~0; 57551#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55935#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56242#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55814#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 55815#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 56115#L797 assume !(1 == ~t10_pc~0); 56116#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 56252#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57523#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56662#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 56663#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56971#L816 assume 1 == ~t11_pc~0; 55849#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55850#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56800#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56558#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 56559#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57111#L835 assume 1 == ~t12_pc~0; 56986#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55999#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55839#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55840#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 56718#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 56719#L854 assume !(1 == ~t13_pc~0); 56332#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 56333#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56382#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56033#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56034#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57482#L1401 assume !(1 == ~M_E~0); 56545#L1401-2 assume !(1 == ~T1_E~0); 56546#L1406-1 assume !(1 == ~T2_E~0); 57167#L1411-1 assume !(1 == ~T3_E~0); 57168#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56810#L1421-1 assume !(1 == ~T5_E~0); 56328#L1426-1 assume !(1 == ~T6_E~0); 56329#L1431-1 assume !(1 == ~T7_E~0); 55886#L1436-1 assume !(1 == ~T8_E~0); 55887#L1441-1 assume !(1 == ~T9_E~0); 56655#L1446-1 assume !(1 == ~T10_E~0); 56656#L1451-1 assume !(1 == ~T11_E~0); 57387#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 57037#L1461-1 assume !(1 == ~T13_E~0); 56575#L1466-1 assume !(1 == ~E_1~0); 56576#L1471-1 assume !(1 == ~E_2~0); 57364#L1476-1 assume !(1 == ~E_3~0); 57365#L1481-1 assume !(1 == ~E_4~0); 57530#L1486-1 assume !(1 == ~E_5~0); 56155#L1491-1 assume !(1 == ~E_6~0); 55824#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 55825#L1501-1 assume !(1 == ~E_8~0); 56650#L1506-1 assume !(1 == ~E_9~0); 56651#L1511-1 assume !(1 == ~E_10~0); 56605#L1516-1 assume !(1 == ~E_11~0); 55776#L1521-1 assume !(1 == ~E_12~0); 55777#L1526-1 assume !(1 == ~E_13~0); 55823#L1531-1 assume { :end_inline_reset_delta_events } true; 56354#L1892-2 [2024-11-13 13:49:14,849 INFO L747 eck$LassoCheckResult]: Loop: 56354#L1892-2 assume !false; 57823#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57819#L1233-1 assume !false; 57634#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56922#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56901#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 57464#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55865#L1046 assume !(0 != eval_~tmp~0#1); 55867#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59302#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59301#L1258-3 assume !(0 == ~M_E~0); 59300#L1258-5 assume !(0 == ~T1_E~0); 59299#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59298#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59297#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59296#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59295#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 59294#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59293#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59292#L1298-3 assume !(0 == ~T9_E~0); 59291#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59290#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59289#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59288#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59287#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 59286#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59285#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59284#L1338-3 assume !(0 == ~E_4~0); 59283#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59282#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59281#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59280#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59279#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59278#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59277#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59276#L1378-3 assume !(0 == ~E_12~0); 59275#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59274#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59273#L607-42 assume !(1 == ~m_pc~0); 59271#L607-44 is_master_triggered_~__retres1~0#1 := 0; 59270#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59269#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59268#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59267#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59266#L626-42 assume 1 == ~t1_pc~0; 59264#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59263#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59262#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59261#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 59260#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59259#L645-42 assume !(1 == ~t2_pc~0); 59257#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 59256#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59255#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59254#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59253#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59252#L664-42 assume 1 == ~t3_pc~0; 59250#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 59249#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59248#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59247#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59246#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59245#L683-42 assume !(1 == ~t4_pc~0); 59243#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 59242#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59241#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59240#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59239#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59238#L702-42 assume 1 == ~t5_pc~0; 59236#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59235#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59234#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59233#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 59232#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59231#L721-42 assume 1 == ~t6_pc~0; 59229#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59228#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59227#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59226#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59225#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59224#L740-42 assume 1 == ~t7_pc~0; 59222#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 56763#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56764#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58733#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58732#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58731#L759-42 assume 1 == ~t8_pc~0; 58729#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58728#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58727#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58726#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58725#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58724#L778-42 assume !(1 == ~t9_pc~0); 58722#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 58721#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58720#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58719#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58718#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58717#L797-42 assume 1 == ~t10_pc~0; 58715#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58714#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58713#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58712#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58711#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58710#L816-42 assume !(1 == ~t11_pc~0); 58708#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 58707#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58706#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58705#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58704#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58703#L835-42 assume 1 == ~t12_pc~0; 58701#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58700#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58699#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58698#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 58697#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58696#L854-42 assume !(1 == ~t13_pc~0); 58694#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 58693#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56456#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56457#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56571#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56572#L1401-3 assume !(1 == ~M_E~0); 57377#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56118#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55994#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55995#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56621#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56622#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56160#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56161#L1436-3 assume !(1 == ~T8_E~0); 55780#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55781#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57405#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56710#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56336#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 56337#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57704#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56278#L1476-3 assume !(1 == ~E_3~0); 56279#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56704#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56306#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 56307#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56744#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56745#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57195#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57183#L1516-3 assume !(1 == ~E_11~0); 57184#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 56854#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 56855#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57277#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56093#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56140#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 56141#L1911 assume !(0 == start_simulation_~tmp~3#1); 56676#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57216#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56234#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 55818#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 55819#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55941#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56708#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57543#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 56354#L1892-2 [2024-11-13 13:49:14,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:14,850 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2024-11-13 13:49:14,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:14,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821239930] [2024-11-13 13:49:14,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:14,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:14,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:14,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:14,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:14,992 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821239930] [2024-11-13 13:49:14,992 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821239930] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:14,992 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:14,992 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:14,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [387082167] [2024-11-13 13:49:14,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:14,993 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:14,993 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:14,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1294806701, now seen corresponding path program 1 times [2024-11-13 13:49:14,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:14,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421858797] [2024-11-13 13:49:14,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:14,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:15,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:15,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:15,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:15,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1421858797] [2024-11-13 13:49:15,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1421858797] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:15,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:15,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:15,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2144378454] [2024-11-13 13:49:15,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:15,107 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:15,107 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:15,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:49:15,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:49:15,108 INFO L87 Difference]: Start difference. First operand 3583 states and 5241 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:15,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:15,330 INFO L93 Difference]: Finished difference Result 7018 states and 10255 transitions. [2024-11-13 13:49:15,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7018 states and 10255 transitions. [2024-11-13 13:49:15,408 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6820 [2024-11-13 13:49:15,431 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7018 states to 7018 states and 10255 transitions. [2024-11-13 13:49:15,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7018 [2024-11-13 13:49:15,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7018 [2024-11-13 13:49:15,438 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7018 states and 10255 transitions. [2024-11-13 13:49:15,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:15,448 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2024-11-13 13:49:15,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7018 states and 10255 transitions. [2024-11-13 13:49:15,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7018 to 7018. [2024-11-13 13:49:15,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7018 states, 7018 states have (on average 1.4612425192362497) internal successors, (10255), 7017 states have internal predecessors, (10255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:15,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7018 states to 7018 states and 10255 transitions. [2024-11-13 13:49:15,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2024-11-13 13:49:15,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:49:15,568 INFO L424 stractBuchiCegarLoop]: Abstraction has 7018 states and 10255 transitions. [2024-11-13 13:49:15,568 INFO L331 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-13 13:49:15,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7018 states and 10255 transitions. [2024-11-13 13:49:15,600 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6820 [2024-11-13 13:49:15,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:15,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:15,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:15,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:15,603 INFO L745 eck$LassoCheckResult]: Stem: 66655#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66656#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 67569#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67570#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68322#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 67976#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67977#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66883#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66884#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67369#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67201#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 67202#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66949#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66950#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 67375#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 67560#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 67728#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 67761#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 66965#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66966#L1258 assume !(0 == ~M_E~0); 68203#L1258-2 assume !(0 == ~T1_E~0); 67286#L1263-1 assume !(0 == ~T2_E~0); 67287#L1268-1 assume !(0 == ~T3_E~0); 67606#L1273-1 assume !(0 == ~T4_E~0); 68181#L1278-1 assume !(0 == ~T5_E~0); 68033#L1283-1 assume !(0 == ~T6_E~0); 68034#L1288-1 assume !(0 == ~T7_E~0); 68283#L1293-1 assume !(0 == ~T8_E~0); 68272#L1298-1 assume !(0 == ~T9_E~0); 68198#L1303-1 assume !(0 == ~T10_E~0); 66756#L1308-1 assume !(0 == ~T11_E~0); 66695#L1313-1 assume !(0 == ~T12_E~0); 66696#L1318-1 assume !(0 == ~T13_E~0); 66701#L1323-1 assume !(0 == ~E_1~0); 66702#L1328-1 assume !(0 == ~E_2~0); 66893#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 67901#L1338-1 assume !(0 == ~E_4~0); 67902#L1343-1 assume !(0 == ~E_5~0); 68010#L1348-1 assume !(0 == ~E_6~0); 68304#L1353-1 assume !(0 == ~E_7~0); 67629#L1358-1 assume !(0 == ~E_8~0); 67630#L1363-1 assume !(0 == ~E_9~0); 67924#L1368-1 assume !(0 == ~E_10~0); 66548#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 66549#L1378-1 assume !(0 == ~E_12~0); 66834#L1383-1 assume !(0 == ~E_13~0); 66835#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67633#L607 assume !(1 == ~m_pc~0); 66910#L607-2 is_master_triggered_~__retres1~0#1 := 0; 66911#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67430#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67431#L1560 assume !(0 != activate_threads_~tmp~1#1); 67541#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66716#L626 assume !(1 == ~t1_pc~0); 66717#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 67006#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67007#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67909#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 66623#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66624#L645 assume 1 == ~t2_pc~0; 66733#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66689#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66800#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66801#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 67515#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67516#L664 assume 1 == ~t3_pc~0; 68301#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66483#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66484#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 67155#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 67156#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68211#L683 assume !(1 == ~t4_pc~0); 67745#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 67699#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66507#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66508#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67859#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67456#L702 assume 1 == ~t5_pc~0; 67457#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67390#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67853#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68201#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 68104#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66520#L721 assume !(1 == ~t6_pc~0); 66500#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 66501#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66647#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66785#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 67171#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67795#L740 assume 1 == ~t7_pc~0; 66564#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66399#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66400#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66389#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 66390#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67096#L759 assume !(1 == ~t8_pc~0); 67097#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 67127#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68260#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67987#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 67988#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68282#L778 assume 1 == ~t9_pc~0; 68165#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66547#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66857#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66425#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 66426#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66730#L797 assume !(1 == ~t10_pc~0); 66731#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 66869#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68142#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67282#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 67283#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 67586#L816 assume 1 == ~t11_pc~0; 66463#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 66464#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 67419#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 67177#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 67178#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67727#L835 assume 1 == ~t12_pc~0; 67601#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66611#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 66450#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66451#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 67338#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 67339#L854 assume !(1 == ~t13_pc~0); 66951#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 66952#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 67001#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66645#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66646#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68098#L1401 assume !(1 == ~M_E~0); 67164#L1401-2 assume !(1 == ~T1_E~0); 67165#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67784#L1411-1 assume !(1 == ~T3_E~0); 67785#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67429#L1421-1 assume !(1 == ~T5_E~0); 66947#L1426-1 assume !(1 == ~T6_E~0); 66948#L1431-1 assume !(1 == ~T7_E~0); 66498#L1436-1 assume !(1 == ~T8_E~0); 66499#L1441-1 assume !(1 == ~T9_E~0); 67275#L1446-1 assume !(1 == ~T10_E~0); 67276#L1451-1 assume !(1 == ~T11_E~0); 68006#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67652#L1461-1 assume !(1 == ~T13_E~0); 67194#L1466-1 assume !(1 == ~E_1~0); 67195#L1471-1 assume !(1 == ~E_2~0); 67985#L1476-1 assume !(1 == ~E_3~0); 67986#L1481-1 assume !(1 == ~E_4~0); 68148#L1486-1 assume !(1 == ~E_5~0); 66769#L1491-1 assume !(1 == ~E_6~0); 66435#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 66436#L1501-1 assume !(1 == ~E_8~0); 67271#L1506-1 assume !(1 == ~E_9~0); 67272#L1511-1 assume !(1 == ~E_10~0); 67225#L1516-1 assume !(1 == ~E_11~0); 67226#L1521-1 assume !(1 == ~E_12~0); 68463#L1526-1 assume !(1 == ~E_13~0); 68459#L1531-1 assume { :end_inline_reset_delta_events } true; 68423#L1892-2 [2024-11-13 13:49:15,604 INFO L747 eck$LassoCheckResult]: Loop: 68423#L1892-2 assume !false; 68411#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68403#L1233-1 assume !false; 68396#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68389#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68361#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68359#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 68356#L1046 assume !(0 != eval_~tmp~0#1); 68353#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68351#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68349#L1258-3 assume !(0 == ~M_E~0); 68345#L1258-5 assume !(0 == ~T1_E~0); 68346#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 71726#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71721#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71716#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71712#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 71706#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 71701#L1293-3 assume !(0 == ~T8_E~0); 71696#L1298-3 assume !(0 == ~T9_E~0); 71691#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 71685#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 71681#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 71675#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 71670#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 71665#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 71660#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71654#L1338-3 assume !(0 == ~E_4~0); 71649#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71643#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 71638#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71632#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 71628#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 71624#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 71620#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 71613#L1378-3 assume !(0 == ~E_12~0); 71608#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 71602#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71596#L607-42 assume !(1 == ~m_pc~0); 71590#L607-44 is_master_triggered_~__retres1~0#1 := 0; 71585#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71579#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71572#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 71565#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71557#L626-42 assume !(1 == ~t1_pc~0); 71551#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 71544#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71537#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71530#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 71523#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71516#L645-42 assume !(1 == ~t2_pc~0); 71511#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 71507#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71502#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71497#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 71491#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71482#L664-42 assume 1 == ~t3_pc~0; 71475#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 71469#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71462#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71455#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 71449#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71440#L683-42 assume !(1 == ~t4_pc~0); 71433#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 71427#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71420#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 71413#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 71407#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71398#L702-42 assume !(1 == ~t5_pc~0); 71392#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 71385#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71378#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 71372#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 71367#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71360#L721-42 assume !(1 == ~t6_pc~0); 71355#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 71350#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71349#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 71348#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 71347#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 71346#L740-42 assume !(1 == ~t7_pc~0); 71345#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 71343#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71342#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 71341#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 71339#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 71338#L759-42 assume !(1 == ~t8_pc~0); 71337#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 71333#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71331#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 71329#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 71327#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 71325#L778-42 assume !(1 == ~t9_pc~0); 71321#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 71319#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 71316#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71314#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 71312#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 71310#L797-42 assume 1 == ~t10_pc~0; 71307#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 71305#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 71302#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 71300#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 71298#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 71296#L816-42 assume !(1 == ~t11_pc~0); 71293#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 71291#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71288#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 71286#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 71284#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71282#L835-42 assume 1 == ~t12_pc~0; 71227#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 71225#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 71223#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 71221#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 71218#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 71216#L854-42 assume !(1 == ~t13_pc~0); 71213#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 71211#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 71209#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 71207#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 71155#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71145#L1401-3 assume !(1 == ~M_E~0); 68339#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71130#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71122#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 71115#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 71106#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71097#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 71090#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 71082#L1436-3 assume !(1 == ~T8_E~0); 71076#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 71070#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 71062#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 71054#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 71049#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 71043#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 71038#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 71032#L1476-3 assume !(1 == ~E_3~0); 71023#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 71016#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 71010#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 71004#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70999#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70995#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70989#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 70986#L1516-3 assume !(1 == ~E_11~0); 70984#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 70981#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 70979#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 70635#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 70625#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 70619#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 70611#L1911 assume !(0 == start_simulation_~tmp~3#1); 70605#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69112#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 69096#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 69094#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 69092#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69090#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68616#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68458#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 68423#L1892-2 [2024-11-13 13:49:15,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:15,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2024-11-13 13:49:15,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:15,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885265374] [2024-11-13 13:49:15,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:15,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:15,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:15,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:15,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:15,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885265374] [2024-11-13 13:49:15,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1885265374] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:15,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:15,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:15,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734104851] [2024-11-13 13:49:15,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:15,714 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:15,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:15,715 INFO L85 PathProgramCache]: Analyzing trace with hash 325318342, now seen corresponding path program 1 times [2024-11-13 13:49:15,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:15,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1344479494] [2024-11-13 13:49:15,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:15,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:15,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:15,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:15,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:15,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1344479494] [2024-11-13 13:49:15,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1344479494] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:15,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:15,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:15,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559069786] [2024-11-13 13:49:15,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:15,796 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:15,796 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:15,796 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:49:15,796 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:49:15,796 INFO L87 Difference]: Start difference. First operand 7018 states and 10255 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:16,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:16,083 INFO L93 Difference]: Finished difference Result 13472 states and 19680 transitions. [2024-11-13 13:49:16,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13472 states and 19680 transitions. [2024-11-13 13:49:16,221 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13240 [2024-11-13 13:49:16,267 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13472 states to 13472 states and 19680 transitions. [2024-11-13 13:49:16,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13472 [2024-11-13 13:49:16,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13472 [2024-11-13 13:49:16,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13472 states and 19680 transitions. [2024-11-13 13:49:16,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:16,296 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13472 states and 19680 transitions. [2024-11-13 13:49:16,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13472 states and 19680 transitions. [2024-11-13 13:49:16,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13472 to 13468. [2024-11-13 13:49:16,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13468 states, 13468 states have (on average 1.4609444609444608) internal successors, (19676), 13467 states have internal predecessors, (19676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:16,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13468 states to 13468 states and 19676 transitions. [2024-11-13 13:49:16,542 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13468 states and 19676 transitions. [2024-11-13 13:49:16,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:49:16,543 INFO L424 stractBuchiCegarLoop]: Abstraction has 13468 states and 19676 transitions. [2024-11-13 13:49:16,543 INFO L331 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-13 13:49:16,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13468 states and 19676 transitions. [2024-11-13 13:49:16,601 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13240 [2024-11-13 13:49:16,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:16,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:16,604 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:16,604 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:16,605 INFO L745 eck$LassoCheckResult]: Stem: 87155#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 87156#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 88081#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88082#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88914#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 88502#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88503#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87380#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87381#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87867#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 87701#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 87702#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 87447#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 87448#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 87878#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 88072#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 88245#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 88280#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 87465#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87466#L1258 assume !(0 == ~M_E~0); 88763#L1258-2 assume !(0 == ~T1_E~0); 87786#L1263-1 assume !(0 == ~T2_E~0); 87787#L1268-1 assume !(0 == ~T3_E~0); 88119#L1273-1 assume !(0 == ~T4_E~0); 88738#L1278-1 assume !(0 == ~T5_E~0); 88572#L1283-1 assume !(0 == ~T6_E~0); 88573#L1288-1 assume !(0 == ~T7_E~0); 88856#L1293-1 assume !(0 == ~T8_E~0); 88841#L1298-1 assume !(0 == ~T9_E~0); 88757#L1303-1 assume !(0 == ~T10_E~0); 87255#L1308-1 assume !(0 == ~T11_E~0); 87194#L1313-1 assume !(0 == ~T12_E~0); 87195#L1318-1 assume !(0 == ~T13_E~0); 87200#L1323-1 assume !(0 == ~E_1~0); 87201#L1328-1 assume !(0 == ~E_2~0); 87390#L1333-1 assume !(0 == ~E_3~0); 88422#L1338-1 assume !(0 == ~E_4~0); 88423#L1343-1 assume !(0 == ~E_5~0); 88544#L1348-1 assume !(0 == ~E_6~0); 88888#L1353-1 assume !(0 == ~E_7~0); 88142#L1358-1 assume !(0 == ~E_8~0); 88143#L1363-1 assume !(0 == ~E_9~0); 88444#L1368-1 assume !(0 == ~E_10~0); 87047#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 87048#L1378-1 assume !(0 == ~E_12~0); 87331#L1383-1 assume !(0 == ~E_13~0); 87332#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88146#L607 assume !(1 == ~m_pc~0); 87408#L607-2 is_master_triggered_~__retres1~0#1 := 0; 87409#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87935#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87936#L1560 assume !(0 != activate_threads_~tmp~1#1); 88050#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87215#L626 assume !(1 == ~t1_pc~0); 87216#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 87506#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87507#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88430#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 87123#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 87124#L645 assume 1 == ~t2_pc~0; 87232#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 87188#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87299#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87300#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 88023#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88024#L664 assume 1 == ~t3_pc~0; 88883#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86982#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86983#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87656#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 87657#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88771#L683 assume !(1 == ~t4_pc~0); 88264#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88215#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87006#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87007#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88379#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87959#L702 assume 1 == ~t5_pc~0; 87960#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 87893#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88374#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88761#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 88647#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87017#L721 assume !(1 == ~t6_pc~0); 86999#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 87000#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87147#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87284#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 87672#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88318#L740 assume 1 == ~t7_pc~0; 87063#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 86899#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86900#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86889#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 86890#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87596#L759 assume !(1 == ~t8_pc~0); 87597#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 87628#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88827#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88514#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 88515#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88855#L778 assume 1 == ~t9_pc~0; 88718#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 87046#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87355#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86925#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 86926#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87227#L797 assume !(1 == ~t10_pc~0); 87228#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 87366#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 88691#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 87782#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 87783#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 88098#L816 assume 1 == ~t11_pc~0; 86960#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86961#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87923#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87678#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 87679#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88244#L835 assume 1 == ~t12_pc~0; 88114#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 87111#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86950#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86951#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 87838#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87839#L854 assume !(1 == ~t13_pc~0); 87449#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 87450#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 87501#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 87145#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 87146#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88643#L1401 assume !(1 == ~M_E~0); 87665#L1401-2 assume !(1 == ~T1_E~0); 87666#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88650#L1411-1 assume !(1 == ~T3_E~0); 88872#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88873#L1421-1 assume !(1 == ~T5_E~0); 87445#L1426-1 assume !(1 == ~T6_E~0); 87446#L1431-1 assume !(1 == ~T7_E~0); 86997#L1436-1 assume !(1 == ~T8_E~0); 86998#L1441-1 assume !(1 == ~T9_E~0); 92198#L1446-1 assume !(1 == ~T10_E~0); 92196#L1451-1 assume !(1 == ~T11_E~0); 92194#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 92192#L1461-1 assume !(1 == ~T13_E~0); 87694#L1466-1 assume !(1 == ~E_1~0); 87695#L1471-1 assume !(1 == ~E_2~0); 88920#L1476-1 assume !(1 == ~E_3~0); 92157#L1481-1 assume !(1 == ~E_4~0); 92141#L1486-1 assume !(1 == ~E_5~0); 92130#L1491-1 assume !(1 == ~E_6~0); 92120#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 92111#L1501-1 assume !(1 == ~E_8~0); 92102#L1506-1 assume !(1 == ~E_9~0); 92092#L1511-1 assume !(1 == ~E_10~0); 92075#L1516-1 assume !(1 == ~E_11~0); 92071#L1521-1 assume !(1 == ~E_12~0); 90463#L1526-1 assume !(1 == ~E_13~0); 90434#L1531-1 assume { :end_inline_reset_delta_events } true; 90402#L1892-2 [2024-11-13 13:49:16,605 INFO L747 eck$LassoCheckResult]: Loop: 90402#L1892-2 assume !false; 90385#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90373#L1233-1 assume !false; 90364#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 90341#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 90313#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 90311#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 90308#L1046 assume !(0 != eval_~tmp~0#1); 90305#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 90303#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 90300#L1258-3 assume !(0 == ~M_E~0); 90301#L1258-5 assume !(0 == ~T1_E~0); 90295#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90296#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 99535#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 99533#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 99531#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 99529#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 99527#L1293-3 assume !(0 == ~T8_E~0); 99525#L1298-3 assume !(0 == ~T9_E~0); 99523#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 99521#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 99519#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 99517#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 99515#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 99513#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 99511#L1333-3 assume !(0 == ~E_3~0); 99509#L1338-3 assume !(0 == ~E_4~0); 99507#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 99505#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 99503#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 99501#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 99499#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 99497#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 99495#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 99493#L1378-3 assume !(0 == ~E_12~0); 99491#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 99489#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99487#L607-42 assume !(1 == ~m_pc~0); 99481#L607-44 is_master_triggered_~__retres1~0#1 := 0; 99480#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 99479#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 99478#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 99477#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99476#L626-42 assume !(1 == ~t1_pc~0); 99475#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 99473#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99472#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 99471#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 99470#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 99469#L645-42 assume !(1 == ~t2_pc~0); 99467#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 99466#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99465#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 99464#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99463#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99460#L664-42 assume 1 == ~t3_pc~0; 99461#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 100085#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100084#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 100083#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100082#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100081#L683-42 assume 1 == ~t4_pc~0; 100080#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 100078#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100077#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100076#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100075#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100074#L702-42 assume !(1 == ~t5_pc~0); 100073#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 100071#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100070#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100069#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 100068#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100067#L721-42 assume 1 == ~t6_pc~0; 100065#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 100064#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100063#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 100062#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100041#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99981#L740-42 assume 1 == ~t7_pc~0; 99977#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 99975#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99973#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 99971#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 99661#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99660#L759-42 assume !(1 == ~t8_pc~0); 99659#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 93833#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93830#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93823#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 93818#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 93814#L778-42 assume !(1 == ~t9_pc~0); 93809#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 93806#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 93803#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 93799#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 93797#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 93553#L797-42 assume 1 == ~t10_pc~0; 93549#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 93547#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 93545#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 93543#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 93541#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 93539#L816-42 assume !(1 == ~t11_pc~0); 93437#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 93435#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93432#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 93430#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 93428#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93426#L835-42 assume !(1 == ~t12_pc~0); 93421#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 93418#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93416#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 93414#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 93412#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 93410#L854-42 assume 1 == ~t13_pc~0; 93393#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 93390#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 93236#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 93235#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 93155#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93153#L1401-3 assume !(1 == ~M_E~0); 92734#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93151#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87231#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93148#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 93097#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 93095#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93093#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 93048#L1436-3 assume !(1 == ~T8_E~0); 93046#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 93045#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 93044#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 93012#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 93009#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 93007#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 93005#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 93000#L1476-3 assume !(1 == ~E_3~0); 92998#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 92954#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 92952#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 92933#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 92900#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 92898#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 92896#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 92895#L1516-3 assume !(1 == ~E_11~0); 92894#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 92892#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 92841#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 92807#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 92803#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 92801#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 92782#L1911 assume !(0 == start_simulation_~tmp~3#1); 92766#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 90484#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 90469#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 90467#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 90464#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 90462#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 90458#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 90433#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 90402#L1892-2 [2024-11-13 13:49:16,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:16,606 INFO L85 PathProgramCache]: Analyzing trace with hash -312397191, now seen corresponding path program 1 times [2024-11-13 13:49:16,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:16,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256472577] [2024-11-13 13:49:16,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:16,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:16,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:16,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:16,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:16,719 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [256472577] [2024-11-13 13:49:16,719 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [256472577] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:16,719 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:16,719 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:16,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885569541] [2024-11-13 13:49:16,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:16,719 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:16,720 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:16,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1159632473, now seen corresponding path program 1 times [2024-11-13 13:49:16,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:16,720 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378114348] [2024-11-13 13:49:16,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:16,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:16,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:16,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:16,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:16,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378114348] [2024-11-13 13:49:16,863 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1378114348] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:16,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:16,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:16,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663903058] [2024-11-13 13:49:16,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:16,864 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:16,864 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:16,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:49:16,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:49:16,864 INFO L87 Difference]: Start difference. First operand 13468 states and 19676 transitions. cyclomatic complexity: 6212 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:17,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:17,211 INFO L93 Difference]: Finished difference Result 25936 states and 37873 transitions. [2024-11-13 13:49:17,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25936 states and 37873 transitions. [2024-11-13 13:49:17,348 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25680 [2024-11-13 13:49:17,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25936 states to 25936 states and 37873 transitions. [2024-11-13 13:49:17,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25936 [2024-11-13 13:49:17,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25936 [2024-11-13 13:49:17,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25936 states and 37873 transitions. [2024-11-13 13:49:17,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:17,544 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25936 states and 37873 transitions. [2024-11-13 13:49:17,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25936 states and 37873 transitions. [2024-11-13 13:49:17,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25936 to 25928. [2024-11-13 13:49:17,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25928 states, 25928 states have (on average 1.4603903116322123) internal successors, (37865), 25927 states have internal predecessors, (37865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:18,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25928 states to 25928 states and 37865 transitions. [2024-11-13 13:49:18,260 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25928 states and 37865 transitions. [2024-11-13 13:49:18,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:49:18,260 INFO L424 stractBuchiCegarLoop]: Abstraction has 25928 states and 37865 transitions. [2024-11-13 13:49:18,261 INFO L331 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-13 13:49:18,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25928 states and 37865 transitions. [2024-11-13 13:49:18,333 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25680 [2024-11-13 13:49:18,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:18,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:18,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:18,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:18,337 INFO L745 eck$LassoCheckResult]: Stem: 126569#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 126570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 127505#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 127506#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 128395#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 127931#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127932#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126795#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126796#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127289#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127119#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 127120#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 126860#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 126861#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 127297#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 127496#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 127669#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 127704#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 126876#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126877#L1258 assume !(0 == ~M_E~0); 128212#L1258-2 assume !(0 == ~T1_E~0); 127205#L1263-1 assume !(0 == ~T2_E~0); 127206#L1268-1 assume !(0 == ~T3_E~0); 127544#L1273-1 assume !(0 == ~T4_E~0); 128183#L1278-1 assume !(0 == ~T5_E~0); 128002#L1283-1 assume !(0 == ~T6_E~0); 128003#L1288-1 assume !(0 == ~T7_E~0); 128322#L1293-1 assume !(0 == ~T8_E~0); 128305#L1298-1 assume !(0 == ~T9_E~0); 128203#L1303-1 assume !(0 == ~T10_E~0); 126670#L1308-1 assume !(0 == ~T11_E~0); 126609#L1313-1 assume !(0 == ~T12_E~0); 126610#L1318-1 assume !(0 == ~T13_E~0); 126615#L1323-1 assume !(0 == ~E_1~0); 126616#L1328-1 assume !(0 == ~E_2~0); 126805#L1333-1 assume !(0 == ~E_3~0); 127852#L1338-1 assume !(0 == ~E_4~0); 127853#L1343-1 assume !(0 == ~E_5~0); 127975#L1348-1 assume !(0 == ~E_6~0); 128371#L1353-1 assume !(0 == ~E_7~0); 127567#L1358-1 assume !(0 == ~E_8~0); 127568#L1363-1 assume !(0 == ~E_9~0); 127874#L1368-1 assume !(0 == ~E_10~0); 126462#L1373-1 assume !(0 == ~E_11~0); 126463#L1378-1 assume !(0 == ~E_12~0); 126748#L1383-1 assume !(0 == ~E_13~0); 126749#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 127571#L607 assume !(1 == ~m_pc~0); 126822#L607-2 is_master_triggered_~__retres1~0#1 := 0; 126823#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 127357#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 127358#L1560 assume !(0 != activate_threads_~tmp~1#1); 127473#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126630#L626 assume !(1 == ~t1_pc~0); 126631#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126918#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126919#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 127860#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 126537#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126538#L645 assume 1 == ~t2_pc~0; 126647#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 126603#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126715#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126716#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 127446#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127447#L664 assume 1 == ~t3_pc~0; 128363#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 126396#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126397#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 127074#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 127075#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128220#L683 assume !(1 == ~t4_pc~0); 127687#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 127638#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126420#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126421#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 127808#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 127381#L702 assume 1 == ~t5_pc~0; 127382#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 127313#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127799#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 128207#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 128082#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 126431#L721 assume !(1 == ~t6_pc~0); 126413#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 126414#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 126561#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126700#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 127090#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 127740#L740 assume 1 == ~t7_pc~0; 126478#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 126313#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 126314#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 126303#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 126304#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 127012#L759 assume !(1 == ~t8_pc~0); 127013#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 127044#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128286#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 127943#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 127944#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 128321#L778 assume 1 == ~t9_pc~0; 128160#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 126460#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 126771#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 126339#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 126340#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 126642#L797 assume !(1 == ~t10_pc~0); 126643#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 126781#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 128131#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 127201#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 127202#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 127522#L816 assume 1 == ~t11_pc~0; 126374#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 126375#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 127345#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 127096#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 127097#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 127668#L835 assume 1 == ~t12_pc~0; 127539#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 126525#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 126364#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 126365#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 127260#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 127261#L854 assume !(1 == ~t13_pc~0); 126862#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 126863#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 126913#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 126559#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 126560#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128077#L1401 assume !(1 == ~M_E~0); 127083#L1401-2 assume !(1 == ~T1_E~0); 127084#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 127728#L1411-1 assume !(1 == ~T3_E~0); 127729#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 131888#L1421-1 assume !(1 == ~T5_E~0); 126858#L1426-1 assume !(1 == ~T6_E~0); 126859#L1431-1 assume !(1 == ~T7_E~0); 126411#L1436-1 assume !(1 == ~T8_E~0); 126412#L1441-1 assume !(1 == ~T9_E~0); 127194#L1446-1 assume !(1 == ~T10_E~0); 127195#L1451-1 assume !(1 == ~T11_E~0); 127971#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 127590#L1461-1 assume !(1 == ~T13_E~0); 127112#L1466-1 assume !(1 == ~E_1~0); 127113#L1471-1 assume !(1 == ~E_2~0); 127941#L1476-1 assume !(1 == ~E_3~0); 127942#L1481-1 assume !(1 == ~E_4~0); 138828#L1486-1 assume !(1 == ~E_5~0); 138826#L1491-1 assume !(1 == ~E_6~0); 138824#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 138822#L1501-1 assume !(1 == ~E_8~0); 138820#L1506-1 assume !(1 == ~E_9~0); 138819#L1511-1 assume !(1 == ~E_10~0); 138818#L1516-1 assume !(1 == ~E_11~0); 127144#L1521-1 assume !(1 == ~E_12~0); 138815#L1526-1 assume !(1 == ~E_13~0); 138813#L1531-1 assume { :end_inline_reset_delta_events } true; 138811#L1892-2 [2024-11-13 13:49:18,337 INFO L747 eck$LassoCheckResult]: Loop: 138811#L1892-2 assume !false; 138804#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 138802#L1233-1 assume !false; 138800#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 136393#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 136378#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 136376#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 136373#L1046 assume !(0 != eval_~tmp~0#1); 136371#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136369#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136366#L1258-3 assume !(0 == ~M_E~0); 136364#L1258-5 assume !(0 == ~T1_E~0); 136362#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 136360#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136358#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 136356#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 136353#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 136351#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 136349#L1293-3 assume !(0 == ~T8_E~0); 136347#L1298-3 assume !(0 == ~T9_E~0); 136345#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 136343#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 136340#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 136338#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 136336#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 136334#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136332#L1333-3 assume !(0 == ~E_3~0); 136330#L1338-3 assume !(0 == ~E_4~0); 136327#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136325#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136323#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 136321#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 136319#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 136317#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 136314#L1373-3 assume !(0 == ~E_11~0); 136312#L1378-3 assume !(0 == ~E_12~0); 136310#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 136308#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136306#L607-42 assume !(1 == ~m_pc~0); 136304#L607-44 is_master_triggered_~__retres1~0#1 := 0; 136300#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136298#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 136296#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136295#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136292#L626-42 assume !(1 == ~t1_pc~0); 136288#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 136283#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136279#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 136275#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136271#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136270#L645-42 assume !(1 == ~t2_pc~0); 136268#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 136267#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136266#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 136265#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136264#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136263#L664-42 assume !(1 == ~t3_pc~0); 136262#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 136260#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136259#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 136258#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136257#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136256#L683-42 assume !(1 == ~t4_pc~0); 136254#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 136253#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136252#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 136251#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136250#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136249#L702-42 assume 1 == ~t5_pc~0; 136247#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 136246#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136245#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 136244#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 136243#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136241#L721-42 assume 1 == ~t6_pc~0; 136238#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 136236#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136234#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 136233#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136232#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 136229#L740-42 assume 1 == ~t7_pc~0; 136226#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 136224#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 136222#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 136220#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 136218#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 136215#L759-42 assume 1 == ~t8_pc~0; 136212#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 136210#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 136208#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 136206#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 136204#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 136201#L778-42 assume !(1 == ~t9_pc~0); 136198#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 136196#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 136194#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 136192#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 136190#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 136187#L797-42 assume 1 == ~t10_pc~0; 136184#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 136182#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 136180#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 136178#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 136176#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 136173#L816-42 assume !(1 == ~t11_pc~0); 136170#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 136168#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 136166#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 136164#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 136163#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 136159#L835-42 assume 1 == ~t12_pc~0; 136156#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 136154#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 136153#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 136150#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 136146#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 136142#L854-42 assume 1 == ~t13_pc~0; 136138#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 136133#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 136129#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 136125#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 136121#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136116#L1401-3 assume !(1 == ~M_E~0); 131147#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 136113#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 126646#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 136097#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 136095#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 136092#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 136090#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 136088#L1436-3 assume !(1 == ~T8_E~0); 126837#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 136085#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 136083#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 136081#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 136079#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 136077#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 136075#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 136073#L1476-3 assume !(1 == ~E_3~0); 132312#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 136070#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 136068#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 136066#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 136064#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 136062#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 136060#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 136058#L1516-3 assume !(1 == ~E_11~0); 130484#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 136055#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 136053#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 136026#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 136022#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 136020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 136018#L1911 assume !(0 == start_simulation_~tmp~3#1); 136019#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 138843#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 138829#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 138827#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 138825#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138823#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 138821#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 138812#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 138811#L1892-2 [2024-11-13 13:49:18,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:18,338 INFO L85 PathProgramCache]: Analyzing trace with hash -645040329, now seen corresponding path program 1 times [2024-11-13 13:49:18,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:18,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069617084] [2024-11-13 13:49:18,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:18,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:18,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:18,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:18,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:18,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069617084] [2024-11-13 13:49:18,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069617084] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:18,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:18,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:49:18,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [335858022] [2024-11-13 13:49:18,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:18,457 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:18,457 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:18,457 INFO L85 PathProgramCache]: Analyzing trace with hash -2076683578, now seen corresponding path program 1 times [2024-11-13 13:49:18,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:18,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1489534500] [2024-11-13 13:49:18,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:18,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:18,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:18,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:18,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:18,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1489534500] [2024-11-13 13:49:18,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1489534500] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:18,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:18,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:49:18,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853711920] [2024-11-13 13:49:18,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:18,550 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:18,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:18,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:18,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:18,551 INFO L87 Difference]: Start difference. First operand 25928 states and 37865 transitions. cyclomatic complexity: 11945 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:18,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:18,822 INFO L93 Difference]: Finished difference Result 50583 states and 73532 transitions. [2024-11-13 13:49:18,822 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50583 states and 73532 transitions. [2024-11-13 13:49:19,170 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 50304 [2024-11-13 13:49:19,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50583 states to 50583 states and 73532 transitions. [2024-11-13 13:49:19,352 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50583 [2024-11-13 13:49:19,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50583 [2024-11-13 13:49:19,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50583 states and 73532 transitions. [2024-11-13 13:49:19,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:19,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50583 states and 73532 transitions. [2024-11-13 13:49:19,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50583 states and 73532 transitions. [2024-11-13 13:49:20,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50583 to 50551. [2024-11-13 13:49:20,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50551 states, 50551 states have (on average 1.4539771715693062) internal successors, (73500), 50550 states have internal predecessors, (73500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:20,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50551 states to 50551 states and 73500 transitions. [2024-11-13 13:49:20,828 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50551 states and 73500 transitions. [2024-11-13 13:49:20,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:20,829 INFO L424 stractBuchiCegarLoop]: Abstraction has 50551 states and 73500 transitions. [2024-11-13 13:49:20,829 INFO L331 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-13 13:49:20,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50551 states and 73500 transitions. [2024-11-13 13:49:21,199 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 50272 [2024-11-13 13:49:21,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:21,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:21,202 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:21,202 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:21,203 INFO L745 eck$LassoCheckResult]: Stem: 203094#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 203095#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 204009#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 204010#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 204923#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 204450#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 204451#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 203316#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 203317#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 203798#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 203631#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 203632#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 203381#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 203382#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 203806#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 203997#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 204176#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 204216#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 203397#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 203398#L1258 assume !(0 == ~M_E~0); 204725#L1258-2 assume !(0 == ~T1_E~0); 203716#L1263-1 assume !(0 == ~T2_E~0); 203717#L1268-1 assume !(0 == ~T3_E~0); 204046#L1273-1 assume !(0 == ~T4_E~0); 204697#L1278-1 assume !(0 == ~T5_E~0); 204515#L1283-1 assume !(0 == ~T6_E~0); 204516#L1288-1 assume !(0 == ~T7_E~0); 204842#L1293-1 assume !(0 == ~T8_E~0); 204827#L1298-1 assume !(0 == ~T9_E~0); 204719#L1303-1 assume !(0 == ~T10_E~0); 203193#L1308-1 assume !(0 == ~T11_E~0); 203133#L1313-1 assume !(0 == ~T12_E~0); 203134#L1318-1 assume !(0 == ~T13_E~0); 203139#L1323-1 assume !(0 == ~E_1~0); 203140#L1328-1 assume !(0 == ~E_2~0); 203326#L1333-1 assume !(0 == ~E_3~0); 204368#L1338-1 assume !(0 == ~E_4~0); 204369#L1343-1 assume !(0 == ~E_5~0); 204488#L1348-1 assume !(0 == ~E_6~0); 204890#L1353-1 assume !(0 == ~E_7~0); 204070#L1358-1 assume !(0 == ~E_8~0); 204071#L1363-1 assume !(0 == ~E_9~0); 204394#L1368-1 assume !(0 == ~E_10~0); 202986#L1373-1 assume !(0 == ~E_11~0); 202987#L1378-1 assume !(0 == ~E_12~0); 203269#L1383-1 assume !(0 == ~E_13~0); 203270#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 204074#L607 assume !(1 == ~m_pc~0); 203343#L607-2 is_master_triggered_~__retres1~0#1 := 0; 203344#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 203863#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 203864#L1560 assume !(0 != activate_threads_~tmp~1#1); 203977#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 203154#L626 assume !(1 == ~t1_pc~0); 203155#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 203438#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 203439#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 204379#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 203062#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 203063#L645 assume !(1 == ~t2_pc~0); 203126#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 203127#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 203236#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 203237#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 203951#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203952#L664 assume 1 == ~t3_pc~0; 204878#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 202916#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 202917#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 203587#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 203588#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 204741#L683 assume !(1 == ~t4_pc~0); 204198#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 204145#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 202941#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 202942#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 204324#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 203888#L702 assume 1 == ~t5_pc~0; 203889#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 203823#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 204318#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 204722#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 204596#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 202953#L721 assume !(1 == ~t6_pc~0); 202934#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 202935#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 203086#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 203221#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 203603#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 204254#L740 assume 1 == ~t7_pc~0; 203003#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 202833#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 202834#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 202823#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 202824#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 203527#L759 assume !(1 == ~t8_pc~0); 203528#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 203559#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 204808#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 204461#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 204462#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 204841#L778 assume 1 == ~t9_pc~0; 204678#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 202985#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 203292#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 202859#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 202860#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203166#L797 assume !(1 == ~t10_pc~0); 203167#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 203302#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 204650#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 203712#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 203713#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 204026#L816 assume 1 == ~t11_pc~0; 202894#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 202895#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 203852#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 203609#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 203610#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 204175#L835 assume 1 == ~t12_pc~0; 204041#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 203050#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 202884#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 202885#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 203769#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 203770#L854 assume !(1 == ~t13_pc~0); 203383#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 203384#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 203433#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 203084#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 203085#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 204589#L1401 assume !(1 == ~M_E~0); 203596#L1401-2 assume !(1 == ~T1_E~0); 203597#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 204598#L1411-1 assume !(1 == ~T3_E~0); 228812#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 228810#L1421-1 assume !(1 == ~T5_E~0); 228808#L1426-1 assume !(1 == ~T6_E~0); 228806#L1431-1 assume !(1 == ~T7_E~0); 228804#L1436-1 assume !(1 == ~T8_E~0); 228802#L1441-1 assume !(1 == ~T9_E~0); 228799#L1446-1 assume !(1 == ~T10_E~0); 228797#L1451-1 assume !(1 == ~T11_E~0); 228795#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 228793#L1461-1 assume !(1 == ~T13_E~0); 228791#L1466-1 assume !(1 == ~E_1~0); 228789#L1471-1 assume !(1 == ~E_2~0); 228786#L1476-1 assume !(1 == ~E_3~0); 228784#L1481-1 assume !(1 == ~E_4~0); 228782#L1486-1 assume !(1 == ~E_5~0); 228780#L1491-1 assume !(1 == ~E_6~0); 228778#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 228776#L1501-1 assume !(1 == ~E_8~0); 228773#L1506-1 assume !(1 == ~E_9~0); 228771#L1511-1 assume !(1 == ~E_10~0); 228769#L1516-1 assume !(1 == ~E_11~0); 228765#L1521-1 assume !(1 == ~E_12~0); 228648#L1526-1 assume !(1 == ~E_13~0); 228482#L1531-1 assume { :end_inline_reset_delta_events } true; 228446#L1892-2 [2024-11-13 13:49:21,203 INFO L747 eck$LassoCheckResult]: Loop: 228446#L1892-2 assume !false; 228437#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 228432#L1233-1 assume !false; 228428#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 228378#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 228355#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 228351#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 228345#L1046 assume !(0 != eval_~tmp~0#1); 228346#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 245502#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 245499#L1258-3 assume !(0 == ~M_E~0); 245495#L1258-5 assume !(0 == ~T1_E~0); 245491#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 245487#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 245483#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 245479#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 245475#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 245471#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 245466#L1293-3 assume !(0 == ~T8_E~0); 245464#L1298-3 assume !(0 == ~T9_E~0); 245462#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 245447#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 245445#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 245443#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 245440#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 245438#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 245436#L1333-3 assume !(0 == ~E_3~0); 245434#L1338-3 assume !(0 == ~E_4~0); 245432#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 245430#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 245428#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 245426#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 245424#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 245422#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 245420#L1373-3 assume !(0 == ~E_11~0); 245418#L1378-3 assume !(0 == ~E_12~0); 245416#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 245414#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 245412#L607-42 assume !(1 == ~m_pc~0); 245409#L607-44 is_master_triggered_~__retres1~0#1 := 0; 245407#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 245405#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 245403#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 245401#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 245399#L626-42 assume !(1 == ~t1_pc~0); 245397#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 245394#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 245392#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 245390#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 245388#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 245386#L645-42 assume !(1 == ~t2_pc~0); 245384#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 245382#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 245380#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 245378#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 245375#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 245373#L664-42 assume !(1 == ~t3_pc~0); 245371#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 245368#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 245366#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 245364#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 245362#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 245359#L683-42 assume 1 == ~t4_pc~0; 245357#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 245354#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 245352#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 245350#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 245348#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 245346#L702-42 assume !(1 == ~t5_pc~0); 245344#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 245341#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245339#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 245337#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 245335#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 245332#L721-42 assume !(1 == ~t6_pc~0); 245330#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 245327#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 245325#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 245323#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 245321#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 245318#L740-42 assume 1 == ~t7_pc~0; 245315#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 245313#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 245311#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 245309#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 245307#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 245304#L759-42 assume !(1 == ~t8_pc~0); 245302#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 245299#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 245297#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 245295#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 245293#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 245290#L778-42 assume !(1 == ~t9_pc~0); 245287#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 245285#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 245283#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 245281#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 245279#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 245276#L797-42 assume !(1 == ~t10_pc~0); 245274#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 245271#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 245269#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 245267#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 245265#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 245262#L816-42 assume !(1 == ~t11_pc~0); 245259#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 245257#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 245255#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 245253#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 245251#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 245248#L835-42 assume !(1 == ~t12_pc~0); 245246#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 245243#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 245241#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 245239#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 245237#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 245234#L854-42 assume 1 == ~t13_pc~0; 245232#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 245229#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 245227#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 245225#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 245223#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 245220#L1401-3 assume !(1 == ~M_E~0); 240437#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 245217#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 203170#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 245214#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 245212#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 245209#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 245207#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 245205#L1436-3 assume !(1 == ~T8_E~0); 203358#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 245202#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 245200#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 245197#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 245195#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 245193#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 245191#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 235512#L1476-3 assume !(1 == ~E_3~0); 235510#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 235508#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 235506#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 235504#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 235503#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 235502#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 235501#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 229187#L1516-3 assume !(1 == ~E_11~0); 229185#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 229183#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 229182#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 229157#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 229153#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 229151#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 229148#L1911 assume !(0 == start_simulation_~tmp~3#1); 229145#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 228874#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 228860#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 228857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 228856#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 228764#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 228647#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 228481#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 228446#L1892-2 [2024-11-13 13:49:21,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:21,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1648097194, now seen corresponding path program 1 times [2024-11-13 13:49:21,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:21,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121795221] [2024-11-13 13:49:21,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:21,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:21,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:21,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:21,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:21,301 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121795221] [2024-11-13 13:49:21,301 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [121795221] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:21,301 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:21,301 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:49:21,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285663412] [2024-11-13 13:49:21,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:21,302 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:21,303 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:21,303 INFO L85 PathProgramCache]: Analyzing trace with hash 484031362, now seen corresponding path program 1 times [2024-11-13 13:49:21,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:21,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199116799] [2024-11-13 13:49:21,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:21,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:21,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:21,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:21,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:21,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199116799] [2024-11-13 13:49:21,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199116799] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:21,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:21,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:49:21,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641276292] [2024-11-13 13:49:21,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:21,503 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:21,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:21,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:21,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:21,504 INFO L87 Difference]: Start difference. First operand 50551 states and 73500 transitions. cyclomatic complexity: 22965 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:21,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:21,877 INFO L93 Difference]: Finished difference Result 97214 states and 140809 transitions. [2024-11-13 13:49:21,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97214 states and 140809 transitions. [2024-11-13 13:49:22,412 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 96872 [2024-11-13 13:49:22,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97214 states to 97214 states and 140809 transitions. [2024-11-13 13:49:22,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97214 [2024-11-13 13:49:22,956 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97214 [2024-11-13 13:49:22,956 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97214 states and 140809 transitions. [2024-11-13 13:49:23,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:23,006 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97214 states and 140809 transitions. [2024-11-13 13:49:23,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97214 states and 140809 transitions. [2024-11-13 13:49:24,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97214 to 97150. [2024-11-13 13:49:24,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97150 states, 97150 states have (on average 1.4487390633041688) internal successors, (140745), 97149 states have internal predecessors, (140745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:24,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97150 states to 97150 states and 140745 transitions. [2024-11-13 13:49:24,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97150 states and 140745 transitions. [2024-11-13 13:49:24,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:24,643 INFO L424 stractBuchiCegarLoop]: Abstraction has 97150 states and 140745 transitions. [2024-11-13 13:49:24,643 INFO L331 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-13 13:49:24,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97150 states and 140745 transitions. [2024-11-13 13:49:25,068 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 96808 [2024-11-13 13:49:25,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:25,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:25,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:25,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:25,072 INFO L745 eck$LassoCheckResult]: Stem: 350863#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 350864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 351778#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 351779#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 352628#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 352209#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 352210#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 351085#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 351086#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 351570#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 351403#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 351404#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 351152#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 351153#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 351576#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 351767#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 351945#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 351981#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 351168#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 351169#L1258 assume !(0 == ~M_E~0); 352464#L1258-2 assume !(0 == ~T1_E~0); 351487#L1263-1 assume !(0 == ~T2_E~0); 351488#L1268-1 assume !(0 == ~T3_E~0); 351816#L1273-1 assume !(0 == ~T4_E~0); 352437#L1278-1 assume !(0 == ~T5_E~0); 352271#L1283-1 assume !(0 == ~T6_E~0); 352272#L1288-1 assume !(0 == ~T7_E~0); 352567#L1293-1 assume !(0 == ~T8_E~0); 352548#L1298-1 assume !(0 == ~T9_E~0); 352459#L1303-1 assume !(0 == ~T10_E~0); 350962#L1308-1 assume !(0 == ~T11_E~0); 350905#L1313-1 assume !(0 == ~T12_E~0); 350906#L1318-1 assume !(0 == ~T13_E~0); 350910#L1323-1 assume !(0 == ~E_1~0); 350911#L1328-1 assume !(0 == ~E_2~0); 351096#L1333-1 assume !(0 == ~E_3~0); 352129#L1338-1 assume !(0 == ~E_4~0); 352130#L1343-1 assume !(0 == ~E_5~0); 352244#L1348-1 assume !(0 == ~E_6~0); 352599#L1353-1 assume !(0 == ~E_7~0); 351839#L1358-1 assume !(0 == ~E_8~0); 351840#L1363-1 assume !(0 == ~E_9~0); 352152#L1368-1 assume !(0 == ~E_10~0); 350756#L1373-1 assume !(0 == ~E_11~0); 350757#L1378-1 assume !(0 == ~E_12~0); 351040#L1383-1 assume !(0 == ~E_13~0); 351041#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 351843#L607 assume !(1 == ~m_pc~0); 351115#L607-2 is_master_triggered_~__retres1~0#1 := 0; 351116#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 351639#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 351640#L1560 assume !(0 != activate_threads_~tmp~1#1); 351747#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350923#L626 assume !(1 == ~t1_pc~0); 350924#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 351212#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 351213#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 352137#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 350832#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350833#L645 assume !(1 == ~t2_pc~0); 350895#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 350896#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 351007#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 351008#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 351722#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 351723#L664 assume !(1 == ~t3_pc~0); 352172#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 350694#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350695#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 351359#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 351360#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 352476#L683 assume !(1 == ~t4_pc~0); 351963#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 351915#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350714#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350715#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 352083#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 351664#L702 assume 1 == ~t5_pc~0; 351665#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 351592#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 352076#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 352462#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 352350#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350730#L721 assume !(1 == ~t6_pc~0); 350707#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 350708#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350855#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 350990#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 351375#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 352012#L740 assume 1 == ~t7_pc~0; 350772#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 350607#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350608#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 350597#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 350598#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 351300#L759 assume !(1 == ~t8_pc~0); 351301#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 351331#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 352539#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 352220#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 352221#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 352565#L778 assume 1 == ~t9_pc~0; 352417#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 350755#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 351061#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 350633#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 350634#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 350937#L797 assume !(1 == ~t10_pc~0); 350938#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 351071#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352392#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 351483#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 351484#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 351795#L816 assume 1 == ~t11_pc~0; 350670#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 350671#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 351625#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 351381#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 351382#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 351944#L835 assume 1 == ~t12_pc~0; 351810#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 350819#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 350658#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 350659#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 351539#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 351540#L854 assume !(1 == ~t13_pc~0); 351154#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 351155#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 351207#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 350853#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 350854#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352344#L1401 assume !(1 == ~M_E~0); 351368#L1401-2 assume !(1 == ~T1_E~0); 351369#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 352351#L1411-1 assume !(1 == ~T3_E~0); 356766#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 351634#L1421-1 assume !(1 == ~T5_E~0); 351635#L1426-1 assume !(1 == ~T6_E~0); 356758#L1431-1 assume !(1 == ~T7_E~0); 350705#L1436-1 assume !(1 == ~T8_E~0); 350706#L1441-1 assume !(1 == ~T9_E~0); 351865#L1446-1 assume !(1 == ~T10_E~0); 356637#L1451-1 assume !(1 == ~T11_E~0); 356635#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 356633#L1461-1 assume !(1 == ~T13_E~0); 356631#L1466-1 assume !(1 == ~E_1~0); 356629#L1471-1 assume !(1 == ~E_2~0); 355601#L1476-1 assume !(1 == ~E_3~0); 355599#L1481-1 assume !(1 == ~E_4~0); 355597#L1486-1 assume !(1 == ~E_5~0); 355484#L1491-1 assume !(1 == ~E_6~0); 355477#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 355469#L1501-1 assume !(1 == ~E_8~0); 355460#L1506-1 assume !(1 == ~E_9~0); 355149#L1511-1 assume !(1 == ~E_10~0); 355108#L1516-1 assume !(1 == ~E_11~0); 355095#L1521-1 assume !(1 == ~E_12~0); 355085#L1526-1 assume !(1 == ~E_13~0); 355075#L1531-1 assume { :end_inline_reset_delta_events } true; 355067#L1892-2 [2024-11-13 13:49:25,072 INFO L747 eck$LassoCheckResult]: Loop: 355067#L1892-2 assume !false; 355062#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 355060#L1233-1 assume !false; 355058#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 355054#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 355039#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 355037#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 355035#L1046 assume !(0 != eval_~tmp~0#1); 355036#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 375166#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 375162#L1258-3 assume !(0 == ~M_E~0); 375158#L1258-5 assume !(0 == ~T1_E~0); 375154#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 375150#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 375143#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 375138#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 375133#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 375128#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 375123#L1293-3 assume !(0 == ~T8_E~0); 375118#L1298-3 assume !(0 == ~T9_E~0); 375112#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 375106#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 375101#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 375095#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 375090#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 375085#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 375079#L1333-3 assume !(0 == ~E_3~0); 375073#L1338-3 assume !(0 == ~E_4~0); 375068#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 375062#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 375057#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 375052#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 375046#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 375040#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 375035#L1373-3 assume !(0 == ~E_11~0); 375031#L1378-3 assume !(0 == ~E_12~0); 375027#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 375024#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 375020#L607-42 assume !(1 == ~m_pc~0); 375015#L607-44 is_master_triggered_~__retres1~0#1 := 0; 375011#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 375006#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 375003#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 374999#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 374995#L626-42 assume 1 == ~t1_pc~0; 374989#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 374985#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 374980#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 374976#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 374972#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 374968#L645-42 assume !(1 == ~t2_pc~0); 374963#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 374959#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 374955#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 374951#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 374947#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 374943#L664-42 assume !(1 == ~t3_pc~0); 374938#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 374933#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 374927#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 374922#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 374917#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 374912#L683-42 assume !(1 == ~t4_pc~0); 374905#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 374901#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 374895#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 374891#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 374887#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 374886#L702-42 assume !(1 == ~t5_pc~0); 374885#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 374883#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 374882#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 374881#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 374880#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 374879#L721-42 assume 1 == ~t6_pc~0; 374877#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 374876#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 374874#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 374872#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 374870#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 374868#L740-42 assume 1 == ~t7_pc~0; 374865#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 374863#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 374861#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 374860#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 374858#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 374856#L759-42 assume 1 == ~t8_pc~0; 374853#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 374851#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 374849#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 374847#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 374845#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 374844#L778-42 assume !(1 == ~t9_pc~0); 374839#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 374837#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 374835#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 374832#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 374830#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 374828#L797-42 assume 1 == ~t10_pc~0; 374825#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 374823#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 374821#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 374820#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 374817#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 374815#L816-42 assume 1 == ~t11_pc~0; 374813#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 374810#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 374808#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 374790#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 374784#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 374779#L835-42 assume !(1 == ~t12_pc~0); 374773#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 374767#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 374762#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 374756#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 374750#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 374745#L854-42 assume 1 == ~t13_pc~0; 374740#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 374734#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 374728#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 374722#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 359851#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 358421#L1401-3 assume !(1 == ~M_E~0); 358418#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 358416#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 355686#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 358411#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 358409#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 358407#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 358405#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 356718#L1436-3 assume !(1 == ~T8_E~0); 356717#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 356713#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 356711#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 356709#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 356707#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 356705#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 356703#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 355973#L1476-3 assume !(1 == ~E_3~0); 355971#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 355969#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 355967#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 355964#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 355962#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 355960#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 355958#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 355629#L1516-3 assume !(1 == ~E_11~0); 355627#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 355625#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 355623#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 355490#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 355479#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 355471#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 355462#L1911 assume !(0 == start_simulation_~tmp~3#1); 355456#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 355144#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 355129#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 355127#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 355105#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 355094#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 355084#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 355074#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 355067#L1892-2 [2024-11-13 13:49:25,073 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:25,073 INFO L85 PathProgramCache]: Analyzing trace with hash -1375101771, now seen corresponding path program 1 times [2024-11-13 13:49:25,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:25,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001932170] [2024-11-13 13:49:25,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:25,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:25,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:25,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:25,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:25,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2001932170] [2024-11-13 13:49:25,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2001932170] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:25,175 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:25,175 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:49:25,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754978906] [2024-11-13 13:49:25,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:25,175 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:25,176 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:25,176 INFO L85 PathProgramCache]: Analyzing trace with hash -486354170, now seen corresponding path program 1 times [2024-11-13 13:49:25,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:25,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467028008] [2024-11-13 13:49:25,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:25,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:25,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:25,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:25,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:25,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467028008] [2024-11-13 13:49:25,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [467028008] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:25,238 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:25,238 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:25,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858447323] [2024-11-13 13:49:25,238 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:25,239 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:25,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:25,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:49:25,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:49:25,239 INFO L87 Difference]: Start difference. First operand 97150 states and 140745 transitions. cyclomatic complexity: 43627 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:26,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:26,087 INFO L93 Difference]: Finished difference Result 99601 states and 143196 transitions. [2024-11-13 13:49:26,087 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99601 states and 143196 transitions. [2024-11-13 13:49:26,451 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99256 [2024-11-13 13:49:26,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99601 states to 99601 states and 143196 transitions. [2024-11-13 13:49:26,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99601 [2024-11-13 13:49:26,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99601 [2024-11-13 13:49:26,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99601 states and 143196 transitions. [2024-11-13 13:49:27,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:27,236 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99601 states and 143196 transitions. [2024-11-13 13:49:27,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99601 states and 143196 transitions. [2024-11-13 13:49:28,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99601 to 99601. [2024-11-13 13:49:28,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99601 states, 99601 states have (on average 1.4376964086705957) internal successors, (143196), 99600 states have internal predecessors, (143196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:28,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99601 states to 99601 states and 143196 transitions. [2024-11-13 13:49:28,600 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99601 states and 143196 transitions. [2024-11-13 13:49:28,601 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:49:28,601 INFO L424 stractBuchiCegarLoop]: Abstraction has 99601 states and 143196 transitions. [2024-11-13 13:49:28,601 INFO L331 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-13 13:49:28,601 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99601 states and 143196 transitions. [2024-11-13 13:49:28,884 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99256 [2024-11-13 13:49:28,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:28,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:28,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:28,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:28,888 INFO L745 eck$LassoCheckResult]: Stem: 547622#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 547623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 548554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 548555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 549441#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 548986#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 548987#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 547846#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 547847#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 548338#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 548168#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 548169#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 547914#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 547915#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 548344#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 548545#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 548719#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 548755#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 547930#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 547931#L1258 assume !(0 == ~M_E~0); 549267#L1258-2 assume !(0 == ~T1_E~0); 548252#L1263-1 assume !(0 == ~T2_E~0); 548253#L1268-1 assume !(0 == ~T3_E~0); 548592#L1273-1 assume !(0 == ~T4_E~0); 549242#L1278-1 assume !(0 == ~T5_E~0); 549066#L1283-1 assume !(0 == ~T6_E~0); 549067#L1288-1 assume !(0 == ~T7_E~0); 549370#L1293-1 assume !(0 == ~T8_E~0); 549357#L1298-1 assume !(0 == ~T9_E~0); 549260#L1303-1 assume !(0 == ~T10_E~0); 547721#L1308-1 assume !(0 == ~T11_E~0); 547661#L1313-1 assume !(0 == ~T12_E~0); 547662#L1318-1 assume !(0 == ~T13_E~0); 547669#L1323-1 assume !(0 == ~E_1~0); 547670#L1328-1 assume !(0 == ~E_2~0); 547857#L1333-1 assume !(0 == ~E_3~0); 548901#L1338-1 assume !(0 == ~E_4~0); 548902#L1343-1 assume !(0 == ~E_5~0); 549031#L1348-1 assume !(0 == ~E_6~0); 549407#L1353-1 assume !(0 == ~E_7~0); 548616#L1358-1 assume !(0 == ~E_8~0); 548617#L1363-1 assume !(0 == ~E_9~0); 548926#L1368-1 assume !(0 == ~E_10~0); 547515#L1373-1 assume !(0 == ~E_11~0); 547516#L1378-1 assume !(0 == ~E_12~0); 547800#L1383-1 assume !(0 == ~E_13~0); 547801#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 548620#L607 assume !(1 == ~m_pc~0); 547874#L607-2 is_master_triggered_~__retres1~0#1 := 0; 547875#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 548407#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 548408#L1560 assume !(0 != activate_threads_~tmp~1#1); 548522#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 547682#L626 assume !(1 == ~t1_pc~0); 547683#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 547971#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 547972#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 548909#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 547590#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 547591#L645 assume !(1 == ~t2_pc~0); 547654#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 547655#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547765#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 547766#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 548496#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 548497#L664 assume !(1 == ~t3_pc~0); 548948#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 547452#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 547453#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 548124#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 548125#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 549280#L683 assume !(1 == ~t4_pc~0); 548739#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 548911#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 547474#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 547475#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 548856#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 548433#L702 assume 1 == ~t5_pc~0; 548434#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 548361#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 548851#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 549264#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 549149#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 547489#L721 assume !(1 == ~t6_pc~0); 547467#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 547468#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 547614#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 547750#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 548140#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548790#L740 assume 1 == ~t7_pc~0; 547531#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 547367#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 547368#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 547357#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 547358#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 548065#L759 assume !(1 == ~t8_pc~0); 548066#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 548096#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 549341#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 548997#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 548998#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 549368#L778 assume 1 == ~t9_pc~0; 549222#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 547514#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 547821#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 547393#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 547394#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 547696#L797 assume !(1 == ~t10_pc~0); 547697#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 547832#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 549193#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 548248#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 548249#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 548571#L816 assume 1 == ~t11_pc~0; 547430#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 547431#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 548395#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 548146#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 548147#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 548718#L835 assume 1 == ~t12_pc~0; 548587#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 547578#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 547418#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 547419#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 548307#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 548308#L854 assume !(1 == ~t13_pc~0); 547916#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 547917#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 547966#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 547612#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 547613#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 549141#L1401 assume !(1 == ~M_E~0); 548133#L1401-2 assume !(1 == ~T1_E~0); 548134#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 549150#L1411-1 assume !(1 == ~T3_E~0); 549390#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 548403#L1421-1 assume !(1 == ~T5_E~0); 547912#L1426-1 assume !(1 == ~T6_E~0); 547913#L1431-1 assume !(1 == ~T7_E~0); 547465#L1436-1 assume !(1 == ~T8_E~0); 547466#L1441-1 assume !(1 == ~T9_E~0); 573923#L1446-1 assume !(1 == ~T10_E~0); 573921#L1451-1 assume !(1 == ~T11_E~0); 549027#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 548640#L1461-1 assume !(1 == ~T13_E~0); 548162#L1466-1 assume !(1 == ~E_1~0); 548163#L1471-1 assume !(1 == ~E_2~0); 548995#L1476-1 assume !(1 == ~E_3~0); 548996#L1481-1 assume !(1 == ~E_4~0); 549199#L1486-1 assume !(1 == ~E_5~0); 547734#L1491-1 assume !(1 == ~E_6~0); 547403#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 547404#L1501-1 assume !(1 == ~E_8~0); 548237#L1506-1 assume !(1 == ~E_9~0); 548238#L1511-1 assume !(1 == ~E_10~0); 548190#L1516-1 assume !(1 == ~E_11~0); 547355#L1521-1 assume !(1 == ~E_12~0); 547356#L1526-1 assume !(1 == ~E_13~0); 547402#L1531-1 assume { :end_inline_reset_delta_events } true; 547938#L1892-2 [2024-11-13 13:49:28,888 INFO L747 eck$LassoCheckResult]: Loop: 547938#L1892-2 assume !false; 594155#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 594148#L1233-1 assume !false; 594142#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 593967#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 593930#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 593921#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 593911#L1046 assume !(0 != eval_~tmp~0#1); 593912#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 594673#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 594671#L1258-3 assume !(0 == ~M_E~0); 594669#L1258-5 assume !(0 == ~T1_E~0); 594667#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 594664#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 594662#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 594660#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 594658#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 594656#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 594654#L1293-3 assume !(0 == ~T8_E~0); 594651#L1298-3 assume !(0 == ~T9_E~0); 594649#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 594647#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 594645#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 594643#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 594641#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 594638#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 594636#L1333-3 assume !(0 == ~E_3~0); 594634#L1338-3 assume !(0 == ~E_4~0); 594632#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 594630#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 594628#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 594625#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 594623#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 594621#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 594619#L1373-3 assume !(0 == ~E_11~0); 594617#L1378-3 assume !(0 == ~E_12~0); 594615#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 594612#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 594610#L607-42 assume !(1 == ~m_pc~0); 594607#L607-44 is_master_triggered_~__retres1~0#1 := 0; 594605#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 594603#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 594601#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 594600#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 594599#L626-42 assume 1 == ~t1_pc~0; 594597#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 594596#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 594595#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 594594#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 594593#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 594592#L645-42 assume !(1 == ~t2_pc~0); 594591#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 594590#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 594589#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 594588#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 594587#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 594586#L664-42 assume !(1 == ~t3_pc~0); 594585#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 594584#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 594583#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 594582#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 594581#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 594580#L683-42 assume 1 == ~t4_pc~0; 594579#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 594577#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 594575#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 594572#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 594571#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 594570#L702-42 assume !(1 == ~t5_pc~0); 594568#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 594566#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 594564#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 594562#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 594560#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 594558#L721-42 assume 1 == ~t6_pc~0; 594555#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 594554#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 594552#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 594550#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 594548#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 594546#L740-42 assume 1 == ~t7_pc~0; 594543#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 594541#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 594539#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 594538#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 594536#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 594534#L759-42 assume 1 == ~t8_pc~0; 594531#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 594529#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 594527#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 594525#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 594523#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 594522#L778-42 assume 1 == ~t9_pc~0; 594520#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 594518#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 594517#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 594516#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 594515#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 594514#L797-42 assume !(1 == ~t10_pc~0); 594513#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 594510#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 594509#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 594508#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 594507#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 594506#L816-42 assume 1 == ~t11_pc~0; 594505#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 594503#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 594502#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 594501#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 594499#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 594496#L835-42 assume 1 == ~t12_pc~0; 594493#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 594491#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 594489#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 594487#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 594485#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 594483#L854-42 assume !(1 == ~t13_pc~0); 594479#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 594477#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 594475#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 594473#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 594471#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 594469#L1401-3 assume !(1 == ~M_E~0); 555320#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 594466#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 561235#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 594463#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 594461#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 594459#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 594457#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 594455#L1436-3 assume !(1 == ~T8_E~0); 561628#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 594452#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 594450#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 594446#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 594444#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 594442#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 594440#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 594437#L1476-3 assume !(1 == ~E_3~0); 570162#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 594434#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 594431#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 594429#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 594427#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 594425#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 594423#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 594421#L1516-3 assume !(1 == ~E_11~0); 565922#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 594417#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 594415#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 594384#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 594380#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 594378#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 594376#L1911 assume !(0 == start_simulation_~tmp~3#1); 594373#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 594371#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 594355#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 594353#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 594351#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 594213#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 594188#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 594173#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 547938#L1892-2 [2024-11-13 13:49:28,889 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:28,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1040734579, now seen corresponding path program 1 times [2024-11-13 13:49:28,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:28,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327499916] [2024-11-13 13:49:28,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:28,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:28,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:28,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:28,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:28,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327499916] [2024-11-13 13:49:28,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327499916] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:28,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:28,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:49:28,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105660779] [2024-11-13 13:49:28,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:28,972 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:28,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:28,973 INFO L85 PathProgramCache]: Analyzing trace with hash -291571609, now seen corresponding path program 1 times [2024-11-13 13:49:28,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:28,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684775212] [2024-11-13 13:49:28,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:28,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:28,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:29,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:29,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:29,027 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684775212] [2024-11-13 13:49:29,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684775212] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:29,027 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:29,027 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:29,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475823364] [2024-11-13 13:49:29,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:29,028 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:29,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:29,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:29,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:29,028 INFO L87 Difference]: Start difference. First operand 99601 states and 143196 transitions. cyclomatic complexity: 43627 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:30,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:30,017 INFO L93 Difference]: Finished difference Result 191608 states and 274545 transitions. [2024-11-13 13:49:30,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191608 states and 274545 transitions. [2024-11-13 13:49:31,406 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 191040 [2024-11-13 13:49:32,048 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191608 states to 191608 states and 274545 transitions. [2024-11-13 13:49:32,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191608 [2024-11-13 13:49:32,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191608 [2024-11-13 13:49:32,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191608 states and 274545 transitions. [2024-11-13 13:49:32,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:32,291 INFO L218 hiAutomatonCegarLoop]: Abstraction has 191608 states and 274545 transitions. [2024-11-13 13:49:32,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191608 states and 274545 transitions. [2024-11-13 13:49:34,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191608 to 191480. [2024-11-13 13:49:34,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191480 states, 191480 states have (on average 1.433136620012534) internal successors, (274417), 191479 states have internal predecessors, (274417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:34,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191480 states to 191480 states and 274417 transitions. [2024-11-13 13:49:34,862 INFO L240 hiAutomatonCegarLoop]: Abstraction has 191480 states and 274417 transitions. [2024-11-13 13:49:34,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-13 13:49:34,863 INFO L424 stractBuchiCegarLoop]: Abstraction has 191480 states and 274417 transitions. [2024-11-13 13:49:34,863 INFO L331 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-13 13:49:34,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191480 states and 274417 transitions. [2024-11-13 13:49:35,817 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 190912 [2024-11-13 13:49:35,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:35,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:35,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:35,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:35,820 INFO L745 eck$LassoCheckResult]: Stem: 838838#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 838839#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 839771#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 839772#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 840731#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 840232#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 840233#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 839066#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 839067#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 839564#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 839389#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 839390#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 839134#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 839135#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 839570#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 839761#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 839942#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 839975#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 839150#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 839151#L1258 assume !(0 == ~M_E~0); 840523#L1258-2 assume !(0 == ~T1_E~0); 839476#L1263-1 assume !(0 == ~T2_E~0); 839477#L1268-1 assume !(0 == ~T3_E~0); 839810#L1273-1 assume !(0 == ~T4_E~0); 840497#L1278-1 assume !(0 == ~T5_E~0); 840300#L1283-1 assume !(0 == ~T6_E~0); 840301#L1288-1 assume !(0 == ~T7_E~0); 840641#L1293-1 assume !(0 == ~T8_E~0); 840626#L1298-1 assume !(0 == ~T9_E~0); 840517#L1303-1 assume !(0 == ~T10_E~0); 838936#L1308-1 assume !(0 == ~T11_E~0); 838877#L1313-1 assume !(0 == ~T12_E~0); 838878#L1318-1 assume !(0 == ~T13_E~0); 838885#L1323-1 assume !(0 == ~E_1~0); 838886#L1328-1 assume !(0 == ~E_2~0); 839076#L1333-1 assume !(0 == ~E_3~0); 840134#L1338-1 assume !(0 == ~E_4~0); 840135#L1343-1 assume !(0 == ~E_5~0); 840271#L1348-1 assume !(0 == ~E_6~0); 840693#L1353-1 assume !(0 == ~E_7~0); 839833#L1358-1 assume !(0 == ~E_8~0); 839834#L1363-1 assume !(0 == ~E_9~0); 840165#L1368-1 assume !(0 == ~E_10~0); 838730#L1373-1 assume !(0 == ~E_11~0); 838731#L1378-1 assume !(0 == ~E_12~0); 839016#L1383-1 assume !(0 == ~E_13~0); 839017#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 839837#L607 assume !(1 == ~m_pc~0); 839098#L607-2 is_master_triggered_~__retres1~0#1 := 0; 839099#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 839630#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 839631#L1560 assume !(0 != activate_threads_~tmp~1#1); 839742#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 838898#L626 assume !(1 == ~t1_pc~0); 838899#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 839193#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839194#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 840144#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 838805#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 838806#L645 assume !(1 == ~t2_pc~0); 838870#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 838871#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 838980#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 838981#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 839716#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 839717#L664 assume !(1 == ~t3_pc~0); 840190#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 838667#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 838668#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 839345#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 839346#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 840536#L683 assume !(1 == ~t4_pc~0); 839959#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 840146#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 838689#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 838690#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 840084#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 839657#L702 assume !(1 == ~t5_pc~0); 839585#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 839586#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 840079#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 840521#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 840392#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 838704#L721 assume !(1 == ~t6_pc~0); 838682#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 838683#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 838830#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 838966#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 839361#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 840013#L740 assume 1 == ~t7_pc~0; 838746#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 838583#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 838584#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 838573#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 838574#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 839284#L759 assume !(1 == ~t8_pc~0); 839285#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 839316#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 840611#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 840242#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 840243#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 840639#L778 assume 1 == ~t9_pc~0; 840477#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 838729#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 839040#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 838608#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 838609#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 838911#L797 assume !(1 == ~t10_pc~0); 838912#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 839052#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 840442#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 839472#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 839473#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 839789#L816 assume 1 == ~t11_pc~0; 838645#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 838646#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 839618#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 839367#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 839368#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 839941#L835 assume 1 == ~t12_pc~0; 839804#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 838793#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 838633#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 838634#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 839531#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 839532#L854 assume !(1 == ~t13_pc~0); 839136#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 839137#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 839186#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 838828#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 838829#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 840385#L1401 assume !(1 == ~M_E~0); 839354#L1401-2 assume !(1 == ~T1_E~0); 839355#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 840393#L1411-1 assume !(1 == ~T3_E~0); 853111#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 839626#L1421-1 assume !(1 == ~T5_E~0); 839132#L1426-1 assume !(1 == ~T6_E~0); 839133#L1431-1 assume !(1 == ~T7_E~0); 838680#L1436-1 assume !(1 == ~T8_E~0); 838681#L1441-1 assume !(1 == ~T9_E~0); 839467#L1446-1 assume !(1 == ~T10_E~0); 839468#L1451-1 assume !(1 == ~T11_E~0); 840267#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 839860#L1461-1 assume !(1 == ~T13_E~0); 839383#L1466-1 assume !(1 == ~E_1~0); 839384#L1471-1 assume !(1 == ~E_2~0); 840240#L1476-1 assume !(1 == ~E_3~0); 840241#L1481-1 assume !(1 == ~E_4~0); 857844#L1486-1 assume !(1 == ~E_5~0); 857841#L1491-1 assume !(1 == ~E_6~0); 838618#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 838619#L1501-1 assume !(1 == ~E_8~0); 839461#L1506-1 assume !(1 == ~E_9~0); 839462#L1511-1 assume !(1 == ~E_10~0); 839412#L1516-1 assume !(1 == ~E_11~0); 838571#L1521-1 assume !(1 == ~E_12~0); 838572#L1526-1 assume !(1 == ~E_13~0); 838617#L1531-1 assume { :end_inline_reset_delta_events } true; 839158#L1892-2 [2024-11-13 13:49:35,820 INFO L747 eck$LassoCheckResult]: Loop: 839158#L1892-2 assume !false; 859050#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 857862#L1233-1 assume !false; 857861#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 857860#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 857846#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 857845#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 857842#L1046 assume !(0 != eval_~tmp~0#1); 857840#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 857839#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 857838#L1258-3 assume !(0 == ~M_E~0); 857836#L1258-5 assume !(0 == ~T1_E~0); 857834#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 857832#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 857831#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 857829#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 857815#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 857813#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 857811#L1293-3 assume !(0 == ~T8_E~0); 857809#L1298-3 assume !(0 == ~T9_E~0); 857807#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 857793#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 857790#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 857788#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 857786#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 857784#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 857782#L1333-3 assume !(0 == ~E_3~0); 857780#L1338-3 assume !(0 == ~E_4~0); 857777#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 857775#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 857773#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 857771#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 857769#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 857767#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 857765#L1373-3 assume !(0 == ~E_11~0); 857764#L1378-3 assume !(0 == ~E_12~0); 857152#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 857149#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 857147#L607-42 assume !(1 == ~m_pc~0); 857111#L607-44 is_master_triggered_~__retres1~0#1 := 0; 857110#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 857109#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 857093#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 857089#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 857069#L626-42 assume 1 == ~t1_pc~0; 857065#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 857062#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 857057#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 857055#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 857053#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 857050#L645-42 assume !(1 == ~t2_pc~0); 857048#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 857046#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 857043#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 857041#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 857038#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 857036#L664-42 assume !(1 == ~t3_pc~0); 857034#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 857032#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 857027#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 857022#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 857017#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 857011#L683-42 assume 1 == ~t4_pc~0; 857005#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 857000#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 856994#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 856990#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 856987#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 856984#L702-42 assume !(1 == ~t5_pc~0); 856981#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 856979#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 856978#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 856977#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 856976#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 856975#L721-42 assume !(1 == ~t6_pc~0); 856973#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 856970#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 856968#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 856966#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 856965#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 856963#L740-42 assume !(1 == ~t7_pc~0); 856961#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 856958#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 856955#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 856953#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 856951#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 856949#L759-42 assume !(1 == ~t8_pc~0); 856947#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 856944#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 856941#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 856939#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 856937#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 856935#L778-42 assume 1 == ~t9_pc~0; 856933#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 856930#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 856928#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 856926#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 856924#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 856922#L797-42 assume !(1 == ~t10_pc~0); 856920#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 856917#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 856915#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 856876#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 856871#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 856866#L816-42 assume 1 == ~t11_pc~0; 856863#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 856857#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 856852#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 856845#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 856703#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 856699#L835-42 assume 1 == ~t12_pc~0; 856697#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 856696#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 856690#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 856684#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 856681#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 856679#L854-42 assume 1 == ~t13_pc~0; 856676#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 856673#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 856671#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 856669#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 856666#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 856664#L1401-3 assume !(1 == ~M_E~0); 855052#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 856661#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 851279#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 856658#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 856654#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 856651#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 856643#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 856073#L1436-3 assume !(1 == ~T8_E~0); 856071#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 856069#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 856067#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 856066#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 856064#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 856062#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 856060#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 855796#L1476-3 assume !(1 == ~E_3~0); 855794#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 855792#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 855790#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 855788#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 855786#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 855783#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 855781#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 855779#L1516-3 assume !(1 == ~E_11~0); 855752#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 855776#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 855774#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 855266#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 855262#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 855260#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 855257#L1911 assume !(0 == start_simulation_~tmp~3#1); 855258#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 859528#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 859513#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 859509#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 859507#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 859505#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 859504#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 859285#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 839158#L1892-2 [2024-11-13 13:49:35,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:35,821 INFO L85 PathProgramCache]: Analyzing trace with hash -944094126, now seen corresponding path program 1 times [2024-11-13 13:49:35,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:35,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426316206] [2024-11-13 13:49:35,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:35,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:35,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:35,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:35,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:35,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426316206] [2024-11-13 13:49:35,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1426316206] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:35,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:35,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:35,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310827090] [2024-11-13 13:49:35,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:35,912 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:35,913 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:35,913 INFO L85 PathProgramCache]: Analyzing trace with hash 312916645, now seen corresponding path program 1 times [2024-11-13 13:49:35,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:35,913 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076232229] [2024-11-13 13:49:35,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:35,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:35,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:35,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:35,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:35,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1076232229] [2024-11-13 13:49:35,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1076232229] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:35,961 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:35,961 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:35,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466557985] [2024-11-13 13:49:35,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:35,961 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:35,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:35,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:49:35,962 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:49:35,962 INFO L87 Difference]: Start difference. First operand 191480 states and 274417 transitions. cyclomatic complexity: 83001 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:38,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:38,396 INFO L93 Difference]: Finished difference Result 459055 states and 654742 transitions. [2024-11-13 13:49:38,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 459055 states and 654742 transitions. [2024-11-13 13:49:40,763 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 457592 [2024-11-13 13:49:42,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 459055 states to 459055 states and 654742 transitions. [2024-11-13 13:49:42,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 459055 [2024-11-13 13:49:42,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 459055 [2024-11-13 13:49:42,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 459055 states and 654742 transitions. [2024-11-13 13:49:42,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-13 13:49:42,538 INFO L218 hiAutomatonCegarLoop]: Abstraction has 459055 states and 654742 transitions. [2024-11-13 13:49:43,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459055 states and 654742 transitions. [2024-11-13 13:49:46,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459055 to 367895. [2024-11-13 13:49:47,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 367895 states, 367895 states have (on average 1.4288805229753054) internal successors, (525678), 367894 states have internal predecessors, (525678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:47,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367895 states to 367895 states and 525678 transitions. [2024-11-13 13:49:47,774 INFO L240 hiAutomatonCegarLoop]: Abstraction has 367895 states and 525678 transitions. [2024-11-13 13:49:47,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:49:47,776 INFO L424 stractBuchiCegarLoop]: Abstraction has 367895 states and 525678 transitions. [2024-11-13 13:49:47,777 INFO L331 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-13 13:49:47,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 367895 states and 525678 transitions. [2024-11-13 13:49:49,378 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 367008 [2024-11-13 13:49:49,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-13 13:49:49,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-13 13:49:49,385 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:49,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:49:49,385 INFO L745 eck$LassoCheckResult]: Stem: 1489380#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1489381#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1490306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1490307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1491207#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1490764#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1490765#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1489603#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1489604#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1490095#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1489924#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1489925#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1489667#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1489668#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1490101#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1490296#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1490477#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1490514#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1489683#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1489684#L1258 assume !(0 == ~M_E~0); 1491042#L1258-2 assume !(0 == ~T1_E~0); 1490010#L1263-1 assume !(0 == ~T2_E~0); 1490011#L1268-1 assume !(0 == ~T3_E~0); 1490343#L1273-1 assume !(0 == ~T4_E~0); 1491011#L1278-1 assume !(0 == ~T5_E~0); 1490834#L1283-1 assume !(0 == ~T6_E~0); 1490835#L1288-1 assume !(0 == ~T7_E~0); 1491136#L1293-1 assume !(0 == ~T8_E~0); 1491120#L1298-1 assume !(0 == ~T9_E~0); 1491029#L1303-1 assume !(0 == ~T10_E~0); 1489478#L1308-1 assume !(0 == ~T11_E~0); 1489422#L1313-1 assume !(0 == ~T12_E~0); 1489423#L1318-1 assume !(0 == ~T13_E~0); 1489427#L1323-1 assume !(0 == ~E_1~0); 1489428#L1328-1 assume !(0 == ~E_2~0); 1489613#L1333-1 assume !(0 == ~E_3~0); 1490665#L1338-1 assume !(0 == ~E_4~0); 1490666#L1343-1 assume !(0 == ~E_5~0); 1490805#L1348-1 assume !(0 == ~E_6~0); 1491166#L1353-1 assume !(0 == ~E_7~0); 1490366#L1358-1 assume !(0 == ~E_8~0); 1490367#L1363-1 assume !(0 == ~E_9~0); 1490695#L1368-1 assume !(0 == ~E_10~0); 1489275#L1373-1 assume !(0 == ~E_11~0); 1489276#L1378-1 assume !(0 == ~E_12~0); 1489554#L1383-1 assume !(0 == ~E_13~0); 1489555#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1490371#L607 assume !(1 == ~m_pc~0); 1489632#L607-2 is_master_triggered_~__retres1~0#1 := 0; 1489633#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1490166#is_master_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1490167#L1560 assume !(0 != activate_threads_~tmp~1#1); 1490273#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1489440#L626 assume !(1 == ~t1_pc~0); 1489441#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1489727#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1489728#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1490674#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 1489349#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1489350#L645 assume !(1 == ~t2_pc~0); 1489412#L645-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1489413#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1489523#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1489524#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 1490248#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1490249#L664 assume !(1 == ~t3_pc~0); 1490719#L664-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1489215#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1489216#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1489880#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 1489881#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1491054#L683 assume !(1 == ~t4_pc~0); 1490496#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1490676#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1489235#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1489236#L1592 assume !(0 != activate_threads_~tmp___3~0#1); 1490618#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1490191#L702 assume !(1 == ~t5_pc~0); 1490119#L702-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1490120#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1490611#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1491034#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 1490915#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1489250#L721 assume !(1 == ~t6_pc~0); 1489228#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1489229#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1489372#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1489507#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 1489896#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1490551#L740 assume !(1 == ~t7_pc~0); 1490552#L740-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1489128#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1489129#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1489118#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 1489119#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1489816#L759 assume !(1 == ~t8_pc~0); 1489817#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1489848#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1491110#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1490775#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 1490776#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1491134#L778 assume 1 == ~t9_pc~0; 1490992#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1489274#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1489577#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1489153#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 1489154#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1489453#L797 assume !(1 == ~t10_pc~0); 1489454#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1489588#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1490962#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1490006#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 1490007#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1490322#L816 assume 1 == ~t11_pc~0; 1489191#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1489192#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1490153#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1489902#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 1489903#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1490476#L835 assume 1 == ~t12_pc~0; 1490338#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1489336#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1489179#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1489180#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 1490065#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1490066#L854 assume !(1 == ~t13_pc~0); 1489669#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1489670#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1489722#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1489370#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1489371#L1664-2 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1490905#L1401 assume !(1 == ~M_E~0); 1489889#L1401-2 assume !(1 == ~T1_E~0); 1489890#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1490916#L1411-1 assume !(1 == ~T3_E~0); 1491153#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1491154#L1421-1 assume !(1 == ~T5_E~0); 1489665#L1426-1 assume !(1 == ~T6_E~0); 1489666#L1431-1 assume !(1 == ~T7_E~0); 1489226#L1436-1 assume !(1 == ~T8_E~0); 1489227#L1441-1 assume !(1 == ~T9_E~0); 1490001#L1446-1 assume !(1 == ~T10_E~0); 1490002#L1451-1 assume !(1 == ~T11_E~0); 1490800#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1490801#L1461-1 assume !(1 == ~T13_E~0); 1489918#L1466-1 assume !(1 == ~E_1~0); 1489919#L1471-1 assume !(1 == ~E_2~0); 1490773#L1476-1 assume !(1 == ~E_3~0); 1490774#L1481-1 assume !(1 == ~E_4~0); 1490968#L1486-1 assume !(1 == ~E_5~0); 1489493#L1491-1 assume !(1 == ~E_6~0); 1489164#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1489165#L1501-1 assume !(1 == ~E_8~0); 1489995#L1506-1 assume !(1 == ~E_9~0); 1489996#L1511-1 assume !(1 == ~E_10~0); 1489947#L1516-1 assume !(1 == ~E_11~0); 1489948#L1521-1 assume !(1 == ~E_12~0); 1780578#L1526-1 assume !(1 == ~E_13~0); 1780577#L1531-1 assume { :end_inline_reset_delta_events } true; 1780575#L1892-2 [2024-11-13 13:49:49,385 INFO L747 eck$LassoCheckResult]: Loop: 1780575#L1892-2 assume !false; 1778631#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1778626#L1233-1 assume !false; 1778624#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1778622#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1778594#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1778592#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1778589#L1046 assume !(0 != eval_~tmp~0#1); 1778586#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1778584#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1778582#L1258-3 assume !(0 == ~M_E~0); 1778580#L1258-5 assume !(0 == ~T1_E~0); 1778578#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1778576#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1778574#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1778572#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1778570#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1778568#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1778566#L1293-3 assume !(0 == ~T8_E~0); 1778564#L1298-3 assume !(0 == ~T9_E~0); 1778562#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1778560#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1778558#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1778556#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1778554#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1778552#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1778550#L1333-3 assume !(0 == ~E_3~0); 1778548#L1338-3 assume !(0 == ~E_4~0); 1778546#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1778544#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1778542#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1778540#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1778538#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1778536#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1778534#L1373-3 assume !(0 == ~E_11~0); 1778532#L1378-3 assume !(0 == ~E_12~0); 1778530#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1778528#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1778526#L607-42 assume !(1 == ~m_pc~0); 1778522#L607-44 is_master_triggered_~__retres1~0#1 := 0; 1778520#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1778518#is_master_triggered_returnLabel#15 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1778516#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1778514#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1778512#L626-42 assume !(1 == ~t1_pc~0); 1778510#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1778506#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1778504#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1778502#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1778500#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1778498#L645-42 assume !(1 == ~t2_pc~0); 1778496#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1778494#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1778492#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1778490#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1778488#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1778486#L664-42 assume !(1 == ~t3_pc~0); 1778484#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1778482#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1778480#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1778478#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1778476#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1778474#L683-42 assume 1 == ~t4_pc~0; 1778472#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1778473#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1781731#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1778461#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1778458#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1778456#L702-42 assume !(1 == ~t5_pc~0); 1778454#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 1778452#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1778450#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1778448#L1600-42 assume !(0 != activate_threads_~tmp___4~0#1); 1778446#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1778444#L721-42 assume !(1 == ~t6_pc~0); 1778442#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1778438#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1778436#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1778434#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1778432#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1778430#L740-42 assume !(1 == ~t7_pc~0); 1597447#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1778428#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1778426#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1778424#L1616-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1778422#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1778420#L759-42 assume !(1 == ~t8_pc~0); 1778418#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 1778414#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1778412#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1778410#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1778408#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1778406#L778-42 assume !(1 == ~t9_pc~0); 1778403#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1778400#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1778398#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1778396#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1778394#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1778392#L797-42 assume !(1 == ~t10_pc~0); 1778390#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 1778386#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1778384#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1778382#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1778380#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1778378#L816-42 assume 1 == ~t11_pc~0; 1778376#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1778372#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1778370#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1778368#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1778366#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1778364#L835-42 assume !(1 == ~t12_pc~0); 1778362#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 1778358#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1778356#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1778354#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1778352#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1778350#L854-42 assume !(1 == ~t13_pc~0); 1778347#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 1778344#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1778342#is_transmit13_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1778340#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1778338#L1664-44 havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1778336#L1401-3 assume !(1 == ~M_E~0); 1777912#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1778334#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1685538#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1778331#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1778329#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1778327#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1778325#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1778321#L1436-3 assume !(1 == ~T8_E~0); 1778320#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1778319#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1778318#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1778317#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1778316#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1778315#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1778314#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1778313#L1476-3 assume !(1 == ~E_3~0); 1744709#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1778312#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1778310#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1778308#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1778307#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1778306#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1778304#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1778302#L1516-3 assume !(1 == ~E_11~0); 1749829#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1778301#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1778300#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1778288#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1778285#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1778284#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1778280#L1911 assume !(0 == start_simulation_~tmp~3#1); 1778281#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1838290#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1838272#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1838266#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1838260#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1809663#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1780580#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1780576#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1780575#L1892-2 [2024-11-13 13:49:49,386 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:49,386 INFO L85 PathProgramCache]: Analyzing trace with hash -37337679, now seen corresponding path program 1 times [2024-11-13 13:49:49,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:49,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825489626] [2024-11-13 13:49:49,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:49,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:49,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:49,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:49,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:49,470 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825489626] [2024-11-13 13:49:49,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825489626] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:49,470 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:49,470 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:49:49,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927904780] [2024-11-13 13:49:49,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:49,471 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-13 13:49:49,471 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:49:49,471 INFO L85 PathProgramCache]: Analyzing trace with hash -1667154719, now seen corresponding path program 1 times [2024-11-13 13:49:49,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:49:49,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460232770] [2024-11-13 13:49:49,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:49:49,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:49:49,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:49:49,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:49:49,516 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:49:49,516 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460232770] [2024-11-13 13:49:49,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460232770] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:49:49,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:49:49,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-13 13:49:49,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815345230] [2024-11-13 13:49:49,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:49:49,517 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-13 13:49:49,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:49:49,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-13 13:49:49,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-13 13:49:49,518 INFO L87 Difference]: Start difference. First operand 367895 states and 525678 transitions. cyclomatic complexity: 157847 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-13 13:49:53,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:49:53,189 INFO L93 Difference]: Finished difference Result 706678 states and 1006731 transitions. [2024-11-13 13:49:53,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 706678 states and 1006731 transitions.