./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 826ab2ba Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:31:13,162 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:31:13,271 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-11-13 13:31:13,277 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:31:13,280 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:31:13,324 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:31:13,327 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:31:13,327 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:31:13,328 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:31:13,328 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:31:13,329 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-13 13:31:13,330 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-13 13:31:13,330 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:31:13,331 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:31:13,331 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:31:13,331 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:31:13,332 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-13 13:31:13,332 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-13 13:31:13,333 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:31:13,333 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-13 13:31:13,333 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-13 13:31:13,333 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-13 13:31:13,333 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:31:13,333 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:31:13,333 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:31:13,334 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:31:13,334 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:31:13,334 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-13 13:31:13,334 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-13 13:31:13,335 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-13 13:31:13,335 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:31:13,335 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-13 13:31:13,335 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-13 13:31:13,335 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-13 13:31:13,336 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-13 13:31:13,336 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-13 13:31:13,336 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-13 13:31:13,337 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-13 13:31:13,337 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-13 13:31:13,337 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 [2024-11-13 13:31:13,690 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:31:13,705 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:31:13,709 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:31:13,711 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:31:13,711 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:31:13,714 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c Unable to find full path for "g++" [2024-11-13 13:31:15,655 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:31:16,059 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:31:16,060 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-11-13 13:31:16,078 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/data/4e7d055c9/0d08ac76e7684cca85b02e411d5d4389/FLAG28c057f84 [2024-11-13 13:31:16,232 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/data/4e7d055c9/0d08ac76e7684cca85b02e411d5d4389 [2024-11-13 13:31:16,239 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:31:16,241 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:31:16,242 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:31:16,242 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:31:16,252 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:31:16,253 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:16,254 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7677c47 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16, skipping insertion in model container [2024-11-13 13:31:16,254 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:16,295 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:31:16,509 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-11-13 13:31:16,736 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:31:16,757 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:31:16,774 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-11-13 13:31:16,921 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:31:16,946 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:31:16,946 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16 WrapperNode [2024-11-13 13:31:16,946 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:31:16,947 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:31:16,948 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:31:16,948 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:31:16,955 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:16,981 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,124 INFO L138 Inliner]: procedures = 17, calls = 10, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 898 [2024-11-13 13:31:17,124 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:31:17,125 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:31:17,126 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:31:17,126 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:31:17,137 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,138 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,160 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,216 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 13:31:17,217 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,217 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,248 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,256 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,264 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,271 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,286 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:31:17,287 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:31:17,287 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:31:17,287 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:31:17,288 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (1/1) ... [2024-11-13 13:31:17,303 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-13 13:31:17,330 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:17,348 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:17,356 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-13 13:31:17,390 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 13:31:17,390 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-13 13:31:17,390 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-13 13:31:17,391 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-13 13:31:17,391 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:31:17,391 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:31:17,643 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:31:17,645 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:31:19,628 INFO L? ?]: Removed 480 outVars from TransFormulas that were not future-live. [2024-11-13 13:31:19,628 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:31:19,656 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:31:19,660 INFO L316 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-13 13:31:19,660 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:19 BoogieIcfgContainer [2024-11-13 13:31:19,660 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:31:19,664 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-13 13:31:19,664 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-13 13:31:19,671 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-13 13:31:19,671 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 13.11 01:31:16" (1/3) ... [2024-11-13 13:31:19,672 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1ff02191 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.11 01:31:19, skipping insertion in model container [2024-11-13 13:31:19,673 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:16" (2/3) ... [2024-11-13 13:31:19,673 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1ff02191 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.11 01:31:19, skipping insertion in model container [2024-11-13 13:31:19,673 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:19" (3/3) ... [2024-11-13 13:31:19,677 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-11-13 13:31:19,698 INFO L217 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-13 13:31:19,701 INFO L154 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c that has 2 procedures, 280 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-13 13:31:19,800 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-13 13:31:19,817 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@75456e0a, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-13 13:31:19,817 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-13 13:31:19,824 INFO L276 IsEmpty]: Start isEmpty. Operand has 280 states, 275 states have (on average 1.4945454545454546) internal successors, (411), 276 states have internal predecessors, (411), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:19,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2024-11-13 13:31:19,844 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:19,845 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:19,846 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:19,851 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:19,852 INFO L85 PathProgramCache]: Analyzing trace with hash -851723277, now seen corresponding path program 1 times [2024-11-13 13:31:19,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:19,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801809357] [2024-11-13 13:31:19,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:19,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:20,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:20,479 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:20,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:20,487 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2024-11-13 13:31:20,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:20,497 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:20,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:20,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801809357] [2024-11-13 13:31:20,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801809357] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:20,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:20,500 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:31:20,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790901616] [2024-11-13 13:31:20,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:20,516 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-13 13:31:20,516 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:20,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-13 13:31:20,550 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 13:31:20,556 INFO L87 Difference]: Start difference. First operand has 280 states, 275 states have (on average 1.4945454545454546) internal successors, (411), 276 states have internal predecessors, (411), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 2 states, 2 states have (on average 58.0) internal successors, (116), 2 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:20,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:20,640 INFO L93 Difference]: Finished difference Result 535 states and 798 transitions. [2024-11-13 13:31:20,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-13 13:31:20,646 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 58.0) internal successors, (116), 2 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 123 [2024-11-13 13:31:20,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:20,661 INFO L225 Difference]: With dead ends: 535 [2024-11-13 13:31:20,661 INFO L226 Difference]: Without dead ends: 277 [2024-11-13 13:31:20,669 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 13:31:20,674 INFO L432 NwaCegarLoop]: 410 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 410 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:20,676 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 410 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-13 13:31:20,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2024-11-13 13:31:20,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 277. [2024-11-13 13:31:20,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277 states, 273 states have (on average 1.4871794871794872) internal successors, (406), 273 states have internal predecessors, (406), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:20,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 410 transitions. [2024-11-13 13:31:20,761 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 410 transitions. Word has length 123 [2024-11-13 13:31:20,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:20,763 INFO L471 AbstractCegarLoop]: Abstraction has 277 states and 410 transitions. [2024-11-13 13:31:20,764 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 58.0) internal successors, (116), 2 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:20,764 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 410 transitions. [2024-11-13 13:31:20,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2024-11-13 13:31:20,769 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:20,770 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:20,770 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2024-11-13 13:31:20,770 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:20,771 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:20,771 INFO L85 PathProgramCache]: Analyzing trace with hash -912801297, now seen corresponding path program 1 times [2024-11-13 13:31:20,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:20,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32600352] [2024-11-13 13:31:20,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:20,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:21,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:22,339 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:22,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:22,347 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2024-11-13 13:31:22,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:22,355 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:22,355 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:22,355 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [32600352] [2024-11-13 13:31:22,355 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [32600352] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:22,355 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:22,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:31:22,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012551412] [2024-11-13 13:31:22,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:22,359 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-13 13:31:22,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:22,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:31:22,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:31:22,361 INFO L87 Difference]: Start difference. First operand 277 states and 410 transitions. Second operand has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:22,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:22,449 INFO L93 Difference]: Finished difference Result 281 states and 414 transitions. [2024-11-13 13:31:22,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:31:22,450 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 123 [2024-11-13 13:31:22,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:22,452 INFO L225 Difference]: With dead ends: 281 [2024-11-13 13:31:22,452 INFO L226 Difference]: Without dead ends: 279 [2024-11-13 13:31:22,455 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:31:22,457 INFO L432 NwaCegarLoop]: 408 mSDtfsCounter, 0 mSDsluCounter, 810 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1218 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:22,458 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1218 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-13 13:31:22,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states. [2024-11-13 13:31:22,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 279. [2024-11-13 13:31:22,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 279 states, 275 states have (on average 1.4836363636363636) internal successors, (408), 275 states have internal predecessors, (408), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:22,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 279 states to 279 states and 412 transitions. [2024-11-13 13:31:22,487 INFO L78 Accepts]: Start accepts. Automaton has 279 states and 412 transitions. Word has length 123 [2024-11-13 13:31:22,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:22,493 INFO L471 AbstractCegarLoop]: Abstraction has 279 states and 412 transitions. [2024-11-13 13:31:22,493 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:22,493 INFO L276 IsEmpty]: Start isEmpty. Operand 279 states and 412 transitions. [2024-11-13 13:31:22,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2024-11-13 13:31:22,496 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:22,496 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:22,496 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-13 13:31:22,496 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:22,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:22,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1769626721, now seen corresponding path program 1 times [2024-11-13 13:31:22,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:22,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876100744] [2024-11-13 13:31:22,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:22,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:22,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:23,167 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:23,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:23,175 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2024-11-13 13:31:23,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:23,185 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:23,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:23,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876100744] [2024-11-13 13:31:23,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876100744] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:23,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:23,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:23,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906650368] [2024-11-13 13:31:23,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:23,189 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-13 13:31:23,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:23,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:31:23,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:23,191 INFO L87 Difference]: Start difference. First operand 279 states and 412 transitions. Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:23,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:23,625 INFO L93 Difference]: Finished difference Result 761 states and 1129 transitions. [2024-11-13 13:31:23,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-13 13:31:23,626 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 124 [2024-11-13 13:31:23,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:23,630 INFO L225 Difference]: With dead ends: 761 [2024-11-13 13:31:23,632 INFO L226 Difference]: Without dead ends: 279 [2024-11-13 13:31:23,633 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:23,634 INFO L432 NwaCegarLoop]: 686 mSDtfsCounter, 635 mSDsluCounter, 1028 mSDsCounter, 0 mSdLazyCounter, 133 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 636 SdHoareTripleChecker+Valid, 1714 SdHoareTripleChecker+Invalid, 145 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 133 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:23,634 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [636 Valid, 1714 Invalid, 145 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 133 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-13 13:31:23,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states. [2024-11-13 13:31:23,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 279. [2024-11-13 13:31:23,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 279 states, 275 states have (on average 1.48) internal successors, (407), 275 states have internal predecessors, (407), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:23,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 279 states to 279 states and 411 transitions. [2024-11-13 13:31:23,666 INFO L78 Accepts]: Start accepts. Automaton has 279 states and 411 transitions. Word has length 124 [2024-11-13 13:31:23,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:23,667 INFO L471 AbstractCegarLoop]: Abstraction has 279 states and 411 transitions. [2024-11-13 13:31:23,667 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:23,667 INFO L276 IsEmpty]: Start isEmpty. Operand 279 states and 411 transitions. [2024-11-13 13:31:23,669 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2024-11-13 13:31:23,669 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:23,669 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:23,670 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-13 13:31:23,673 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:23,674 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:23,674 INFO L85 PathProgramCache]: Analyzing trace with hash -1850420174, now seen corresponding path program 1 times [2024-11-13 13:31:23,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:23,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447368800] [2024-11-13 13:31:23,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:23,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:23,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:24,210 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:24,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:24,214 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-13 13:31:24,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:24,219 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:24,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:24,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447368800] [2024-11-13 13:31:24,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447368800] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:24,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:24,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:31:24,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445999022] [2024-11-13 13:31:24,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:24,223 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-13 13:31:24,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:24,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:31:24,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:31:24,225 INFO L87 Difference]: Start difference. First operand 279 states and 411 transitions. Second operand has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:24,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:24,276 INFO L93 Difference]: Finished difference Result 538 states and 793 transitions. [2024-11-13 13:31:24,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:31:24,277 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 125 [2024-11-13 13:31:24,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:24,279 INFO L225 Difference]: With dead ends: 538 [2024-11-13 13:31:24,279 INFO L226 Difference]: Without dead ends: 281 [2024-11-13 13:31:24,280 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:31:24,281 INFO L432 NwaCegarLoop]: 407 mSDtfsCounter, 0 mSDsluCounter, 804 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1211 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:24,283 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1211 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-13 13:31:24,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states. [2024-11-13 13:31:24,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2024-11-13 13:31:24,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 277 states have (on average 1.476534296028881) internal successors, (409), 277 states have internal predecessors, (409), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:24,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 413 transitions. [2024-11-13 13:31:24,303 INFO L78 Accepts]: Start accepts. Automaton has 281 states and 413 transitions. Word has length 125 [2024-11-13 13:31:24,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:24,304 INFO L471 AbstractCegarLoop]: Abstraction has 281 states and 413 transitions. [2024-11-13 13:31:24,304 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:24,304 INFO L276 IsEmpty]: Start isEmpty. Operand 281 states and 413 transitions. [2024-11-13 13:31:24,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2024-11-13 13:31:24,306 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:24,306 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:24,306 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-11-13 13:31:24,306 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:24,307 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:24,307 INFO L85 PathProgramCache]: Analyzing trace with hash 1668551511, now seen corresponding path program 1 times [2024-11-13 13:31:24,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:24,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362097521] [2024-11-13 13:31:24,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:24,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:24,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:25,008 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:25,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:25,017 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-13 13:31:25,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:25,025 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:25,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:25,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362097521] [2024-11-13 13:31:25,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362097521] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:25,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:25,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:31:25,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213832477] [2024-11-13 13:31:25,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:25,029 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-13 13:31:25,030 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:25,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:31:25,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:31:25,031 INFO L87 Difference]: Start difference. First operand 281 states and 413 transitions. Second operand has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:25,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:25,141 INFO L93 Difference]: Finished difference Result 540 states and 794 transitions. [2024-11-13 13:31:25,142 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:31:25,142 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 126 [2024-11-13 13:31:25,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:25,144 INFO L225 Difference]: With dead ends: 540 [2024-11-13 13:31:25,146 INFO L226 Difference]: Without dead ends: 281 [2024-11-13 13:31:25,147 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:25,148 INFO L432 NwaCegarLoop]: 393 mSDtfsCounter, 372 mSDsluCounter, 395 mSDsCounter, 0 mSdLazyCounter, 31 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 372 SdHoareTripleChecker+Valid, 788 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 31 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:25,148 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [372 Valid, 788 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 31 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-13 13:31:25,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states. [2024-11-13 13:31:25,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2024-11-13 13:31:25,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 277 states have (on average 1.4729241877256318) internal successors, (408), 277 states have internal predecessors, (408), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:25,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 412 transitions. [2024-11-13 13:31:25,168 INFO L78 Accepts]: Start accepts. Automaton has 281 states and 412 transitions. Word has length 126 [2024-11-13 13:31:25,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:25,168 INFO L471 AbstractCegarLoop]: Abstraction has 281 states and 412 transitions. [2024-11-13 13:31:25,168 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:25,168 INFO L276 IsEmpty]: Start isEmpty. Operand 281 states and 412 transitions. [2024-11-13 13:31:25,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2024-11-13 13:31:25,170 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:25,170 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:25,171 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-11-13 13:31:25,171 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:25,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:25,173 INFO L85 PathProgramCache]: Analyzing trace with hash 553444609, now seen corresponding path program 1 times [2024-11-13 13:31:25,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:25,173 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743010347] [2024-11-13 13:31:25,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:25,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:25,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:25,774 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:25,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:25,780 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-13 13:31:25,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:25,786 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:25,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:25,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743010347] [2024-11-13 13:31:25,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [743010347] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:25,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:25,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-13 13:31:25,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220864618] [2024-11-13 13:31:25,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:25,790 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-13 13:31:25,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:25,791 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:31:25,791 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-13 13:31:25,792 INFO L87 Difference]: Start difference. First operand 281 states and 412 transitions. Second operand has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:25,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:25,905 INFO L93 Difference]: Finished difference Result 540 states and 792 transitions. [2024-11-13 13:31:25,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:31:25,906 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 127 [2024-11-13 13:31:25,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:25,908 INFO L225 Difference]: With dead ends: 540 [2024-11-13 13:31:25,908 INFO L226 Difference]: Without dead ends: 281 [2024-11-13 13:31:25,908 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:25,910 INFO L432 NwaCegarLoop]: 393 mSDtfsCounter, 370 mSDsluCounter, 395 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 370 SdHoareTripleChecker+Valid, 788 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:25,910 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [370 Valid, 788 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-13 13:31:25,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states. [2024-11-13 13:31:25,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2024-11-13 13:31:25,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 277 states have (on average 1.4693140794223827) internal successors, (407), 277 states have internal predecessors, (407), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:25,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 411 transitions. [2024-11-13 13:31:25,929 INFO L78 Accepts]: Start accepts. Automaton has 281 states and 411 transitions. Word has length 127 [2024-11-13 13:31:25,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:25,929 INFO L471 AbstractCegarLoop]: Abstraction has 281 states and 411 transitions. [2024-11-13 13:31:25,929 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:25,930 INFO L276 IsEmpty]: Start isEmpty. Operand 281 states and 411 transitions. [2024-11-13 13:31:25,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2024-11-13 13:31:25,932 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:25,932 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:25,932 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-11-13 13:31:25,933 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:25,933 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:25,933 INFO L85 PathProgramCache]: Analyzing trace with hash -326343756, now seen corresponding path program 1 times [2024-11-13 13:31:25,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:25,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354947219] [2024-11-13 13:31:25,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:25,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:26,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:27,352 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:27,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:27,356 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-13 13:31:27,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:27,362 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:27,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:27,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354947219] [2024-11-13 13:31:27,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354947219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:27,363 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:27,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-13 13:31:27,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [343584305] [2024-11-13 13:31:27,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:27,364 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-13 13:31:27,364 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:27,364 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-13 13:31:27,365 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:27,365 INFO L87 Difference]: Start difference. First operand 281 states and 411 transitions. Second operand has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:27,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:27,843 INFO L93 Difference]: Finished difference Result 663 states and 974 transitions. [2024-11-13 13:31:27,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-13 13:31:27,843 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 128 [2024-11-13 13:31:27,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:27,846 INFO L225 Difference]: With dead ends: 663 [2024-11-13 13:31:27,846 INFO L226 Difference]: Without dead ends: 404 [2024-11-13 13:31:27,847 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2024-11-13 13:31:27,847 INFO L432 NwaCegarLoop]: 335 mSDtfsCounter, 620 mSDsluCounter, 1300 mSDsCounter, 0 mSdLazyCounter, 391 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 621 SdHoareTripleChecker+Valid, 1635 SdHoareTripleChecker+Invalid, 394 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 391 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:27,848 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [621 Valid, 1635 Invalid, 394 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 391 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-13 13:31:27,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 404 states. [2024-11-13 13:31:27,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 404 to 403. [2024-11-13 13:31:27,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 403 states, 399 states have (on average 1.4761904761904763) internal successors, (589), 399 states have internal predecessors, (589), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:27,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 593 transitions. [2024-11-13 13:31:27,862 INFO L78 Accepts]: Start accepts. Automaton has 403 states and 593 transitions. Word has length 128 [2024-11-13 13:31:27,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:27,863 INFO L471 AbstractCegarLoop]: Abstraction has 403 states and 593 transitions. [2024-11-13 13:31:27,863 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:27,863 INFO L276 IsEmpty]: Start isEmpty. Operand 403 states and 593 transitions. [2024-11-13 13:31:27,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2024-11-13 13:31:27,865 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:27,865 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:27,865 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-11-13 13:31:27,865 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:27,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:27,866 INFO L85 PathProgramCache]: Analyzing trace with hash 509903304, now seen corresponding path program 1 times [2024-11-13 13:31:27,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:27,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565468742] [2024-11-13 13:31:27,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:27,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:28,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:28,987 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:28,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:28,990 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-13 13:31:28,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:28,993 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:28,993 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:28,993 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565468742] [2024-11-13 13:31:28,993 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565468742] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:28,993 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:28,993 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-13 13:31:28,993 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [995812545] [2024-11-13 13:31:28,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:28,994 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-13 13:31:28,994 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:28,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-13 13:31:28,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:28,999 INFO L87 Difference]: Start difference. First operand 403 states and 593 transitions. Second operand has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:29,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:29,546 INFO L93 Difference]: Finished difference Result 792 states and 1166 transitions. [2024-11-13 13:31:29,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-13 13:31:29,547 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 129 [2024-11-13 13:31:29,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:29,550 INFO L225 Difference]: With dead ends: 792 [2024-11-13 13:31:29,550 INFO L226 Difference]: Without dead ends: 411 [2024-11-13 13:31:29,551 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:29,555 INFO L432 NwaCegarLoop]: 331 mSDtfsCounter, 403 mSDsluCounter, 1633 mSDsCounter, 0 mSdLazyCounter, 472 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 405 SdHoareTripleChecker+Valid, 1964 SdHoareTripleChecker+Invalid, 475 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 472 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:29,555 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [405 Valid, 1964 Invalid, 475 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 472 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-13 13:31:29,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2024-11-13 13:31:29,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 408. [2024-11-13 13:31:29,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 408 states, 404 states have (on average 1.4727722772277227) internal successors, (595), 404 states have internal predecessors, (595), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:29,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 599 transitions. [2024-11-13 13:31:29,578 INFO L78 Accepts]: Start accepts. Automaton has 408 states and 599 transitions. Word has length 129 [2024-11-13 13:31:29,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:29,578 INFO L471 AbstractCegarLoop]: Abstraction has 408 states and 599 transitions. [2024-11-13 13:31:29,578 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:29,578 INFO L276 IsEmpty]: Start isEmpty. Operand 408 states and 599 transitions. [2024-11-13 13:31:29,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2024-11-13 13:31:29,580 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:29,580 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:29,581 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-11-13 13:31:29,581 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:29,581 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:29,581 INFO L85 PathProgramCache]: Analyzing trace with hash 23793489, now seen corresponding path program 1 times [2024-11-13 13:31:29,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:29,582 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340724687] [2024-11-13 13:31:29,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:29,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:29,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:30,719 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:30,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:30,724 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 37 [2024-11-13 13:31:30,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:30,730 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:30,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:30,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [340724687] [2024-11-13 13:31:30,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [340724687] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:30,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:30,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-13 13:31:30,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228233665] [2024-11-13 13:31:30,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:30,732 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-13 13:31:30,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:30,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-13 13:31:30,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:30,735 INFO L87 Difference]: Start difference. First operand 408 states and 599 transitions. Second operand has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:31,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:31,218 INFO L93 Difference]: Finished difference Result 797 states and 1170 transitions. [2024-11-13 13:31:31,219 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-13 13:31:31,219 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 130 [2024-11-13 13:31:31,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:31,221 INFO L225 Difference]: With dead ends: 797 [2024-11-13 13:31:31,221 INFO L226 Difference]: Without dead ends: 411 [2024-11-13 13:31:31,224 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:31,225 INFO L432 NwaCegarLoop]: 332 mSDtfsCounter, 382 mSDsluCounter, 1626 mSDsCounter, 0 mSdLazyCounter, 466 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 383 SdHoareTripleChecker+Valid, 1958 SdHoareTripleChecker+Invalid, 467 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 466 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:31,226 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [383 Valid, 1958 Invalid, 467 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 466 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-13 13:31:31,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2024-11-13 13:31:31,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 409. [2024-11-13 13:31:31,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 409 states, 405 states have (on average 1.471604938271605) internal successors, (596), 405 states have internal predecessors, (596), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:31,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 409 states and 600 transitions. [2024-11-13 13:31:31,254 INFO L78 Accepts]: Start accepts. Automaton has 409 states and 600 transitions. Word has length 130 [2024-11-13 13:31:31,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:31,255 INFO L471 AbstractCegarLoop]: Abstraction has 409 states and 600 transitions. [2024-11-13 13:31:31,255 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:31,255 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 600 transitions. [2024-11-13 13:31:31,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2024-11-13 13:31:31,257 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:31,257 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:31,257 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-11-13 13:31:31,261 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:31,261 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:31,261 INFO L85 PathProgramCache]: Analyzing trace with hash -526365314, now seen corresponding path program 1 times [2024-11-13 13:31:31,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:31,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70927156] [2024-11-13 13:31:31,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:31,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:31,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:31,641 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:31,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:31,645 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 37 [2024-11-13 13:31:31,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:31,648 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:31,648 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:31,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70927156] [2024-11-13 13:31:31,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [70927156] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:31,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:31,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:31,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1957213839] [2024-11-13 13:31:31,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:31,650 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-13 13:31:31,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:31,650 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:31:31,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:31,651 INFO L87 Difference]: Start difference. First operand 409 states and 600 transitions. Second operand has 5 states, 5 states have (on average 24.6) internal successors, (123), 5 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:31,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:31,765 INFO L93 Difference]: Finished difference Result 1161 states and 1705 transitions. [2024-11-13 13:31:31,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:31:31,766 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 24.6) internal successors, (123), 5 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 130 [2024-11-13 13:31:31,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:31,770 INFO L225 Difference]: With dead ends: 1161 [2024-11-13 13:31:31,770 INFO L226 Difference]: Without dead ends: 774 [2024-11-13 13:31:31,771 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-13 13:31:31,772 INFO L432 NwaCegarLoop]: 400 mSDtfsCounter, 334 mSDsluCounter, 1183 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 335 SdHoareTripleChecker+Valid, 1583 SdHoareTripleChecker+Invalid, 44 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:31,773 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [335 Valid, 1583 Invalid, 44 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 44 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-13 13:31:31,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 774 states. [2024-11-13 13:31:31,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 774 to 425. [2024-11-13 13:31:31,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 420 states have (on average 1.4666666666666666) internal successors, (616), 420 states have internal predecessors, (616), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-13 13:31:31,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 622 transitions. [2024-11-13 13:31:31,796 INFO L78 Accepts]: Start accepts. Automaton has 425 states and 622 transitions. Word has length 130 [2024-11-13 13:31:31,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:31,796 INFO L471 AbstractCegarLoop]: Abstraction has 425 states and 622 transitions. [2024-11-13 13:31:31,796 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 24.6) internal successors, (123), 5 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:31,796 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 622 transitions. [2024-11-13 13:31:31,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2024-11-13 13:31:31,799 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:31,799 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:31,799 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-11-13 13:31:31,799 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:31,800 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:31,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1968618997, now seen corresponding path program 1 times [2024-11-13 13:31:31,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:31,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574782834] [2024-11-13 13:31:31,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:31,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:32,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:33,753 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:33,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:33,758 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 38 [2024-11-13 13:31:33,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:33,767 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:33,767 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:33,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574782834] [2024-11-13 13:31:33,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574782834] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:33,768 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:33,768 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-11-13 13:31:33,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295678664] [2024-11-13 13:31:33,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:33,768 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-13 13:31:33,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:33,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-13 13:31:33,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2024-11-13 13:31:33,770 INFO L87 Difference]: Start difference. First operand 425 states and 622 transitions. Second operand has 10 states, 10 states have (on average 12.4) internal successors, (124), 10 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:34,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:34,888 INFO L93 Difference]: Finished difference Result 1546 states and 2268 transitions. [2024-11-13 13:31:34,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-13 13:31:34,889 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 12.4) internal successors, (124), 10 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 131 [2024-11-13 13:31:34,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:34,897 INFO L225 Difference]: With dead ends: 1546 [2024-11-13 13:31:34,897 INFO L226 Difference]: Without dead ends: 1143 [2024-11-13 13:31:34,898 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=67, Invalid=205, Unknown=0, NotChecked=0, Total=272 [2024-11-13 13:31:34,899 INFO L432 NwaCegarLoop]: 632 mSDtfsCounter, 1503 mSDsluCounter, 3419 mSDsCounter, 0 mSdLazyCounter, 687 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1505 SdHoareTripleChecker+Valid, 4051 SdHoareTripleChecker+Invalid, 690 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 687 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:34,899 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [1505 Valid, 4051 Invalid, 690 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 687 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-11-13 13:31:34,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states. [2024-11-13 13:31:34,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 763. [2024-11-13 13:31:34,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 755 states have (on average 1.471523178807947) internal successors, (1111), 755 states have internal predecessors, (1111), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-13 13:31:34,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1123 transitions. [2024-11-13 13:31:34,939 INFO L78 Accepts]: Start accepts. Automaton has 763 states and 1123 transitions. Word has length 131 [2024-11-13 13:31:34,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:34,940 INFO L471 AbstractCegarLoop]: Abstraction has 763 states and 1123 transitions. [2024-11-13 13:31:34,940 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 12.4) internal successors, (124), 10 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:34,941 INFO L276 IsEmpty]: Start isEmpty. Operand 763 states and 1123 transitions. [2024-11-13 13:31:34,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2024-11-13 13:31:34,943 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:34,944 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:34,944 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-11-13 13:31:34,944 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:34,944 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:34,945 INFO L85 PathProgramCache]: Analyzing trace with hash -895861534, now seen corresponding path program 1 times [2024-11-13 13:31:34,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:34,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355769531] [2024-11-13 13:31:34,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:34,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:35,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:35,629 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-13 13:31:35,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:35,661 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 38 [2024-11-13 13:31:35,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:35,664 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-11-13 13:31:35,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:35,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355769531] [2024-11-13 13:31:35,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355769531] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:31:35,666 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1792665190] [2024-11-13 13:31:35,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:35,666 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:35,666 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:35,670 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:31:35,672 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-13 13:31:36,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:36,148 INFO L255 TraceCheckSpWp]: Trace formula consists of 699 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-13 13:31:36,155 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:36,202 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-13 13:31:36,203 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-13 13:31:36,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1792665190] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:36,203 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-13 13:31:36,203 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 6 [2024-11-13 13:31:36,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016789426] [2024-11-13 13:31:36,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:36,204 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-13 13:31:36,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:36,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-13 13:31:36,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-13 13:31:36,205 INFO L87 Difference]: Start difference. First operand 763 states and 1123 transitions. Second operand has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:36,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:36,286 INFO L93 Difference]: Finished difference Result 1484 states and 2184 transitions. [2024-11-13 13:31:36,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-13 13:31:36,287 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 132 [2024-11-13 13:31:36,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:36,290 INFO L225 Difference]: With dead ends: 1484 [2024-11-13 13:31:36,291 INFO L226 Difference]: Without dead ends: 763 [2024-11-13 13:31:36,292 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 136 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-13 13:31:36,293 INFO L432 NwaCegarLoop]: 403 mSDtfsCounter, 0 mSDsluCounter, 1599 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2002 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:36,293 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2002 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-13 13:31:36,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states. [2024-11-13 13:31:36,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 763. [2024-11-13 13:31:36,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 755 states have (on average 1.466225165562914) internal successors, (1107), 755 states have internal predecessors, (1107), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-13 13:31:36,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1119 transitions. [2024-11-13 13:31:36,325 INFO L78 Accepts]: Start accepts. Automaton has 763 states and 1119 transitions. Word has length 132 [2024-11-13 13:31:36,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:36,325 INFO L471 AbstractCegarLoop]: Abstraction has 763 states and 1119 transitions. [2024-11-13 13:31:36,326 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:36,326 INFO L276 IsEmpty]: Start isEmpty. Operand 763 states and 1119 transitions. [2024-11-13 13:31:36,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2024-11-13 13:31:36,329 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:36,329 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:36,355 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-13 13:31:36,533 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:36,534 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:36,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:36,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1436739828, now seen corresponding path program 1 times [2024-11-13 13:31:36,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:36,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631586343] [2024-11-13 13:31:36,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:36,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:36,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:37,309 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 22 [2024-11-13 13:31:37,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:37,312 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 39 [2024-11-13 13:31:37,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:37,315 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:37,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:37,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631586343] [2024-11-13 13:31:37,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631586343] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:37,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:37,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-13 13:31:37,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637036227] [2024-11-13 13:31:37,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:37,317 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-13 13:31:37,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:37,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-13 13:31:37,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:37,319 INFO L87 Difference]: Start difference. First operand 763 states and 1119 transitions. Second operand has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:37,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:37,811 INFO L93 Difference]: Finished difference Result 1525 states and 2235 transitions. [2024-11-13 13:31:37,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-13 13:31:37,812 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 133 [2024-11-13 13:31:37,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:37,815 INFO L225 Difference]: With dead ends: 1525 [2024-11-13 13:31:37,816 INFO L226 Difference]: Without dead ends: 794 [2024-11-13 13:31:37,817 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:37,818 INFO L432 NwaCegarLoop]: 337 mSDtfsCounter, 447 mSDsluCounter, 1646 mSDsCounter, 0 mSdLazyCounter, 434 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 449 SdHoareTripleChecker+Valid, 1983 SdHoareTripleChecker+Invalid, 436 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 434 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:37,818 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [449 Valid, 1983 Invalid, 436 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 434 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-13 13:31:37,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 794 states. [2024-11-13 13:31:37,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 794 to 794. [2024-11-13 13:31:37,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 794 states, 786 states have (on average 1.4631043256997456) internal successors, (1150), 786 states have internal predecessors, (1150), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-13 13:31:37,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 794 states to 794 states and 1162 transitions. [2024-11-13 13:31:37,857 INFO L78 Accepts]: Start accepts. Automaton has 794 states and 1162 transitions. Word has length 133 [2024-11-13 13:31:37,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:37,857 INFO L471 AbstractCegarLoop]: Abstraction has 794 states and 1162 transitions. [2024-11-13 13:31:37,857 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:37,858 INFO L276 IsEmpty]: Start isEmpty. Operand 794 states and 1162 transitions. [2024-11-13 13:31:37,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-11-13 13:31:37,861 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:37,861 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:37,862 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-11-13 13:31:37,862 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:37,862 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:37,862 INFO L85 PathProgramCache]: Analyzing trace with hash 752915177, now seen corresponding path program 1 times [2024-11-13 13:31:37,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:37,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92783622] [2024-11-13 13:31:37,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:37,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:37,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:38,299 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2024-11-13 13:31:38,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:38,303 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 40 [2024-11-13 13:31:38,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:38,305 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:38,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:38,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92783622] [2024-11-13 13:31:38,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92783622] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:38,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:38,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-13 13:31:38,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341666186] [2024-11-13 13:31:38,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:38,308 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-13 13:31:38,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:38,309 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-13 13:31:38,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:38,309 INFO L87 Difference]: Start difference. First operand 794 states and 1162 transitions. Second operand has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:38,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:38,368 INFO L93 Difference]: Finished difference Result 1519 states and 2225 transitions. [2024-11-13 13:31:38,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-13 13:31:38,369 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 134 [2024-11-13 13:31:38,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:38,372 INFO L225 Difference]: With dead ends: 1519 [2024-11-13 13:31:38,372 INFO L226 Difference]: Without dead ends: 763 [2024-11-13 13:31:38,373 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-13 13:31:38,374 INFO L432 NwaCegarLoop]: 404 mSDtfsCounter, 24 mSDsluCounter, 1200 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 1604 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:38,374 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [24 Valid, 1604 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-13 13:31:38,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states. [2024-11-13 13:31:38,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 763. [2024-11-13 13:31:38,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 755 states have (on average 1.4649006622516556) internal successors, (1106), 755 states have internal predecessors, (1106), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-13 13:31:38,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1118 transitions. [2024-11-13 13:31:38,408 INFO L78 Accepts]: Start accepts. Automaton has 763 states and 1118 transitions. Word has length 134 [2024-11-13 13:31:38,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:38,409 INFO L471 AbstractCegarLoop]: Abstraction has 763 states and 1118 transitions. [2024-11-13 13:31:38,409 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:38,409 INFO L276 IsEmpty]: Start isEmpty. Operand 763 states and 1118 transitions. [2024-11-13 13:31:38,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-11-13 13:31:38,411 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:38,412 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:38,412 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-11-13 13:31:38,412 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:38,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:38,412 INFO L85 PathProgramCache]: Analyzing trace with hash -1626696904, now seen corresponding path program 1 times [2024-11-13 13:31:38,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:38,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275921998] [2024-11-13 13:31:38,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:38,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:38,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:39,036 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2024-11-13 13:31:39,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:39,039 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 40 [2024-11-13 13:31:39,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:39,067 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-11-13 13:31:39,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-13 13:31:39,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275921998] [2024-11-13 13:31:39,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275921998] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:39,067 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:39,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-13 13:31:39,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524416814] [2024-11-13 13:31:39,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:39,068 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-13 13:31:39,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-13 13:31:39,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-13 13:31:39,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-13 13:31:39,069 INFO L87 Difference]: Start difference. First operand 763 states and 1118 transitions. Second operand has 6 states, 5 states have (on average 26.0) internal successors, (130), 6 states have internal predecessors, (130), 2 states have call successors, (2), 1 states have call predecessors, (2), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:39,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:39,146 INFO L93 Difference]: Finished difference Result 1451 states and 2131 transitions. [2024-11-13 13:31:39,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-13 13:31:39,147 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 26.0) internal successors, (130), 6 states have internal predecessors, (130), 2 states have call successors, (2), 1 states have call predecessors, (2), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 134 [2024-11-13 13:31:39,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:39,150 INFO L225 Difference]: With dead ends: 1451 [2024-11-13 13:31:39,150 INFO L226 Difference]: Without dead ends: 763 [2024-11-13 13:31:39,152 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-13 13:31:39,152 INFO L432 NwaCegarLoop]: 401 mSDtfsCounter, 0 mSDsluCounter, 1591 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1992 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:39,152 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1992 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-13 13:31:39,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states. [2024-11-13 13:31:39,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 763. [2024-11-13 13:31:39,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 755 states have (on average 1.4622516556291392) internal successors, (1104), 755 states have internal predecessors, (1104), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-13 13:31:39,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1116 transitions. [2024-11-13 13:31:39,181 INFO L78 Accepts]: Start accepts. Automaton has 763 states and 1116 transitions. Word has length 134 [2024-11-13 13:31:39,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:39,183 INFO L471 AbstractCegarLoop]: Abstraction has 763 states and 1116 transitions. [2024-11-13 13:31:39,183 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 26.0) internal successors, (130), 6 states have internal predecessors, (130), 2 states have call successors, (2), 1 states have call predecessors, (2), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:39,183 INFO L276 IsEmpty]: Start isEmpty. Operand 763 states and 1116 transitions. [2024-11-13 13:31:39,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-11-13 13:31:39,186 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:39,186 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:39,186 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-11-13 13:31:39,187 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:39,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:39,187 INFO L85 PathProgramCache]: Analyzing trace with hash -576645736, now seen corresponding path program 1 times [2024-11-13 13:31:39,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-13 13:31:39,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [691956786] [2024-11-13 13:31:39,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:39,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-13 13:31:39,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:39,431 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:31:39,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:31:39,797 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-13 13:31:39,797 INFO L325 BasicCegarLoop]: Counterexample is feasible [2024-11-13 13:31:39,800 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-13 13:31:39,802 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2024-11-13 13:31:39,805 INFO L407 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:39,960 INFO L173 ceAbstractionStarter]: Computing trace abstraction results [2024-11-13 13:31:39,963 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 13.11 01:31:39 BoogieIcfgContainer [2024-11-13 13:31:39,963 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-13 13:31:39,964 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 13:31:39,964 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 13:31:39,964 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 13:31:39,965 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:19" (3/4) ... [2024-11-13 13:31:39,968 INFO L145 WitnessPrinter]: No result that supports witness generation found [2024-11-13 13:31:39,969 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 13:31:39,970 INFO L158 Benchmark]: Toolchain (without parser) took 23729.17ms. Allocated memory was 142.6MB in the beginning and 629.1MB in the end (delta: 486.5MB). Free memory was 117.8MB in the beginning and 392.7MB in the end (delta: -274.9MB). Peak memory consumption was 215.3MB. Max. memory is 16.1GB. [2024-11-13 13:31:39,970 INFO L158 Benchmark]: CDTParser took 1.28ms. Allocated memory is still 142.6MB. Free memory is still 80.7MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:31:39,970 INFO L158 Benchmark]: CACSL2BoogieTranslator took 704.91ms. Allocated memory is still 142.6MB. Free memory was 117.6MB in the beginning and 95.2MB in the end (delta: 22.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-13 13:31:39,970 INFO L158 Benchmark]: Boogie Procedure Inliner took 176.64ms. Allocated memory is still 142.6MB. Free memory was 94.9MB in the beginning and 80.4MB in the end (delta: 14.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:31:39,971 INFO L158 Benchmark]: Boogie Preprocessor took 161.14ms. Allocated memory is still 142.6MB. Free memory was 80.4MB in the beginning and 71.5MB in the end (delta: 8.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:31:39,971 INFO L158 Benchmark]: RCFGBuilder took 2373.77ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 71.5MB in the beginning and 340.7MB in the end (delta: -269.2MB). Peak memory consumption was 36.1MB. Max. memory is 16.1GB. [2024-11-13 13:31:39,971 INFO L158 Benchmark]: TraceAbstraction took 20299.41ms. Allocated memory was 427.8MB in the beginning and 629.1MB in the end (delta: 201.3MB). Free memory was 339.9MB in the beginning and 392.8MB in the end (delta: -52.9MB). Peak memory consumption was 143.2MB. Max. memory is 16.1GB. [2024-11-13 13:31:39,972 INFO L158 Benchmark]: Witness Printer took 4.70ms. Allocated memory is still 629.1MB. Free memory was 392.8MB in the beginning and 392.7MB in the end (delta: 83.8kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-13 13:31:39,974 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.28ms. Allocated memory is still 142.6MB. Free memory is still 80.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 704.91ms. Allocated memory is still 142.6MB. Free memory was 117.6MB in the beginning and 95.2MB in the end (delta: 22.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 176.64ms. Allocated memory is still 142.6MB. Free memory was 94.9MB in the beginning and 80.4MB in the end (delta: 14.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 161.14ms. Allocated memory is still 142.6MB. Free memory was 80.4MB in the beginning and 71.5MB in the end (delta: 8.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2373.77ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 71.5MB in the beginning and 340.7MB in the end (delta: -269.2MB). Peak memory consumption was 36.1MB. Max. memory is 16.1GB. * TraceAbstraction took 20299.41ms. Allocated memory was 427.8MB in the beginning and 629.1MB in the end (delta: 201.3MB). Free memory was 339.9MB in the beginning and 392.8MB in the end (delta: -52.9MB). Peak memory consumption was 143.2MB. Max. memory is 16.1GB. * Witness Printer took 4.70ms. Allocated memory is still 629.1MB. Free memory was 392.8MB in the beginning and 392.7MB in the end (delta: 83.8kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseAnd at line 296, overapproximation of bitwiseAnd at line 157, overapproximation of bitwiseAnd at line 152. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_9 mask_SORT_9 = (SORT_9)-1 >> (sizeof(SORT_9) * 8 - 31); [L30] const SORT_9 msb_SORT_9 = (SORT_9)1 << (31 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 16); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (16 - 1); [L35] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 8); [L36] const SORT_12 msb_SORT_12 = (SORT_12)1 << (8 - 1); [L38] const SORT_20 mask_SORT_20 = (SORT_20)-1 >> (sizeof(SORT_20) * 8 - 32); [L39] const SORT_20 msb_SORT_20 = (SORT_20)1 << (32 - 1); [L41] const SORT_23 mask_SORT_23 = (SORT_23)-1 >> (sizeof(SORT_23) * 8 - 17); [L42] const SORT_23 msb_SORT_23 = (SORT_23)1 << (17 - 1); [L44] const SORT_26 mask_SORT_26 = (SORT_26)-1 >> (sizeof(SORT_26) * 8 - 18); [L45] const SORT_26 msb_SORT_26 = (SORT_26)1 << (18 - 1); [L47] const SORT_29 mask_SORT_29 = (SORT_29)-1 >> (sizeof(SORT_29) * 8 - 19); [L48] const SORT_29 msb_SORT_29 = (SORT_29)1 << (19 - 1); [L50] const SORT_32 mask_SORT_32 = (SORT_32)-1 >> (sizeof(SORT_32) * 8 - 20); [L51] const SORT_32 msb_SORT_32 = (SORT_32)1 << (20 - 1); [L53] const SORT_35 mask_SORT_35 = (SORT_35)-1 >> (sizeof(SORT_35) * 8 - 21); [L54] const SORT_35 msb_SORT_35 = (SORT_35)1 << (21 - 1); [L56] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 22); [L57] const SORT_38 msb_SORT_38 = (SORT_38)1 << (22 - 1); [L59] const SORT_41 mask_SORT_41 = (SORT_41)-1 >> (sizeof(SORT_41) * 8 - 23); [L60] const SORT_41 msb_SORT_41 = (SORT_41)1 << (23 - 1); [L62] const SORT_44 mask_SORT_44 = (SORT_44)-1 >> (sizeof(SORT_44) * 8 - 24); [L63] const SORT_44 msb_SORT_44 = (SORT_44)1 << (24 - 1); [L65] const SORT_47 mask_SORT_47 = (SORT_47)-1 >> (sizeof(SORT_47) * 8 - 25); [L66] const SORT_47 msb_SORT_47 = (SORT_47)1 << (25 - 1); [L68] const SORT_50 mask_SORT_50 = (SORT_50)-1 >> (sizeof(SORT_50) * 8 - 26); [L69] const SORT_50 msb_SORT_50 = (SORT_50)1 << (26 - 1); [L71] const SORT_53 mask_SORT_53 = (SORT_53)-1 >> (sizeof(SORT_53) * 8 - 27); [L72] const SORT_53 msb_SORT_53 = (SORT_53)1 << (27 - 1); [L74] const SORT_56 mask_SORT_56 = (SORT_56)-1 >> (sizeof(SORT_56) * 8 - 28); [L75] const SORT_56 msb_SORT_56 = (SORT_56)1 << (28 - 1); [L77] const SORT_59 mask_SORT_59 = (SORT_59)-1 >> (sizeof(SORT_59) * 8 - 29); [L78] const SORT_59 msb_SORT_59 = (SORT_59)1 << (29 - 1); [L80] const SORT_62 mask_SORT_62 = (SORT_62)-1 >> (sizeof(SORT_62) * 8 - 30); [L81] const SORT_62 msb_SORT_62 = (SORT_62)1 << (30 - 1); [L83] const SORT_72 mask_SORT_72 = (SORT_72)-1 >> (sizeof(SORT_72) * 8 - 3); [L84] const SORT_72 msb_SORT_72 = (SORT_72)1 << (3 - 1); [L86] const SORT_96 mask_SORT_96 = (SORT_96)-1 >> (sizeof(SORT_96) * 8 - 4); [L87] const SORT_96 msb_SORT_96 = (SORT_96)1 << (4 - 1); [L89] const SORT_101 mask_SORT_101 = (SORT_101)-1 >> (sizeof(SORT_101) * 8 - 6); [L90] const SORT_101 msb_SORT_101 = (SORT_101)1 << (6 - 1); [L92] const SORT_1 var_7 = 0; [L93] const SORT_1 var_8 = 1; [L94] const SORT_9 var_10 = 0; [L95] const SORT_12 var_13 = 0; [L96] const SORT_12 var_14 = 200; [L97] const SORT_72 var_73 = 5; [L98] const SORT_11 var_75 = 0; [L99] const SORT_11 var_108 = 200; [L100] const SORT_72 var_113 = 4; [L101] const SORT_72 var_116 = 6; [L102] const SORT_96 var_120 = 9; [L103] const SORT_72 var_137 = 0; [L104] const SORT_96 var_140 = 0; [L106] SORT_1 input_2; [L107] SORT_1 input_3; [L108] SORT_1 input_4; [L110] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L110] SORT_1 state_5 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L111] EXPR __VERIFIER_nondet_ushort() & mask_SORT_11 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L111] SORT_11 state_17 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L112] EXPR __VERIFIER_nondet_ushort() & mask_SORT_11 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L112] SORT_11 state_76 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L113] EXPR __VERIFIER_nondet_uchar() & mask_SORT_96 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L113] SORT_96 state_97 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L114] EXPR __VERIFIER_nondet_uchar() & mask_SORT_96 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L114] SORT_96 state_100 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L116] SORT_11 init_77_arg_1 = var_75; [L117] state_76 = init_77_arg_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] EXPR input_3 & mask_SORT_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] EXPR input_4 & mask_SORT_1 VAL [input_3=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_86_arg_0=1, var_86_arg_1=-255, var_8=1] [L132] EXPR var_86_arg_0 | var_86_arg_1 VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] EXPR var_86 & mask_SORT_1 VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_88_arg_0=1, var_8=1] [L137] EXPR var_88_arg_0 & mask_SORT_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1, var_90_arg_0=0, var_90_arg_1=1] [L144] EXPR var_90_arg_0 ^ var_90_arg_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1, var_93_arg_0=-2, var_93_arg_1=-2] [L151] EXPR var_93_arg_0 | var_93_arg_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] EXPR var_93 & mask_SORT_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_74_arg_0=5, var_75=0, var_7=0, var_8=1] [L157] EXPR var_74_arg_0 & mask_SORT_72 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_15=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L166] EXPR var_15 & mask_SORT_12 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_16_arg_0=0, var_16_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L169] EXPR ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L173] EXPR var_18 & mask_SORT_11 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_21_arg_0=0, var_21_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L178] EXPR ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] EXPR var_21 & mask_SORT_20 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_24_arg_0=0, var_24_arg_1=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L212] EXPR ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] EXPR var_24 & mask_SORT_23 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_27_arg_0=0, var_27_arg_1=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L216] EXPR ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] EXPR var_27 & mask_SORT_26 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_30_arg_0=0, var_30_arg_1=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L220] EXPR ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] EXPR var_30 & mask_SORT_29 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_33_arg_0=0, var_33_arg_1=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L224] EXPR ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] EXPR var_33 & mask_SORT_32 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_36_arg_0=0, var_36_arg_1=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L228] EXPR ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] EXPR var_36 & mask_SORT_35 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_39_arg_0=0, var_39_arg_1=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L232] EXPR ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] EXPR var_39 & mask_SORT_38 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_42_arg_0=0, var_42_arg_1=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L236] EXPR ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] EXPR var_42 & mask_SORT_41 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_45_arg_0=0, var_45_arg_1=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L240] EXPR ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] EXPR var_45 & mask_SORT_44 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_48_arg_0=0, var_48_arg_1=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L244] EXPR ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] EXPR var_48 & mask_SORT_47 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_51_arg_0=0, var_51_arg_1=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L248] EXPR ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] EXPR var_51 & mask_SORT_50 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_54_arg_0=0, var_54_arg_1=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L252] EXPR ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] EXPR var_54 & mask_SORT_53 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_57_arg_0=0, var_57_arg_1=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L256] EXPR ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] EXPR var_57 & mask_SORT_56 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_60_arg_0=0, var_60_arg_1=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L260] EXPR ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] EXPR var_60 & mask_SORT_59 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_63_arg_0=0, var_63_arg_1=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L264] EXPR ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] EXPR var_63 & mask_SORT_62 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_65_arg_0=0, var_65_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L268] EXPR ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_66_arg_0=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L270] EXPR var_66_arg_0 & mask_SORT_9 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L279] EXPR var_68 & mask_SORT_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_69_arg_0=0, var_69_arg_1=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L282] EXPR var_69_arg_0 ^ var_69_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_82_arg_0=-2, var_82_arg_1=-2, var_8=1] [L295] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_8=1] [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] EXPR var_82 & mask_SORT_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_8=1] [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 280 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 20.0s, OverallIterations: 16, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.1s, AutomataDifference: 4.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5100 SdHoareTripleChecker+Valid, 3.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5090 mSDsluCounter, 24901 SdHoareTripleChecker+Invalid, 2.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 18629 mSDsCounter, 24 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 2790 IncrementalHoareTripleChecker+Invalid, 2814 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 24 mSolverCounterUnsat, 6272 mSDtfsCounter, 2790 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 299 GetRequests, 228 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=794occurred in iteration=13, InterpolantAutomatonStates: 87, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 15 MinimizatonAttempts, 735 StatesRemovedByMinimization, 5 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 2.7s SatisfiabilityAnalysisTime, 10.2s InterpolantComputationTime, 2195 NumberOfCodeBlocks, 2195 NumberOfCodeBlocksAsserted, 17 NumberOfCheckSat, 2045 ConstructedInterpolants, 0 QuantifiedInterpolants, 5573 SizeOfPredicates, 0 NumberOfNonLiveVariables, 699 ConjunctsInSsa, 11 ConjunctsInUnsatCore, 16 InterpolantComputations, 15 PerfectInterpolantSequences, 61/64 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-11-13 13:31:40,011 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-826ab2b [2024-11-13 13:31:42,634 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-13 13:31:42,757 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-11-13 13:31:42,773 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-13 13:31:42,773 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-13 13:31:42,804 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-13 13:31:42,805 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-13 13:31:42,805 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-13 13:31:42,806 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-13 13:31:42,806 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-13 13:31:42,806 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-13 13:31:42,806 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-13 13:31:42,806 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-13 13:31:42,807 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-13 13:31:42,807 INFO L153 SettingsManager]: * Use SBE=true [2024-11-13 13:31:42,807 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-13 13:31:42,807 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-13 13:31:42,807 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-13 13:31:42,807 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-13 13:31:42,808 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-13 13:31:42,808 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-13 13:31:42,808 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-11-13 13:31:42,808 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-11-13 13:31:42,808 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-13 13:31:42,808 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-11-13 13:31:42,808 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-13 13:31:42,809 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-13 13:31:42,809 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-13 13:31:42,809 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-13 13:31:42,809 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-13 13:31:42,809 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-13 13:31:42,809 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-13 13:31:42,810 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-13 13:31:42,810 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-13 13:31:42,810 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-13 13:31:42,810 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-11-13 13:31:42,810 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-11-13 13:31:42,810 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-13 13:31:42,810 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-13 13:31:42,811 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-13 13:31:42,811 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-13 13:31:42,811 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 [2024-11-13 13:31:43,089 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-13 13:31:43,097 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-13 13:31:43,100 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-13 13:31:43,101 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-13 13:31:43,101 INFO L274 PluginConnector]: CDTParser initialized [2024-11-13 13:31:43,103 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c Unable to find full path for "g++" [2024-11-13 13:31:44,936 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-13 13:31:45,317 INFO L384 CDTParser]: Found 1 translation units. [2024-11-13 13:31:45,318 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-11-13 13:31:45,335 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/data/bfd519341/90394d37f8c9417e983a45741d186181/FLAG1feb41ada [2024-11-13 13:31:45,544 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/data/bfd519341/90394d37f8c9417e983a45741d186181 [2024-11-13 13:31:45,546 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-13 13:31:45,548 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-13 13:31:45,550 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-13 13:31:45,550 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-13 13:31:45,554 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-13 13:31:45,554 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:31:45" (1/1) ... [2024-11-13 13:31:45,555 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6bcc9589 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:45, skipping insertion in model container [2024-11-13 13:31:45,555 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 01:31:45" (1/1) ... [2024-11-13 13:31:45,582 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-13 13:31:45,772 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-11-13 13:31:45,935 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:31:45,950 INFO L200 MainTranslator]: Completed pre-run [2024-11-13 13:31:45,960 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-11-13 13:31:46,042 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-13 13:31:46,063 INFO L204 MainTranslator]: Completed translation [2024-11-13 13:31:46,063 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46 WrapperNode [2024-11-13 13:31:46,064 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-13 13:31:46,065 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-13 13:31:46,065 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-13 13:31:46,065 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-13 13:31:46,073 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,087 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,139 INFO L138 Inliner]: procedures = 17, calls = 10, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 374 [2024-11-13 13:31:46,143 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-13 13:31:46,144 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-13 13:31:46,144 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-13 13:31:46,144 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-13 13:31:46,169 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,170 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,183 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,219 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-13 13:31:46,219 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,219 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,240 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,247 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,253 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,259 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,267 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-13 13:31:46,268 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-13 13:31:46,272 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-13 13:31:46,272 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-13 13:31:46,273 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (1/1) ... [2024-11-13 13:31:46,283 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-13 13:31:46,304 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:46,320 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-13 13:31:46,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-13 13:31:46,360 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-13 13:31:46,360 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-11-13 13:31:46,360 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-13 13:31:46,360 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-13 13:31:46,361 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-13 13:31:46,361 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-13 13:31:46,573 INFO L238 CfgBuilder]: Building ICFG [2024-11-13 13:31:46,575 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-13 13:31:47,170 INFO L? ?]: Removed 176 outVars from TransFormulas that were not future-live. [2024-11-13 13:31:47,170 INFO L287 CfgBuilder]: Performing block encoding [2024-11-13 13:31:47,181 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-13 13:31:47,182 INFO L316 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-13 13:31:47,182 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:47 BoogieIcfgContainer [2024-11-13 13:31:47,182 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-13 13:31:47,185 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-13 13:31:47,186 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-13 13:31:47,195 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-13 13:31:47,195 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 13.11 01:31:45" (1/3) ... [2024-11-13 13:31:47,196 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6442bc38 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.11 01:31:47, skipping insertion in model container [2024-11-13 13:31:47,196 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 01:31:46" (2/3) ... [2024-11-13 13:31:47,196 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6442bc38 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 13.11 01:31:47, skipping insertion in model container [2024-11-13 13:31:47,196 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:47" (3/3) ... [2024-11-13 13:31:47,198 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-11-13 13:31:47,218 INFO L217 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-13 13:31:47,219 INFO L154 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c that has 2 procedures, 18 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-13 13:31:47,289 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-13 13:31:47,307 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@2a7ec643, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-13 13:31:47,308 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-13 13:31:47,312 INFO L276 IsEmpty]: Start isEmpty. Operand has 18 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:47,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2024-11-13 13:31:47,321 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:47,322 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:47,322 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:47,328 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:47,330 INFO L85 PathProgramCache]: Analyzing trace with hash 584130565, now seen corresponding path program 1 times [2024-11-13 13:31:47,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-13 13:31:47,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [211651931] [2024-11-13 13:31:47,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:47,345 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:47,345 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:47,350 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:31:47,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-13 13:31:47,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:47,697 INFO L255 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-13 13:31:47,704 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:47,734 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-11-13 13:31:47,734 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-13 13:31:47,735 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-13 13:31:47,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [211651931] [2024-11-13 13:31:47,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [211651931] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:47,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-13 13:31:47,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-13 13:31:47,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1316476620] [2024-11-13 13:31:47,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:47,745 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-13 13:31:47,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-13 13:31:47,760 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-13 13:31:47,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 13:31:47,763 INFO L87 Difference]: Start difference. First operand has 18 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:47,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:47,777 INFO L93 Difference]: Finished difference Result 31 states and 40 transitions. [2024-11-13 13:31:47,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-13 13:31:47,779 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 17 [2024-11-13 13:31:47,779 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:47,783 INFO L225 Difference]: With dead ends: 31 [2024-11-13 13:31:47,783 INFO L226 Difference]: Without dead ends: 15 [2024-11-13 13:31:47,785 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-13 13:31:47,788 INFO L432 NwaCegarLoop]: 16 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 16 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:47,789 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-13 13:31:47,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2024-11-13 13:31:47,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2024-11-13 13:31:47,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:47,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2024-11-13 13:31:47,822 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 16 transitions. Word has length 17 [2024-11-13 13:31:47,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:47,822 INFO L471 AbstractCegarLoop]: Abstraction has 15 states and 16 transitions. [2024-11-13 13:31:47,823 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-13 13:31:47,823 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 16 transitions. [2024-11-13 13:31:47,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2024-11-13 13:31:47,824 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:47,824 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:47,846 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-13 13:31:48,028 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:48,029 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:48,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:48,032 INFO L85 PathProgramCache]: Analyzing trace with hash 899554305, now seen corresponding path program 1 times [2024-11-13 13:31:48,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-13 13:31:48,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [815170366] [2024-11-13 13:31:48,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:48,033 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:48,033 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:48,035 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:31:48,036 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-13 13:31:48,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:48,301 INFO L255 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 23 conjuncts are in the unsatisfiable core [2024-11-13 13:31:48,307 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:48,771 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-11-13 13:31:48,772 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:31:49,124 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-13 13:31:49,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [815170366] [2024-11-13 13:31:49,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [815170366] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:31:49,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [324915352] [2024-11-13 13:31:49,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:49,126 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-13 13:31:49,126 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 [2024-11-13 13:31:49,138 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-13 13:31:49,141 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (4)] Waiting until timeout for monitored process [2024-11-13 13:31:49,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:49,577 INFO L255 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-11-13 13:31:49,582 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:49,793 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-13 13:31:49,794 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-13 13:31:49,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [324915352] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-13 13:31:49,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-13 13:31:49,795 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 7 [2024-11-13 13:31:49,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016361407] [2024-11-13 13:31:49,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-13 13:31:49,797 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-13 13:31:49,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-13 13:31:49,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-13 13:31:49,797 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-13 13:31:49,798 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. Second operand has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:49,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:49,915 INFO L93 Difference]: Finished difference Result 24 states and 27 transitions. [2024-11-13 13:31:49,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-13 13:31:49,915 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 17 [2024-11-13 13:31:49,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:49,916 INFO L225 Difference]: With dead ends: 24 [2024-11-13 13:31:49,916 INFO L226 Difference]: Without dead ends: 22 [2024-11-13 13:31:49,917 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2024-11-13 13:31:49,917 INFO L432 NwaCegarLoop]: 11 mSDtfsCounter, 2 mSDsluCounter, 21 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:49,918 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 32 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-13 13:31:49,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2024-11-13 13:31:49,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2024-11-13 13:31:49,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 15 states have internal predecessors, (16), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-13 13:31:49,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 24 transitions. [2024-11-13 13:31:49,929 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 24 transitions. Word has length 17 [2024-11-13 13:31:49,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:49,931 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 24 transitions. [2024-11-13 13:31:49,931 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-13 13:31:49,931 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 24 transitions. [2024-11-13 13:31:49,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2024-11-13 13:31:49,933 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:49,933 INFO L215 NwaCegarLoop]: trace histogram [4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-11-13 13:31:49,940 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (4)] Ended with exit code 0 [2024-11-13 13:31:50,146 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-13 13:31:50,333 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:50,334 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:50,334 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:50,334 INFO L85 PathProgramCache]: Analyzing trace with hash -1718916253, now seen corresponding path program 1 times [2024-11-13 13:31:50,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-13 13:31:50,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1995288640] [2024-11-13 13:31:50,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:50,335 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:50,336 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:50,339 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:31:50,340 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-13 13:31:50,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:50,708 INFO L255 TraceCheckSpWp]: Trace formula consists of 409 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-13 13:31:50,714 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:51,238 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-11-13 13:31:51,238 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:31:51,440 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-13 13:31:51,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1995288640] [2024-11-13 13:31:51,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1995288640] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:31:51,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1249716135] [2024-11-13 13:31:51,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-13 13:31:51,440 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-13 13:31:51,441 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 [2024-11-13 13:31:51,445 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-13 13:31:51,447 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (6)] Waiting until timeout for monitored process [2024-11-13 13:31:52,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-13 13:31:52,161 INFO L255 TraceCheckSpWp]: Trace formula consists of 409 conjuncts, 26 conjuncts are in the unsatisfiable core [2024-11-13 13:31:52,175 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:52,518 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-11-13 13:31:52,518 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:31:52,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1249716135] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:31:52,670 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-13 13:31:52,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 6 [2024-11-13 13:31:52,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547728976] [2024-11-13 13:31:52,671 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-13 13:31:52,671 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-13 13:31:52,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-13 13:31:52,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-13 13:31:52,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:52,672 INFO L87 Difference]: Start difference. First operand 21 states and 24 transitions. Second operand has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-11-13 13:31:52,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:52,878 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2024-11-13 13:31:52,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-13 13:31:52,878 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) Word has length 32 [2024-11-13 13:31:52,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:52,879 INFO L225 Difference]: With dead ends: 31 [2024-11-13 13:31:52,880 INFO L226 Difference]: Without dead ends: 29 [2024-11-13 13:31:52,880 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 63 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90 [2024-11-13 13:31:52,881 INFO L432 NwaCegarLoop]: 11 mSDtfsCounter, 2 mSDsluCounter, 21 mSDsCounter, 0 mSdLazyCounter, 28 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 28 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 28 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:52,881 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 32 Invalid, 28 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 28 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-13 13:31:52,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2024-11-13 13:31:52,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 28. [2024-11-13 13:31:52,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 20 states have (on average 1.05) internal successors, (21), 20 states have internal predecessors, (21), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-13 13:31:52,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2024-11-13 13:31:52,894 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 33 transitions. Word has length 32 [2024-11-13 13:31:52,895 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:52,895 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-11-13 13:31:52,895 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-11-13 13:31:52,895 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2024-11-13 13:31:52,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2024-11-13 13:31:52,896 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:52,896 INFO L215 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-11-13 13:31:52,903 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (6)] Forceful destruction successful, exit code 0 [2024-11-13 13:31:53,110 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-11-13 13:31:53,297 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:53,297 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:53,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:53,298 INFO L85 PathProgramCache]: Analyzing trace with hash -1689441343, now seen corresponding path program 2 times [2024-11-13 13:31:53,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-13 13:31:53,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [121946311] [2024-11-13 13:31:53,299 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-13 13:31:53,299 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:53,299 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:53,302 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:31:53,304 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-13 13:31:53,753 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-13 13:31:53,754 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:31:53,760 INFO L255 TraceCheckSpWp]: Trace formula consists of 578 conjuncts, 25 conjuncts are in the unsatisfiable core [2024-11-13 13:31:53,766 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:54,303 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 19 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-13 13:31:54,304 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:31:54,497 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-13 13:31:54,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [121946311] [2024-11-13 13:31:54,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [121946311] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:31:54,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1253496971] [2024-11-13 13:31:54,498 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-13 13:31:54,498 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-13 13:31:54,498 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 [2024-11-13 13:31:54,500 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-13 13:31:54,504 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (8)] Waiting until timeout for monitored process [2024-11-13 13:31:55,399 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-13 13:31:55,399 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:31:55,408 INFO L255 TraceCheckSpWp]: Trace formula consists of 578 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-11-13 13:31:55,417 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:55,837 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 19 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-13 13:31:55,837 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:31:55,965 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1253496971] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:31:55,966 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-13 13:31:55,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2024-11-13 13:31:55,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652121653] [2024-11-13 13:31:55,966 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-13 13:31:55,967 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-13 13:31:55,967 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-13 13:31:55,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-13 13:31:55,967 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-13 13:31:55,968 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. Second operand has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-13 13:31:56,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:31:56,261 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2024-11-13 13:31:56,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-13 13:31:56,262 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 47 [2024-11-13 13:31:56,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:31:56,263 INFO L225 Difference]: With dead ends: 38 [2024-11-13 13:31:56,263 INFO L226 Difference]: Without dead ends: 36 [2024-11-13 13:31:56,263 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 93 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=38, Invalid=72, Unknown=0, NotChecked=0, Total=110 [2024-11-13 13:31:56,264 INFO L432 NwaCegarLoop]: 15 mSDtfsCounter, 2 mSDsluCounter, 44 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 59 SdHoareTripleChecker+Invalid, 51 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-13 13:31:56,265 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 59 Invalid, 51 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-13 13:31:56,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2024-11-13 13:31:56,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 35. [2024-11-13 13:31:56,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 25 states have (on average 1.04) internal successors, (26), 25 states have internal predecessors, (26), 8 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 8 states have call predecessors, (8), 8 states have call successors, (8) [2024-11-13 13:31:56,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 42 transitions. [2024-11-13 13:31:56,272 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 42 transitions. Word has length 47 [2024-11-13 13:31:56,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:31:56,273 INFO L471 AbstractCegarLoop]: Abstraction has 35 states and 42 transitions. [2024-11-13 13:31:56,273 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-13 13:31:56,273 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 42 transitions. [2024-11-13 13:31:56,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2024-11-13 13:31:56,274 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:31:56,274 INFO L215 NwaCegarLoop]: trace histogram [8, 8, 8, 4, 4, 4, 4, 4, 4, 4, 3, 3, 1, 1, 1, 1] [2024-11-13 13:31:56,281 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (8)] Ended with exit code 0 [2024-11-13 13:31:56,497 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-13 13:31:56,675 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:56,675 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:31:56,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:31:56,676 INFO L85 PathProgramCache]: Analyzing trace with hash -110959709, now seen corresponding path program 3 times [2024-11-13 13:31:56,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-13 13:31:56,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [254149328] [2024-11-13 13:31:56,677 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-13 13:31:56,677 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:31:56,677 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:31:56,679 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:31:56,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-13 13:31:57,252 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2024-11-13 13:31:57,252 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:31:57,260 INFO L255 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-13 13:31:57,270 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:58,003 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2024-11-13 13:31:58,003 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:31:58,154 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-13 13:31:58,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [254149328] [2024-11-13 13:31:58,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [254149328] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:31:58,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [743510697] [2024-11-13 13:31:58,155 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-13 13:31:58,155 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-13 13:31:58,155 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 [2024-11-13 13:31:58,159 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-13 13:31:58,161 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (10)] Waiting until timeout for monitored process [2024-11-13 13:31:59,254 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2024-11-13 13:31:59,254 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:31:59,284 INFO L255 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 37 conjuncts are in the unsatisfiable core [2024-11-13 13:31:59,290 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:31:59,944 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2024-11-13 13:31:59,944 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:32:00,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [743510697] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:32:00,066 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-13 13:32:00,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2024-11-13 13:32:00,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246067343] [2024-11-13 13:32:00,066 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-13 13:32:00,067 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-13 13:32:00,067 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-13 13:32:00,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-13 13:32:00,068 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-11-13 13:32:00,068 INFO L87 Difference]: Start difference. First operand 35 states and 42 transitions. Second operand has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2024-11-13 13:32:00,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:00,445 INFO L93 Difference]: Finished difference Result 45 states and 54 transitions. [2024-11-13 13:32:00,445 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-13 13:32:00,445 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) Word has length 62 [2024-11-13 13:32:00,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:32:00,446 INFO L225 Difference]: With dead ends: 45 [2024-11-13 13:32:00,446 INFO L226 Difference]: Without dead ends: 43 [2024-11-13 13:32:00,447 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 122 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2024-11-13 13:32:00,447 INFO L432 NwaCegarLoop]: 23 mSDtfsCounter, 2 mSDsluCounter, 78 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 101 SdHoareTripleChecker+Invalid, 129 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-13 13:32:00,448 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 101 Invalid, 129 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-13 13:32:00,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2024-11-13 13:32:00,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2024-11-13 13:32:00,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 30 states have (on average 1.0333333333333334) internal successors, (31), 30 states have internal predecessors, (31), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-13 13:32:00,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 51 transitions. [2024-11-13 13:32:00,457 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 51 transitions. Word has length 62 [2024-11-13 13:32:00,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:32:00,458 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 51 transitions. [2024-11-13 13:32:00,458 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2024-11-13 13:32:00,458 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 51 transitions. [2024-11-13 13:32:00,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2024-11-13 13:32:00,460 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:32:00,460 INFO L215 NwaCegarLoop]: trace histogram [10, 10, 10, 5, 5, 5, 5, 5, 5, 5, 4, 4, 1, 1, 1, 1] [2024-11-13 13:32:00,476 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-11-13 13:32:00,666 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (10)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:00,861 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt [2024-11-13 13:32:00,861 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:32:00,861 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:00,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1997417345, now seen corresponding path program 4 times [2024-11-13 13:32:00,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-13 13:32:00,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1440763177] [2024-11-13 13:32:00,862 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-13 13:32:00,862 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:32:00,862 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:00,864 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:32:00,865 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-13 13:32:01,505 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-13 13:32:01,505 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:32:01,514 INFO L255 TraceCheckSpWp]: Trace formula consists of 916 conjuncts, 31 conjuncts are in the unsatisfiable core [2024-11-13 13:32:01,521 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:32:02,244 INFO L134 CoverageAnalysis]: Checked inductivity of 246 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2024-11-13 13:32:02,245 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:32:02,396 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-13 13:32:02,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1440763177] [2024-11-13 13:32:02,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1440763177] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:32:02,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [748092274] [2024-11-13 13:32:02,397 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-13 13:32:02,397 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-13 13:32:02,397 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 [2024-11-13 13:32:02,399 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-13 13:32:02,402 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (12)] Waiting until timeout for monitored process [2024-11-13 13:32:03,752 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-13 13:32:03,752 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:32:03,786 INFO L255 TraceCheckSpWp]: Trace formula consists of 916 conjuncts, 33 conjuncts are in the unsatisfiable core [2024-11-13 13:32:03,793 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:32:04,404 INFO L134 CoverageAnalysis]: Checked inductivity of 246 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2024-11-13 13:32:04,404 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:32:04,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [748092274] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:32:04,505 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-13 13:32:04,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8] total 9 [2024-11-13 13:32:04,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196710772] [2024-11-13 13:32:04,505 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-13 13:32:04,506 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-13 13:32:04,506 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-13 13:32:04,506 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-13 13:32:04,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-13 13:32:04,507 INFO L87 Difference]: Start difference. First operand 42 states and 51 transitions. Second operand has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) [2024-11-13 13:32:05,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:05,014 INFO L93 Difference]: Finished difference Result 52 states and 63 transitions. [2024-11-13 13:32:05,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-13 13:32:05,014 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) Word has length 77 [2024-11-13 13:32:05,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:32:05,015 INFO L225 Difference]: With dead ends: 52 [2024-11-13 13:32:05,016 INFO L226 Difference]: Without dead ends: 50 [2024-11-13 13:32:05,016 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 150 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=58, Invalid=182, Unknown=0, NotChecked=0, Total=240 [2024-11-13 13:32:05,017 INFO L432 NwaCegarLoop]: 27 mSDtfsCounter, 2 mSDsluCounter, 106 mSDsCounter, 0 mSdLazyCounter, 198 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 202 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 198 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-13 13:32:05,017 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 133 Invalid, 202 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 198 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-13 13:32:05,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2024-11-13 13:32:05,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 49. [2024-11-13 13:32:05,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 35 states have (on average 1.0285714285714285) internal successors, (36), 35 states have internal predecessors, (36), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-13 13:32:05,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 60 transitions. [2024-11-13 13:32:05,028 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 60 transitions. Word has length 77 [2024-11-13 13:32:05,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:32:05,029 INFO L471 AbstractCegarLoop]: Abstraction has 49 states and 60 transitions. [2024-11-13 13:32:05,029 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) [2024-11-13 13:32:05,029 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 60 transitions. [2024-11-13 13:32:05,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2024-11-13 13:32:05,031 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:32:05,031 INFO L215 NwaCegarLoop]: trace histogram [12, 12, 12, 6, 6, 6, 6, 6, 6, 6, 5, 5, 1, 1, 1, 1] [2024-11-13 13:32:05,039 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (12)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:05,247 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-13 13:32:05,432 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:32:05,432 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:32:05,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:05,432 INFO L85 PathProgramCache]: Analyzing trace with hash -1626706973, now seen corresponding path program 5 times [2024-11-13 13:32:05,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-13 13:32:05,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1697037749] [2024-11-13 13:32:05,433 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-13 13:32:05,433 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:32:05,433 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:05,435 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:32:05,436 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-13 13:32:06,420 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2024-11-13 13:32:06,420 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:32:06,433 INFO L255 TraceCheckSpWp]: Trace formula consists of 1085 conjuncts, 32 conjuncts are in the unsatisfiable core [2024-11-13 13:32:06,438 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:32:07,269 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2024-11-13 13:32:07,269 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:32:07,404 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-13 13:32:07,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1697037749] [2024-11-13 13:32:07,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1697037749] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:32:07,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [972042109] [2024-11-13 13:32:07,404 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-13 13:32:07,404 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-13 13:32:07,404 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 [2024-11-13 13:32:07,406 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-13 13:32:07,407 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (14)] Waiting until timeout for monitored process [2024-11-13 13:32:09,128 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2024-11-13 13:32:09,128 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-13 13:32:09,171 INFO L255 TraceCheckSpWp]: Trace formula consists of 1085 conjuncts, 34 conjuncts are in the unsatisfiable core [2024-11-13 13:32:09,179 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-13 13:32:10,037 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2024-11-13 13:32:10,037 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-13 13:32:10,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [972042109] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-13 13:32:10,170 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-13 13:32:10,170 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 10 [2024-11-13 13:32:10,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832421185] [2024-11-13 13:32:10,171 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-13 13:32:10,171 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-13 13:32:10,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-13 13:32:10,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-13 13:32:10,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2024-11-13 13:32:10,172 INFO L87 Difference]: Start difference. First operand 49 states and 60 transitions. Second operand has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) [2024-11-13 13:32:10,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-13 13:32:10,840 INFO L93 Difference]: Finished difference Result 59 states and 72 transitions. [2024-11-13 13:32:10,840 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-11-13 13:32:10,841 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) Word has length 92 [2024-11-13 13:32:10,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-13 13:32:10,842 INFO L225 Difference]: With dead ends: 59 [2024-11-13 13:32:10,842 INFO L226 Difference]: Without dead ends: 57 [2024-11-13 13:32:10,842 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 179 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2024-11-13 13:32:10,843 INFO L432 NwaCegarLoop]: 31 mSDtfsCounter, 2 mSDsluCounter, 155 mSDsCounter, 0 mSdLazyCounter, 315 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 186 SdHoareTripleChecker+Invalid, 320 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 315 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-13 13:32:10,843 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 186 Invalid, 320 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 315 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-13 13:32:10,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2024-11-13 13:32:10,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 56. [2024-11-13 13:32:10,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 40 states have (on average 1.025) internal successors, (41), 40 states have internal predecessors, (41), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-11-13 13:32:10,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 69 transitions. [2024-11-13 13:32:10,855 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 69 transitions. Word has length 92 [2024-11-13 13:32:10,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-13 13:32:10,855 INFO L471 AbstractCegarLoop]: Abstraction has 56 states and 69 transitions. [2024-11-13 13:32:10,855 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) [2024-11-13 13:32:10,855 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 69 transitions. [2024-11-13 13:32:10,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2024-11-13 13:32:10,857 INFO L207 NwaCegarLoop]: Found error trace [2024-11-13 13:32:10,857 INFO L215 NwaCegarLoop]: trace histogram [14, 14, 14, 7, 7, 7, 7, 7, 7, 7, 6, 6, 1, 1, 1, 1] [2024-11-13 13:32:10,881 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2024-11-13 13:32:11,068 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt (14)] Ended with exit code 0 [2024-11-13 13:32:11,257 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/cvc4 --incremental --print-success --lang smt [2024-11-13 13:32:11,257 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-13 13:32:11,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-13 13:32:11,258 INFO L85 PathProgramCache]: Analyzing trace with hash -790815935, now seen corresponding path program 6 times [2024-11-13 13:32:11,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-13 13:32:11,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [978255230] [2024-11-13 13:32:11,259 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-13 13:32:11,259 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:32:11,259 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 [2024-11-13 13:32:11,260 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-13 13:32:11,262 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-13 13:32:12,426 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2024-11-13 13:32:12,426 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-13 13:32:12,426 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-13 13:32:12,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-13 13:32:13,168 INFO L130 FreeRefinementEngine]: Strategy FOX found a feasible trace [2024-11-13 13:32:13,168 INFO L325 BasicCegarLoop]: Counterexample is feasible [2024-11-13 13:32:13,169 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-13 13:32:13,202 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-11-13 13:32:13,371 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-13 13:32:13,374 INFO L407 BasicCegarLoop]: Path program histogram: [6, 1, 1] [2024-11-13 13:32:13,538 INFO L173 ceAbstractionStarter]: Computing trace abstraction results [2024-11-13 13:32:13,542 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 13.11 01:32:13 BoogieIcfgContainer [2024-11-13 13:32:13,542 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-13 13:32:13,543 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-13 13:32:13,543 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-13 13:32:13,543 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-13 13:32:13,544 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 01:31:47" (3/4) ... [2024-11-13 13:32:13,547 INFO L136 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-13 13:32:13,821 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/witness.graphml [2024-11-13 13:32:13,822 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-13 13:32:13,823 INFO L158 Benchmark]: Toolchain (without parser) took 28274.64ms. Allocated memory was 83.9MB in the beginning and 369.1MB in the end (delta: 285.2MB). Free memory was 59.4MB in the beginning and 206.9MB in the end (delta: -147.5MB). Peak memory consumption was 133.8MB. Max. memory is 16.1GB. [2024-11-13 13:32:13,823 INFO L158 Benchmark]: CDTParser took 0.43ms. Allocated memory is still 83.9MB. Free memory is still 65.6MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:32:13,823 INFO L158 Benchmark]: CACSL2BoogieTranslator took 514.40ms. Allocated memory is still 83.9MB. Free memory was 59.4MB in the beginning and 38.1MB in the end (delta: 21.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-13 13:32:13,824 INFO L158 Benchmark]: Boogie Procedure Inliner took 78.51ms. Allocated memory is still 83.9MB. Free memory was 38.1MB in the beginning and 34.7MB in the end (delta: 3.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:32:13,824 INFO L158 Benchmark]: Boogie Preprocessor took 123.82ms. Allocated memory is still 83.9MB. Free memory was 34.7MB in the beginning and 31.3MB in the end (delta: 3.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-13 13:32:13,825 INFO L158 Benchmark]: RCFGBuilder took 914.04ms. Allocated memory is still 83.9MB. Free memory was 30.9MB in the beginning and 29.1MB in the end (delta: 1.8MB). Peak memory consumption was 13.2MB. Max. memory is 16.1GB. [2024-11-13 13:32:13,825 INFO L158 Benchmark]: TraceAbstraction took 26356.98ms. Allocated memory was 83.9MB in the beginning and 369.1MB in the end (delta: 285.2MB). Free memory was 28.6MB in the beginning and 236.1MB in the end (delta: -207.6MB). Peak memory consumption was 78.6MB. Max. memory is 16.1GB. [2024-11-13 13:32:13,825 INFO L158 Benchmark]: Witness Printer took 278.87ms. Allocated memory is still 369.1MB. Free memory was 236.1MB in the beginning and 206.9MB in the end (delta: 29.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-13 13:32:13,827 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.43ms. Allocated memory is still 83.9MB. Free memory is still 65.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 514.40ms. Allocated memory is still 83.9MB. Free memory was 59.4MB in the beginning and 38.1MB in the end (delta: 21.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 78.51ms. Allocated memory is still 83.9MB. Free memory was 38.1MB in the beginning and 34.7MB in the end (delta: 3.4MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 123.82ms. Allocated memory is still 83.9MB. Free memory was 34.7MB in the beginning and 31.3MB in the end (delta: 3.4MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 914.04ms. Allocated memory is still 83.9MB. Free memory was 30.9MB in the beginning and 29.1MB in the end (delta: 1.8MB). Peak memory consumption was 13.2MB. Max. memory is 16.1GB. * TraceAbstraction took 26356.98ms. Allocated memory was 83.9MB in the beginning and 369.1MB in the end (delta: 285.2MB). Free memory was 28.6MB in the beginning and 236.1MB in the end (delta: -207.6MB). Peak memory consumption was 78.6MB. Max. memory is 16.1GB. * Witness Printer took 278.87ms. Allocated memory is still 369.1MB. Free memory was 236.1MB in the beginning and 206.9MB in the end (delta: 29.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_9 mask_SORT_9 = (SORT_9)-1 >> (sizeof(SORT_9) * 8 - 31); [L30] const SORT_9 msb_SORT_9 = (SORT_9)1 << (31 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 16); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (16 - 1); [L35] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 8); [L36] const SORT_12 msb_SORT_12 = (SORT_12)1 << (8 - 1); [L38] const SORT_20 mask_SORT_20 = (SORT_20)-1 >> (sizeof(SORT_20) * 8 - 32); [L39] const SORT_20 msb_SORT_20 = (SORT_20)1 << (32 - 1); [L41] const SORT_23 mask_SORT_23 = (SORT_23)-1 >> (sizeof(SORT_23) * 8 - 17); [L42] const SORT_23 msb_SORT_23 = (SORT_23)1 << (17 - 1); [L44] const SORT_26 mask_SORT_26 = (SORT_26)-1 >> (sizeof(SORT_26) * 8 - 18); [L45] const SORT_26 msb_SORT_26 = (SORT_26)1 << (18 - 1); [L47] const SORT_29 mask_SORT_29 = (SORT_29)-1 >> (sizeof(SORT_29) * 8 - 19); [L48] const SORT_29 msb_SORT_29 = (SORT_29)1 << (19 - 1); [L50] const SORT_32 mask_SORT_32 = (SORT_32)-1 >> (sizeof(SORT_32) * 8 - 20); [L51] const SORT_32 msb_SORT_32 = (SORT_32)1 << (20 - 1); [L53] const SORT_35 mask_SORT_35 = (SORT_35)-1 >> (sizeof(SORT_35) * 8 - 21); [L54] const SORT_35 msb_SORT_35 = (SORT_35)1 << (21 - 1); [L56] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 22); [L57] const SORT_38 msb_SORT_38 = (SORT_38)1 << (22 - 1); [L59] const SORT_41 mask_SORT_41 = (SORT_41)-1 >> (sizeof(SORT_41) * 8 - 23); [L60] const SORT_41 msb_SORT_41 = (SORT_41)1 << (23 - 1); [L62] const SORT_44 mask_SORT_44 = (SORT_44)-1 >> (sizeof(SORT_44) * 8 - 24); [L63] const SORT_44 msb_SORT_44 = (SORT_44)1 << (24 - 1); [L65] const SORT_47 mask_SORT_47 = (SORT_47)-1 >> (sizeof(SORT_47) * 8 - 25); [L66] const SORT_47 msb_SORT_47 = (SORT_47)1 << (25 - 1); [L68] const SORT_50 mask_SORT_50 = (SORT_50)-1 >> (sizeof(SORT_50) * 8 - 26); [L69] const SORT_50 msb_SORT_50 = (SORT_50)1 << (26 - 1); [L71] const SORT_53 mask_SORT_53 = (SORT_53)-1 >> (sizeof(SORT_53) * 8 - 27); [L72] const SORT_53 msb_SORT_53 = (SORT_53)1 << (27 - 1); [L74] const SORT_56 mask_SORT_56 = (SORT_56)-1 >> (sizeof(SORT_56) * 8 - 28); [L75] const SORT_56 msb_SORT_56 = (SORT_56)1 << (28 - 1); [L77] const SORT_59 mask_SORT_59 = (SORT_59)-1 >> (sizeof(SORT_59) * 8 - 29); [L78] const SORT_59 msb_SORT_59 = (SORT_59)1 << (29 - 1); [L80] const SORT_62 mask_SORT_62 = (SORT_62)-1 >> (sizeof(SORT_62) * 8 - 30); [L81] const SORT_62 msb_SORT_62 = (SORT_62)1 << (30 - 1); [L83] const SORT_72 mask_SORT_72 = (SORT_72)-1 >> (sizeof(SORT_72) * 8 - 3); [L84] const SORT_72 msb_SORT_72 = (SORT_72)1 << (3 - 1); [L86] const SORT_96 mask_SORT_96 = (SORT_96)-1 >> (sizeof(SORT_96) * 8 - 4); [L87] const SORT_96 msb_SORT_96 = (SORT_96)1 << (4 - 1); [L89] const SORT_101 mask_SORT_101 = (SORT_101)-1 >> (sizeof(SORT_101) * 8 - 6); [L90] const SORT_101 msb_SORT_101 = (SORT_101)1 << (6 - 1); [L92] const SORT_1 var_7 = 0; [L93] const SORT_1 var_8 = 1; [L94] const SORT_9 var_10 = 0; [L95] const SORT_12 var_13 = 0; [L96] const SORT_12 var_14 = 200; [L97] const SORT_72 var_73 = 5; [L98] const SORT_11 var_75 = 0; [L99] const SORT_11 var_108 = 200; [L100] const SORT_72 var_113 = 4; [L101] const SORT_72 var_116 = 6; [L102] const SORT_96 var_120 = 9; [L103] const SORT_72 var_137 = 0; [L104] const SORT_96 var_140 = 0; [L106] SORT_1 input_2; [L107] SORT_1 input_3; [L108] SORT_1 input_4; [L110] SORT_1 state_5 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L111] SORT_11 state_17 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L112] SORT_11 state_76 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L113] SORT_96 state_97 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L114] SORT_96 state_100 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L116] SORT_11 init_77_arg_1 = var_75; [L117] state_76 = init_77_arg_1 VAL [mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_5=1, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=1, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=1, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=2, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=2, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=2, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=2, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 18 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 26.1s, OverallIterations: 8, TraceHistogramMax: 14, PathProgramHistogramMax: 6, EmptinessCheckTime: 0.0s, AutomataDifference: 2.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12 SdHoareTripleChecker+Valid, 1.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12 mSDsluCounter, 559 SdHoareTripleChecker+Invalid, 1.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 425 mSDsCounter, 13 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 732 IncrementalHoareTripleChecker+Invalid, 745 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 13 mSolverCounterUnsat, 134 mSDtfsCounter, 732 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 723 GetRequests, 652 SyntacticMatches, 5 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 1.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=56occurred in iteration=7, InterpolantAutomatonStates: 56, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 7 MinimizatonAttempts, 6 StatesRemovedByMinimization, 6 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 1.9s SsaConstructionTime, 4.4s SatisfiabilityAnalysisTime, 9.1s InterpolantComputationTime, 778 NumberOfCodeBlocks, 766 NumberOfCodeBlocksAsserted, 51 NumberOfCheckSat, 658 ConstructedInterpolants, 21 QuantifiedInterpolants, 5800 SizeOfPredicates, 81 NumberOfNonLiveVariables, 8144 ConjunctsInSsa, 342 ConjunctsInUnsatCore, 13 InterpolantComputations, 2 PerfectInterpolantSequences, 1289/1752 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-11-13 13:32:13,887 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fecfbd35-98b7-44b5-a0e7-458f3a9474a2/bin/uautomizer-verify-qhAvR1uOyd/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE