./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.11.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c7c6ca5d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.11.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e --- Real Ultimate output --- This is Ultimate 0.2.5-?-c7c6ca5-m [2024-11-09 16:08:31,384 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-09 16:08:31,436 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-09 16:08:31,442 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-09 16:08:31,444 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-09 16:08:31,469 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-09 16:08:31,470 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-09 16:08:31,471 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-09 16:08:31,471 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-09 16:08:31,473 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-09 16:08:31,473 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-09 16:08:31,474 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-09 16:08:31,474 INFO L153 SettingsManager]: * Use SBE=true [2024-11-09 16:08:31,474 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-09 16:08:31,474 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-09 16:08:31,477 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-09 16:08:31,477 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-09 16:08:31,477 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-09 16:08:31,477 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-09 16:08:31,477 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-09 16:08:31,478 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-09 16:08:31,478 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-09 16:08:31,478 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-09 16:08:31,478 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-09 16:08:31,479 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-09 16:08:31,479 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-09 16:08:31,479 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-09 16:08:31,479 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-09 16:08:31,479 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-09 16:08:31,479 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-09 16:08:31,479 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-09 16:08:31,480 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-09 16:08:31,480 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-09 16:08:31,480 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-09 16:08:31,480 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-09 16:08:31,480 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-09 16:08:31,481 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-09 16:08:31,481 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-09 16:08:31,483 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-09 16:08:31,484 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e [2024-11-09 16:08:31,709 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-09 16:08:31,730 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-09 16:08:31,732 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-09 16:08:31,734 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-09 16:08:31,734 INFO L274 PluginConnector]: CDTParser initialized [2024-11-09 16:08:31,735 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2024-11-09 16:08:33,185 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-09 16:08:33,395 INFO L384 CDTParser]: Found 1 translation units. [2024-11-09 16:08:33,395 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2024-11-09 16:08:33,410 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/334005dca/8e78a00e68b545fb9499b7200f695833/FLAGe22c2751f [2024-11-09 16:08:33,755 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/334005dca/8e78a00e68b545fb9499b7200f695833 [2024-11-09 16:08:33,759 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-09 16:08:33,761 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-09 16:08:33,766 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-09 16:08:33,767 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-09 16:08:33,773 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-09 16:08:33,774 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:08:33" (1/1) ... [2024-11-09 16:08:33,776 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@485a2835 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:33, skipping insertion in model container [2024-11-09 16:08:33,776 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:08:33" (1/1) ... [2024-11-09 16:08:33,808 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-09 16:08:34,150 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:08:34,165 INFO L200 MainTranslator]: Completed pre-run [2024-11-09 16:08:34,222 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:08:34,243 INFO L204 MainTranslator]: Completed translation [2024-11-09 16:08:34,243 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34 WrapperNode [2024-11-09 16:08:34,243 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-09 16:08:34,244 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-09 16:08:34,244 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-09 16:08:34,244 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-09 16:08:34,250 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,261 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,326 INFO L138 Inliner]: procedures = 50, calls = 65, calls flagged for inlining = 60, calls inlined = 239, statements flattened = 3670 [2024-11-09 16:08:34,326 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-09 16:08:34,327 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-09 16:08:34,327 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-09 16:08:34,327 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-09 16:08:34,336 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,337 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,344 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,370 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-09 16:08:34,370 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,371 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,405 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,432 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,441 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,447 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,457 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-09 16:08:34,459 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-09 16:08:34,459 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-09 16:08:34,459 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-09 16:08:34,459 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (1/1) ... [2024-11-09 16:08:34,464 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:34,473 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:34,490 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:34,493 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-09 16:08:34,531 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-09 16:08:34,531 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-09 16:08:34,531 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-09 16:08:34,531 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-09 16:08:34,629 INFO L238 CfgBuilder]: Building ICFG [2024-11-09 16:08:34,631 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-09 16:08:36,746 INFO L? ?]: Removed 768 outVars from TransFormulas that were not future-live. [2024-11-09 16:08:36,747 INFO L287 CfgBuilder]: Performing block encoding [2024-11-09 16:08:36,784 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-09 16:08:36,785 INFO L316 CfgBuilder]: Removed 14 assume(true) statements. [2024-11-09 16:08:36,785 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:08:36 BoogieIcfgContainer [2024-11-09 16:08:36,785 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-09 16:08:36,786 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-09 16:08:36,786 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-09 16:08:36,789 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-09 16:08:36,790 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:08:36,790 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 04:08:33" (1/3) ... [2024-11-09 16:08:36,791 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5beb240d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:08:36, skipping insertion in model container [2024-11-09 16:08:36,791 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:08:36,791 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:34" (2/3) ... [2024-11-09 16:08:36,791 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5beb240d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:08:36, skipping insertion in model container [2024-11-09 16:08:36,791 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:08:36,791 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:08:36" (3/3) ... [2024-11-09 16:08:36,792 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-2.c [2024-11-09 16:08:36,866 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-09 16:08:36,866 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-09 16:08:36,866 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-09 16:08:36,866 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-09 16:08:36,867 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-09 16:08:36,867 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-09 16:08:36,867 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-09 16:08:36,867 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-09 16:08:36,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:36,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1430 [2024-11-09 16:08:36,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:36,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:36,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:36,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:36,943 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-09 16:08:36,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:36,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1430 [2024-11-09 16:08:36,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:36,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:36,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:36,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:36,967 INFO L745 eck$LassoCheckResult]: Stem: 123#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1525#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 608#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1521#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109#L780true assume !(1 == ~m_i~0);~m_st~0 := 2; 1157#L780-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1415#L785-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1091#L790-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1413#L795-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 302#L800-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 581#L805-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1101#L810-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1030#L815-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 250#L820-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 730#L825-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 193#L830-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 921#L835-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1471#L1109true assume !(0 == ~M_E~0); 956#L1109-2true assume !(0 == ~T1_E~0); 198#L1114-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1542#L1119-1true assume !(0 == ~T3_E~0); 1035#L1124-1true assume !(0 == ~T4_E~0); 21#L1129-1true assume !(0 == ~T5_E~0); 353#L1134-1true assume !(0 == ~T6_E~0); 940#L1139-1true assume !(0 == ~T7_E~0); 1013#L1144-1true assume !(0 == ~T8_E~0); 780#L1149-1true assume !(0 == ~T9_E~0); 72#L1154-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 915#L1159-1true assume !(0 == ~T11_E~0); 769#L1164-1true assume !(0 == ~E_M~0); 279#L1169-1true assume !(0 == ~E_1~0); 224#L1174-1true assume !(0 == ~E_2~0); 151#L1179-1true assume !(0 == ~E_3~0); 112#L1184-1true assume !(0 == ~E_4~0); 130#L1189-1true assume !(0 == ~E_5~0); 174#L1194-1true assume 0 == ~E_6~0;~E_6~0 := 1; 788#L1199-1true assume !(0 == ~E_7~0); 964#L1204-1true assume !(0 == ~E_8~0); 726#L1209-1true assume !(0 == ~E_9~0); 1183#L1214-1true assume !(0 == ~E_10~0); 1544#L1219-1true assume !(0 == ~E_11~0); 1489#L1224-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 290#L544true assume 1 == ~m_pc~0; 1026#L545true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1193#L555true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 516#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92#L1379true assume !(0 != activate_threads_~tmp~1#1); 1408#L1379-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 567#L563true assume !(1 == ~t1_pc~0); 1189#L563-2true is_transmit1_triggered_~__retres1~1#1 := 0; 26#L574true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 825#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 671#L1387true assume !(0 != activate_threads_~tmp___0~0#1); 24#L1387-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 414#L582true assume 1 == ~t2_pc~0; 884#L583true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 679#L593true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 838#L1395true assume !(0 != activate_threads_~tmp___1~0#1); 40#L1395-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 759#L601true assume !(1 == ~t3_pc~0); 473#L601-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1008#L612true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 806#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 708#L1403true assume !(0 != activate_threads_~tmp___2~0#1); 1426#L1403-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 660#L620true assume 1 == ~t4_pc~0; 31#L621true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 370#L631true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 578#L1411true assume !(0 != activate_threads_~tmp___3~0#1); 760#L1411-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 743#L639true assume 1 == ~t5_pc~0; 637#L640true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 177#L650true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1281#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 593#L1419true assume !(0 != activate_threads_~tmp___4~0#1); 846#L1419-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 537#L658true assume !(1 == ~t6_pc~0); 288#L658-2true is_transmit6_triggered_~__retres1~6#1 := 0; 700#L669true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1497#L1427true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 712#L1427-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 203#L677true assume 1 == ~t7_pc~0; 1251#L678true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 887#L688true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1536#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1076#L1435true assume !(0 != activate_threads_~tmp___6~0#1); 1234#L1435-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1314#L696true assume !(1 == ~t8_pc~0); 325#L696-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1154#L707true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1237#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1360#L1443true assume !(0 != activate_threads_~tmp___7~0#1); 1540#L1443-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 628#L715true assume 1 == ~t9_pc~0; 1225#L716true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 387#L726true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 223#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 613#L1451true assume !(0 != activate_threads_~tmp___8~0#1); 1406#L1451-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 885#L734true assume !(1 == ~t10_pc~0); 1036#L734-2true is_transmit10_triggered_~__retres1~10#1 := 0; 264#L745true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1088#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 810#L1459true assume !(0 != activate_threads_~tmp___9~0#1); 1263#L1459-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 310#L753true assume 1 == ~t11_pc~0; 718#L754true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1583#L764true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1171#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 486#L1467true assume !(0 != activate_threads_~tmp___10~0#1); 774#L1467-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 521#L1237true assume !(1 == ~M_E~0); 1307#L1237-2true assume !(1 == ~T1_E~0); 1438#L1242-1true assume !(1 == ~T2_E~0); 367#L1247-1true assume !(1 == ~T3_E~0); 1072#L1252-1true assume !(1 == ~T4_E~0); 232#L1257-1true assume !(1 == ~T5_E~0); 905#L1262-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1058#L1267-1true assume !(1 == ~T7_E~0); 1059#L1272-1true assume !(1 == ~T8_E~0); 421#L1277-1true assume !(1 == ~T9_E~0); 818#L1282-1true assume !(1 == ~T10_E~0); 754#L1287-1true assume !(1 == ~T11_E~0); 789#L1292-1true assume !(1 == ~E_M~0); 711#L1297-1true assume !(1 == ~E_1~0); 304#L1302-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1039#L1307-1true assume !(1 == ~E_3~0); 1371#L1312-1true assume !(1 == ~E_4~0); 449#L1317-1true assume !(1 == ~E_5~0); 622#L1322-1true assume !(1 == ~E_6~0); 272#L1327-1true assume !(1 == ~E_7~0); 670#L1332-1true assume !(1 == ~E_8~0); 1350#L1337-1true assume !(1 == ~E_9~0); 617#L1342-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1240#L1347-1true assume !(1 == ~E_11~0); 1038#L1352-1true assume { :end_inline_reset_delta_events } true; 1580#L1678-2true [2024-11-09 16:08:36,969 INFO L747 eck$LassoCheckResult]: Loop: 1580#L1678-2true assume !false; 662#L1679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1286#L1084-1true assume !true; 477#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 301#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1442#L1109-3true assume 0 == ~M_E~0;~M_E~0 := 1; 32#L1109-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1218#L1114-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 713#L1119-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1575#L1124-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 740#L1129-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 948#L1134-3true assume !(0 == ~T6_E~0); 1122#L1139-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1024#L1144-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 295#L1149-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1569#L1154-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 453#L1159-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1553#L1164-3true assume 0 == ~E_M~0;~E_M~0 := 1; 657#L1169-3true assume 0 == ~E_1~0;~E_1~0 := 1; 980#L1174-3true assume !(0 == ~E_2~0); 702#L1179-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1316#L1184-3true assume 0 == ~E_4~0;~E_4~0 := 1; 865#L1189-3true assume 0 == ~E_5~0;~E_5~0 := 1; 561#L1194-3true assume 0 == ~E_6~0;~E_6~0 := 1; 163#L1199-3true assume 0 == ~E_7~0;~E_7~0 := 1; 791#L1204-3true assume 0 == ~E_8~0;~E_8~0 := 1; 284#L1209-3true assume 0 == ~E_9~0;~E_9~0 := 1; 10#L1214-3true assume !(0 == ~E_10~0); 607#L1219-3true assume 0 == ~E_11~0;~E_11~0 := 1; 395#L1224-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 650#L544-39true assume !(1 == ~m_pc~0); 4#L544-41true is_master_triggered_~__retres1~0#1 := 0; 742#L555-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 629#is_master_triggered_returnLabel#14true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207#L1379-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 845#L1379-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1327#L563-39true assume !(1 == ~t1_pc~0); 70#L563-41true is_transmit1_triggered_~__retres1~1#1 := 0; 1554#L574-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1419#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1453#L1387-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1464#L1387-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 994#L582-39true assume !(1 == ~t2_pc~0); 1248#L582-41true is_transmit2_triggered_~__retres1~2#1 := 0; 761#L593-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 434#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 966#L1395-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117#L1395-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15#L601-39true assume !(1 == ~t3_pc~0); 37#L601-41true is_transmit3_triggered_~__retres1~3#1 := 0; 803#L612-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1565#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1510#L1403-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 853#L1403-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 535#L620-39true assume !(1 == ~t4_pc~0); 1560#L620-41true is_transmit4_triggered_~__retres1~4#1 := 0; 934#L631-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 553#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 814#L1411-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1563#L1411-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1558#L639-39true assume !(1 == ~t5_pc~0); 1295#L639-41true is_transmit5_triggered_~__retres1~5#1 := 0; 371#L650-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 570#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27#L1419-39true assume !(0 != activate_threads_~tmp___4~0#1); 1391#L1419-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 565#L658-39true assume !(1 == ~t6_pc~0); 1447#L658-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1070#L669-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1494#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 723#L1427-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 696#L1427-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1244#L677-39true assume 1 == ~t7_pc~0; 664#L678-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 111#L688-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 815#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 141#L1435-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1381#L1435-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 488#L696-39true assume 1 == ~t8_pc~0; 460#L697-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 382#L707-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 935#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 588#L1443-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 557#L1443-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 471#L715-39true assume 1 == ~t9_pc~0; 17#L716-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 812#L726-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1582#L1451-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 746#L1451-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1146#L734-39true assume !(1 == ~t10_pc~0); 278#L734-41true is_transmit10_triggered_~__retres1~10#1 := 0; 490#L745-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1167#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 87#L1459-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1476#L1459-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1097#L753-39true assume !(1 == ~t11_pc~0); 51#L753-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1010#L764-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 586#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 464#L1467-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 753#L1467-41true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 533#L1237-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1092#L1237-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 771#L1242-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1529#L1247-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1057#L1252-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 692#L1257-3true assume !(1 == ~T5_E~0); 1016#L1262-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1104#L1267-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1545#L1272-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1348#L1277-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 126#L1282-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 672#L1287-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 79#L1292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1507#L1297-3true assume !(1 == ~E_1~0); 899#L1302-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1231#L1307-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1527#L1312-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1518#L1317-3true assume 1 == ~E_5~0;~E_5~0 := 2; 792#L1322-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1573#L1327-3true assume 1 == ~E_7~0;~E_7~0 := 2; 107#L1332-3true assume 1 == ~E_8~0;~E_8~0 := 2; 95#L1337-3true assume !(1 == ~E_9~0); 512#L1342-3true assume 1 == ~E_10~0;~E_10~0 := 2; 938#L1347-3true assume 1 == ~E_11~0;~E_11~0 := 2; 612#L1352-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 889#L848-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 212#L910-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 178#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 744#L1697true assume !(0 == start_simulation_~tmp~3#1); 528#L1697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1319#L848-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 854#L910-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1126#L1652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 584#L1659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1107#stop_simulation_returnLabel#1true start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 886#L1710true assume !(0 != start_simulation_~tmp___0~1#1); 1580#L1678-2true [2024-11-09 16:08:36,974 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:36,974 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2024-11-09 16:08:36,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:36,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333502699] [2024-11-09 16:08:36,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:36,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:37,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:37,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:37,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:37,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333502699] [2024-11-09 16:08:37,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333502699] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:37,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:37,262 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:37,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284741538] [2024-11-09 16:08:37,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:37,270 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:37,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:37,272 INFO L85 PathProgramCache]: Analyzing trace with hash -784888959, now seen corresponding path program 1 times [2024-11-09 16:08:37,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:37,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931169411] [2024-11-09 16:08:37,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:37,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:37,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:37,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:37,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:37,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931169411] [2024-11-09 16:08:37,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931169411] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:37,316 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:37,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:08:37,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021087588] [2024-11-09 16:08:37,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:37,318 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:37,319 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:37,345 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-09 16:08:37,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-09 16:08:37,354 INFO L87 Difference]: Start difference. First operand has 1585 states, 1584 states have (on average 1.4981060606060606) internal successors, (2373), 1584 states have internal predecessors, (2373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:37,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:37,427 INFO L93 Difference]: Finished difference Result 1583 states and 2342 transitions. [2024-11-09 16:08:37,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1583 states and 2342 transitions. [2024-11-09 16:08:37,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:37,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1583 states to 1578 states and 2337 transitions. [2024-11-09 16:08:37,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:37,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:37,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2337 transitions. [2024-11-09 16:08:37,464 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:37,465 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2024-11-09 16:08:37,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2337 transitions. [2024-11-09 16:08:37,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:37,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4809885931558935) internal successors, (2337), 1577 states have internal predecessors, (2337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:37,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2337 transitions. [2024-11-09 16:08:37,553 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2024-11-09 16:08:37,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-09 16:08:37,560 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2337 transitions. [2024-11-09 16:08:37,561 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-09 16:08:37,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2337 transitions. [2024-11-09 16:08:37,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:37,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:37,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:37,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:37,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:37,574 INFO L745 eck$LassoCheckResult]: Stem: 3433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4214#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4215#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3407#L780 assume !(1 == ~m_i~0);~m_st~0 := 2; 3408#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4648#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4617#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4618#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3766#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3767#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4182#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4584#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3670#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3671#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3561#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3562#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4515#L1109 assume !(0 == ~M_E~0); 4532#L1109-2 assume !(0 == ~T1_E~0); 3570#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3571#L1119-1 assume !(0 == ~T3_E~0); 4587#L1124-1 assume !(0 == ~T4_E~0); 3221#L1129-1 assume !(0 == ~T5_E~0); 3222#L1134-1 assume !(0 == ~T6_E~0); 3853#L1139-1 assume !(0 == ~T7_E~0); 4523#L1144-1 assume !(0 == ~T8_E~0); 4393#L1149-1 assume !(0 == ~T9_E~0); 3332#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3333#L1159-1 assume !(0 == ~T11_E~0); 4383#L1164-1 assume !(0 == ~E_M~0); 3728#L1169-1 assume !(0 == ~E_1~0); 3622#L1174-1 assume !(0 == ~E_2~0); 3486#L1179-1 assume !(0 == ~E_3~0); 3413#L1184-1 assume !(0 == ~E_4~0); 3414#L1189-1 assume !(0 == ~E_5~0); 3446#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3529#L1199-1 assume !(0 == ~E_7~0); 4402#L1204-1 assume !(0 == ~E_8~0); 4343#L1209-1 assume !(0 == ~E_9~0); 4344#L1214-1 assume !(0 == ~E_10~0); 4661#L1219-1 assume !(0 == ~E_11~0); 4748#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3745#L544 assume 1 == ~m_pc~0; 3746#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4571#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4101#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3375#L1379 assume !(0 != activate_threads_~tmp~1#1); 3376#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4169#L563 assume !(1 == ~t1_pc~0); 3975#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3231#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3232#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4291#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 3227#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3228#L582 assume 1 == ~t2_pc~0; 3953#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4296#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3566#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3567#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 3260#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3261#L601 assume !(1 == ~t3_pc~0); 3970#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3969#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4328#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4329#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4277#L620 assume 1 == ~t4_pc~0; 3241#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3242#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3274#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3275#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4179#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4361#L639 assume 1 == ~t5_pc~0; 4251#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3534#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3535#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4199#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4200#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4134#L658 assume !(1 == ~t6_pc~0); 3742#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3743#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3558#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3559#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4332#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3581#L677 assume 1 == ~t7_pc~0; 3582#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3479#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4489#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4610#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4611#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4681#L696 assume !(1 == ~t8_pc~0); 3806#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3807#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4646#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4684#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4729#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4238#L715 assume 1 == ~t9_pc~0; 4239#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3906#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3620#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3621#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4221#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4484#L734 assume !(1 == ~t10_pc~0); 4485#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3698#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3699#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4427#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4428#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3780#L753 assume 1 == ~t11_pc~0; 3781#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4337#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4655#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4056#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4057#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4108#L1237 assume !(1 == ~M_E~0); 4109#L1237-2 assume !(1 == ~T1_E~0); 4712#L1242-1 assume !(1 == ~T2_E~0); 3874#L1247-1 assume !(1 == ~T3_E~0); 3875#L1252-1 assume !(1 == ~T4_E~0); 3639#L1257-1 assume !(1 == ~T5_E~0); 3640#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4504#L1267-1 assume !(1 == ~T7_E~0); 4602#L1272-1 assume !(1 == ~T8_E~0); 3964#L1277-1 assume !(1 == ~T9_E~0); 3965#L1282-1 assume !(1 == ~T10_E~0); 4370#L1287-1 assume !(1 == ~T11_E~0); 4371#L1292-1 assume !(1 == ~E_M~0); 4331#L1297-1 assume !(1 == ~E_1~0); 3771#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3772#L1307-1 assume !(1 == ~E_3~0); 4591#L1312-1 assume !(1 == ~E_4~0); 4010#L1317-1 assume !(1 == ~E_5~0); 4011#L1322-1 assume !(1 == ~E_6~0); 3715#L1327-1 assume !(1 == ~E_7~0); 3716#L1332-1 assume !(1 == ~E_8~0); 4290#L1337-1 assume !(1 == ~E_9~0); 4224#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4225#L1347-1 assume !(1 == ~E_11~0); 4590#L1352-1 assume { :end_inline_reset_delta_events } true; 4488#L1678-2 [2024-11-09 16:08:37,575 INFO L747 eck$LassoCheckResult]: Loop: 4488#L1678-2 assume !false; 4280#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4281#L1084-1 assume !false; 4077#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4078#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3351#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3271#L925 assume !(0 != eval_~tmp~0#1); 3273#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3764#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3765#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3244#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3245#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4333#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4334#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4358#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4359#L1134-3 assume !(0 == ~T6_E~0); 4528#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4579#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3755#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3756#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4017#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4018#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4273#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4274#L1174-3 assume !(0 == ~E_2~0); 4321#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4322#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4467#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4163#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3508#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3509#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3735#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3194#L1214-3 assume !(0 == ~E_10~0); 3195#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3918#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3919#L544-39 assume 1 == ~m_pc~0; 4265#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3183#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4241#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3589#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3590#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4454#L563-39 assume 1 == ~t1_pc~0; 4460#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3328#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4739#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4740#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4743#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4562#L582-39 assume 1 == ~t2_pc~0; 3651#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3652#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3987#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3988#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3422#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3206#L601-39 assume 1 == ~t3_pc~0; 3207#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3255#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4421#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4750#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4458#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4129#L620-39 assume 1 == ~t4_pc~0; 4130#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4319#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4154#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4155#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4431#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4754#L639-39 assume 1 == ~t5_pc~0; 4545#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3877#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3878#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3233#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 3234#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4166#L658-39 assume 1 == ~t6_pc~0; 4149#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4150#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4606#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4342#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4316#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4317#L677-39 assume !(1 == ~t7_pc~0); 3962#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 3411#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3412#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3467#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3468#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4059#L696-39 assume 1 == ~t8_pc~0; 4025#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3900#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3901#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4191#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4159#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4039#L715-39 assume 1 == ~t9_pc~0; 3211#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3213#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3288#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3289#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4364#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4365#L734-39 assume 1 == ~t10_pc~0; 4294#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3727#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4062#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3365#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3366#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4620#L753-39 assume !(1 == ~t11_pc~0); 3284#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 3285#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4188#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4030#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4031#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4126#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4127#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4385#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4386#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4601#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4309#L1257-3 assume !(1 == ~T5_E~0); 4310#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4574#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4623#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4726#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3438#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3439#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3348#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3349#L1297-3 assume !(1 == ~E_1~0); 4497#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4498#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4678#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4751#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4405#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4406#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3404#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3381#L1337-3 assume !(1 == ~E_9~0); 3382#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4097#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4219#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4220#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3330#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3536#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3537#L1697 assume !(0 == start_simulation_~tmp~3#1); 4116#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4117#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3455#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3223#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 3224#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4185#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4186#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4487#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4488#L1678-2 [2024-11-09 16:08:37,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:37,576 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2024-11-09 16:08:37,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:37,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953359373] [2024-11-09 16:08:37,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:37,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:37,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:37,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:37,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:37,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953359373] [2024-11-09 16:08:37,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [953359373] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:37,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:37,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:37,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593441969] [2024-11-09 16:08:37,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:37,728 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:37,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:37,728 INFO L85 PathProgramCache]: Analyzing trace with hash 705815280, now seen corresponding path program 1 times [2024-11-09 16:08:37,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:37,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936346830] [2024-11-09 16:08:37,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:37,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:37,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:37,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:37,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:37,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936346830] [2024-11-09 16:08:37,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936346830] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:37,861 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:37,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:37,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097911097] [2024-11-09 16:08:37,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:37,862 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:37,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:37,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:37,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:37,864 INFO L87 Difference]: Start difference. First operand 1578 states and 2337 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:37,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:37,900 INFO L93 Difference]: Finished difference Result 1578 states and 2336 transitions. [2024-11-09 16:08:37,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2336 transitions. [2024-11-09 16:08:37,907 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:37,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2336 transitions. [2024-11-09 16:08:37,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:37,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:37,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2336 transitions. [2024-11-09 16:08:37,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:37,917 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2024-11-09 16:08:37,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2336 transitions. [2024-11-09 16:08:37,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:37,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4803548795944232) internal successors, (2336), 1577 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:37,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2336 transitions. [2024-11-09 16:08:37,937 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2024-11-09 16:08:37,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:37,938 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2336 transitions. [2024-11-09 16:08:37,938 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-09 16:08:37,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2336 transitions. [2024-11-09 16:08:37,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:37,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:37,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:37,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:37,949 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:37,951 INFO L745 eck$LassoCheckResult]: Stem: 6596#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6597#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7377#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7378#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6570#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 6571#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7811#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7780#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7781#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6929#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6930#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7345#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7747#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6833#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6834#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6724#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6725#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7678#L1109 assume !(0 == ~M_E~0); 7695#L1109-2 assume !(0 == ~T1_E~0); 6733#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6734#L1119-1 assume !(0 == ~T3_E~0); 7750#L1124-1 assume !(0 == ~T4_E~0); 6384#L1129-1 assume !(0 == ~T5_E~0); 6385#L1134-1 assume !(0 == ~T6_E~0); 7016#L1139-1 assume !(0 == ~T7_E~0); 7686#L1144-1 assume !(0 == ~T8_E~0); 7556#L1149-1 assume !(0 == ~T9_E~0); 6495#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6496#L1159-1 assume !(0 == ~T11_E~0); 7546#L1164-1 assume !(0 == ~E_M~0); 6891#L1169-1 assume !(0 == ~E_1~0); 6785#L1174-1 assume !(0 == ~E_2~0); 6649#L1179-1 assume !(0 == ~E_3~0); 6576#L1184-1 assume !(0 == ~E_4~0); 6577#L1189-1 assume !(0 == ~E_5~0); 6609#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6692#L1199-1 assume !(0 == ~E_7~0); 7565#L1204-1 assume !(0 == ~E_8~0); 7506#L1209-1 assume !(0 == ~E_9~0); 7507#L1214-1 assume !(0 == ~E_10~0); 7824#L1219-1 assume !(0 == ~E_11~0); 7911#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6908#L544 assume 1 == ~m_pc~0; 6909#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7734#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7264#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6538#L1379 assume !(0 != activate_threads_~tmp~1#1); 6539#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7332#L563 assume !(1 == ~t1_pc~0); 7138#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6394#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6395#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7454#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 6390#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6391#L582 assume 1 == ~t2_pc~0; 7116#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7459#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6729#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6730#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 6423#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6424#L601 assume !(1 == ~t3_pc~0); 7133#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7132#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7491#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 7492#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7440#L620 assume 1 == ~t4_pc~0; 6404#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6405#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6438#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 7342#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7524#L639 assume 1 == ~t5_pc~0; 7414#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6697#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6698#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7362#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 7363#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7297#L658 assume !(1 == ~t6_pc~0); 6905#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6906#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6721#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6722#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7495#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6744#L677 assume 1 == ~t7_pc~0; 6745#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6642#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7652#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7773#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 7774#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7844#L696 assume !(1 == ~t8_pc~0); 6969#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6970#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7809#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7847#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 7892#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7401#L715 assume 1 == ~t9_pc~0; 7402#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7069#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6784#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 7384#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7647#L734 assume !(1 == ~t10_pc~0); 7648#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6861#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6862#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7590#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 7591#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6943#L753 assume 1 == ~t11_pc~0; 6944#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7500#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7818#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7219#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 7220#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7271#L1237 assume !(1 == ~M_E~0); 7272#L1237-2 assume !(1 == ~T1_E~0); 7875#L1242-1 assume !(1 == ~T2_E~0); 7037#L1247-1 assume !(1 == ~T3_E~0); 7038#L1252-1 assume !(1 == ~T4_E~0); 6802#L1257-1 assume !(1 == ~T5_E~0); 6803#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7667#L1267-1 assume !(1 == ~T7_E~0); 7765#L1272-1 assume !(1 == ~T8_E~0); 7127#L1277-1 assume !(1 == ~T9_E~0); 7128#L1282-1 assume !(1 == ~T10_E~0); 7533#L1287-1 assume !(1 == ~T11_E~0); 7534#L1292-1 assume !(1 == ~E_M~0); 7494#L1297-1 assume !(1 == ~E_1~0); 6934#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6935#L1307-1 assume !(1 == ~E_3~0); 7754#L1312-1 assume !(1 == ~E_4~0); 7173#L1317-1 assume !(1 == ~E_5~0); 7174#L1322-1 assume !(1 == ~E_6~0); 6878#L1327-1 assume !(1 == ~E_7~0); 6879#L1332-1 assume !(1 == ~E_8~0); 7453#L1337-1 assume !(1 == ~E_9~0); 7387#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7388#L1347-1 assume !(1 == ~E_11~0); 7753#L1352-1 assume { :end_inline_reset_delta_events } true; 7651#L1678-2 [2024-11-09 16:08:37,951 INFO L747 eck$LassoCheckResult]: Loop: 7651#L1678-2 assume !false; 7443#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7444#L1084-1 assume !false; 7240#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7241#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6514#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7739#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6434#L925 assume !(0 != eval_~tmp~0#1); 6436#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6927#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6928#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6407#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6408#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7496#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7497#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7521#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7522#L1134-3 assume !(0 == ~T6_E~0); 7691#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7742#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6918#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6919#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7180#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7181#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7436#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7437#L1174-3 assume !(0 == ~E_2~0); 7484#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7485#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7630#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7326#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6671#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6672#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6898#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6357#L1214-3 assume !(0 == ~E_10~0); 6358#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7081#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7082#L544-39 assume 1 == ~m_pc~0; 7428#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6346#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7404#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6752#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6753#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7617#L563-39 assume 1 == ~t1_pc~0; 7623#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6491#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7902#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7903#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7906#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7725#L582-39 assume !(1 == ~t2_pc~0); 6816#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 6815#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7150#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7151#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6585#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6369#L601-39 assume 1 == ~t3_pc~0; 6370#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6418#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7584#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7913#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7621#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7292#L620-39 assume 1 == ~t4_pc~0; 7293#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7482#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7317#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7318#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7594#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7917#L639-39 assume 1 == ~t5_pc~0; 7708#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7040#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7041#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6396#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 6397#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7329#L658-39 assume 1 == ~t6_pc~0; 7312#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7313#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7769#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7505#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7479#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7480#L677-39 assume !(1 == ~t7_pc~0); 7125#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 6574#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6575#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6630#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6631#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7222#L696-39 assume 1 == ~t8_pc~0; 7188#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7063#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7064#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7354#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7322#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7202#L715-39 assume 1 == ~t9_pc~0; 6374#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6376#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6451#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6452#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7527#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7528#L734-39 assume 1 == ~t10_pc~0; 7457#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6890#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7225#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6528#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6529#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7783#L753-39 assume !(1 == ~t11_pc~0); 6447#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 6448#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7351#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7193#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7194#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7289#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7290#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7548#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7549#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7764#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7472#L1257-3 assume !(1 == ~T5_E~0); 7473#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7737#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7786#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7889#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6601#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6602#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6511#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6512#L1297-3 assume !(1 == ~E_1~0); 7660#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7661#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7841#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7914#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7568#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7569#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6567#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6544#L1337-3 assume !(1 == ~E_9~0); 6545#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7260#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7382#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7383#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6493#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6699#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6700#L1697 assume !(0 == start_simulation_~tmp~3#1); 7279#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7280#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6618#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6386#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 6387#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7348#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7349#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7650#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 7651#L1678-2 [2024-11-09 16:08:37,952 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:37,952 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2024-11-09 16:08:37,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:37,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [883212306] [2024-11-09 16:08:37,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:37,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:37,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [883212306] [2024-11-09 16:08:38,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [883212306] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3238933] [2024-11-09 16:08:38,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,012 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:38,012 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,012 INFO L85 PathProgramCache]: Analyzing trace with hash -1155596751, now seen corresponding path program 1 times [2024-11-09 16:08:38,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857542445] [2024-11-09 16:08:38,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857542445] [2024-11-09 16:08:38,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857542445] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243398989] [2024-11-09 16:08:38,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,074 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:38,074 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:38,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:38,075 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:38,075 INFO L87 Difference]: Start difference. First operand 1578 states and 2336 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:38,094 INFO L93 Difference]: Finished difference Result 1578 states and 2335 transitions. [2024-11-09 16:08:38,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2335 transitions. [2024-11-09 16:08:38,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2335 transitions. [2024-11-09 16:08:38,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:38,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:38,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2335 transitions. [2024-11-09 16:08:38,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:38,108 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2024-11-09 16:08:38,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2335 transitions. [2024-11-09 16:08:38,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:38,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.479721166032953) internal successors, (2335), 1577 states have internal predecessors, (2335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2335 transitions. [2024-11-09 16:08:38,125 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2024-11-09 16:08:38,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:38,127 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2335 transitions. [2024-11-09 16:08:38,127 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-09 16:08:38,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2335 transitions. [2024-11-09 16:08:38,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:38,133 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:38,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,137 INFO L745 eck$LassoCheckResult]: Stem: 9759#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 9760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10541#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10542#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9733#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 9734#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10974#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10943#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10944#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10092#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10093#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10508#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10910#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9998#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9999#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9887#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9888#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10843#L1109 assume !(0 == ~M_E~0); 10858#L1109-2 assume !(0 == ~T1_E~0); 9896#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9897#L1119-1 assume !(0 == ~T3_E~0); 10913#L1124-1 assume !(0 == ~T4_E~0); 9547#L1129-1 assume !(0 == ~T5_E~0); 9548#L1134-1 assume !(0 == ~T6_E~0); 10179#L1139-1 assume !(0 == ~T7_E~0); 10849#L1144-1 assume !(0 == ~T8_E~0); 10719#L1149-1 assume !(0 == ~T9_E~0); 9660#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9661#L1159-1 assume !(0 == ~T11_E~0); 10709#L1164-1 assume !(0 == ~E_M~0); 10054#L1169-1 assume !(0 == ~E_1~0); 9948#L1174-1 assume !(0 == ~E_2~0); 9817#L1179-1 assume !(0 == ~E_3~0); 9739#L1184-1 assume !(0 == ~E_4~0); 9740#L1189-1 assume !(0 == ~E_5~0); 9772#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9859#L1199-1 assume !(0 == ~E_7~0); 10728#L1204-1 assume !(0 == ~E_8~0); 10670#L1209-1 assume !(0 == ~E_9~0); 10671#L1214-1 assume !(0 == ~E_10~0); 10987#L1219-1 assume !(0 == ~E_11~0); 11074#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10073#L544 assume 1 == ~m_pc~0; 10074#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10897#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10427#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9701#L1379 assume !(0 != activate_threads_~tmp~1#1); 9702#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10497#L563 assume !(1 == ~t1_pc~0); 10301#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9557#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9558#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10617#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 9553#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9554#L582 assume 1 == ~t2_pc~0; 10279#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10622#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9892#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9893#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 9586#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9587#L601 assume !(1 == ~t3_pc~0); 10296#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10295#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10749#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10654#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 10655#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10603#L620 assume 1 == ~t4_pc~0; 9567#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9568#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9601#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 10505#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10688#L639 assume 1 == ~t5_pc~0; 10577#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9862#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9863#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10525#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 10526#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10462#L658 assume !(1 == ~t6_pc~0); 10068#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10069#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9884#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9885#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10658#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9909#L677 assume 1 == ~t7_pc~0; 9910#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9808#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10815#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10936#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 10937#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11007#L696 assume !(1 == ~t8_pc~0); 10133#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10134#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10972#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11010#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 11055#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10564#L715 assume 1 == ~t9_pc~0; 10565#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10232#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9946#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9947#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 10547#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10812#L734 assume !(1 == ~t10_pc~0); 10813#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10024#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10025#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10753#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 10754#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10106#L753 assume 1 == ~t11_pc~0; 10107#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10663#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10981#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10384#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 10385#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10436#L1237 assume !(1 == ~M_E~0); 10437#L1237-2 assume !(1 == ~T1_E~0); 11039#L1242-1 assume !(1 == ~T2_E~0); 10200#L1247-1 assume !(1 == ~T3_E~0); 10201#L1252-1 assume !(1 == ~T4_E~0); 9965#L1257-1 assume !(1 == ~T5_E~0); 9966#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10830#L1267-1 assume !(1 == ~T7_E~0); 10928#L1272-1 assume !(1 == ~T8_E~0); 10290#L1277-1 assume !(1 == ~T9_E~0); 10291#L1282-1 assume !(1 == ~T10_E~0); 10696#L1287-1 assume !(1 == ~T11_E~0); 10697#L1292-1 assume !(1 == ~E_M~0); 10657#L1297-1 assume !(1 == ~E_1~0); 10097#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10098#L1307-1 assume !(1 == ~E_3~0); 10917#L1312-1 assume !(1 == ~E_4~0); 10336#L1317-1 assume !(1 == ~E_5~0); 10337#L1322-1 assume !(1 == ~E_6~0); 10043#L1327-1 assume !(1 == ~E_7~0); 10044#L1332-1 assume !(1 == ~E_8~0); 10616#L1337-1 assume !(1 == ~E_9~0); 10550#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10551#L1347-1 assume !(1 == ~E_11~0); 10916#L1352-1 assume { :end_inline_reset_delta_events } true; 10811#L1678-2 [2024-11-09 16:08:38,138 INFO L747 eck$LassoCheckResult]: Loop: 10811#L1678-2 assume !false; 10608#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10609#L1084-1 assume !false; 10403#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10404#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9677#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10902#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9597#L925 assume !(0 != eval_~tmp~0#1); 9599#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10090#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10091#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9570#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9571#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10659#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10660#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10685#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10686#L1134-3 assume !(0 == ~T6_E~0); 10854#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10905#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10081#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10082#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10343#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 10344#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10599#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10600#L1174-3 assume !(0 == ~E_2~0); 10647#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10648#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10793#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10489#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9834#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9835#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10061#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9520#L1214-3 assume !(0 == ~E_10~0); 9521#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10244#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10245#L544-39 assume !(1 == ~m_pc~0); 9508#L544-41 is_master_triggered_~__retres1~0#1 := 0; 9509#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10567#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9915#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9916#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10780#L563-39 assume 1 == ~t1_pc~0; 10786#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9654#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11065#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11066#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11069#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10888#L582-39 assume 1 == ~t2_pc~0; 9977#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9978#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10313#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10314#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9748#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9532#L601-39 assume 1 == ~t3_pc~0; 9533#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9581#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10747#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11076#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10784#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10455#L620-39 assume 1 == ~t4_pc~0; 10456#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10645#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10480#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10481#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10757#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11080#L639-39 assume 1 == ~t5_pc~0; 10871#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10203#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10204#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9559#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 9560#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10492#L658-39 assume 1 == ~t6_pc~0; 10475#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10476#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10932#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10668#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10642#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10643#L677-39 assume !(1 == ~t7_pc~0); 10288#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 9737#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9738#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9793#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9794#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10383#L696-39 assume !(1 == ~t8_pc~0); 10352#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 10226#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10227#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10517#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10485#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10365#L715-39 assume 1 == ~t9_pc~0; 9537#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9539#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9614#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9615#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10690#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10691#L734-39 assume !(1 == ~t10_pc~0); 10052#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 10053#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10388#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9691#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9692#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10946#L753-39 assume !(1 == ~t11_pc~0); 9610#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9611#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10514#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10356#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10357#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10452#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10453#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10711#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10712#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10927#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10635#L1257-3 assume !(1 == ~T5_E~0); 10636#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10900#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10949#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11052#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9764#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9765#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9674#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9675#L1297-3 assume !(1 == ~E_1~0); 10823#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10824#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11004#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11077#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10731#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10732#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9730#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9707#L1337-3 assume !(1 == ~E_9~0); 9708#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10423#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10545#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10546#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9656#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9861#L1697 assume !(0 == start_simulation_~tmp~3#1); 10442#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10443#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9781#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9549#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 9550#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10511#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10512#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10810#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 10811#L1678-2 [2024-11-09 16:08:38,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2024-11-09 16:08:38,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116599249] [2024-11-09 16:08:38,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,179 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116599249] [2024-11-09 16:08:38,179 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116599249] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,180 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,180 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547839633] [2024-11-09 16:08:38,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,181 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:38,181 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,181 INFO L85 PathProgramCache]: Analyzing trace with hash -2057024077, now seen corresponding path program 1 times [2024-11-09 16:08:38,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807247253] [2024-11-09 16:08:38,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1807247253] [2024-11-09 16:08:38,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1807247253] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,244 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,244 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187702006] [2024-11-09 16:08:38,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,244 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:38,245 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:38,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:38,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:38,245 INFO L87 Difference]: Start difference. First operand 1578 states and 2335 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:38,269 INFO L93 Difference]: Finished difference Result 1578 states and 2334 transitions. [2024-11-09 16:08:38,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2334 transitions. [2024-11-09 16:08:38,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2334 transitions. [2024-11-09 16:08:38,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:38,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:38,315 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2334 transitions. [2024-11-09 16:08:38,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:38,318 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2024-11-09 16:08:38,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2334 transitions. [2024-11-09 16:08:38,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:38,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.479087452471483) internal successors, (2334), 1577 states have internal predecessors, (2334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2334 transitions. [2024-11-09 16:08:38,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2024-11-09 16:08:38,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:38,340 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2334 transitions. [2024-11-09 16:08:38,341 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-09 16:08:38,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2334 transitions. [2024-11-09 16:08:38,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:38,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:38,347 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,347 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,347 INFO L745 eck$LassoCheckResult]: Stem: 12922#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 12923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12896#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 12897#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14137#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14106#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14107#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13255#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13256#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13671#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14073#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13159#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13160#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13050#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13051#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14004#L1109 assume !(0 == ~M_E~0); 14021#L1109-2 assume !(0 == ~T1_E~0); 13059#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13060#L1119-1 assume !(0 == ~T3_E~0); 14076#L1124-1 assume !(0 == ~T4_E~0); 12710#L1129-1 assume !(0 == ~T5_E~0); 12711#L1134-1 assume !(0 == ~T6_E~0); 13342#L1139-1 assume !(0 == ~T7_E~0); 14012#L1144-1 assume !(0 == ~T8_E~0); 13882#L1149-1 assume !(0 == ~T9_E~0); 12821#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12822#L1159-1 assume !(0 == ~T11_E~0); 13872#L1164-1 assume !(0 == ~E_M~0); 13217#L1169-1 assume !(0 == ~E_1~0); 13111#L1174-1 assume !(0 == ~E_2~0); 12977#L1179-1 assume !(0 == ~E_3~0); 12902#L1184-1 assume !(0 == ~E_4~0); 12903#L1189-1 assume !(0 == ~E_5~0); 12935#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 13018#L1199-1 assume !(0 == ~E_7~0); 13891#L1204-1 assume !(0 == ~E_8~0); 13832#L1209-1 assume !(0 == ~E_9~0); 13833#L1214-1 assume !(0 == ~E_10~0); 14150#L1219-1 assume !(0 == ~E_11~0); 14237#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13234#L544 assume 1 == ~m_pc~0; 13235#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14060#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13590#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12864#L1379 assume !(0 != activate_threads_~tmp~1#1); 12865#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13658#L563 assume !(1 == ~t1_pc~0); 13464#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12720#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12721#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13780#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 12716#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12717#L582 assume 1 == ~t2_pc~0; 13442#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13785#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13055#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13056#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 12749#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12750#L601 assume !(1 == ~t3_pc~0); 13459#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13458#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13912#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13817#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 13818#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13766#L620 assume 1 == ~t4_pc~0; 12730#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12731#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12763#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12764#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 13668#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13851#L639 assume 1 == ~t5_pc~0; 13740#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13025#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13026#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13688#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 13689#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13623#L658 assume !(1 == ~t6_pc~0); 13231#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13232#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13047#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13048#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13821#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13070#L677 assume 1 == ~t7_pc~0; 13071#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12968#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13978#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14099#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 14100#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14170#L696 assume !(1 == ~t8_pc~0); 13295#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13296#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14135#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14173#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 14218#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13727#L715 assume 1 == ~t9_pc~0; 13728#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13395#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13109#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13110#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 13710#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13975#L734 assume !(1 == ~t10_pc~0); 13976#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13187#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13188#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13916#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 13917#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13269#L753 assume 1 == ~t11_pc~0; 13270#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13826#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14144#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13546#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 13547#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13597#L1237 assume !(1 == ~M_E~0); 13598#L1237-2 assume !(1 == ~T1_E~0); 14201#L1242-1 assume !(1 == ~T2_E~0); 13363#L1247-1 assume !(1 == ~T3_E~0); 13364#L1252-1 assume !(1 == ~T4_E~0); 13128#L1257-1 assume !(1 == ~T5_E~0); 13129#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13993#L1267-1 assume !(1 == ~T7_E~0); 14091#L1272-1 assume !(1 == ~T8_E~0); 13453#L1277-1 assume !(1 == ~T9_E~0); 13454#L1282-1 assume !(1 == ~T10_E~0); 13859#L1287-1 assume !(1 == ~T11_E~0); 13860#L1292-1 assume !(1 == ~E_M~0); 13820#L1297-1 assume !(1 == ~E_1~0); 13260#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13261#L1307-1 assume !(1 == ~E_3~0); 14080#L1312-1 assume !(1 == ~E_4~0); 13499#L1317-1 assume !(1 == ~E_5~0); 13500#L1322-1 assume !(1 == ~E_6~0); 13204#L1327-1 assume !(1 == ~E_7~0); 13205#L1332-1 assume !(1 == ~E_8~0); 13779#L1337-1 assume !(1 == ~E_9~0); 13713#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13714#L1347-1 assume !(1 == ~E_11~0); 14079#L1352-1 assume { :end_inline_reset_delta_events } true; 13974#L1678-2 [2024-11-09 16:08:38,349 INFO L747 eck$LassoCheckResult]: Loop: 13974#L1678-2 assume !false; 13769#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13770#L1084-1 assume !false; 13566#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13567#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12840#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 14065#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12760#L925 assume !(0 != eval_~tmp~0#1); 12762#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13253#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13254#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12733#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12734#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13822#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13823#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13847#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13848#L1134-3 assume !(0 == ~T6_E~0); 14017#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14068#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13244#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13245#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13506#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13507#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13762#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13763#L1174-3 assume !(0 == ~E_2~0); 13810#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13811#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13956#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13652#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13000#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13001#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13226#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12686#L1214-3 assume !(0 == ~E_10~0); 12687#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13407#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13408#L544-39 assume 1 == ~m_pc~0; 13755#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12672#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13730#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13078#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13079#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13943#L563-39 assume !(1 == ~t1_pc~0); 12819#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 12820#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14228#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14229#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14232#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14051#L582-39 assume 1 == ~t2_pc~0; 13140#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13141#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13476#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13477#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12911#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12695#L601-39 assume 1 == ~t3_pc~0; 12696#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12744#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13910#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14239#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13947#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13620#L620-39 assume 1 == ~t4_pc~0; 13621#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13808#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13643#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13644#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13920#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14243#L639-39 assume 1 == ~t5_pc~0; 14034#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13366#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13367#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12722#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 12723#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13655#L658-39 assume 1 == ~t6_pc~0; 13638#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13639#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14095#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13831#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13805#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13806#L677-39 assume !(1 == ~t7_pc~0); 13448#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 12898#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12899#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12956#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12957#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13545#L696-39 assume 1 == ~t8_pc~0; 13514#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13389#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13390#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13680#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13648#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13526#L715-39 assume 1 == ~t9_pc~0; 12698#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12700#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12775#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12776#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13853#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13854#L734-39 assume 1 == ~t10_pc~0; 13783#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13216#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13551#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12854#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12855#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14109#L753-39 assume !(1 == ~t11_pc~0); 12773#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 12774#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13677#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13519#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13520#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13611#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13612#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13874#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13875#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14089#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13798#L1257-3 assume !(1 == ~T5_E~0); 13799#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14062#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14112#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14215#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12926#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12927#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12837#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12838#L1297-3 assume !(1 == ~E_1~0); 13983#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13984#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14167#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14240#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13894#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13895#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12893#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12870#L1337-3 assume !(1 == ~E_9~0); 12871#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13586#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13706#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13707#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12814#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13023#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 13024#L1697 assume !(0 == start_simulation_~tmp~3#1); 13605#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13606#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12944#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12712#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 12713#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13674#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13675#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 13973#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 13974#L1678-2 [2024-11-09 16:08:38,349 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,349 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2024-11-09 16:08:38,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369759808] [2024-11-09 16:08:38,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,388 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369759808] [2024-11-09 16:08:38,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369759808] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [374621804] [2024-11-09 16:08:38,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,389 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:38,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,390 INFO L85 PathProgramCache]: Analyzing trace with hash -1273771663, now seen corresponding path program 1 times [2024-11-09 16:08:38,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376972446] [2024-11-09 16:08:38,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376972446] [2024-11-09 16:08:38,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376972446] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778915559] [2024-11-09 16:08:38,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,437 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:38,437 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:38,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:38,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:38,438 INFO L87 Difference]: Start difference. First operand 1578 states and 2334 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:38,464 INFO L93 Difference]: Finished difference Result 1578 states and 2333 transitions. [2024-11-09 16:08:38,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2333 transitions. [2024-11-09 16:08:38,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2333 transitions. [2024-11-09 16:08:38,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:38,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:38,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2333 transitions. [2024-11-09 16:08:38,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:38,478 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2024-11-09 16:08:38,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2333 transitions. [2024-11-09 16:08:38,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:38,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4784537389100127) internal successors, (2333), 1577 states have internal predecessors, (2333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2333 transitions. [2024-11-09 16:08:38,499 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2024-11-09 16:08:38,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:38,501 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2333 transitions. [2024-11-09 16:08:38,501 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-09 16:08:38,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2333 transitions. [2024-11-09 16:08:38,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:38,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:38,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,510 INFO L745 eck$LassoCheckResult]: Stem: 16085#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16086#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16059#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 16060#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17300#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17269#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17270#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16418#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16419#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16834#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17236#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16322#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16323#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16213#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16214#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17167#L1109 assume !(0 == ~M_E~0); 17184#L1109-2 assume !(0 == ~T1_E~0); 16222#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16223#L1119-1 assume !(0 == ~T3_E~0); 17239#L1124-1 assume !(0 == ~T4_E~0); 15873#L1129-1 assume !(0 == ~T5_E~0); 15874#L1134-1 assume !(0 == ~T6_E~0); 16505#L1139-1 assume !(0 == ~T7_E~0); 17175#L1144-1 assume !(0 == ~T8_E~0); 17045#L1149-1 assume !(0 == ~T9_E~0); 15984#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15985#L1159-1 assume !(0 == ~T11_E~0); 17035#L1164-1 assume !(0 == ~E_M~0); 16380#L1169-1 assume !(0 == ~E_1~0); 16274#L1174-1 assume !(0 == ~E_2~0); 16138#L1179-1 assume !(0 == ~E_3~0); 16065#L1184-1 assume !(0 == ~E_4~0); 16066#L1189-1 assume !(0 == ~E_5~0); 16098#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16181#L1199-1 assume !(0 == ~E_7~0); 17054#L1204-1 assume !(0 == ~E_8~0); 16995#L1209-1 assume !(0 == ~E_9~0); 16996#L1214-1 assume !(0 == ~E_10~0); 17313#L1219-1 assume !(0 == ~E_11~0); 17400#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16397#L544 assume 1 == ~m_pc~0; 16398#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17223#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16753#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16027#L1379 assume !(0 != activate_threads_~tmp~1#1); 16028#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16821#L563 assume !(1 == ~t1_pc~0); 16627#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15883#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15884#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16943#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 15879#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15880#L582 assume 1 == ~t2_pc~0; 16605#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16948#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16218#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16219#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 15912#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15913#L601 assume !(1 == ~t3_pc~0); 16622#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16621#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16980#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 16981#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16929#L620 assume 1 == ~t4_pc~0; 15893#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15894#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15926#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15927#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 16831#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17013#L639 assume 1 == ~t5_pc~0; 16903#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16186#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16187#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16851#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 16852#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16786#L658 assume !(1 == ~t6_pc~0); 16394#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16395#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16210#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16211#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16984#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16233#L677 assume 1 == ~t7_pc~0; 16234#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16131#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17141#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17262#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 17263#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17333#L696 assume !(1 == ~t8_pc~0); 16458#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16459#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17298#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17336#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 17381#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16890#L715 assume 1 == ~t9_pc~0; 16891#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16558#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16272#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16273#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 16873#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17136#L734 assume !(1 == ~t10_pc~0); 17137#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16350#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16351#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17079#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 17080#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16432#L753 assume 1 == ~t11_pc~0; 16433#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16989#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17307#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16708#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 16709#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16760#L1237 assume !(1 == ~M_E~0); 16761#L1237-2 assume !(1 == ~T1_E~0); 17364#L1242-1 assume !(1 == ~T2_E~0); 16526#L1247-1 assume !(1 == ~T3_E~0); 16527#L1252-1 assume !(1 == ~T4_E~0); 16291#L1257-1 assume !(1 == ~T5_E~0); 16292#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17156#L1267-1 assume !(1 == ~T7_E~0); 17254#L1272-1 assume !(1 == ~T8_E~0); 16616#L1277-1 assume !(1 == ~T9_E~0); 16617#L1282-1 assume !(1 == ~T10_E~0); 17022#L1287-1 assume !(1 == ~T11_E~0); 17023#L1292-1 assume !(1 == ~E_M~0); 16983#L1297-1 assume !(1 == ~E_1~0); 16423#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16424#L1307-1 assume !(1 == ~E_3~0); 17243#L1312-1 assume !(1 == ~E_4~0); 16662#L1317-1 assume !(1 == ~E_5~0); 16663#L1322-1 assume !(1 == ~E_6~0); 16367#L1327-1 assume !(1 == ~E_7~0); 16368#L1332-1 assume !(1 == ~E_8~0); 16942#L1337-1 assume !(1 == ~E_9~0); 16876#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16877#L1347-1 assume !(1 == ~E_11~0); 17242#L1352-1 assume { :end_inline_reset_delta_events } true; 17140#L1678-2 [2024-11-09 16:08:38,511 INFO L747 eck$LassoCheckResult]: Loop: 17140#L1678-2 assume !false; 16932#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16933#L1084-1 assume !false; 16729#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16730#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16003#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 17228#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15923#L925 assume !(0 != eval_~tmp~0#1); 15925#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16416#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16417#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15896#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15897#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16985#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16986#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17010#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17011#L1134-3 assume !(0 == ~T6_E~0); 17180#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17231#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16407#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16408#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16669#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16670#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16925#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16926#L1174-3 assume !(0 == ~E_2~0); 16973#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16974#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17119#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16815#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16160#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16161#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16387#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15846#L1214-3 assume !(0 == ~E_10~0); 15847#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16570#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16571#L544-39 assume 1 == ~m_pc~0; 16917#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15835#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16893#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16241#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16242#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17106#L563-39 assume 1 == ~t1_pc~0; 17112#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15980#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17391#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17392#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17395#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17214#L582-39 assume !(1 == ~t2_pc~0); 16305#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 16304#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16639#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16640#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16074#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15858#L601-39 assume 1 == ~t3_pc~0; 15859#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15907#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17073#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17402#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17110#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16781#L620-39 assume 1 == ~t4_pc~0; 16782#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16971#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16806#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16807#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17083#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17406#L639-39 assume 1 == ~t5_pc~0; 17197#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16529#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16530#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15885#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 15886#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16818#L658-39 assume 1 == ~t6_pc~0; 16801#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16802#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17258#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16994#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16968#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16969#L677-39 assume !(1 == ~t7_pc~0); 16614#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 16063#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16064#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16119#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16120#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16711#L696-39 assume 1 == ~t8_pc~0; 16677#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16552#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16553#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16843#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16811#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16691#L715-39 assume 1 == ~t9_pc~0; 15863#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15865#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15940#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15941#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17016#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17017#L734-39 assume 1 == ~t10_pc~0; 16946#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16379#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16714#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16017#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16018#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17272#L753-39 assume !(1 == ~t11_pc~0); 15936#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 15937#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16840#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16682#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16683#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16778#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16779#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17037#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17038#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17253#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16961#L1257-3 assume !(1 == ~T5_E~0); 16962#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17226#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17275#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17378#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16090#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16091#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16000#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16001#L1297-3 assume !(1 == ~E_1~0); 17149#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17150#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17330#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17403#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17057#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17058#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16056#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16033#L1337-3 assume !(1 == ~E_9~0); 16034#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16749#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16871#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16872#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15982#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16188#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 16189#L1697 assume !(0 == start_simulation_~tmp~3#1); 16768#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16769#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16107#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 15875#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 15876#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16837#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16838#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17139#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 17140#L1678-2 [2024-11-09 16:08:38,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,512 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2024-11-09 16:08:38,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125061365] [2024-11-09 16:08:38,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,547 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2125061365] [2024-11-09 16:08:38,547 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2125061365] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,547 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969491038] [2024-11-09 16:08:38,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,548 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:38,548 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,548 INFO L85 PathProgramCache]: Analyzing trace with hash -1155596751, now seen corresponding path program 2 times [2024-11-09 16:08:38,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343588818] [2024-11-09 16:08:38,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343588818] [2024-11-09 16:08:38,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [343588818] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131168245] [2024-11-09 16:08:38,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,591 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:38,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:38,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:38,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:38,592 INFO L87 Difference]: Start difference. First operand 1578 states and 2333 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:38,610 INFO L93 Difference]: Finished difference Result 1578 states and 2332 transitions. [2024-11-09 16:08:38,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2332 transitions. [2024-11-09 16:08:38,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2332 transitions. [2024-11-09 16:08:38,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:38,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:38,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2332 transitions. [2024-11-09 16:08:38,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:38,623 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2024-11-09 16:08:38,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2332 transitions. [2024-11-09 16:08:38,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:38,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4778200253485425) internal successors, (2332), 1577 states have internal predecessors, (2332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2332 transitions. [2024-11-09 16:08:38,643 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2024-11-09 16:08:38,643 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:38,643 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2332 transitions. [2024-11-09 16:08:38,644 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-09 16:08:38,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2332 transitions. [2024-11-09 16:08:38,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:38,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:38,650 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,650 INFO L745 eck$LassoCheckResult]: Stem: 19248#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19249#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20029#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20030#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19222#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 19223#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20463#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20432#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20433#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19581#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19582#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19997#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20399#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19485#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19486#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19376#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19377#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20330#L1109 assume !(0 == ~M_E~0); 20347#L1109-2 assume !(0 == ~T1_E~0); 19385#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19386#L1119-1 assume !(0 == ~T3_E~0); 20402#L1124-1 assume !(0 == ~T4_E~0); 19036#L1129-1 assume !(0 == ~T5_E~0); 19037#L1134-1 assume !(0 == ~T6_E~0); 19668#L1139-1 assume !(0 == ~T7_E~0); 20338#L1144-1 assume !(0 == ~T8_E~0); 20208#L1149-1 assume !(0 == ~T9_E~0); 19147#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19148#L1159-1 assume !(0 == ~T11_E~0); 20198#L1164-1 assume !(0 == ~E_M~0); 19543#L1169-1 assume !(0 == ~E_1~0); 19437#L1174-1 assume !(0 == ~E_2~0); 19301#L1179-1 assume !(0 == ~E_3~0); 19228#L1184-1 assume !(0 == ~E_4~0); 19229#L1189-1 assume !(0 == ~E_5~0); 19261#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 19344#L1199-1 assume !(0 == ~E_7~0); 20217#L1204-1 assume !(0 == ~E_8~0); 20158#L1209-1 assume !(0 == ~E_9~0); 20159#L1214-1 assume !(0 == ~E_10~0); 20476#L1219-1 assume !(0 == ~E_11~0); 20563#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19560#L544 assume 1 == ~m_pc~0; 19561#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20386#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19916#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19190#L1379 assume !(0 != activate_threads_~tmp~1#1); 19191#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19984#L563 assume !(1 == ~t1_pc~0); 19790#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19046#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19047#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20106#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 19042#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19043#L582 assume 1 == ~t2_pc~0; 19768#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20111#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19381#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19382#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 19075#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19076#L601 assume !(1 == ~t3_pc~0); 19785#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19784#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20238#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20143#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 20144#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20092#L620 assume 1 == ~t4_pc~0; 19056#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19057#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19090#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 19994#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20176#L639 assume 1 == ~t5_pc~0; 20066#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19349#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19350#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20014#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 20015#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19949#L658 assume !(1 == ~t6_pc~0); 19557#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19558#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19373#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19374#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20147#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19396#L677 assume 1 == ~t7_pc~0; 19397#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19294#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20304#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20425#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 20426#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20496#L696 assume !(1 == ~t8_pc~0); 19621#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19622#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20461#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20499#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 20544#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20053#L715 assume 1 == ~t9_pc~0; 20054#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19721#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19435#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19436#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 20036#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20299#L734 assume !(1 == ~t10_pc~0); 20300#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19513#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19514#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20242#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 20243#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19595#L753 assume 1 == ~t11_pc~0; 19596#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20152#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20470#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19871#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 19872#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19923#L1237 assume !(1 == ~M_E~0); 19924#L1237-2 assume !(1 == ~T1_E~0); 20527#L1242-1 assume !(1 == ~T2_E~0); 19689#L1247-1 assume !(1 == ~T3_E~0); 19690#L1252-1 assume !(1 == ~T4_E~0); 19454#L1257-1 assume !(1 == ~T5_E~0); 19455#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20319#L1267-1 assume !(1 == ~T7_E~0); 20417#L1272-1 assume !(1 == ~T8_E~0); 19779#L1277-1 assume !(1 == ~T9_E~0); 19780#L1282-1 assume !(1 == ~T10_E~0); 20185#L1287-1 assume !(1 == ~T11_E~0); 20186#L1292-1 assume !(1 == ~E_M~0); 20146#L1297-1 assume !(1 == ~E_1~0); 19586#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19587#L1307-1 assume !(1 == ~E_3~0); 20406#L1312-1 assume !(1 == ~E_4~0); 19825#L1317-1 assume !(1 == ~E_5~0); 19826#L1322-1 assume !(1 == ~E_6~0); 19530#L1327-1 assume !(1 == ~E_7~0); 19531#L1332-1 assume !(1 == ~E_8~0); 20105#L1337-1 assume !(1 == ~E_9~0); 20039#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20040#L1347-1 assume !(1 == ~E_11~0); 20405#L1352-1 assume { :end_inline_reset_delta_events } true; 20303#L1678-2 [2024-11-09 16:08:38,651 INFO L747 eck$LassoCheckResult]: Loop: 20303#L1678-2 assume !false; 20095#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20096#L1084-1 assume !false; 19892#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19893#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19166#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20391#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19086#L925 assume !(0 != eval_~tmp~0#1); 19088#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19579#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19580#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19059#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19060#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20148#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20149#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20173#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20174#L1134-3 assume !(0 == ~T6_E~0); 20343#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20394#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19570#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19571#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19832#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19833#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20088#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20089#L1174-3 assume !(0 == ~E_2~0); 20136#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20137#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20282#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19978#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19323#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19324#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19550#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19009#L1214-3 assume !(0 == ~E_10~0); 19010#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19733#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19734#L544-39 assume 1 == ~m_pc~0; 20080#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18998#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20056#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19404#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19405#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20269#L563-39 assume 1 == ~t1_pc~0; 20275#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19143#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20554#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20555#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20558#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20377#L582-39 assume 1 == ~t2_pc~0; 19466#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19467#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19802#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19803#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19237#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19021#L601-39 assume 1 == ~t3_pc~0; 19022#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19070#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20236#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20565#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20273#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19944#L620-39 assume 1 == ~t4_pc~0; 19945#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20134#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19969#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19970#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20246#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20569#L639-39 assume 1 == ~t5_pc~0; 20360#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19692#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19693#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19048#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 19049#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19981#L658-39 assume 1 == ~t6_pc~0; 19964#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19965#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20421#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20157#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20131#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20132#L677-39 assume !(1 == ~t7_pc~0); 19777#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 19226#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19227#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19282#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19283#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19874#L696-39 assume 1 == ~t8_pc~0; 19840#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19715#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19716#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20006#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19974#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19854#L715-39 assume 1 == ~t9_pc~0; 19026#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19028#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19103#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19104#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20179#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20180#L734-39 assume !(1 == ~t10_pc~0); 19541#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 19542#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19877#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19180#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19181#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20435#L753-39 assume !(1 == ~t11_pc~0); 19099#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 19100#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20003#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19845#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19846#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19941#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19942#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20200#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20201#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20416#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20124#L1257-3 assume !(1 == ~T5_E~0); 20125#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20389#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20438#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20541#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19253#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19254#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19163#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19164#L1297-3 assume !(1 == ~E_1~0); 20312#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20313#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20493#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20566#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20220#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20221#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19219#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19196#L1337-3 assume !(1 == ~E_9~0); 19197#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19912#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20034#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 20035#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19145#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19351#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 19352#L1697 assume !(0 == start_simulation_~tmp~3#1); 19931#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19932#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19270#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19038#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 19039#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20000#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20001#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 20302#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 20303#L1678-2 [2024-11-09 16:08:38,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,654 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2024-11-09 16:08:38,654 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655899645] [2024-11-09 16:08:38,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1655899645] [2024-11-09 16:08:38,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1655899645] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607915817] [2024-11-09 16:08:38,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,688 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:38,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,688 INFO L85 PathProgramCache]: Analyzing trace with hash -2120948687, now seen corresponding path program 1 times [2024-11-09 16:08:38,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030707980] [2024-11-09 16:08:38,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030707980] [2024-11-09 16:08:38,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1030707980] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,780 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734612584] [2024-11-09 16:08:38,781 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,781 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:38,781 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:38,781 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:38,781 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:38,782 INFO L87 Difference]: Start difference. First operand 1578 states and 2332 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:38,804 INFO L93 Difference]: Finished difference Result 1578 states and 2331 transitions. [2024-11-09 16:08:38,804 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2331 transitions. [2024-11-09 16:08:38,810 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2331 transitions. [2024-11-09 16:08:38,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:38,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:38,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2331 transitions. [2024-11-09 16:08:38,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:38,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2024-11-09 16:08:38,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2331 transitions. [2024-11-09 16:08:38,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:38,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4771863117870723) internal successors, (2331), 1577 states have internal predecessors, (2331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2331 transitions. [2024-11-09 16:08:38,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2024-11-09 16:08:38,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:38,843 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2331 transitions. [2024-11-09 16:08:38,843 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-09 16:08:38,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2331 transitions. [2024-11-09 16:08:38,847 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:38,847 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:38,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,848 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:38,849 INFO L745 eck$LassoCheckResult]: Stem: 22411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23192#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23193#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22385#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 22386#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23626#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23595#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23596#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22744#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22745#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23160#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23562#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22648#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22649#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22539#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22540#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23493#L1109 assume !(0 == ~M_E~0); 23510#L1109-2 assume !(0 == ~T1_E~0); 22548#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22549#L1119-1 assume !(0 == ~T3_E~0); 23565#L1124-1 assume !(0 == ~T4_E~0); 22199#L1129-1 assume !(0 == ~T5_E~0); 22200#L1134-1 assume !(0 == ~T6_E~0); 22831#L1139-1 assume !(0 == ~T7_E~0); 23501#L1144-1 assume !(0 == ~T8_E~0); 23371#L1149-1 assume !(0 == ~T9_E~0); 22310#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22311#L1159-1 assume !(0 == ~T11_E~0); 23361#L1164-1 assume !(0 == ~E_M~0); 22706#L1169-1 assume !(0 == ~E_1~0); 22600#L1174-1 assume !(0 == ~E_2~0); 22464#L1179-1 assume !(0 == ~E_3~0); 22391#L1184-1 assume !(0 == ~E_4~0); 22392#L1189-1 assume !(0 == ~E_5~0); 22424#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22507#L1199-1 assume !(0 == ~E_7~0); 23380#L1204-1 assume !(0 == ~E_8~0); 23321#L1209-1 assume !(0 == ~E_9~0); 23322#L1214-1 assume !(0 == ~E_10~0); 23639#L1219-1 assume !(0 == ~E_11~0); 23726#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22723#L544 assume 1 == ~m_pc~0; 22724#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23549#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23079#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22353#L1379 assume !(0 != activate_threads_~tmp~1#1); 22354#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23147#L563 assume !(1 == ~t1_pc~0); 22953#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22209#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22210#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23269#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 22205#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22206#L582 assume 1 == ~t2_pc~0; 22931#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23274#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22544#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22545#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 22238#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22239#L601 assume !(1 == ~t3_pc~0); 22948#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22947#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23401#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23306#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 23307#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23255#L620 assume 1 == ~t4_pc~0; 22219#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22220#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22252#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22253#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 23157#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23339#L639 assume 1 == ~t5_pc~0; 23229#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22512#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22513#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23177#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 23178#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23112#L658 assume !(1 == ~t6_pc~0); 22720#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22721#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22536#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22537#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23310#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22559#L677 assume 1 == ~t7_pc~0; 22560#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22457#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23467#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23588#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 23589#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23659#L696 assume !(1 == ~t8_pc~0); 22784#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22785#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23624#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23662#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 23707#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23216#L715 assume 1 == ~t9_pc~0; 23217#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22884#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22598#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22599#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 23199#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23462#L734 assume !(1 == ~t10_pc~0); 23463#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22676#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22677#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23405#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 23406#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22758#L753 assume 1 == ~t11_pc~0; 22759#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23315#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23633#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23034#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 23035#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23086#L1237 assume !(1 == ~M_E~0); 23087#L1237-2 assume !(1 == ~T1_E~0); 23690#L1242-1 assume !(1 == ~T2_E~0); 22852#L1247-1 assume !(1 == ~T3_E~0); 22853#L1252-1 assume !(1 == ~T4_E~0); 22617#L1257-1 assume !(1 == ~T5_E~0); 22618#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23482#L1267-1 assume !(1 == ~T7_E~0); 23580#L1272-1 assume !(1 == ~T8_E~0); 22942#L1277-1 assume !(1 == ~T9_E~0); 22943#L1282-1 assume !(1 == ~T10_E~0); 23348#L1287-1 assume !(1 == ~T11_E~0); 23349#L1292-1 assume !(1 == ~E_M~0); 23309#L1297-1 assume !(1 == ~E_1~0); 22749#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22750#L1307-1 assume !(1 == ~E_3~0); 23569#L1312-1 assume !(1 == ~E_4~0); 22988#L1317-1 assume !(1 == ~E_5~0); 22989#L1322-1 assume !(1 == ~E_6~0); 22693#L1327-1 assume !(1 == ~E_7~0); 22694#L1332-1 assume !(1 == ~E_8~0); 23268#L1337-1 assume !(1 == ~E_9~0); 23202#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23203#L1347-1 assume !(1 == ~E_11~0); 23568#L1352-1 assume { :end_inline_reset_delta_events } true; 23466#L1678-2 [2024-11-09 16:08:38,849 INFO L747 eck$LassoCheckResult]: Loop: 23466#L1678-2 assume !false; 23258#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23259#L1084-1 assume !false; 23055#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23056#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22329#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23554#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22249#L925 assume !(0 != eval_~tmp~0#1); 22251#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22742#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22743#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22222#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22223#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23311#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23312#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23336#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23337#L1134-3 assume !(0 == ~T6_E~0); 23506#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23557#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22733#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22734#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22995#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22996#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23251#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23252#L1174-3 assume !(0 == ~E_2~0); 23299#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23300#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23445#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23141#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22486#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22487#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22713#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22172#L1214-3 assume !(0 == ~E_10~0); 22173#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22896#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22897#L544-39 assume !(1 == ~m_pc~0); 22160#L544-41 is_master_triggered_~__retres1~0#1 := 0; 22161#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23219#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22567#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22568#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23432#L563-39 assume !(1 == ~t1_pc~0); 22305#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 22306#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23717#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23718#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23721#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23540#L582-39 assume 1 == ~t2_pc~0; 22629#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22630#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22965#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22966#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22400#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22184#L601-39 assume 1 == ~t3_pc~0; 22185#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22233#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23399#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23728#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23436#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23107#L620-39 assume 1 == ~t4_pc~0; 23108#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23297#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23132#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23133#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23409#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23732#L639-39 assume 1 == ~t5_pc~0; 23523#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22855#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22856#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22211#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 22212#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23144#L658-39 assume 1 == ~t6_pc~0; 23127#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23128#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23584#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23320#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23294#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23295#L677-39 assume !(1 == ~t7_pc~0); 22940#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 22389#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22390#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22445#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22446#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23037#L696-39 assume 1 == ~t8_pc~0; 23003#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22878#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22879#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23169#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23137#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23017#L715-39 assume 1 == ~t9_pc~0; 22189#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22191#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22266#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22267#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23342#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23343#L734-39 assume !(1 == ~t10_pc~0); 22704#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 22705#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23040#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22343#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22344#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23598#L753-39 assume !(1 == ~t11_pc~0); 22262#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 22263#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23166#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23008#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23009#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23104#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23105#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23363#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23364#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23579#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23287#L1257-3 assume !(1 == ~T5_E~0); 23288#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23552#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23601#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23704#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22416#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22417#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22326#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22327#L1297-3 assume !(1 == ~E_1~0); 23475#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23476#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23656#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23729#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23383#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23384#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22382#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22359#L1337-3 assume !(1 == ~E_9~0); 22360#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23075#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23197#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23198#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22308#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22514#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 22515#L1697 assume !(0 == start_simulation_~tmp~3#1); 23094#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23095#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22433#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22201#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 22202#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23163#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23164#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 23465#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 23466#L1678-2 [2024-11-09 16:08:38,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,850 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2024-11-09 16:08:38,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117874608] [2024-11-09 16:08:38,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117874608] [2024-11-09 16:08:38,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117874608] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,895 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,895 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192123032] [2024-11-09 16:08:38,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,896 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:38,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:38,896 INFO L85 PathProgramCache]: Analyzing trace with hash -770175885, now seen corresponding path program 1 times [2024-11-09 16:08:38,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:38,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006529109] [2024-11-09 16:08:38,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:38,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:38,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:38,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:38,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:38,953 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006529109] [2024-11-09 16:08:38,954 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1006529109] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:38,954 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:38,954 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:38,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269891760] [2024-11-09 16:08:38,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:38,955 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:38,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:38,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:38,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:38,956 INFO L87 Difference]: Start difference. First operand 1578 states and 2331 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:38,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:38,979 INFO L93 Difference]: Finished difference Result 1578 states and 2330 transitions. [2024-11-09 16:08:38,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2330 transitions. [2024-11-09 16:08:38,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:38,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2330 transitions. [2024-11-09 16:08:38,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:38,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:38,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2330 transitions. [2024-11-09 16:08:38,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:38,995 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2024-11-09 16:08:38,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2330 transitions. [2024-11-09 16:08:39,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:39,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.476552598225602) internal successors, (2330), 1577 states have internal predecessors, (2330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2330 transitions. [2024-11-09 16:08:39,020 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2024-11-09 16:08:39,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:39,020 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2330 transitions. [2024-11-09 16:08:39,021 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-09 16:08:39,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2330 transitions. [2024-11-09 16:08:39,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:39,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:39,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:39,027 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,028 INFO L745 eck$LassoCheckResult]: Stem: 25574#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25548#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 25549#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26789#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26758#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26759#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25907#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25908#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26323#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26725#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25811#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25812#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25702#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25703#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26656#L1109 assume !(0 == ~M_E~0); 26673#L1109-2 assume !(0 == ~T1_E~0); 25711#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25712#L1119-1 assume !(0 == ~T3_E~0); 26728#L1124-1 assume !(0 == ~T4_E~0); 25362#L1129-1 assume !(0 == ~T5_E~0); 25363#L1134-1 assume !(0 == ~T6_E~0); 25994#L1139-1 assume !(0 == ~T7_E~0); 26664#L1144-1 assume !(0 == ~T8_E~0); 26534#L1149-1 assume !(0 == ~T9_E~0); 25475#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25476#L1159-1 assume !(0 == ~T11_E~0); 26524#L1164-1 assume !(0 == ~E_M~0); 25869#L1169-1 assume !(0 == ~E_1~0); 25763#L1174-1 assume !(0 == ~E_2~0); 25629#L1179-1 assume !(0 == ~E_3~0); 25554#L1184-1 assume !(0 == ~E_4~0); 25555#L1189-1 assume !(0 == ~E_5~0); 25587#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 25672#L1199-1 assume !(0 == ~E_7~0); 26543#L1204-1 assume !(0 == ~E_8~0); 26484#L1209-1 assume !(0 == ~E_9~0); 26485#L1214-1 assume !(0 == ~E_10~0); 26802#L1219-1 assume !(0 == ~E_11~0); 26889#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25886#L544 assume 1 == ~m_pc~0; 25887#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26712#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26242#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25516#L1379 assume !(0 != activate_threads_~tmp~1#1); 25517#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26312#L563 assume !(1 == ~t1_pc~0); 26116#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25372#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25373#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26432#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 25368#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25369#L582 assume 1 == ~t2_pc~0; 26094#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26437#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25707#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25708#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 25401#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25402#L601 assume !(1 == ~t3_pc~0); 26111#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26110#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26564#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26469#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 26470#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26418#L620 assume 1 == ~t4_pc~0; 25382#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25383#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25415#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25416#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 26320#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26503#L639 assume 1 == ~t5_pc~0; 26392#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25677#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25678#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26340#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 26341#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26275#L658 assume !(1 == ~t6_pc~0); 25883#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25884#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25699#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25700#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26473#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25724#L677 assume 1 == ~t7_pc~0; 25725#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25623#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26630#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26751#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 26752#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26822#L696 assume !(1 == ~t8_pc~0); 25948#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25949#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26787#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26825#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 26870#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26379#L715 assume 1 == ~t9_pc~0; 26380#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26047#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25761#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25762#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 26362#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26627#L734 assume !(1 == ~t10_pc~0); 26628#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25839#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25840#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26568#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 26569#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25921#L753 assume 1 == ~t11_pc~0; 25922#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26478#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26796#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26199#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 26200#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26251#L1237 assume !(1 == ~M_E~0); 26252#L1237-2 assume !(1 == ~T1_E~0); 26854#L1242-1 assume !(1 == ~T2_E~0); 26015#L1247-1 assume !(1 == ~T3_E~0); 26016#L1252-1 assume !(1 == ~T4_E~0); 25780#L1257-1 assume !(1 == ~T5_E~0); 25781#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26645#L1267-1 assume !(1 == ~T7_E~0); 26743#L1272-1 assume !(1 == ~T8_E~0); 26105#L1277-1 assume !(1 == ~T9_E~0); 26106#L1282-1 assume !(1 == ~T10_E~0); 26511#L1287-1 assume !(1 == ~T11_E~0); 26512#L1292-1 assume !(1 == ~E_M~0); 26472#L1297-1 assume !(1 == ~E_1~0); 25912#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25913#L1307-1 assume !(1 == ~E_3~0); 26732#L1312-1 assume !(1 == ~E_4~0); 26151#L1317-1 assume !(1 == ~E_5~0); 26152#L1322-1 assume !(1 == ~E_6~0); 25856#L1327-1 assume !(1 == ~E_7~0); 25857#L1332-1 assume !(1 == ~E_8~0); 26431#L1337-1 assume !(1 == ~E_9~0); 26365#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26366#L1347-1 assume !(1 == ~E_11~0); 26731#L1352-1 assume { :end_inline_reset_delta_events } true; 26626#L1678-2 [2024-11-09 16:08:39,030 INFO L747 eck$LassoCheckResult]: Loop: 26626#L1678-2 assume !false; 26421#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26422#L1084-1 assume !false; 26218#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26219#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25492#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26717#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25412#L925 assume !(0 != eval_~tmp~0#1); 25414#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25906#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25385#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25386#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26474#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26475#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26499#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26500#L1134-3 assume !(0 == ~T6_E~0); 26669#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26720#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25896#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25897#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26159#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26160#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26414#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26415#L1174-3 assume !(0 == ~E_2~0); 26462#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26463#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26608#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26304#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25652#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25653#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25880#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25340#L1214-3 assume !(0 == ~E_10~0); 25341#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26059#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26060#L544-39 assume 1 == ~m_pc~0; 26407#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25324#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26382#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25730#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25731#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26595#L563-39 assume 1 == ~t1_pc~0; 26601#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25472#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26880#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26881#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26884#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26703#L582-39 assume 1 == ~t2_pc~0; 25792#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25793#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26128#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26129#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25565#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25347#L601-39 assume 1 == ~t3_pc~0; 25348#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25393#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26562#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26891#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26599#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26269#L620-39 assume 1 == ~t4_pc~0; 26270#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26460#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26295#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26296#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26572#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26894#L639-39 assume 1 == ~t5_pc~0; 26686#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26018#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26019#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25374#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 25375#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26307#L658-39 assume 1 == ~t6_pc~0; 26290#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26291#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26747#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26483#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26457#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26458#L677-39 assume !(1 == ~t7_pc~0); 26101#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 25552#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25553#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25608#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25609#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26198#L696-39 assume 1 == ~t8_pc~0; 26166#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26041#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26042#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26332#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26300#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26180#L715-39 assume 1 == ~t9_pc~0; 25350#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25352#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25429#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25430#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26505#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26506#L734-39 assume 1 == ~t10_pc~0; 26435#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25868#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26203#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25506#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25507#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26761#L753-39 assume !(1 == ~t11_pc~0); 25425#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 25426#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26329#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26171#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26172#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26263#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26264#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26526#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26527#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26742#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26450#L1257-3 assume !(1 == ~T5_E~0); 26451#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26714#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26764#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26867#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25579#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25580#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25489#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25490#L1297-3 assume !(1 == ~E_1~0); 26638#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26639#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26819#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26892#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26546#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26547#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25545#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25522#L1337-3 assume !(1 == ~E_9~0); 25523#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26238#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26360#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26361#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25466#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25675#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 25676#L1697 assume !(0 == start_simulation_~tmp~3#1); 26257#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26258#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25596#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25364#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 25365#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26326#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26327#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 26625#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 26626#L1678-2 [2024-11-09 16:08:39,031 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,031 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2024-11-09 16:08:39,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001015364] [2024-11-09 16:08:39,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001015364] [2024-11-09 16:08:39,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001015364] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109439227] [2024-11-09 16:08:39,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,073 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:39,073 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,074 INFO L85 PathProgramCache]: Analyzing trace with hash 705815280, now seen corresponding path program 2 times [2024-11-09 16:08:39,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485748523] [2024-11-09 16:08:39,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485748523] [2024-11-09 16:08:39,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485748523] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,120 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576474472] [2024-11-09 16:08:39,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,120 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:39,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:39,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:39,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:39,121 INFO L87 Difference]: Start difference. First operand 1578 states and 2330 transitions. cyclomatic complexity: 753 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:39,141 INFO L93 Difference]: Finished difference Result 1578 states and 2329 transitions. [2024-11-09 16:08:39,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2329 transitions. [2024-11-09 16:08:39,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:39,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2329 transitions. [2024-11-09 16:08:39,150 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:39,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:39,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2329 transitions. [2024-11-09 16:08:39,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:39,153 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2024-11-09 16:08:39,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2329 transitions. [2024-11-09 16:08:39,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:39,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4759188846641318) internal successors, (2329), 1577 states have internal predecessors, (2329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2329 transitions. [2024-11-09 16:08:39,171 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2024-11-09 16:08:39,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:39,172 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2329 transitions. [2024-11-09 16:08:39,173 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-09 16:08:39,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2329 transitions. [2024-11-09 16:08:39,176 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:39,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:39,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:39,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,178 INFO L745 eck$LassoCheckResult]: Stem: 28737#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 28738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29518#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29519#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28711#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 28712#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29952#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29921#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29922#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29070#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29071#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29486#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29888#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28974#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28975#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28865#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28866#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29819#L1109 assume !(0 == ~M_E~0); 29836#L1109-2 assume !(0 == ~T1_E~0); 28874#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28875#L1119-1 assume !(0 == ~T3_E~0); 29891#L1124-1 assume !(0 == ~T4_E~0); 28525#L1129-1 assume !(0 == ~T5_E~0); 28526#L1134-1 assume !(0 == ~T6_E~0); 29157#L1139-1 assume !(0 == ~T7_E~0); 29827#L1144-1 assume !(0 == ~T8_E~0); 29697#L1149-1 assume !(0 == ~T9_E~0); 28636#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28637#L1159-1 assume !(0 == ~T11_E~0); 29687#L1164-1 assume !(0 == ~E_M~0); 29032#L1169-1 assume !(0 == ~E_1~0); 28926#L1174-1 assume !(0 == ~E_2~0); 28790#L1179-1 assume !(0 == ~E_3~0); 28717#L1184-1 assume !(0 == ~E_4~0); 28718#L1189-1 assume !(0 == ~E_5~0); 28750#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28833#L1199-1 assume !(0 == ~E_7~0); 29706#L1204-1 assume !(0 == ~E_8~0); 29647#L1209-1 assume !(0 == ~E_9~0); 29648#L1214-1 assume !(0 == ~E_10~0); 29965#L1219-1 assume !(0 == ~E_11~0); 30052#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29049#L544 assume 1 == ~m_pc~0; 29050#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29875#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29405#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28679#L1379 assume !(0 != activate_threads_~tmp~1#1); 28680#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29473#L563 assume !(1 == ~t1_pc~0); 29279#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28535#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28536#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29595#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 28531#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28532#L582 assume 1 == ~t2_pc~0; 29257#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29600#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28870#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28871#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 28564#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28565#L601 assume !(1 == ~t3_pc~0); 29274#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29273#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29727#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29632#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 29633#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29581#L620 assume 1 == ~t4_pc~0; 28545#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28546#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28578#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28579#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 29483#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29665#L639 assume 1 == ~t5_pc~0; 29555#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28838#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28839#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29503#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 29504#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29438#L658 assume !(1 == ~t6_pc~0); 29046#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 29047#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28862#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28863#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29636#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28885#L677 assume 1 == ~t7_pc~0; 28886#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28783#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29793#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29914#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 29915#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29985#L696 assume !(1 == ~t8_pc~0); 29110#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29111#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29950#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29988#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 30033#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29542#L715 assume 1 == ~t9_pc~0; 29543#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29210#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28924#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28925#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 29525#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29788#L734 assume !(1 == ~t10_pc~0); 29789#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29002#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29003#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29731#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 29732#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29084#L753 assume 1 == ~t11_pc~0; 29085#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29641#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29959#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29360#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 29361#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29412#L1237 assume !(1 == ~M_E~0); 29413#L1237-2 assume !(1 == ~T1_E~0); 30016#L1242-1 assume !(1 == ~T2_E~0); 29178#L1247-1 assume !(1 == ~T3_E~0); 29179#L1252-1 assume !(1 == ~T4_E~0); 28943#L1257-1 assume !(1 == ~T5_E~0); 28944#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29808#L1267-1 assume !(1 == ~T7_E~0); 29906#L1272-1 assume !(1 == ~T8_E~0); 29268#L1277-1 assume !(1 == ~T9_E~0); 29269#L1282-1 assume !(1 == ~T10_E~0); 29674#L1287-1 assume !(1 == ~T11_E~0); 29675#L1292-1 assume !(1 == ~E_M~0); 29635#L1297-1 assume !(1 == ~E_1~0); 29075#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29076#L1307-1 assume !(1 == ~E_3~0); 29895#L1312-1 assume !(1 == ~E_4~0); 29314#L1317-1 assume !(1 == ~E_5~0); 29315#L1322-1 assume !(1 == ~E_6~0); 29019#L1327-1 assume !(1 == ~E_7~0); 29020#L1332-1 assume !(1 == ~E_8~0); 29594#L1337-1 assume !(1 == ~E_9~0); 29528#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29529#L1347-1 assume !(1 == ~E_11~0); 29894#L1352-1 assume { :end_inline_reset_delta_events } true; 29792#L1678-2 [2024-11-09 16:08:39,178 INFO L747 eck$LassoCheckResult]: Loop: 29792#L1678-2 assume !false; 29584#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29585#L1084-1 assume !false; 29381#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29382#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28655#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29880#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28575#L925 assume !(0 != eval_~tmp~0#1); 28577#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29068#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29069#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28548#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28549#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29637#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29638#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29662#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29663#L1134-3 assume !(0 == ~T6_E~0); 29832#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29883#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29059#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29060#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29321#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29322#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29577#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29578#L1174-3 assume !(0 == ~E_2~0); 29625#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29626#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29771#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29467#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28812#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28813#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29039#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28498#L1214-3 assume !(0 == ~E_10~0); 28499#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29222#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29223#L544-39 assume 1 == ~m_pc~0; 29569#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28487#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29545#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28893#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28894#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29758#L563-39 assume 1 == ~t1_pc~0; 29764#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28632#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30043#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30044#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30047#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29866#L582-39 assume 1 == ~t2_pc~0; 28955#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28956#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29291#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29292#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28726#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28510#L601-39 assume !(1 == ~t3_pc~0); 28512#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 28559#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29725#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30054#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29762#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29433#L620-39 assume 1 == ~t4_pc~0; 29434#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29623#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29458#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29459#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29735#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30058#L639-39 assume 1 == ~t5_pc~0; 29849#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29181#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29182#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28537#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 28538#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29470#L658-39 assume 1 == ~t6_pc~0; 29453#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29454#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29910#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29646#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29620#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29621#L677-39 assume !(1 == ~t7_pc~0); 29266#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 28715#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28716#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28771#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28772#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29363#L696-39 assume 1 == ~t8_pc~0; 29329#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29204#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29205#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29495#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29463#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29343#L715-39 assume 1 == ~t9_pc~0; 28515#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28517#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28592#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28593#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29668#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29669#L734-39 assume !(1 == ~t10_pc~0); 29030#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 29031#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29366#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28669#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28670#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29924#L753-39 assume !(1 == ~t11_pc~0); 28588#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 28589#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29492#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29334#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29335#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29430#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29431#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29689#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29690#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29905#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29613#L1257-3 assume !(1 == ~T5_E~0); 29614#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29878#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29927#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30030#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28742#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28743#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28652#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28653#L1297-3 assume !(1 == ~E_1~0); 29801#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29802#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29982#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30055#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29709#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29710#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28708#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28685#L1337-3 assume !(1 == ~E_9~0); 28686#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29401#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29523#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29524#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28634#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 28841#L1697 assume !(0 == start_simulation_~tmp~3#1); 29420#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29421#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28759#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 28528#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29489#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29490#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 29791#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 29792#L1678-2 [2024-11-09 16:08:39,179 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,179 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2024-11-09 16:08:39,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886251997] [2024-11-09 16:08:39,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,180 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886251997] [2024-11-09 16:08:39,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886251997] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595197086] [2024-11-09 16:08:39,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,252 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:39,252 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,252 INFO L85 PathProgramCache]: Analyzing trace with hash 1013171250, now seen corresponding path program 1 times [2024-11-09 16:08:39,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865783967] [2024-11-09 16:08:39,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,339 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865783967] [2024-11-09 16:08:39,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865783967] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616457113] [2024-11-09 16:08:39,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,339 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:39,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:39,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:39,340 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:39,340 INFO L87 Difference]: Start difference. First operand 1578 states and 2329 transitions. cyclomatic complexity: 752 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:39,358 INFO L93 Difference]: Finished difference Result 1578 states and 2328 transitions. [2024-11-09 16:08:39,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2328 transitions. [2024-11-09 16:08:39,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:39,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2328 transitions. [2024-11-09 16:08:39,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:39,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:39,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2328 transitions. [2024-11-09 16:08:39,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:39,370 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2024-11-09 16:08:39,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2328 transitions. [2024-11-09 16:08:39,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:39,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4752851711026616) internal successors, (2328), 1577 states have internal predecessors, (2328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2328 transitions. [2024-11-09 16:08:39,389 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2024-11-09 16:08:39,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:39,390 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2328 transitions. [2024-11-09 16:08:39,390 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-09 16:08:39,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2328 transitions. [2024-11-09 16:08:39,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:39,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:39,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:39,395 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,395 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,396 INFO L745 eck$LassoCheckResult]: Stem: 31900#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 31901#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32681#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32682#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31874#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 31875#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33115#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33084#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33085#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32233#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32234#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32649#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33051#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32137#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32138#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 32028#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32029#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32982#L1109 assume !(0 == ~M_E~0); 32999#L1109-2 assume !(0 == ~T1_E~0); 32037#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32038#L1119-1 assume !(0 == ~T3_E~0); 33054#L1124-1 assume !(0 == ~T4_E~0); 31688#L1129-1 assume !(0 == ~T5_E~0); 31689#L1134-1 assume !(0 == ~T6_E~0); 32320#L1139-1 assume !(0 == ~T7_E~0); 32990#L1144-1 assume !(0 == ~T8_E~0); 32860#L1149-1 assume !(0 == ~T9_E~0); 31799#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31800#L1159-1 assume !(0 == ~T11_E~0); 32850#L1164-1 assume !(0 == ~E_M~0); 32195#L1169-1 assume !(0 == ~E_1~0); 32089#L1174-1 assume !(0 == ~E_2~0); 31953#L1179-1 assume !(0 == ~E_3~0); 31880#L1184-1 assume !(0 == ~E_4~0); 31881#L1189-1 assume !(0 == ~E_5~0); 31913#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 31996#L1199-1 assume !(0 == ~E_7~0); 32869#L1204-1 assume !(0 == ~E_8~0); 32810#L1209-1 assume !(0 == ~E_9~0); 32811#L1214-1 assume !(0 == ~E_10~0); 33128#L1219-1 assume !(0 == ~E_11~0); 33215#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32212#L544 assume 1 == ~m_pc~0; 32213#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33038#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32568#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31842#L1379 assume !(0 != activate_threads_~tmp~1#1); 31843#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32636#L563 assume !(1 == ~t1_pc~0); 32442#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31698#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32758#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 31694#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31695#L582 assume 1 == ~t2_pc~0; 32420#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32763#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32033#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32034#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 31727#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31728#L601 assume !(1 == ~t3_pc~0); 32437#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32436#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32890#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32795#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 32796#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32744#L620 assume 1 == ~t4_pc~0; 31708#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31709#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31741#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31742#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 32646#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32828#L639 assume 1 == ~t5_pc~0; 32718#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32001#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32002#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32666#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 32667#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32601#L658 assume !(1 == ~t6_pc~0); 32209#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 32210#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32025#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32026#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32799#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32048#L677 assume 1 == ~t7_pc~0; 32049#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31946#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32956#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33077#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 33078#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33148#L696 assume !(1 == ~t8_pc~0); 32273#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32274#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33113#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33151#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 33196#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32705#L715 assume 1 == ~t9_pc~0; 32706#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32373#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32087#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32088#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 32688#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32951#L734 assume !(1 == ~t10_pc~0); 32952#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32165#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32166#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32894#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 32895#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32247#L753 assume 1 == ~t11_pc~0; 32248#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32804#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33122#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32523#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 32524#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32575#L1237 assume !(1 == ~M_E~0); 32576#L1237-2 assume !(1 == ~T1_E~0); 33179#L1242-1 assume !(1 == ~T2_E~0); 32341#L1247-1 assume !(1 == ~T3_E~0); 32342#L1252-1 assume !(1 == ~T4_E~0); 32106#L1257-1 assume !(1 == ~T5_E~0); 32107#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32971#L1267-1 assume !(1 == ~T7_E~0); 33069#L1272-1 assume !(1 == ~T8_E~0); 32431#L1277-1 assume !(1 == ~T9_E~0); 32432#L1282-1 assume !(1 == ~T10_E~0); 32837#L1287-1 assume !(1 == ~T11_E~0); 32838#L1292-1 assume !(1 == ~E_M~0); 32798#L1297-1 assume !(1 == ~E_1~0); 32238#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32239#L1307-1 assume !(1 == ~E_3~0); 33058#L1312-1 assume !(1 == ~E_4~0); 32477#L1317-1 assume !(1 == ~E_5~0); 32478#L1322-1 assume !(1 == ~E_6~0); 32182#L1327-1 assume !(1 == ~E_7~0); 32183#L1332-1 assume !(1 == ~E_8~0); 32757#L1337-1 assume !(1 == ~E_9~0); 32691#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32692#L1347-1 assume !(1 == ~E_11~0); 33057#L1352-1 assume { :end_inline_reset_delta_events } true; 32955#L1678-2 [2024-11-09 16:08:39,396 INFO L747 eck$LassoCheckResult]: Loop: 32955#L1678-2 assume !false; 32747#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32748#L1084-1 assume !false; 32544#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32545#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31818#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 33043#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31738#L925 assume !(0 != eval_~tmp~0#1); 31740#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32232#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31711#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31712#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32800#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32801#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32825#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32826#L1134-3 assume !(0 == ~T6_E~0); 32995#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33046#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32222#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32223#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32484#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32485#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32740#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32741#L1174-3 assume !(0 == ~E_2~0); 32788#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32789#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32934#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32630#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31975#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31976#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32202#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31661#L1214-3 assume !(0 == ~E_10~0); 31662#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32385#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32386#L544-39 assume !(1 == ~m_pc~0); 31649#L544-41 is_master_triggered_~__retres1~0#1 := 0; 31650#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32708#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32056#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32057#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32921#L563-39 assume !(1 == ~t1_pc~0); 31794#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 31795#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33206#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33207#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33210#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33029#L582-39 assume 1 == ~t2_pc~0; 32118#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32119#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32454#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32455#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31889#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31673#L601-39 assume 1 == ~t3_pc~0; 31674#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31722#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32888#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33217#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32925#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32596#L620-39 assume 1 == ~t4_pc~0; 32597#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32786#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32621#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32622#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32898#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33221#L639-39 assume 1 == ~t5_pc~0; 33012#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32344#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32345#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31700#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 31701#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32633#L658-39 assume 1 == ~t6_pc~0; 32616#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32617#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33073#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32809#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32783#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32784#L677-39 assume !(1 == ~t7_pc~0); 32429#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 31878#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31879#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31934#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31935#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32526#L696-39 assume 1 == ~t8_pc~0; 32492#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32367#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32368#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32658#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32626#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32506#L715-39 assume 1 == ~t9_pc~0; 31678#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31680#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31755#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31756#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32831#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32832#L734-39 assume !(1 == ~t10_pc~0); 32193#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 32194#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32529#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31832#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31833#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33087#L753-39 assume !(1 == ~t11_pc~0); 31751#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 31752#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32655#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32497#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32498#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32593#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32594#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32852#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32853#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33068#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32776#L1257-3 assume !(1 == ~T5_E~0); 32777#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33041#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33090#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33193#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31905#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31906#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31815#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31816#L1297-3 assume !(1 == ~E_1~0); 32964#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32965#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33145#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33218#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32872#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32873#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31871#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31848#L1337-3 assume !(1 == ~E_9~0); 31849#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32564#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32686#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32687#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31797#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32003#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 32004#L1697 assume !(0 == start_simulation_~tmp~3#1); 32583#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32584#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31922#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31690#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 31691#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32652#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32653#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 32954#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 32955#L1678-2 [2024-11-09 16:08:39,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,397 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2024-11-09 16:08:39,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919044004] [2024-11-09 16:08:39,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919044004] [2024-11-09 16:08:39,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919044004] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,458 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,458 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [930622633] [2024-11-09 16:08:39,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,458 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:39,459 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,459 INFO L85 PathProgramCache]: Analyzing trace with hash -770175885, now seen corresponding path program 2 times [2024-11-09 16:08:39,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635830626] [2024-11-09 16:08:39,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635830626] [2024-11-09 16:08:39,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635830626] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,504 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,504 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,504 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701228156] [2024-11-09 16:08:39,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,505 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:39,505 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:39,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:39,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:39,505 INFO L87 Difference]: Start difference. First operand 1578 states and 2328 transitions. cyclomatic complexity: 751 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:39,523 INFO L93 Difference]: Finished difference Result 1578 states and 2327 transitions. [2024-11-09 16:08:39,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1578 states and 2327 transitions. [2024-11-09 16:08:39,527 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:39,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1578 states to 1578 states and 2327 transitions. [2024-11-09 16:08:39,532 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1578 [2024-11-09 16:08:39,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1578 [2024-11-09 16:08:39,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1578 states and 2327 transitions. [2024-11-09 16:08:39,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:39,535 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2024-11-09 16:08:39,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1578 states and 2327 transitions. [2024-11-09 16:08:39,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1578 to 1578. [2024-11-09 16:08:39,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1578 states, 1578 states have (on average 1.4746514575411913) internal successors, (2327), 1577 states have internal predecessors, (2327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1578 states to 1578 states and 2327 transitions. [2024-11-09 16:08:39,553 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2024-11-09 16:08:39,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:39,554 INFO L425 stractBuchiCegarLoop]: Abstraction has 1578 states and 2327 transitions. [2024-11-09 16:08:39,554 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-09 16:08:39,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1578 states and 2327 transitions. [2024-11-09 16:08:39,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1427 [2024-11-09 16:08:39,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:39,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:39,558 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,559 INFO L745 eck$LassoCheckResult]: Stem: 35063#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35064#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35844#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35845#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35037#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 35038#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36278#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36247#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36248#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35396#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35397#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35812#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36214#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35300#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35301#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35191#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 35192#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36145#L1109 assume !(0 == ~M_E~0); 36162#L1109-2 assume !(0 == ~T1_E~0); 35200#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35201#L1119-1 assume !(0 == ~T3_E~0); 36217#L1124-1 assume !(0 == ~T4_E~0); 34851#L1129-1 assume !(0 == ~T5_E~0); 34852#L1134-1 assume !(0 == ~T6_E~0); 35483#L1139-1 assume !(0 == ~T7_E~0); 36153#L1144-1 assume !(0 == ~T8_E~0); 36023#L1149-1 assume !(0 == ~T9_E~0); 34962#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34963#L1159-1 assume !(0 == ~T11_E~0); 36013#L1164-1 assume !(0 == ~E_M~0); 35358#L1169-1 assume !(0 == ~E_1~0); 35252#L1174-1 assume !(0 == ~E_2~0); 35116#L1179-1 assume !(0 == ~E_3~0); 35043#L1184-1 assume !(0 == ~E_4~0); 35044#L1189-1 assume !(0 == ~E_5~0); 35076#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 35159#L1199-1 assume !(0 == ~E_7~0); 36032#L1204-1 assume !(0 == ~E_8~0); 35973#L1209-1 assume !(0 == ~E_9~0); 35974#L1214-1 assume !(0 == ~E_10~0); 36291#L1219-1 assume !(0 == ~E_11~0); 36378#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35375#L544 assume 1 == ~m_pc~0; 35376#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36201#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35731#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35005#L1379 assume !(0 != activate_threads_~tmp~1#1); 35006#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35799#L563 assume !(1 == ~t1_pc~0); 35605#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34861#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34862#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35921#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 34857#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34858#L582 assume 1 == ~t2_pc~0; 35583#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35926#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35196#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35197#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 34890#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34891#L601 assume !(1 == ~t3_pc~0); 35600#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35599#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36053#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35958#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 35959#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35907#L620 assume 1 == ~t4_pc~0; 34871#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34872#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34905#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 35809#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35991#L639 assume 1 == ~t5_pc~0; 35881#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35164#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35165#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35829#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 35830#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35764#L658 assume !(1 == ~t6_pc~0); 35372#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35373#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35188#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35189#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35962#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35211#L677 assume 1 == ~t7_pc~0; 35212#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35109#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36119#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36240#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 36241#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36311#L696 assume !(1 == ~t8_pc~0); 35436#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35437#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36276#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36314#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 36359#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35868#L715 assume 1 == ~t9_pc~0; 35869#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35536#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35250#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35251#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 35851#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36114#L734 assume !(1 == ~t10_pc~0); 36115#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35328#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35329#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36057#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 36058#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35410#L753 assume 1 == ~t11_pc~0; 35411#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35967#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36285#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35686#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 35687#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35738#L1237 assume !(1 == ~M_E~0); 35739#L1237-2 assume !(1 == ~T1_E~0); 36342#L1242-1 assume !(1 == ~T2_E~0); 35504#L1247-1 assume !(1 == ~T3_E~0); 35505#L1252-1 assume !(1 == ~T4_E~0); 35269#L1257-1 assume !(1 == ~T5_E~0); 35270#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36134#L1267-1 assume !(1 == ~T7_E~0); 36232#L1272-1 assume !(1 == ~T8_E~0); 35594#L1277-1 assume !(1 == ~T9_E~0); 35595#L1282-1 assume !(1 == ~T10_E~0); 36000#L1287-1 assume !(1 == ~T11_E~0); 36001#L1292-1 assume !(1 == ~E_M~0); 35961#L1297-1 assume !(1 == ~E_1~0); 35401#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35402#L1307-1 assume !(1 == ~E_3~0); 36221#L1312-1 assume !(1 == ~E_4~0); 35640#L1317-1 assume !(1 == ~E_5~0); 35641#L1322-1 assume !(1 == ~E_6~0); 35345#L1327-1 assume !(1 == ~E_7~0); 35346#L1332-1 assume !(1 == ~E_8~0); 35920#L1337-1 assume !(1 == ~E_9~0); 35854#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35855#L1347-1 assume !(1 == ~E_11~0); 36220#L1352-1 assume { :end_inline_reset_delta_events } true; 36118#L1678-2 [2024-11-09 16:08:39,559 INFO L747 eck$LassoCheckResult]: Loop: 36118#L1678-2 assume !false; 35910#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35911#L1084-1 assume !false; 35707#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35708#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34981#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 36206#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34901#L925 assume !(0 != eval_~tmp~0#1); 34903#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35394#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35395#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34874#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34875#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35963#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35964#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35988#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35989#L1134-3 assume !(0 == ~T6_E~0); 36158#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36209#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35385#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35386#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35647#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35648#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35903#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35904#L1174-3 assume !(0 == ~E_2~0); 35951#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35952#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36097#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35793#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35138#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35139#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35365#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34824#L1214-3 assume !(0 == ~E_10~0); 34825#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35548#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35549#L544-39 assume 1 == ~m_pc~0; 35895#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34813#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35871#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35219#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35220#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36084#L563-39 assume 1 == ~t1_pc~0; 36090#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34958#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36369#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36370#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36373#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36192#L582-39 assume 1 == ~t2_pc~0; 35281#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35282#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35617#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35618#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35052#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34836#L601-39 assume 1 == ~t3_pc~0; 34837#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34885#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36051#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36380#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36088#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35759#L620-39 assume 1 == ~t4_pc~0; 35760#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35949#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35784#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35785#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36061#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36384#L639-39 assume !(1 == ~t5_pc~0); 36176#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 35507#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35508#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34863#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 34864#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35796#L658-39 assume 1 == ~t6_pc~0; 35779#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35780#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36236#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35972#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35946#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35947#L677-39 assume !(1 == ~t7_pc~0); 35592#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 35041#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35042#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35097#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35098#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35689#L696-39 assume 1 == ~t8_pc~0; 35655#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35530#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35531#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35821#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35789#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35669#L715-39 assume 1 == ~t9_pc~0; 34841#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34843#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34918#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34919#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35994#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35995#L734-39 assume 1 == ~t10_pc~0; 35924#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35357#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35692#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34995#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34996#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36250#L753-39 assume !(1 == ~t11_pc~0); 34914#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34915#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35818#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35660#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35661#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35756#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35757#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36015#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36016#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36231#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35939#L1257-3 assume !(1 == ~T5_E~0); 35940#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36204#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36253#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36356#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35068#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35069#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34978#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34979#L1297-3 assume !(1 == ~E_1~0); 36127#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36128#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36308#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36381#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36035#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36036#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35034#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35011#L1337-3 assume !(1 == ~E_9~0); 35012#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35727#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35849#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35850#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34960#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35166#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 35167#L1697 assume !(0 == start_simulation_~tmp~3#1); 35746#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35747#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 35085#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34853#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 34854#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35815#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35816#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 36117#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 36118#L1678-2 [2024-11-09 16:08:39,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,560 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2024-11-09 16:08:39,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933170172] [2024-11-09 16:08:39,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,623 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,623 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933170172] [2024-11-09 16:08:39,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1933170172] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036444843] [2024-11-09 16:08:39,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,624 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:39,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,624 INFO L85 PathProgramCache]: Analyzing trace with hash -231211919, now seen corresponding path program 1 times [2024-11-09 16:08:39,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161059744] [2024-11-09 16:08:39,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,662 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161059744] [2024-11-09 16:08:39,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161059744] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1634419949] [2024-11-09 16:08:39,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,663 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:39,663 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:39,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:39,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:39,664 INFO L87 Difference]: Start difference. First operand 1578 states and 2327 transitions. cyclomatic complexity: 750 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:39,760 INFO L93 Difference]: Finished difference Result 2919 states and 4289 transitions. [2024-11-09 16:08:39,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2919 states and 4289 transitions. [2024-11-09 16:08:39,769 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2744 [2024-11-09 16:08:39,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2919 states to 2919 states and 4289 transitions. [2024-11-09 16:08:39,779 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2919 [2024-11-09 16:08:39,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2919 [2024-11-09 16:08:39,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2919 states and 4289 transitions. [2024-11-09 16:08:39,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:39,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2024-11-09 16:08:39,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2919 states and 4289 transitions. [2024-11-09 16:08:39,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2919 to 2919. [2024-11-09 16:08:39,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2919 states, 2919 states have (on average 1.4693388146625557) internal successors, (4289), 2918 states have internal predecessors, (4289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:39,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2919 states to 2919 states and 4289 transitions. [2024-11-09 16:08:39,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2024-11-09 16:08:39,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:08:39,827 INFO L425 stractBuchiCegarLoop]: Abstraction has 2919 states and 4289 transitions. [2024-11-09 16:08:39,827 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-09 16:08:39,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2919 states and 4289 transitions. [2024-11-09 16:08:39,833 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2744 [2024-11-09 16:08:39,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:39,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:39,835 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,835 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:39,836 INFO L745 eck$LassoCheckResult]: Stem: 39570#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 39571#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 40373#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40374#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39544#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 39545#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40886#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40845#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40846#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39906#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39907#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40339#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40803#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39811#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39812#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39699#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39700#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40715#L1109 assume !(0 == ~M_E~0); 40734#L1109-2 assume !(0 == ~T1_E~0); 39708#L1114-1 assume !(0 == ~T2_E~0); 39709#L1119-1 assume !(0 == ~T3_E~0); 40808#L1124-1 assume !(0 == ~T4_E~0); 39358#L1129-1 assume !(0 == ~T5_E~0); 39359#L1134-1 assume !(0 == ~T6_E~0); 39993#L1139-1 assume !(0 == ~T7_E~0); 40721#L1144-1 assume !(0 == ~T8_E~0); 40567#L1149-1 assume !(0 == ~T9_E~0); 39471#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39472#L1159-1 assume !(0 == ~T11_E~0); 40555#L1164-1 assume !(0 == ~E_M~0); 39867#L1169-1 assume !(0 == ~E_1~0); 39760#L1174-1 assume !(0 == ~E_2~0); 39628#L1179-1 assume !(0 == ~E_3~0); 39550#L1184-1 assume !(0 == ~E_4~0); 39551#L1189-1 assume !(0 == ~E_5~0); 39583#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 39670#L1199-1 assume !(0 == ~E_7~0); 40576#L1204-1 assume !(0 == ~E_8~0); 40510#L1209-1 assume !(0 == ~E_9~0); 40511#L1214-1 assume !(0 == ~E_10~0); 40901#L1219-1 assume !(0 == ~E_11~0); 41046#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39887#L544 assume 1 == ~m_pc~0; 39888#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40783#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40251#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39512#L1379 assume !(0 != activate_threads_~tmp~1#1); 39513#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40328#L563 assume !(1 == ~t1_pc~0); 40119#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39368#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 40453#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 39364#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39365#L582 assume 1 == ~t2_pc~0; 40097#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40458#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39704#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39705#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 39397#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39398#L601 assume !(1 == ~t3_pc~0); 40114#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40113#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40494#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 40495#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40438#L620 assume 1 == ~t4_pc~0; 39378#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39379#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39411#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39412#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 40336#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40532#L639 assume 1 == ~t5_pc~0; 40410#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39673#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39674#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40356#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 40357#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40289#L658 assume !(1 == ~t6_pc~0); 39882#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 39883#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39696#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39697#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40498#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39721#L677 assume 1 == ~t7_pc~0; 39722#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39619#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40676#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40837#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 40838#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40931#L696 assume !(1 == ~t8_pc~0); 39947#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 39948#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40884#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40934#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 41011#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40396#L715 assume 1 == ~t9_pc~0; 40397#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40050#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39758#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39759#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 40379#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40673#L734 assume !(1 == ~t10_pc~0); 40674#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39837#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39838#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40602#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 40603#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39920#L753 assume 1 == ~t11_pc~0; 39921#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40503#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40893#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40206#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 40207#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40260#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 40261#L1237-2 assume !(1 == ~T1_E~0); 40982#L1242-1 assume !(1 == ~T2_E~0); 40017#L1247-1 assume !(1 == ~T3_E~0); 40018#L1252-1 assume !(1 == ~T4_E~0); 39777#L1257-1 assume !(1 == ~T5_E~0); 39778#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40697#L1267-1 assume !(1 == ~T7_E~0); 40828#L1272-1 assume !(1 == ~T8_E~0); 40108#L1277-1 assume !(1 == ~T9_E~0); 40109#L1282-1 assume !(1 == ~T10_E~0); 40542#L1287-1 assume !(1 == ~T11_E~0); 40543#L1292-1 assume !(1 == ~E_M~0); 40497#L1297-1 assume !(1 == ~E_1~0); 39911#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 39912#L1307-1 assume !(1 == ~E_3~0); 40812#L1312-1 assume !(1 == ~E_4~0); 40155#L1317-1 assume !(1 == ~E_5~0); 40156#L1322-1 assume !(1 == ~E_6~0); 39854#L1327-1 assume !(1 == ~E_7~0); 39855#L1332-1 assume !(1 == ~E_8~0); 40452#L1337-1 assume !(1 == ~E_9~0); 40382#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 40383#L1347-1 assume !(1 == ~E_11~0); 40936#L1352-1 assume { :end_inline_reset_delta_events } true; 41081#L1678-2 [2024-11-09 16:08:39,836 INFO L747 eck$LassoCheckResult]: Loop: 41081#L1678-2 assume !false; 40443#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40444#L1084-1 assume !false; 41079#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 40923#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 39488#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41027#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 41065#L925 assume !(0 != eval_~tmp~0#1); 40193#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41064#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39381#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39382#L1114-3 assume !(0 == ~T2_E~0); 40499#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40500#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40529#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40530#L1134-3 assume !(0 == ~T6_E~0); 40727#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40797#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39895#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39896#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 40162#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40163#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40434#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40435#L1174-3 assume !(0 == ~E_2~0); 40486#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40487#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40646#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40317#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39645#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39646#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39875#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39331#L1214-3 assume !(0 == ~E_10~0); 39332#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40062#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40063#L544-39 assume !(1 == ~m_pc~0); 39319#L544-41 is_master_triggered_~__retres1~0#1 := 0; 39320#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40399#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39727#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39728#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40630#L563-39 assume !(1 == ~t1_pc~0); 39464#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 39465#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41030#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41031#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41038#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40774#L582-39 assume 1 == ~t2_pc~0; 39789#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39790#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40131#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40132#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39559#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39343#L601-39 assume 1 == ~t3_pc~0; 39344#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39392#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40596#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41050#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40635#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40282#L620-39 assume 1 == ~t4_pc~0; 40283#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40482#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40308#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40309#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40606#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41060#L639-39 assume 1 == ~t5_pc~0; 40749#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40021#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40022#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39370#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 39371#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41025#L658-39 assume !(1 == ~t6_pc~0); 40305#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 40304#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40833#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40508#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40478#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40479#L677-39 assume 1 == ~t7_pc~0; 42021#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42019#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42017#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42015#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42013#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42011#L696-39 assume 1 == ~t8_pc~0; 42007#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42005#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42003#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42001#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41999#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41998#L715-39 assume !(1 == ~t9_pc~0); 41994#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 41992#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41990#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41989#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 41988#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41987#L734-39 assume !(1 == ~t10_pc~0); 41984#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 41982#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41981#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41980#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41979#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41978#L753-39 assume !(1 == ~t11_pc~0); 41976#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 41975#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41974#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41973#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41972#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41971#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40279#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41970#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40558#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41969#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41968#L1257-3 assume !(1 == ~T5_E~0); 41967#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41966#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41965#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41964#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41963#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41962#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41961#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41960#L1297-3 assume !(1 == ~E_1~0); 41959#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41958#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41957#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41956#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41955#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41954#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41953#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41952#L1337-3 assume !(1 == ~E_9~0); 41951#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41950#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41949#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41945#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41936#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41935#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 41934#L1697 assume !(0 == start_simulation_~tmp~3#1); 40769#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41924#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41921#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41920#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 41919#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41918#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40857#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 40858#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 41081#L1678-2 [2024-11-09 16:08:39,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,837 INFO L85 PathProgramCache]: Analyzing trace with hash -1257740808, now seen corresponding path program 1 times [2024-11-09 16:08:39,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398246459] [2024-11-09 16:08:39,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1398246459] [2024-11-09 16:08:39,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1398246459] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [55636865] [2024-11-09 16:08:39,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,897 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:39,898 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:39,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1594991374, now seen corresponding path program 1 times [2024-11-09 16:08:39,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:39,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [32659088] [2024-11-09 16:08:39,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:39,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:39,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:39,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:39,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:39,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [32659088] [2024-11-09 16:08:39,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [32659088] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:39,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:39,945 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:39,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097422432] [2024-11-09 16:08:39,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:39,946 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:39,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:39,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:39,946 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:39,946 INFO L87 Difference]: Start difference. First operand 2919 states and 4289 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:40,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:40,084 INFO L93 Difference]: Finished difference Result 5589 states and 8190 transitions. [2024-11-09 16:08:40,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5589 states and 8190 transitions. [2024-11-09 16:08:40,103 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5378 [2024-11-09 16:08:40,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5589 states to 5589 states and 8190 transitions. [2024-11-09 16:08:40,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5589 [2024-11-09 16:08:40,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5589 [2024-11-09 16:08:40,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5589 states and 8190 transitions. [2024-11-09 16:08:40,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:40,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2024-11-09 16:08:40,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5589 states and 8190 transitions. [2024-11-09 16:08:40,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5589 to 5589. [2024-11-09 16:08:40,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5589 states, 5589 states have (on average 1.465378421900161) internal successors, (8190), 5588 states have internal predecessors, (8190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:40,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5589 states to 5589 states and 8190 transitions. [2024-11-09 16:08:40,224 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2024-11-09 16:08:40,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:08:40,225 INFO L425 stractBuchiCegarLoop]: Abstraction has 5589 states and 8190 transitions. [2024-11-09 16:08:40,225 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-09 16:08:40,225 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5589 states and 8190 transitions. [2024-11-09 16:08:40,240 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5378 [2024-11-09 16:08:40,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:40,240 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:40,241 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:40,242 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:40,242 INFO L745 eck$LassoCheckResult]: Stem: 48088#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 48089#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 48873#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48874#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48062#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 48063#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49318#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49287#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49288#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48422#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48423#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48841#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49251#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48326#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48327#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48217#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48218#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49179#L1109 assume !(0 == ~M_E~0); 49196#L1109-2 assume !(0 == ~T1_E~0); 48226#L1114-1 assume !(0 == ~T2_E~0); 48227#L1119-1 assume !(0 == ~T3_E~0); 49254#L1124-1 assume !(0 == ~T4_E~0); 47876#L1129-1 assume !(0 == ~T5_E~0); 47877#L1134-1 assume !(0 == ~T6_E~0); 48510#L1139-1 assume !(0 == ~T7_E~0); 49187#L1144-1 assume !(0 == ~T8_E~0); 49052#L1149-1 assume !(0 == ~T9_E~0); 47987#L1154-1 assume !(0 == ~T10_E~0); 47988#L1159-1 assume !(0 == ~T11_E~0); 49042#L1164-1 assume !(0 == ~E_M~0); 48384#L1169-1 assume !(0 == ~E_1~0); 48278#L1174-1 assume !(0 == ~E_2~0); 48142#L1179-1 assume !(0 == ~E_3~0); 48068#L1184-1 assume !(0 == ~E_4~0); 48069#L1189-1 assume !(0 == ~E_5~0); 48102#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 48185#L1199-1 assume !(0 == ~E_7~0); 49061#L1204-1 assume !(0 == ~E_8~0); 49002#L1209-1 assume !(0 == ~E_9~0); 49003#L1214-1 assume !(0 == ~E_10~0); 49331#L1219-1 assume !(0 == ~E_11~0); 49423#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48401#L544 assume 1 == ~m_pc~0; 48402#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49237#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48759#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48030#L1379 assume !(0 != activate_threads_~tmp~1#1); 48031#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48828#L563 assume !(1 == ~t1_pc~0); 48633#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 47886#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47887#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48950#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 47882#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47883#L582 assume 1 == ~t2_pc~0; 48610#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48955#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48222#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48223#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 47915#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47916#L601 assume !(1 == ~t3_pc~0); 48628#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48627#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49082#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48987#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 48988#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48936#L620 assume 1 == ~t4_pc~0; 47896#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47897#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47929#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47930#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 48838#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49020#L639 assume 1 == ~t5_pc~0; 48910#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48190#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48191#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48858#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 48859#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48793#L658 assume !(1 == ~t6_pc~0); 48398#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 48399#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48214#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48215#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 48991#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48237#L677 assume 1 == ~t7_pc~0; 48238#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48135#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49150#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49280#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 49281#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49351#L696 assume !(1 == ~t8_pc~0); 48462#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 48463#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49354#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 49400#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48897#L715 assume 1 == ~t9_pc~0; 48898#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48563#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48276#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48277#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 48880#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49145#L734 assume !(1 == ~t10_pc~0); 49146#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48354#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48355#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49086#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 49087#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48436#L753 assume 1 == ~t11_pc~0; 48437#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48996#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49325#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48714#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 48715#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48766#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 48767#L1237-2 assume !(1 == ~T1_E~0); 49382#L1242-1 assume !(1 == ~T2_E~0); 50175#L1247-1 assume !(1 == ~T3_E~0); 50154#L1252-1 assume !(1 == ~T4_E~0); 48295#L1257-1 assume !(1 == ~T5_E~0); 48296#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49168#L1267-1 assume !(1 == ~T7_E~0); 49269#L1272-1 assume !(1 == ~T8_E~0); 48622#L1277-1 assume !(1 == ~T9_E~0); 48623#L1282-1 assume !(1 == ~T10_E~0); 49833#L1287-1 assume !(1 == ~T11_E~0); 49832#L1292-1 assume !(1 == ~E_M~0); 49831#L1297-1 assume !(1 == ~E_1~0); 49829#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 49826#L1307-1 assume !(1 == ~E_3~0); 49824#L1312-1 assume !(1 == ~E_4~0); 49823#L1317-1 assume !(1 == ~E_5~0); 49553#L1322-1 assume !(1 == ~E_6~0); 49534#L1327-1 assume !(1 == ~E_7~0); 49513#L1332-1 assume !(1 == ~E_8~0); 49495#L1337-1 assume !(1 == ~E_9~0); 49483#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 49474#L1347-1 assume !(1 == ~E_11~0); 49466#L1352-1 assume { :end_inline_reset_delta_events } true; 49460#L1678-2 [2024-11-09 16:08:40,242 INFO L747 eck$LassoCheckResult]: Loop: 49460#L1678-2 assume !false; 49456#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49455#L1084-1 assume !false; 49454#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49444#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49441#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49440#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 49438#L925 assume !(0 != eval_~tmp~0#1); 49437#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49436#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49435#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47899#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47900#L1114-3 assume !(0 == ~T2_E~0); 48992#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48993#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49017#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49018#L1134-3 assume !(0 == ~T6_E~0); 49192#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49245#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48411#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48412#L1154-3 assume !(0 == ~T10_E~0); 48675#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48676#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53327#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53326#L1174-3 assume !(0 == ~E_2~0); 53325#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53324#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53323#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53322#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53321#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53320#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53319#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53318#L1214-3 assume !(0 == ~E_10~0); 53317#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 53316#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53315#L544-39 assume !(1 == ~m_pc~0); 53313#L544-41 is_master_triggered_~__retres1~0#1 := 0; 53312#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53311#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53310#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53309#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53308#L563-39 assume 1 == ~t1_pc~0; 53306#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53305#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53304#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53303#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53302#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53301#L582-39 assume !(1 == ~t2_pc~0); 53299#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 53298#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53297#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53296#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53295#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53294#L601-39 assume 1 == ~t3_pc~0; 53292#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53291#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53290#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53289#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53288#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53287#L620-39 assume !(1 == ~t4_pc~0); 53285#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 53284#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53283#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53282#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53281#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53280#L639-39 assume 1 == ~t5_pc~0; 53278#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53277#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53276#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53275#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 53274#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53273#L658-39 assume 1 == ~t6_pc~0; 53271#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53270#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53269#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53268#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53267#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53266#L677-39 assume 1 == ~t7_pc~0; 53264#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48066#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48067#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48123#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48124#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48717#L696-39 assume 1 == ~t8_pc~0; 48683#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48557#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48558#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48850#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48818#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48697#L715-39 assume 1 == ~t9_pc~0; 47866#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47868#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47943#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47944#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49023#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49024#L734-39 assume 1 == ~t10_pc~0; 48953#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48383#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48720#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48020#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48021#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49290#L753-39 assume !(1 == ~t11_pc~0); 47939#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 47940#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48847#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48688#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48689#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48785#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48786#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49044#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49045#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53357#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53356#L1257-3 assume !(1 == ~T5_E~0); 53355#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53354#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49431#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49396#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49397#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50060#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50058#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50056#L1297-3 assume !(1 == ~E_1~0); 50054#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50051#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50049#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50047#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50045#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50043#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50041#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 50038#L1337-3 assume !(1 == ~E_9~0); 50036#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50034#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50032#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 50024#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 50014#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 50012#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 50010#L1697 assume !(0 == start_simulation_~tmp~3#1); 49224#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 49556#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 49535#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 49514#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 49496#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49484#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49475#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 49467#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 49460#L1678-2 [2024-11-09 16:08:40,243 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:40,243 INFO L85 PathProgramCache]: Analyzing trace with hash -786384458, now seen corresponding path program 1 times [2024-11-09 16:08:40,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:40,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144928859] [2024-11-09 16:08:40,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:40,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:40,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:40,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:40,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:40,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144928859] [2024-11-09 16:08:40,299 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144928859] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:40,299 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:40,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:40,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336446929] [2024-11-09 16:08:40,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:40,299 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:40,300 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:40,300 INFO L85 PathProgramCache]: Analyzing trace with hash 55939374, now seen corresponding path program 1 times [2024-11-09 16:08:40,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:40,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448523986] [2024-11-09 16:08:40,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:40,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:40,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:40,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:40,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:40,341 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448523986] [2024-11-09 16:08:40,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448523986] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:40,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:40,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:40,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634269297] [2024-11-09 16:08:40,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:40,342 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:40,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:40,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:40,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:40,343 INFO L87 Difference]: Start difference. First operand 5589 states and 8190 transitions. cyclomatic complexity: 2605 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:40,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:40,489 INFO L93 Difference]: Finished difference Result 10549 states and 15425 transitions. [2024-11-09 16:08:40,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10549 states and 15425 transitions. [2024-11-09 16:08:40,532 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10302 [2024-11-09 16:08:40,560 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10549 states to 10549 states and 15425 transitions. [2024-11-09 16:08:40,560 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10549 [2024-11-09 16:08:40,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10549 [2024-11-09 16:08:40,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10549 states and 15425 transitions. [2024-11-09 16:08:40,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:40,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10549 states and 15425 transitions. [2024-11-09 16:08:40,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10549 states and 15425 transitions. [2024-11-09 16:08:40,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10549 to 10545. [2024-11-09 16:08:40,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10545 states, 10545 states have (on average 1.4623992413466098) internal successors, (15421), 10544 states have internal predecessors, (15421), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:40,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10545 states to 10545 states and 15421 transitions. [2024-11-09 16:08:40,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10545 states and 15421 transitions. [2024-11-09 16:08:40,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:08:40,881 INFO L425 stractBuchiCegarLoop]: Abstraction has 10545 states and 15421 transitions. [2024-11-09 16:08:40,881 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-09 16:08:40,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10545 states and 15421 transitions. [2024-11-09 16:08:40,907 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10302 [2024-11-09 16:08:40,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:40,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:40,909 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:40,909 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:40,910 INFO L745 eck$LassoCheckResult]: Stem: 64236#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 64237#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 65022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64210#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 64211#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65474#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65440#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65441#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64571#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64572#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64990#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65404#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64475#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64476#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64365#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64366#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65333#L1109 assume !(0 == ~M_E~0); 65350#L1109-2 assume !(0 == ~T1_E~0); 64374#L1114-1 assume !(0 == ~T2_E~0); 64375#L1119-1 assume !(0 == ~T3_E~0); 65407#L1124-1 assume !(0 == ~T4_E~0); 64024#L1129-1 assume !(0 == ~T5_E~0); 64025#L1134-1 assume !(0 == ~T6_E~0); 64658#L1139-1 assume !(0 == ~T7_E~0); 65341#L1144-1 assume !(0 == ~T8_E~0); 65207#L1149-1 assume !(0 == ~T9_E~0); 64135#L1154-1 assume !(0 == ~T10_E~0); 64136#L1159-1 assume !(0 == ~T11_E~0); 65196#L1164-1 assume !(0 == ~E_M~0); 64533#L1169-1 assume !(0 == ~E_1~0); 64427#L1174-1 assume !(0 == ~E_2~0); 64289#L1179-1 assume !(0 == ~E_3~0); 64216#L1184-1 assume !(0 == ~E_4~0); 64217#L1189-1 assume !(0 == ~E_5~0); 64249#L1194-1 assume !(0 == ~E_6~0); 64332#L1199-1 assume !(0 == ~E_7~0); 65216#L1204-1 assume !(0 == ~E_8~0); 65156#L1209-1 assume !(0 == ~E_9~0); 65157#L1214-1 assume !(0 == ~E_10~0); 65489#L1219-1 assume !(0 == ~E_11~0); 65584#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64550#L544 assume 1 == ~m_pc~0; 64551#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65391#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64907#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64178#L1379 assume !(0 != activate_threads_~tmp~1#1); 64179#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64977#L563 assume !(1 == ~t1_pc~0); 64780#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64034#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64035#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65103#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 64030#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64031#L582 assume 1 == ~t2_pc~0; 64758#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65109#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64370#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64371#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 64063#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64064#L601 assume !(1 == ~t3_pc~0); 64775#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64774#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65237#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65141#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 65142#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65089#L620 assume 1 == ~t4_pc~0; 64044#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64045#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64077#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64078#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 64987#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65174#L639 assume 1 == ~t5_pc~0; 65063#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64337#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64338#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65007#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 65008#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64942#L658 assume !(1 == ~t6_pc~0); 64547#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64548#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64362#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64363#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 65145#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64385#L677 assume 1 == ~t7_pc~0; 64386#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64282#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65305#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65431#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 65432#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65509#L696 assume !(1 == ~t8_pc~0); 64611#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64612#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65472#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65512#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 65560#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65050#L715 assume 1 == ~t9_pc~0; 65051#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64711#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64425#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64426#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 65030#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65300#L734 assume !(1 == ~t10_pc~0); 65301#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 64503#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64504#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65241#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 65242#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64585#L753 assume 1 == ~t11_pc~0; 64586#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65150#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65483#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64862#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 64863#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64914#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 64915#L1237-2 assume !(1 == ~T1_E~0); 65543#L1242-1 assume !(1 == ~T2_E~0); 65917#L1247-1 assume !(1 == ~T3_E~0); 65866#L1252-1 assume !(1 == ~T4_E~0); 65864#L1257-1 assume !(1 == ~T5_E~0); 65862#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65828#L1267-1 assume !(1 == ~T7_E~0); 65826#L1272-1 assume !(1 == ~T8_E~0); 65792#L1277-1 assume !(1 == ~T9_E~0); 65790#L1282-1 assume !(1 == ~T10_E~0); 65788#L1287-1 assume !(1 == ~T11_E~0); 65785#L1292-1 assume !(1 == ~E_M~0); 65783#L1297-1 assume !(1 == ~E_1~0); 65781#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 65746#L1307-1 assume !(1 == ~E_3~0); 65715#L1312-1 assume !(1 == ~E_4~0); 65702#L1317-1 assume !(1 == ~E_5~0); 65682#L1322-1 assume !(1 == ~E_6~0); 65679#L1327-1 assume !(1 == ~E_7~0); 65657#L1332-1 assume !(1 == ~E_8~0); 65655#L1337-1 assume !(1 == ~E_9~0); 65643#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 65634#L1347-1 assume !(1 == ~E_11~0); 65626#L1352-1 assume { :end_inline_reset_delta_events } true; 65620#L1678-2 [2024-11-09 16:08:40,910 INFO L747 eck$LassoCheckResult]: Loop: 65620#L1678-2 assume !false; 65616#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65615#L1084-1 assume !false; 65614#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65604#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65601#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65600#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65598#L925 assume !(0 != eval_~tmp~0#1); 65597#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65596#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65594#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 65595#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69762#L1114-3 assume !(0 == ~T2_E~0); 69760#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69758#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69756#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69754#L1134-3 assume !(0 == ~T6_E~0); 69751#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 69749#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69747#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69745#L1154-3 assume !(0 == ~T10_E~0); 69743#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69741#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69738#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69736#L1174-3 assume !(0 == ~E_2~0); 69647#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69637#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69629#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69621#L1194-3 assume !(0 == ~E_6~0); 69615#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 66960#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66957#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 66955#L1214-3 assume !(0 == ~E_10~0); 66953#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66951#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66949#L544-39 assume !(1 == ~m_pc~0); 66945#L544-41 is_master_triggered_~__retres1~0#1 := 0; 66943#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66941#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 66939#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66937#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66935#L563-39 assume 1 == ~t1_pc~0; 66931#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 66928#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66926#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66925#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 66858#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66750#L582-39 assume !(1 == ~t2_pc~0); 66747#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 66744#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66742#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66740#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66738#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66736#L601-39 assume 1 == ~t3_pc~0; 66733#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66730#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66728#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66642#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66639#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66548#L620-39 assume !(1 == ~t4_pc~0); 66505#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 66503#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66501#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66499#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66497#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66494#L639-39 assume 1 == ~t5_pc~0; 66491#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66490#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66489#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66488#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 66487#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66485#L658-39 assume !(1 == ~t6_pc~0); 66483#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 66480#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 66477#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66475#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66473#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66471#L677-39 assume 1 == ~t7_pc~0; 66397#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66395#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66393#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66391#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 66389#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66387#L696-39 assume !(1 == ~t8_pc~0); 66384#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 66381#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66379#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66377#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66375#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66373#L715-39 assume !(1 == ~t9_pc~0); 66297#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 66214#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66211#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66209#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66207#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66205#L734-39 assume 1 == ~t10_pc~0; 66199#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 66197#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66195#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66193#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66191#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66189#L753-39 assume !(1 == ~t11_pc~0); 66099#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 66097#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66095#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66043#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65978#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65933#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64934#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65930#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65928#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65927#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65926#L1257-3 assume !(1 == ~T5_E~0); 65925#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65874#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65872#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65870#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65868#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65865#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65863#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65861#L1297-3 assume !(1 == ~E_1~0); 65827#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65793#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65791#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65789#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65787#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65784#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65782#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65780#L1337-3 assume !(1 == ~E_9~0); 65779#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 65778#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65777#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65742#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65733#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65732#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 65731#L1697 assume !(0 == start_simulation_~tmp~3#1); 65378#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 65705#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 65683#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 65658#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 65656#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65644#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65635#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65627#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 65620#L1678-2 [2024-11-09 16:08:40,910 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:40,911 INFO L85 PathProgramCache]: Analyzing trace with hash 602909556, now seen corresponding path program 1 times [2024-11-09 16:08:40,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:40,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817948100] [2024-11-09 16:08:40,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:40,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:40,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:40,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:40,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:40,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817948100] [2024-11-09 16:08:40,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817948100] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:40,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:40,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:08:40,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082709193] [2024-11-09 16:08:40,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:40,975 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:40,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:40,978 INFO L85 PathProgramCache]: Analyzing trace with hash 1775687791, now seen corresponding path program 1 times [2024-11-09 16:08:40,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:40,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671037799] [2024-11-09 16:08:40,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:40,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:40,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:41,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:41,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:41,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [671037799] [2024-11-09 16:08:41,048 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [671037799] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:41,048 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:41,048 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:41,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1472286567] [2024-11-09 16:08:41,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:41,049 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:41,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:41,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:41,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:41,050 INFO L87 Difference]: Start difference. First operand 10545 states and 15421 transitions. cyclomatic complexity: 4884 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:41,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:41,440 INFO L93 Difference]: Finished difference Result 20729 states and 30102 transitions. [2024-11-09 16:08:41,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20729 states and 30102 transitions. [2024-11-09 16:08:41,538 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20471 [2024-11-09 16:08:41,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20729 states to 20729 states and 30102 transitions. [2024-11-09 16:08:41,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20729 [2024-11-09 16:08:41,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20729 [2024-11-09 16:08:41,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20729 states and 30102 transitions. [2024-11-09 16:08:41,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:41,654 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20729 states and 30102 transitions. [2024-11-09 16:08:41,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20729 states and 30102 transitions. [2024-11-09 16:08:42,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20729 to 20065. [2024-11-09 16:08:42,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20065 states, 20065 states have (on average 1.4535758783952155) internal successors, (29166), 20064 states have internal predecessors, (29166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:42,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20065 states to 20065 states and 29166 transitions. [2024-11-09 16:08:42,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20065 states and 29166 transitions. [2024-11-09 16:08:42,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:42,083 INFO L425 stractBuchiCegarLoop]: Abstraction has 20065 states and 29166 transitions. [2024-11-09 16:08:42,083 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-09 16:08:42,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20065 states and 29166 transitions. [2024-11-09 16:08:42,129 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19807 [2024-11-09 16:08:42,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:42,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:42,130 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:42,130 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:42,131 INFO L745 eck$LassoCheckResult]: Stem: 95518#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 95519#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 96344#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96345#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95492#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 95493#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96885#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96839#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96840#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95861#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95862#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96303#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96791#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95761#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 95762#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 95649#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 95650#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96698#L1109 assume !(0 == ~M_E~0); 96722#L1109-2 assume !(0 == ~T1_E~0); 95658#L1114-1 assume !(0 == ~T2_E~0); 95659#L1119-1 assume !(0 == ~T3_E~0); 96794#L1124-1 assume !(0 == ~T4_E~0); 95305#L1129-1 assume !(0 == ~T5_E~0); 95306#L1134-1 assume !(0 == ~T6_E~0); 95952#L1139-1 assume !(0 == ~T7_E~0); 96708#L1144-1 assume !(0 == ~T8_E~0); 96550#L1149-1 assume !(0 == ~T9_E~0); 95416#L1154-1 assume !(0 == ~T10_E~0); 95417#L1159-1 assume !(0 == ~T11_E~0); 96537#L1164-1 assume !(0 == ~E_M~0); 95822#L1169-1 assume !(0 == ~E_1~0); 95711#L1174-1 assume !(0 == ~E_2~0); 95573#L1179-1 assume !(0 == ~E_3~0); 95498#L1184-1 assume !(0 == ~E_4~0); 95499#L1189-1 assume !(0 == ~E_5~0); 95532#L1194-1 assume !(0 == ~E_6~0); 95616#L1199-1 assume !(0 == ~E_7~0); 96559#L1204-1 assume !(0 == ~E_8~0); 96489#L1209-1 assume !(0 == ~E_9~0); 96490#L1214-1 assume !(0 == ~E_10~0); 96903#L1219-1 assume !(0 == ~E_11~0); 97062#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95839#L544 assume !(1 == ~m_pc~0); 95840#L544-2 is_master_triggered_~__retres1~0#1 := 0; 96775#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96212#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 95458#L1379 assume !(0 != activate_threads_~tmp~1#1); 95459#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96287#L563 assume !(1 == ~t1_pc~0); 96079#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95315#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95316#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96430#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 95311#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95312#L582 assume 1 == ~t2_pc~0; 96056#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 96437#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95654#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95655#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 95344#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95345#L601 assume !(1 == ~t3_pc~0); 96074#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 96073#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96582#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96474#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 96475#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96416#L620 assume 1 == ~t4_pc~0; 95325#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95326#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95358#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95359#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 96297#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96511#L639 assume 1 == ~t5_pc~0; 96386#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 95621#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96322#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 96323#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96251#L658 assume !(1 == ~t6_pc~0); 95836#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95837#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95646#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 95647#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96478#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95669#L677 assume 1 == ~t7_pc~0; 95670#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95565#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96664#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96827#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 96828#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96935#L696 assume !(1 == ~t8_pc~0); 95903#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 95904#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96883#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96939#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 97013#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96372#L715 assume 1 == ~t9_pc~0; 96373#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 96007#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95709#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 95710#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 96351#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96659#L734 assume !(1 == ~t10_pc~0); 96660#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95791#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 95792#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96587#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 96588#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95876#L753 assume 1 == ~t11_pc~0; 95877#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 96483#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96893#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96166#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 96167#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96219#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 96220#L1237-2 assume !(1 == ~T1_E~0); 96987#L1242-1 assume !(1 == ~T2_E~0); 95973#L1247-1 assume !(1 == ~T3_E~0); 95974#L1252-1 assume !(1 == ~T4_E~0); 107470#L1257-1 assume !(1 == ~T5_E~0); 107468#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107309#L1267-1 assume !(1 == ~T7_E~0); 107204#L1272-1 assume !(1 == ~T8_E~0); 107202#L1277-1 assume !(1 == ~T9_E~0); 107200#L1282-1 assume !(1 == ~T10_E~0); 107198#L1287-1 assume !(1 == ~T11_E~0); 107197#L1292-1 assume !(1 == ~E_M~0); 107106#L1297-1 assume !(1 == ~E_1~0); 107104#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 107045#L1307-1 assume !(1 == ~E_3~0); 107043#L1312-1 assume !(1 == ~E_4~0); 107041#L1317-1 assume !(1 == ~E_5~0); 107018#L1322-1 assume !(1 == ~E_6~0); 107014#L1327-1 assume !(1 == ~E_7~0); 107011#L1332-1 assume !(1 == ~E_8~0); 106990#L1337-1 assume !(1 == ~E_9~0); 106977#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 106969#L1347-1 assume !(1 == ~E_11~0); 106964#L1352-1 assume { :end_inline_reset_delta_events } true; 106910#L1678-2 [2024-11-09 16:08:42,131 INFO L747 eck$LassoCheckResult]: Loop: 106910#L1678-2 assume !false; 106890#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106889#L1084-1 assume !false; 106888#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 106873#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 106866#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 106859#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 106849#L925 assume !(0 != eval_~tmp~0#1); 106850#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 115239#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 115238#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 115237#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 115236#L1114-3 assume !(0 == ~T2_E~0); 115235#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 115234#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96508#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96509#L1134-3 assume !(0 == ~T6_E~0); 97927#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 96786#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 95848#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 95849#L1154-3 assume !(0 == ~T10_E~0); 96124#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 96125#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 114599#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 114598#L1174-3 assume !(0 == ~E_2~0); 114590#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 114587#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 114584#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 114581#L1194-3 assume !(0 == ~E_6~0); 114569#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 114566#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 114564#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 114562#L1214-3 assume !(0 == ~E_10~0); 114560#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 114558#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114556#L544-39 assume !(1 == ~m_pc~0); 114553#L544-41 is_master_triggered_~__retres1~0#1 := 0; 114551#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114549#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 114547#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 114545#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114543#L563-39 assume 1 == ~t1_pc~0; 114539#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 114537#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114535#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 114533#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 114531#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114529#L582-39 assume !(1 == ~t2_pc~0); 114525#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 114523#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114521#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 114520#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 114519#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114518#L601-39 assume 1 == ~t3_pc~0; 114515#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 114513#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114511#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 114509#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 114507#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114496#L620-39 assume 1 == ~t4_pc~0; 114491#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114483#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114476#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 114471#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 114466#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114461#L639-39 assume 1 == ~t5_pc~0; 114453#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 114448#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114441#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 114436#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 114432#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114427#L658-39 assume 1 == ~t6_pc~0; 114419#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 114412#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 114403#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 114396#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 114389#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 114383#L677-39 assume !(1 == ~t7_pc~0); 114371#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 114362#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 114356#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114330#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 114324#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 114318#L696-39 assume 1 == ~t8_pc~0; 114309#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 114305#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 114300#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 114295#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 114289#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 114284#L715-39 assume 1 == ~t9_pc~0; 111609#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 110040#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 109028#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 109026#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 109023#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 109021#L734-39 assume !(1 == ~t10_pc~0); 108485#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 108482#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 108480#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 108478#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 108475#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 108473#L753-39 assume 1 == ~t11_pc~0; 108471#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 108468#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 108466#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 108464#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 108461#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107882#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 97786#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 107664#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 107485#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 107662#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 107659#L1257-3 assume !(1 == ~T5_E~0); 107657#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107655#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 107653#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 107538#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 107535#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 107531#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 107529#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107527#L1297-3 assume !(1 == ~E_1~0); 107525#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107523#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107521#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 107518#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107516#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107512#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107510#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 107416#L1337-3 assume !(1 == ~E_9~0); 107414#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 107411#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 107409#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 107247#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 107237#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 107235#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 107233#L1697 assume !(0 == start_simulation_~tmp~3#1); 96756#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 107075#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 107070#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 107031#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 106997#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 106982#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106972#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 106965#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 106910#L1678-2 [2024-11-09 16:08:42,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:42,131 INFO L85 PathProgramCache]: Analyzing trace with hash -1258502475, now seen corresponding path program 1 times [2024-11-09 16:08:42,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:42,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247931454] [2024-11-09 16:08:42,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:42,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:42,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:42,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:42,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:42,182 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247931454] [2024-11-09 16:08:42,182 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247931454] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:42,183 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:42,183 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:08:42,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672775103] [2024-11-09 16:08:42,183 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:42,183 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:42,183 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:42,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1647317140, now seen corresponding path program 1 times [2024-11-09 16:08:42,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:42,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433811752] [2024-11-09 16:08:42,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:42,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:42,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:42,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:42,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:42,353 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433811752] [2024-11-09 16:08:42,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433811752] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:42,353 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:42,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:42,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274514196] [2024-11-09 16:08:42,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:42,353 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:42,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:42,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:42,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:42,354 INFO L87 Difference]: Start difference. First operand 20065 states and 29166 transitions. cyclomatic complexity: 9117 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:42,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:42,534 INFO L93 Difference]: Finished difference Result 38325 states and 55428 transitions. [2024-11-09 16:08:42,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38325 states and 55428 transitions. [2024-11-09 16:08:42,797 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38020 [2024-11-09 16:08:42,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38325 states to 38325 states and 55428 transitions. [2024-11-09 16:08:42,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38325 [2024-11-09 16:08:43,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38325 [2024-11-09 16:08:43,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38325 states and 55428 transitions. [2024-11-09 16:08:43,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:43,057 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38325 states and 55428 transitions. [2024-11-09 16:08:43,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38325 states and 55428 transitions. [2024-11-09 16:08:43,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38325 to 38293. [2024-11-09 16:08:43,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38293 states, 38293 states have (on average 1.446635155250307) internal successors, (55396), 38292 states have internal predecessors, (55396), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:43,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38293 states to 38293 states and 55396 transitions. [2024-11-09 16:08:43,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38293 states and 55396 transitions. [2024-11-09 16:08:43,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:43,583 INFO L425 stractBuchiCegarLoop]: Abstraction has 38293 states and 55396 transitions. [2024-11-09 16:08:43,584 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-09 16:08:43,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38293 states and 55396 transitions. [2024-11-09 16:08:43,688 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37988 [2024-11-09 16:08:43,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:43,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:43,690 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:43,690 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:43,690 INFO L745 eck$LassoCheckResult]: Stem: 153916#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 153917#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 154759#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 154760#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153890#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 153891#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 155340#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155290#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155291#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 154252#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154253#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154714#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 155245#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154158#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 154159#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 154043#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 154044#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 155133#L1109 assume !(0 == ~M_E~0); 155166#L1109-2 assume !(0 == ~T1_E~0); 154052#L1114-1 assume !(0 == ~T2_E~0); 154053#L1119-1 assume !(0 == ~T3_E~0); 155248#L1124-1 assume !(0 == ~T4_E~0); 153702#L1129-1 assume !(0 == ~T5_E~0); 153703#L1134-1 assume !(0 == ~T6_E~0); 154351#L1139-1 assume !(0 == ~T7_E~0); 155147#L1144-1 assume !(0 == ~T8_E~0); 154973#L1149-1 assume !(0 == ~T9_E~0); 153815#L1154-1 assume !(0 == ~T10_E~0); 153816#L1159-1 assume !(0 == ~T11_E~0); 154962#L1164-1 assume !(0 == ~E_M~0); 154214#L1169-1 assume !(0 == ~E_1~0); 154105#L1174-1 assume !(0 == ~E_2~0); 153973#L1179-1 assume !(0 == ~E_3~0); 153896#L1184-1 assume !(0 == ~E_4~0); 153897#L1189-1 assume !(0 == ~E_5~0); 153929#L1194-1 assume !(0 == ~E_6~0); 154014#L1199-1 assume !(0 == ~E_7~0); 154983#L1204-1 assume !(0 == ~E_8~0); 154907#L1209-1 assume !(0 == ~E_9~0); 154908#L1214-1 assume !(0 == ~E_10~0); 155360#L1219-1 assume !(0 == ~E_11~0); 155545#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154234#L544 assume !(1 == ~m_pc~0); 154235#L544-2 is_master_triggered_~__retres1~0#1 := 0; 155224#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154618#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153858#L1379 assume !(0 != activate_threads_~tmp~1#1); 153859#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154696#L563 assume !(1 == ~t1_pc~0); 154479#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153712#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 154847#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 153708#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153709#L582 assume !(1 == ~t2_pc~0); 154456#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 154853#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154048#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 154049#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 153741#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153742#L601 assume !(1 == ~t3_pc~0); 154473#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154472#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 155006#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154889#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 154890#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154832#L620 assume 1 == ~t4_pc~0; 153724#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 153725#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153755#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 153756#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 154708#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154933#L639 assume 1 == ~t5_pc~0; 154804#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 154017#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154018#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154734#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 154735#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154654#L658 assume !(1 == ~t6_pc~0); 154229#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 154230#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154040#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 154041#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 154893#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154065#L677 assume 1 == ~t7_pc~0; 154066#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 153965#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 155096#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 155277#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 155278#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 155395#L696 assume !(1 == ~t8_pc~0); 154298#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 154299#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 155338#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 155398#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 155477#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 154786#L715 assume 1 == ~t9_pc~0; 154787#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 154408#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 154103#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 154104#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 154765#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 155093#L734 assume !(1 == ~t10_pc~0); 155094#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 154184#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 154185#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 155011#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 155012#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 154266#L753 assume 1 == ~t11_pc~0; 154267#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 154898#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 155352#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 154572#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 154573#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154627#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 154628#L1237-2 assume !(1 == ~T1_E~0); 155447#L1242-1 assume !(1 == ~T2_E~0); 154373#L1247-1 assume !(1 == ~T3_E~0); 154374#L1252-1 assume !(1 == ~T4_E~0); 154122#L1257-1 assume !(1 == ~T5_E~0); 154123#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 155115#L1267-1 assume !(1 == ~T7_E~0); 155267#L1272-1 assume !(1 == ~T8_E~0); 154467#L1277-1 assume !(1 == ~T9_E~0); 154468#L1282-1 assume !(1 == ~T10_E~0); 155021#L1287-1 assume !(1 == ~T11_E~0); 165518#L1292-1 assume !(1 == ~E_M~0); 165516#L1297-1 assume !(1 == ~E_1~0); 165514#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 165511#L1307-1 assume !(1 == ~E_3~0); 165496#L1312-1 assume !(1 == ~E_4~0); 163233#L1317-1 assume !(1 == ~E_5~0); 163231#L1322-1 assume !(1 == ~E_6~0); 163228#L1327-1 assume !(1 == ~E_7~0); 163226#L1332-1 assume !(1 == ~E_8~0); 163225#L1337-1 assume !(1 == ~E_9~0); 163078#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 163075#L1347-1 assume !(1 == ~E_11~0); 163041#L1352-1 assume { :end_inline_reset_delta_events } true; 163030#L1678-2 [2024-11-09 16:08:43,691 INFO L747 eck$LassoCheckResult]: Loop: 163030#L1678-2 assume !false; 162978#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 162975#L1084-1 assume !false; 162972#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 162807#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 162803#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 162801#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 162798#L925 assume !(0 != eval_~tmp~0#1); 162799#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 169718#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 169713#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 169705#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 169700#L1114-3 assume !(0 == ~T2_E~0); 169167#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 166075#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 166074#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 166072#L1134-3 assume !(0 == ~T6_E~0); 166070#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 166069#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 166068#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 166066#L1154-3 assume !(0 == ~T10_E~0); 166064#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 166063#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 166062#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 166060#L1174-3 assume !(0 == ~E_2~0); 166058#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 166056#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 166054#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 166052#L1194-3 assume !(0 == ~E_6~0); 166050#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 166048#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 166046#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 166044#L1214-3 assume !(0 == ~E_10~0); 166042#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 166040#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 166037#L544-39 assume !(1 == ~m_pc~0); 166035#L544-41 is_master_triggered_~__retres1~0#1 := 0; 166033#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 166031#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 166029#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 166027#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 166024#L563-39 assume !(1 == ~t1_pc~0); 166022#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 166019#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 166017#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 166015#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 166013#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 166012#L582-39 assume !(1 == ~t2_pc~0); 166011#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 166010#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 166009#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 166008#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 166007#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 166006#L601-39 assume 1 == ~t3_pc~0; 166004#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 166003#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 166001#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 165999#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 165997#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 165995#L620-39 assume !(1 == ~t4_pc~0); 165992#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 165990#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 165988#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 165985#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 165983#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 165981#L639-39 assume 1 == ~t5_pc~0; 165978#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 165976#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 165974#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 165972#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 165970#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 165968#L658-39 assume !(1 == ~t6_pc~0); 165966#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 165963#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 165961#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 165958#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 165956#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 165954#L677-39 assume 1 == ~t7_pc~0; 165856#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 165853#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 165851#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 165849#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 165847#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 165844#L696-39 assume !(1 == ~t8_pc~0); 165842#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 165839#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 165837#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 165835#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 165833#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 165830#L715-39 assume !(1 == ~t9_pc~0); 165827#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 165825#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 165823#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 165821#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 165819#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 165816#L734-39 assume !(1 == ~t10_pc~0); 165814#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 165811#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 165809#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 165807#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 165805#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 165802#L753-39 assume !(1 == ~t11_pc~0); 165799#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 165797#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 165795#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 165793#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 165791#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 165788#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 164879#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 165783#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 165779#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 165777#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 165775#L1257-3 assume !(1 == ~T5_E~0); 165772#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 165770#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 165768#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 165766#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 165764#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 165760#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 165757#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 165755#L1297-3 assume !(1 == ~E_1~0); 165753#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 165751#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 165749#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 165747#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 165745#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 165741#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 165739#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 165737#L1337-3 assume !(1 == ~E_9~0); 165735#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 165733#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 165731#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 165707#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 165697#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 165686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 165677#L1697 assume !(0 == start_simulation_~tmp~3#1); 165668#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 165501#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 163234#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 163232#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 163229#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 163227#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 163079#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 163042#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 163030#L1678-2 [2024-11-09 16:08:43,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:43,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1819278198, now seen corresponding path program 1 times [2024-11-09 16:08:43,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:43,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545183850] [2024-11-09 16:08:43,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:43,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:43,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:43,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:43,874 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:43,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1545183850] [2024-11-09 16:08:43,874 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1545183850] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:43,874 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:43,874 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:08:43,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56575273] [2024-11-09 16:08:43,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:43,875 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:43,875 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:43,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1264304177, now seen corresponding path program 1 times [2024-11-09 16:08:43,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:43,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [896257073] [2024-11-09 16:08:43,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:43,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:43,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:43,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:43,910 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:43,910 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [896257073] [2024-11-09 16:08:43,910 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [896257073] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:43,910 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:43,910 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:43,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399342701] [2024-11-09 16:08:43,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:43,910 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:43,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:43,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:43,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:43,911 INFO L87 Difference]: Start difference. First operand 38293 states and 55396 transitions. cyclomatic complexity: 17135 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:44,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:44,349 INFO L93 Difference]: Finished difference Result 73252 states and 105493 transitions. [2024-11-09 16:08:44,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73252 states and 105493 transitions. [2024-11-09 16:08:44,614 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 72820 [2024-11-09 16:08:45,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73252 states to 73252 states and 105493 transitions. [2024-11-09 16:08:45,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73252 [2024-11-09 16:08:45,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73252 [2024-11-09 16:08:45,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73252 states and 105493 transitions. [2024-11-09 16:08:45,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:45,212 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73252 states and 105493 transitions. [2024-11-09 16:08:45,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73252 states and 105493 transitions. [2024-11-09 16:08:45,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73252 to 73188. [2024-11-09 16:08:46,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73188 states, 73188 states have (on average 1.440523036563371) internal successors, (105429), 73187 states have internal predecessors, (105429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:46,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73188 states to 73188 states and 105429 transitions. [2024-11-09 16:08:46,282 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73188 states and 105429 transitions. [2024-11-09 16:08:46,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:46,283 INFO L425 stractBuchiCegarLoop]: Abstraction has 73188 states and 105429 transitions. [2024-11-09 16:08:46,283 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-09 16:08:46,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73188 states and 105429 transitions. [2024-11-09 16:08:46,439 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 72756 [2024-11-09 16:08:46,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:46,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:46,441 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:46,441 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:46,442 INFO L745 eck$LassoCheckResult]: Stem: 265463#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 265464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 266255#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 266256#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 265437#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 265438#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 266757#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 266717#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 266718#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 265800#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 265801#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 266223#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 266673#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 265704#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 265705#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 265593#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 265594#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 266588#L1109 assume !(0 == ~M_E~0); 266610#L1109-2 assume !(0 == ~T1_E~0); 265602#L1114-1 assume !(0 == ~T2_E~0); 265603#L1119-1 assume !(0 == ~T3_E~0); 266676#L1124-1 assume !(0 == ~T4_E~0); 265254#L1129-1 assume !(0 == ~T5_E~0); 265255#L1134-1 assume !(0 == ~T6_E~0); 265886#L1139-1 assume !(0 == ~T7_E~0); 266597#L1144-1 assume !(0 == ~T8_E~0); 266452#L1149-1 assume !(0 == ~T9_E~0); 265362#L1154-1 assume !(0 == ~T10_E~0); 265363#L1159-1 assume !(0 == ~T11_E~0); 266441#L1164-1 assume !(0 == ~E_M~0); 265763#L1169-1 assume !(0 == ~E_1~0); 265656#L1174-1 assume !(0 == ~E_2~0); 265516#L1179-1 assume !(0 == ~E_3~0); 265443#L1184-1 assume !(0 == ~E_4~0); 265444#L1189-1 assume !(0 == ~E_5~0); 265476#L1194-1 assume !(0 == ~E_6~0); 265560#L1199-1 assume !(0 == ~E_7~0); 266461#L1204-1 assume !(0 == ~E_8~0); 266399#L1209-1 assume !(0 == ~E_9~0); 266400#L1214-1 assume !(0 == ~E_10~0); 266774#L1219-1 assume !(0 == ~E_11~0); 266897#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 265780#L544 assume !(1 == ~m_pc~0); 265781#L544-2 is_master_triggered_~__retres1~0#1 := 0; 266659#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 266137#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 265404#L1379 assume !(0 != activate_threads_~tmp~1#1); 265405#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 266208#L563 assume !(1 == ~t1_pc~0); 266007#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 265264#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 265265#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 266341#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 265260#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 265261#L582 assume !(1 == ~t2_pc~0); 265986#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 266346#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 265598#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 265599#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 265290#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 265291#L601 assume !(1 == ~t3_pc~0); 266002#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 266001#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 266483#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 266381#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 266382#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 266324#L620 assume !(1 == ~t4_pc~0); 266325#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 265910#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265304#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 265305#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 266220#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 266420#L639 assume 1 == ~t5_pc~0; 266296#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 265567#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 265568#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 266240#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 266241#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 266173#L658 assume !(1 == ~t6_pc~0); 265777#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 265778#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 265590#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 265591#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 266387#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 265613#L677 assume 1 == ~t7_pc~0; 265614#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 265509#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 266561#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 266706#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 266707#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 266800#L696 assume !(1 == ~t8_pc~0); 265838#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 265839#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 266755#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 266803#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 266858#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 266282#L715 assume 1 == ~t9_pc~0; 266283#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 265939#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 265654#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 265655#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 266262#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 266558#L734 assume !(1 == ~t10_pc~0); 266559#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 265733#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 265734#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 266488#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 266489#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 265813#L753 assume 1 == ~t11_pc~0; 265814#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 266392#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 266767#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 266092#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 266093#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 266144#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 266145#L1237-2 assume !(1 == ~T1_E~0); 266879#L1242-1 assume !(1 == ~T2_E~0); 265907#L1247-1 assume !(1 == ~T3_E~0); 265908#L1252-1 assume !(1 == ~T4_E~0); 265673#L1257-1 assume !(1 == ~T5_E~0); 265674#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 266576#L1267-1 assume !(1 == ~T7_E~0); 266694#L1272-1 assume !(1 == ~T8_E~0); 268435#L1277-1 assume !(1 == ~T9_E~0); 268426#L1282-1 assume !(1 == ~T10_E~0); 267889#L1287-1 assume !(1 == ~T11_E~0); 267887#L1292-1 assume !(1 == ~E_M~0); 267885#L1297-1 assume !(1 == ~E_1~0); 267882#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 267880#L1307-1 assume !(1 == ~E_3~0); 267642#L1312-1 assume !(1 == ~E_4~0); 267640#L1317-1 assume !(1 == ~E_5~0); 267581#L1322-1 assume !(1 == ~E_6~0); 267577#L1327-1 assume !(1 == ~E_7~0); 267558#L1332-1 assume !(1 == ~E_8~0); 267556#L1337-1 assume !(1 == ~E_9~0); 267544#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 267535#L1347-1 assume !(1 == ~E_11~0); 267527#L1352-1 assume { :end_inline_reset_delta_events } true; 267521#L1678-2 [2024-11-09 16:08:46,442 INFO L747 eck$LassoCheckResult]: Loop: 267521#L1678-2 assume !false; 267517#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 267516#L1084-1 assume !false; 267515#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 267505#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 267502#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 267501#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 267499#L925 assume !(0 != eval_~tmp~0#1); 267498#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 267497#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 267494#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 267495#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 270031#L1114-3 assume !(0 == ~T2_E~0); 270029#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 270027#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 270025#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 269963#L1134-3 assume !(0 == ~T6_E~0); 269961#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 269959#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 269957#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 269955#L1154-3 assume !(0 == ~T10_E~0); 269953#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 269951#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 269949#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 269947#L1174-3 assume !(0 == ~E_2~0); 269945#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 269943#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 269941#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 269939#L1194-3 assume !(0 == ~E_6~0); 269937#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 269935#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 269933#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 269931#L1214-3 assume !(0 == ~E_10~0); 269929#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 269926#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269924#L544-39 assume !(1 == ~m_pc~0); 269922#L544-41 is_master_triggered_~__retres1~0#1 := 0; 269920#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 269918#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 269916#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 269914#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 269912#L563-39 assume 1 == ~t1_pc~0; 269908#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 269906#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269904#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 269843#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 269837#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 269831#L582-39 assume !(1 == ~t2_pc~0); 269823#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 269817#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269812#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 269733#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 269731#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 269729#L601-39 assume 1 == ~t3_pc~0; 269726#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 269724#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269722#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 269720#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 269718#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269716#L620-39 assume !(1 == ~t4_pc~0); 269714#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 269711#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 269710#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 269709#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 269708#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 269707#L639-39 assume 1 == ~t5_pc~0; 269705#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 269704#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 267238#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 267236#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 267237#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 269612#L658-39 assume 1 == ~t6_pc~0; 269609#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 269607#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 269565#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 269558#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 269553#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 269544#L677-39 assume !(1 == ~t7_pc~0); 269540#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 269537#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 269535#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 269533#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 269522#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 269442#L696-39 assume 1 == ~t8_pc~0; 269433#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 269426#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 269417#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 269409#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 269402#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 269393#L715-39 assume !(1 == ~t9_pc~0); 269384#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 269377#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 269368#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 269361#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 269354#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 269345#L734-39 assume 1 == ~t10_pc~0; 269337#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 269325#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 269316#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 269228#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 269226#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 269224#L753-39 assume !(1 == ~t11_pc~0); 269221#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 269219#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 269217#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 269214#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 269212#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 269210#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 267139#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 269207#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 267131#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 269204#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 269203#L1257-3 assume !(1 == ~T5_E~0); 269042#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 269039#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 268958#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 268956#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 268955#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 268897#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 268888#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 268881#L1297-3 assume !(1 == ~E_1~0); 268873#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 268866#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 268858#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 268851#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 268842#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 268834#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 268827#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 268819#L1337-3 assume !(1 == ~E_9~0); 268813#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 268808#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 268804#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 268718#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 268705#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 268699#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 267947#L1697 assume !(0 == start_simulation_~tmp~3#1); 267944#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 267683#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 267609#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 267559#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 267557#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267545#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 267536#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 267528#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 267521#L1678-2 [2024-11-09 16:08:46,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:46,443 INFO L85 PathProgramCache]: Analyzing trace with hash -343701065, now seen corresponding path program 1 times [2024-11-09 16:08:46,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:46,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772216294] [2024-11-09 16:08:46,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:46,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:46,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:46,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:46,492 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:46,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772216294] [2024-11-09 16:08:46,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772216294] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:46,492 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:46,492 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:08:46,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380021454] [2024-11-09 16:08:46,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:46,493 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:46,493 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:46,493 INFO L85 PathProgramCache]: Analyzing trace with hash 752661870, now seen corresponding path program 1 times [2024-11-09 16:08:46,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:46,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201889353] [2024-11-09 16:08:46,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:46,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:46,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:46,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:46,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:46,758 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201889353] [2024-11-09 16:08:46,758 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201889353] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:46,758 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:46,758 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:46,759 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264886055] [2024-11-09 16:08:46,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:46,759 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:46,759 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:46,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:46,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:46,760 INFO L87 Difference]: Start difference. First operand 73188 states and 105429 transitions. cyclomatic complexity: 32305 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:47,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:47,536 INFO L93 Difference]: Finished difference Result 142687 states and 204526 transitions. [2024-11-09 16:08:47,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142687 states and 204526 transitions. [2024-11-09 16:08:48,092 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 141936 [2024-11-09 16:08:48,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142687 states to 142687 states and 204526 transitions. [2024-11-09 16:08:48,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142687 [2024-11-09 16:08:48,501 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142687 [2024-11-09 16:08:48,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 142687 states and 204526 transitions. [2024-11-09 16:08:48,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:48,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 142687 states and 204526 transitions. [2024-11-09 16:08:48,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142687 states and 204526 transitions. [2024-11-09 16:08:50,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142687 to 142559. [2024-11-09 16:08:50,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 142559 states, 142559 states have (on average 1.433778295302296) internal successors, (204398), 142558 states have internal predecessors, (204398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:50,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142559 states to 142559 states and 204398 transitions. [2024-11-09 16:08:50,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 142559 states and 204398 transitions. [2024-11-09 16:08:50,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:50,687 INFO L425 stractBuchiCegarLoop]: Abstraction has 142559 states and 204398 transitions. [2024-11-09 16:08:50,687 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-09 16:08:50,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 142559 states and 204398 transitions. [2024-11-09 16:08:51,443 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 141808 [2024-11-09 16:08:51,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:51,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:51,448 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:51,448 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:51,449 INFO L745 eck$LassoCheckResult]: Stem: 481345#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 481346#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 482153#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 482154#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 481319#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 481320#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 482661#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 482625#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 482626#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 481680#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 481681#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 482117#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 482581#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 481585#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 481586#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 481472#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 481473#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 482491#L1109 assume !(0 == ~M_E~0); 482519#L1109-2 assume !(0 == ~T1_E~0); 481481#L1114-1 assume !(0 == ~T2_E~0); 481482#L1119-1 assume !(0 == ~T3_E~0); 482585#L1124-1 assume !(0 == ~T4_E~0); 481136#L1129-1 assume !(0 == ~T5_E~0); 481137#L1134-1 assume !(0 == ~T6_E~0); 481768#L1139-1 assume !(0 == ~T7_E~0); 482503#L1144-1 assume !(0 == ~T8_E~0); 482346#L1149-1 assume !(0 == ~T9_E~0); 481244#L1154-1 assume !(0 == ~T10_E~0); 481245#L1159-1 assume !(0 == ~T11_E~0); 482334#L1164-1 assume !(0 == ~E_M~0); 481643#L1169-1 assume !(0 == ~E_1~0); 481534#L1174-1 assume !(0 == ~E_2~0); 481399#L1179-1 assume !(0 == ~E_3~0); 481325#L1184-1 assume !(0 == ~E_4~0); 481326#L1189-1 assume !(0 == ~E_5~0); 481358#L1194-1 assume !(0 == ~E_6~0); 481440#L1199-1 assume !(0 == ~E_7~0); 482355#L1204-1 assume !(0 == ~E_8~0); 482290#L1209-1 assume !(0 == ~E_9~0); 482291#L1214-1 assume !(0 == ~E_10~0); 482677#L1219-1 assume !(0 == ~E_11~0); 482811#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 481660#L544 assume !(1 == ~m_pc~0); 481661#L544-2 is_master_triggered_~__retres1~0#1 := 0; 482568#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 482024#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 481287#L1379 assume !(0 != activate_threads_~tmp~1#1); 481288#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 482101#L563 assume !(1 == ~t1_pc~0); 481895#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 481146#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 481147#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 482238#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 481142#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 481143#L582 assume !(1 == ~t2_pc~0); 481871#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 482244#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 481477#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 481478#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 481172#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 481173#L601 assume !(1 == ~t3_pc~0); 481890#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 481889#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 482378#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 482275#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 482276#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 482223#L620 assume !(1 == ~t4_pc~0); 482224#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 481794#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481186#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 481187#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 482111#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 482309#L639 assume !(1 == ~t5_pc~0); 482310#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 481445#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 481446#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 482134#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 482135#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 482060#L658 assume !(1 == ~t6_pc~0); 481657#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 481658#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 481469#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 481470#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 482279#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 481492#L677 assume 1 == ~t7_pc~0; 481493#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 481391#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 482461#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 482613#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 482614#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 482706#L696 assume !(1 == ~t8_pc~0); 481719#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 481720#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 482659#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 482709#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 482777#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 482182#L715 assume 1 == ~t9_pc~0; 482183#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 481824#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 481532#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 481533#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 482161#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 482456#L734 assume !(1 == ~t10_pc~0); 482457#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 481613#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 481614#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 482383#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 482384#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 481694#L753 assume 1 == ~t11_pc~0; 481695#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 482284#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 482670#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 481979#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 481980#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 482031#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 482032#L1237-2 assume !(1 == ~T1_E~0); 482751#L1242-1 assume !(1 == ~T2_E~0); 482797#L1247-1 assume !(1 == ~T3_E~0); 512620#L1252-1 assume !(1 == ~T4_E~0); 512618#L1257-1 assume !(1 == ~T5_E~0); 482478#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 482479#L1267-1 assume !(1 == ~T7_E~0); 482605#L1272-1 assume !(1 == ~T8_E~0); 481884#L1277-1 assume !(1 == ~T9_E~0); 481885#L1282-1 assume !(1 == ~T10_E~0); 482390#L1287-1 assume !(1 == ~T11_E~0); 539728#L1292-1 assume !(1 == ~E_M~0); 539727#L1297-1 assume !(1 == ~E_1~0); 539726#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 539725#L1307-1 assume !(1 == ~E_3~0); 539724#L1312-1 assume !(1 == ~E_4~0); 539723#L1317-1 assume !(1 == ~E_5~0); 539722#L1322-1 assume !(1 == ~E_6~0); 482174#L1327-1 assume !(1 == ~E_7~0); 539708#L1332-1 assume !(1 == ~E_8~0); 539706#L1337-1 assume !(1 == ~E_9~0); 539704#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 539702#L1347-1 assume !(1 == ~E_11~0); 539699#L1352-1 assume { :end_inline_reset_delta_events } true; 539698#L1678-2 [2024-11-09 16:08:51,449 INFO L747 eck$LassoCheckResult]: Loop: 539698#L1678-2 assume !false; 539008#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 539006#L1084-1 assume !false; 539004#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 537436#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 537432#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 537429#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 537426#L925 assume !(0 != eval_~tmp~0#1); 537427#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 539996#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 539994#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 539992#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 539990#L1114-3 assume !(0 == ~T2_E~0); 539988#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 539986#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 539983#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 539981#L1134-3 assume !(0 == ~T6_E~0); 539979#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 539977#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 539975#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 539973#L1154-3 assume !(0 == ~T10_E~0); 539970#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 539968#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 539966#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 539964#L1174-3 assume !(0 == ~E_2~0); 539962#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 539960#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 539957#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 539955#L1194-3 assume !(0 == ~E_6~0); 539953#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 539951#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 539949#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 539947#L1214-3 assume !(0 == ~E_10~0); 539944#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 539942#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 539940#L544-39 assume !(1 == ~m_pc~0); 539938#L544-41 is_master_triggered_~__retres1~0#1 := 0; 539936#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 539934#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 539931#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 539929#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 539927#L563-39 assume 1 == ~t1_pc~0; 539924#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 539922#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 539920#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 539917#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 539915#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 539913#L582-39 assume !(1 == ~t2_pc~0); 539911#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 539909#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 539907#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 539905#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 539903#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 539901#L601-39 assume 1 == ~t3_pc~0; 539898#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 539896#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 539894#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 539892#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 539890#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 539888#L620-39 assume !(1 == ~t4_pc~0); 539886#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 539884#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 539882#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 539880#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 539878#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 539876#L639-39 assume !(1 == ~t5_pc~0); 539874#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 539872#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 539870#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 539868#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 539866#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 539864#L658-39 assume 1 == ~t6_pc~0; 539861#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 539859#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 539858#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 539857#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 539856#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 539855#L677-39 assume 1 == ~t7_pc~0; 539853#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 539852#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 539851#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 539850#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 539849#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 539848#L696-39 assume 1 == ~t8_pc~0; 539846#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 539845#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 539844#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 539843#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 539842#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 539841#L715-39 assume !(1 == ~t9_pc~0); 539839#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 539838#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 539836#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 539834#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 539832#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 539830#L734-39 assume 1 == ~t10_pc~0; 539827#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 539825#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 539823#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 539820#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 539818#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 539816#L753-39 assume !(1 == ~t11_pc~0); 539813#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 539811#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 539809#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 539806#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 539804#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 539802#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 483272#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 539799#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 534088#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 539795#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 539793#L1257-3 assume !(1 == ~T5_E~0); 539791#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 539789#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 539787#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 539785#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 539783#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 515798#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 539780#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 539778#L1297-3 assume !(1 == ~E_1~0); 539776#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 539774#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 539772#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 539770#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 539768#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 483227#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 539765#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 539763#L1337-3 assume !(1 == ~E_9~0); 539760#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 539758#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 539756#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 539745#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 539735#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 539733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 539731#L1697 assume !(0 == start_simulation_~tmp~3#1); 539729#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 539712#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 539709#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 539707#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 539705#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 539703#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 539701#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 539700#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 539698#L1678-2 [2024-11-09 16:08:51,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:51,453 INFO L85 PathProgramCache]: Analyzing trace with hash 1793793208, now seen corresponding path program 1 times [2024-11-09 16:08:51,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:51,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084980880] [2024-11-09 16:08:51,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:51,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:51,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:51,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:51,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:51,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084980880] [2024-11-09 16:08:51,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2084980880] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:51,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:51,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:08:51,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2000707813] [2024-11-09 16:08:51,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:51,553 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:51,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:51,554 INFO L85 PathProgramCache]: Analyzing trace with hash 1973107694, now seen corresponding path program 1 times [2024-11-09 16:08:51,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:51,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192169054] [2024-11-09 16:08:51,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:51,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:51,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:51,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:51,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:51,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192169054] [2024-11-09 16:08:51,593 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192169054] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:51,593 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:51,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:51,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1472245518] [2024-11-09 16:08:51,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:51,594 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:51,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:51,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:08:51,595 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:08:51,595 INFO L87 Difference]: Start difference. First operand 142559 states and 204398 transitions. cyclomatic complexity: 61967 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:52,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:52,181 INFO L93 Difference]: Finished difference Result 146738 states and 208577 transitions. [2024-11-09 16:08:52,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 146738 states and 208577 transitions. [2024-11-09 16:08:53,203 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 145984 [2024-11-09 16:08:53,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 146738 states to 146738 states and 208577 transitions. [2024-11-09 16:08:53,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146738 [2024-11-09 16:08:53,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146738 [2024-11-09 16:08:53,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146738 states and 208577 transitions. [2024-11-09 16:08:53,714 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:53,714 INFO L218 hiAutomatonCegarLoop]: Abstraction has 146738 states and 208577 transitions. [2024-11-09 16:08:53,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146738 states and 208577 transitions. [2024-11-09 16:08:55,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146738 to 146738. [2024-11-09 16:08:55,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146738 states, 146738 states have (on average 1.42142457986343) internal successors, (208577), 146737 states have internal predecessors, (208577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146738 states to 146738 states and 208577 transitions. [2024-11-09 16:08:55,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146738 states and 208577 transitions. [2024-11-09 16:08:55,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:08:55,904 INFO L425 stractBuchiCegarLoop]: Abstraction has 146738 states and 208577 transitions. [2024-11-09 16:08:55,904 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-09 16:08:55,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146738 states and 208577 transitions. [2024-11-09 16:08:56,184 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 145984 [2024-11-09 16:08:56,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:56,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:56,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,194 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,195 INFO L745 eck$LassoCheckResult]: Stem: 770650#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 770651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 771445#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 771446#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 770623#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 770624#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 771948#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 771910#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 771911#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 770982#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 770983#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 771411#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 771864#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 770887#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 770888#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 770777#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 770778#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 771776#L1109 assume !(0 == ~M_E~0); 771800#L1109-2 assume !(0 == ~T1_E~0); 770786#L1114-1 assume !(0 == ~T2_E~0); 770787#L1119-1 assume !(0 == ~T3_E~0); 771867#L1124-1 assume !(0 == ~T4_E~0); 770441#L1129-1 assume !(0 == ~T5_E~0); 770442#L1134-1 assume !(0 == ~T6_E~0); 771067#L1139-1 assume !(0 == ~T7_E~0); 771789#L1144-1 assume !(0 == ~T8_E~0); 771638#L1149-1 assume !(0 == ~T9_E~0); 770549#L1154-1 assume !(0 == ~T10_E~0); 770550#L1159-1 assume !(0 == ~T11_E~0); 771628#L1164-1 assume !(0 == ~E_M~0); 770945#L1169-1 assume !(0 == ~E_1~0); 770839#L1174-1 assume !(0 == ~E_2~0); 770703#L1179-1 assume !(0 == ~E_3~0); 770629#L1184-1 assume !(0 == ~E_4~0); 770630#L1189-1 assume !(0 == ~E_5~0); 770663#L1194-1 assume !(0 == ~E_6~0); 770745#L1199-1 assume !(0 == ~E_7~0); 771647#L1204-1 assume !(0 == ~E_8~0); 771585#L1209-1 assume !(0 == ~E_9~0); 771586#L1214-1 assume !(0 == ~E_10~0); 771965#L1219-1 assume !(0 == ~E_11~0); 772086#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 770962#L544 assume !(1 == ~m_pc~0); 770963#L544-2 is_master_triggered_~__retres1~0#1 := 0; 771849#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 771320#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 770591#L1379 assume !(0 != activate_threads_~tmp~1#1); 770592#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 771399#L563 assume !(1 == ~t1_pc~0); 771193#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 770451#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 770452#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 771530#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 770447#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 770448#L582 assume !(1 == ~t2_pc~0); 771171#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 771535#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 770782#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 770783#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 770477#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770478#L601 assume !(1 == ~t3_pc~0); 771187#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 771186#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 771668#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 771566#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 771567#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 771514#L620 assume !(1 == ~t4_pc~0); 771515#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 771092#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 770491#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 770492#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 771408#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 771603#L639 assume !(1 == ~t5_pc~0); 771604#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 770750#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 770751#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 771429#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 771430#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 771356#L658 assume !(1 == ~t6_pc~0); 770959#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 770960#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 772118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 772089#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 771570#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 770797#L677 assume 1 == ~t7_pc~0; 770798#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 770696#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 771749#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 771895#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 771896#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 771989#L696 assume !(1 == ~t8_pc~0); 771020#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 771021#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 771946#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 771992#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 772048#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 771472#L715 assume 1 == ~t9_pc~0; 771473#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 771123#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 770837#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 770838#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 771452#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 771744#L734 assume !(1 == ~t10_pc~0); 771745#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 770916#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 770917#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 771672#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 771673#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 770995#L753 assume 1 == ~t11_pc~0; 770996#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 771578#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 771956#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 771274#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 771275#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 771328#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 771329#L1237-2 assume !(1 == ~T1_E~0); 772029#L1242-1 assume !(1 == ~T2_E~0); 771089#L1247-1 assume !(1 == ~T3_E~0); 771090#L1252-1 assume !(1 == ~T4_E~0); 770856#L1257-1 assume !(1 == ~T5_E~0); 770857#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 771765#L1267-1 assume !(1 == ~T7_E~0); 771885#L1272-1 assume !(1 == ~T8_E~0); 771181#L1277-1 assume !(1 == ~T9_E~0); 771182#L1282-1 assume !(1 == ~T10_E~0); 775246#L1287-1 assume !(1 == ~T11_E~0); 775245#L1292-1 assume !(1 == ~E_M~0); 775242#L1297-1 assume !(1 == ~E_1~0); 775240#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 775238#L1307-1 assume !(1 == ~E_3~0); 775236#L1312-1 assume !(1 == ~E_4~0); 775234#L1317-1 assume !(1 == ~E_5~0); 775232#L1322-1 assume !(1 == ~E_6~0); 775228#L1327-1 assume !(1 == ~E_7~0); 775226#L1332-1 assume !(1 == ~E_8~0); 774817#L1337-1 assume !(1 == ~E_9~0); 774815#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 774813#L1347-1 assume !(1 == ~E_11~0); 774541#L1352-1 assume { :end_inline_reset_delta_events } true; 774538#L1678-2 [2024-11-09 16:08:56,195 INFO L747 eck$LassoCheckResult]: Loop: 774538#L1678-2 assume !false; 774439#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 774436#L1084-1 assume !false; 774434#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 774408#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 774400#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 774393#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 774384#L925 assume !(0 != eval_~tmp~0#1); 774385#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 784336#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 784333#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 784331#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 784329#L1114-3 assume !(0 == ~T2_E~0); 784327#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 784325#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 784323#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 784321#L1134-3 assume !(0 == ~T6_E~0); 784319#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 784317#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 784315#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 784313#L1154-3 assume !(0 == ~T10_E~0); 784311#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 784308#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 784306#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 784304#L1174-3 assume !(0 == ~E_2~0); 784302#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 784300#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 784298#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 784296#L1194-3 assume !(0 == ~E_6~0); 784294#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 784292#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 784290#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 784289#L1214-3 assume !(0 == ~E_10~0); 784288#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 784287#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 784285#L544-39 assume !(1 == ~m_pc~0); 784283#L544-41 is_master_triggered_~__retres1~0#1 := 0; 784281#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 784280#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 782780#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 782767#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 782765#L563-39 assume !(1 == ~t1_pc~0); 782763#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 782759#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 782757#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 782755#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 782753#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 782751#L582-39 assume !(1 == ~t2_pc~0); 782749#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 782747#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 782745#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 782743#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 782741#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 782739#L601-39 assume !(1 == ~t3_pc~0); 782737#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 782734#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 782732#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 782730#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 782728#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 782726#L620-39 assume !(1 == ~t4_pc~0); 782725#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 782721#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 782719#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 782717#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 782715#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 782712#L639-39 assume !(1 == ~t5_pc~0); 782710#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 782708#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 782705#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 782703#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 782701#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 782699#L658-39 assume !(1 == ~t6_pc~0); 782697#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 783251#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 783248#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 782676#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 782673#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 782671#L677-39 assume 1 == ~t7_pc~0; 782667#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 782665#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 782663#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 782660#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 782658#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 782656#L696-39 assume !(1 == ~t8_pc~0); 782654#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 782651#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 782649#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 782648#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 782645#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 782643#L715-39 assume 1 == ~t9_pc~0; 782641#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 782638#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 782636#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 782634#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 782593#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 782582#L734-39 assume 1 == ~t10_pc~0; 782571#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 782563#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 782559#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 782551#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 776082#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 776069#L753-39 assume 1 == ~t11_pc~0; 776067#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 776064#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 776061#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 776059#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 776057#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 776055#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 776051#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 776049#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 776045#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 776043#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 776041#L1257-3 assume !(1 == ~T5_E~0); 776039#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 776037#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 776035#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 776033#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 776031#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 776027#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 776025#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 776023#L1297-3 assume !(1 == ~E_1~0); 776021#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 776019#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 776017#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 776015#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 775865#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 775856#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 775848#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 775839#L1337-3 assume !(1 == ~E_9~0); 775831#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 775823#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 775814#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 775611#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 775601#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 775599#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 775249#L1697 assume !(0 == start_simulation_~tmp~3#1); 775247#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 774826#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 774822#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 774820#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 774818#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 774816#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 774814#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 774542#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 774538#L1678-2 [2024-11-09 16:08:56,196 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,196 INFO L85 PathProgramCache]: Analyzing trace with hash -1240256838, now seen corresponding path program 1 times [2024-11-09 16:08:56,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553220087] [2024-11-09 16:08:56,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553220087] [2024-11-09 16:08:56,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553220087] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:56,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917277949] [2024-11-09 16:08:56,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,269 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:56,269 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,269 INFO L85 PathProgramCache]: Analyzing trace with hash 710165746, now seen corresponding path program 1 times [2024-11-09 16:08:56,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142072576] [2024-11-09 16:08:56,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142072576] [2024-11-09 16:08:56,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142072576] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:56,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451925581] [2024-11-09 16:08:56,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,297 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:56,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:56,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:56,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:56,298 INFO L87 Difference]: Start difference. First operand 146738 states and 208577 transitions. cyclomatic complexity: 61967 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:57,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:57,978 INFO L93 Difference]: Finished difference Result 406752 states and 573867 transitions. [2024-11-09 16:08:57,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 406752 states and 573867 transitions. [2024-11-09 16:09:00,116 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 403952 [2024-11-09 16:09:01,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 406752 states to 406752 states and 573867 transitions. [2024-11-09 16:09:01,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 406752 [2024-11-09 16:09:01,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 406752 [2024-11-09 16:09:01,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 406752 states and 573867 transitions. [2024-11-09 16:09:02,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:02,038 INFO L218 hiAutomatonCegarLoop]: Abstraction has 406752 states and 573867 transitions. [2024-11-09 16:09:02,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 406752 states and 573867 transitions. [2024-11-09 16:09:05,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 406752 to 401376. [2024-11-09 16:09:06,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 401376 states, 401376 states have (on average 1.4118905963485608) internal successors, (566699), 401375 states have internal predecessors, (566699), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:07,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 401376 states to 401376 states and 566699 transitions. [2024-11-09 16:09:07,295 INFO L240 hiAutomatonCegarLoop]: Abstraction has 401376 states and 566699 transitions. [2024-11-09 16:09:07,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:07,296 INFO L425 stractBuchiCegarLoop]: Abstraction has 401376 states and 566699 transitions. [2024-11-09 16:09:07,296 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-09 16:09:07,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 401376 states and 566699 transitions. [2024-11-09 16:09:09,097 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 399344 [2024-11-09 16:09:09,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:09,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:09,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:09,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:09,099 INFO L745 eck$LassoCheckResult]: Stem: 1324154#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1324155#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1324990#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret31#1, start_simulation_#t~ret32#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1324991#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1324127#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 1324128#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1325564#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1325513#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1325514#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1324497#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1324498#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1324945#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1325456#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1324398#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1324399#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1324285#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1324286#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1325352#L1109 assume !(0 == ~M_E~0); 1325376#L1109-2 assume !(0 == ~T1_E~0); 1324294#L1114-1 assume !(0 == ~T2_E~0); 1324295#L1119-1 assume !(0 == ~T3_E~0); 1325461#L1124-1 assume !(0 == ~T4_E~0); 1323941#L1129-1 assume !(0 == ~T5_E~0); 1323942#L1134-1 assume !(0 == ~T6_E~0); 1324590#L1139-1 assume !(0 == ~T7_E~0); 1325364#L1144-1 assume !(0 == ~T8_E~0); 1325192#L1149-1 assume !(0 == ~T9_E~0); 1324053#L1154-1 assume !(0 == ~T10_E~0); 1324054#L1159-1 assume !(0 == ~T11_E~0); 1325181#L1164-1 assume !(0 == ~E_M~0); 1324457#L1169-1 assume !(0 == ~E_1~0); 1324346#L1174-1 assume !(0 == ~E_2~0); 1324213#L1179-1 assume !(0 == ~E_3~0); 1324133#L1184-1 assume !(0 == ~E_4~0); 1324134#L1189-1 assume !(0 == ~E_5~0); 1324167#L1194-1 assume !(0 == ~E_6~0); 1324256#L1199-1 assume !(0 == ~E_7~0); 1325204#L1204-1 assume !(0 == ~E_8~0); 1325134#L1209-1 assume !(0 == ~E_9~0); 1325135#L1214-1 assume !(0 == ~E_10~0); 1325582#L1219-1 assume !(0 == ~E_11~0); 1325759#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1324476#L544 assume !(1 == ~m_pc~0); 1324477#L544-2 is_master_triggered_~__retres1~0#1 := 0; 1325439#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1324852#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1324096#L1379 assume !(0 != activate_threads_~tmp~1#1); 1324097#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1324931#L563 assume !(1 == ~t1_pc~0); 1324715#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1323951#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1323952#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1325078#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 1323947#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1323948#L582 assume !(1 == ~t2_pc~0); 1324694#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1325083#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1324290#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1324291#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 1323978#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1323979#L601 assume !(1 == ~t3_pc~0); 1324789#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1324790#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1325228#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1325116#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 1325117#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1325058#L620 assume !(1 == ~t4_pc~0); 1325059#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1324618#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1323992#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1323993#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 1324939#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1325159#L639 assume !(1 == ~t5_pc~0); 1325160#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1324259#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1324260#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1324964#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 1324965#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1324891#L658 assume !(1 == ~t6_pc~0); 1324471#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1324472#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1325795#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1325762#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 1325121#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1324307#L677 assume !(1 == ~t7_pc~0); 1324202#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1324203#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1325314#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1325501#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 1325502#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1325612#L696 assume !(1 == ~t8_pc~0); 1324540#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1324541#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1325562#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1325615#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 1325697#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1325016#L715 assume 1 == ~t9_pc~0; 1325017#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1324647#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1324344#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1324345#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 1324996#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1325311#L734 assume !(1 == ~t10_pc~0); 1325312#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1324426#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1324427#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1325233#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 1325234#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1324511#L753 assume 1 == ~t11_pc~0; 1324512#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1325128#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1325575#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1324809#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 1324810#L1467-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1324861#L1237 assume 1 == ~M_E~0;~M_E~0 := 2; 1324862#L1237-2 assume !(1 == ~T1_E~0); 1325665#L1242-1 assume !(1 == ~T2_E~0); 1325735#L1247-1 assume !(1 == ~T3_E~0); 1394288#L1252-1 assume !(1 == ~T4_E~0); 1394287#L1257-1 assume !(1 == ~T5_E~0); 1394285#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1394283#L1267-1 assume !(1 == ~T7_E~0); 1394281#L1272-1 assume !(1 == ~T8_E~0); 1394279#L1277-1 assume !(1 == ~T9_E~0); 1394277#L1282-1 assume !(1 == ~T10_E~0); 1394275#L1287-1 assume !(1 == ~T11_E~0); 1394273#L1292-1 assume !(1 == ~E_M~0); 1394271#L1297-1 assume !(1 == ~E_1~0); 1394268#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1394266#L1307-1 assume !(1 == ~E_3~0); 1394265#L1312-1 assume !(1 == ~E_4~0); 1394264#L1317-1 assume !(1 == ~E_5~0); 1392518#L1322-1 assume !(1 == ~E_6~0); 1392504#L1327-1 assume !(1 == ~E_7~0); 1392502#L1332-1 assume !(1 == ~E_8~0); 1392500#L1337-1 assume !(1 == ~E_9~0); 1392498#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1392496#L1347-1 assume !(1 == ~E_11~0); 1392493#L1352-1 assume { :end_inline_reset_delta_events } true; 1392489#L1678-2 [2024-11-09 16:09:09,102 INFO L747 eck$LassoCheckResult]: Loop: 1392489#L1678-2 assume !false; 1392220#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1392218#L1084-1 assume !false; 1392216#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1392173#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1392169#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1392167#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1392164#L925 assume !(0 != eval_~tmp~0#1); 1392165#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1408029#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1408027#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1408025#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1408023#L1114-3 assume !(0 == ~T2_E~0); 1408020#L1119-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1408018#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1408016#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1408014#L1134-3 assume !(0 == ~T6_E~0); 1408012#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1408010#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1408007#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1408005#L1154-3 assume !(0 == ~T10_E~0); 1408003#L1159-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1408001#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1407999#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1407997#L1174-3 assume !(0 == ~E_2~0); 1407995#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1407992#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1407990#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1407988#L1194-3 assume !(0 == ~E_6~0); 1407986#L1199-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1407984#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1407982#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1407980#L1214-3 assume !(0 == ~E_10~0); 1407978#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1407976#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1407975#L544-39 assume !(1 == ~m_pc~0); 1407973#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1407971#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1407969#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1407967#L1379-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1407965#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1407963#L563-39 assume !(1 == ~t1_pc~0); 1407961#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1407959#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1407957#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1407955#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1407953#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1407951#L582-39 assume !(1 == ~t2_pc~0); 1407949#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1407948#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1407947#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1407946#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1407945#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1407932#L601-39 assume !(1 == ~t3_pc~0); 1407930#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1407929#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1407928#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1407927#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1407926#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1407925#L620-39 assume !(1 == ~t4_pc~0); 1407924#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1407923#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1407922#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1407920#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1407919#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1407918#L639-39 assume !(1 == ~t5_pc~0); 1407917#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1407916#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1407914#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1407912#L1419-39 assume !(0 != activate_threads_~tmp___4~0#1); 1407910#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1407908#L658-39 assume !(1 == ~t6_pc~0); 1407904#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1407902#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1407900#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1407897#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 1407894#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1407892#L677-39 assume !(1 == ~t7_pc~0); 1407890#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1407888#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1407886#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1407884#L1435-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1407882#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1407880#L696-39 assume 1 == ~t8_pc~0; 1407877#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1407875#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1407873#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1407871#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1407869#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1407867#L715-39 assume 1 == ~t9_pc~0; 1407865#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1407862#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1407860#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1407857#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1407855#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1407853#L734-39 assume !(1 == ~t10_pc~0); 1407851#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1407848#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1407846#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1407843#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1407841#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1407839#L753-39 assume 1 == ~t11_pc~0; 1407837#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1407834#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1407833#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1407829#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1407827#L1467-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1407825#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1397131#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1407819#L1242-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1407815#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1407813#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1407811#L1257-3 assume !(1 == ~T5_E~0); 1407809#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1407807#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1407805#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1407803#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1407801#L1282-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1407796#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1407794#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1407792#L1297-3 assume !(1 == ~E_1~0); 1407790#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1407788#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1407786#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1407783#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1407781#L1322-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1407777#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1407775#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1407620#L1337-3 assume !(1 == ~E_9~0); 1407613#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1394255#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1394254#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1394223#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1394213#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1394212#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1394210#L1697 assume !(0 == start_simulation_~tmp~3#1); 1394208#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1392507#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1392503#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1392501#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret30#1;havoc stop_simulation_#t~ret30#1; 1392499#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1392497#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1392495#stop_simulation_returnLabel#1 start_simulation_#t~ret32#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret30#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1392494#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 1392489#L1678-2 [2024-11-09 16:09:09,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:09,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1946581819, now seen corresponding path program 1 times [2024-11-09 16:09:09,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:09,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665374839] [2024-11-09 16:09:09,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:09,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:09,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:09,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:09,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:09,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665374839] [2024-11-09 16:09:09,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665374839] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:09,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:09,137 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:09,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273964789] [2024-11-09 16:09:09,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:09,137 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:09,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:09,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1007636109, now seen corresponding path program 1 times [2024-11-09 16:09:09,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:09,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224886575] [2024-11-09 16:09:09,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:09,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:09,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:09,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:09,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:09,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [224886575] [2024-11-09 16:09:09,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [224886575] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:09,166 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:09,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:09,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572237453] [2024-11-09 16:09:09,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:09,166 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:09,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:09,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:09,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:09,167 INFO L87 Difference]: Start difference. First operand 401376 states and 566699 transitions. cyclomatic complexity: 165579 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:11,782 INFO L93 Difference]: Finished difference Result 765695 states and 1077464 transitions. [2024-11-09 16:09:11,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 765695 states and 1077464 transitions. [2024-11-09 16:09:15,986 INFO L131 ngComponentsAnalysis]: Automaton has 512 accepting balls. 761104