./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c7c6ca5d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- This is Ultimate 0.2.5-?-c7c6ca5-m [2024-11-09 16:08:45,566 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-09 16:08:45,657 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-09 16:08:45,662 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-09 16:08:45,664 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-09 16:08:45,698 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-09 16:08:45,699 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-09 16:08:45,700 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-09 16:08:45,701 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-09 16:08:45,702 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-09 16:08:45,702 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-09 16:08:45,703 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-09 16:08:45,703 INFO L153 SettingsManager]: * Use SBE=true [2024-11-09 16:08:45,703 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-09 16:08:45,704 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-09 16:08:45,704 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-09 16:08:45,707 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-09 16:08:45,707 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-09 16:08:45,707 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-09 16:08:45,708 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-09 16:08:45,708 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-09 16:08:45,710 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-09 16:08:45,710 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-09 16:08:45,711 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-09 16:08:45,711 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-09 16:08:45,711 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-09 16:08:45,712 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-09 16:08:45,712 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-09 16:08:45,714 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-09 16:08:45,714 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-09 16:08:45,714 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-09 16:08:45,715 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-09 16:08:45,715 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-09 16:08:45,715 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-09 16:08:45,716 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-09 16:08:45,716 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-09 16:08:45,716 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-09 16:08:45,716 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-09 16:08:45,717 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-09 16:08:45,717 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2024-11-09 16:08:45,997 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-09 16:08:46,026 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-09 16:08:46,029 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-09 16:08:46,031 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-09 16:08:46,032 INFO L274 PluginConnector]: CDTParser initialized [2024-11-09 16:08:46,033 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.14.cil.c [2024-11-09 16:08:47,582 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-09 16:08:47,810 INFO L384 CDTParser]: Found 1 translation units. [2024-11-09 16:08:47,811 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c [2024-11-09 16:08:47,825 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8354c21c7/fa802c40779d416da39cd3fcbb6beb1e/FLAGff9083efa [2024-11-09 16:08:48,167 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8354c21c7/fa802c40779d416da39cd3fcbb6beb1e [2024-11-09 16:08:48,169 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-09 16:08:48,170 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-09 16:08:48,171 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-09 16:08:48,171 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-09 16:08:48,177 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-09 16:08:48,177 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:48,178 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@59a4c94f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48, skipping insertion in model container [2024-11-09 16:08:48,178 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:48,229 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-09 16:08:48,571 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:08:48,583 INFO L200 MainTranslator]: Completed pre-run [2024-11-09 16:08:48,655 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:08:48,681 INFO L204 MainTranslator]: Completed translation [2024-11-09 16:08:48,681 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48 WrapperNode [2024-11-09 16:08:48,681 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-09 16:08:48,683 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-09 16:08:48,683 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-09 16:08:48,683 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-09 16:08:48,690 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:48,708 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:48,885 INFO L138 Inliner]: procedures = 52, calls = 69, calls flagged for inlining = 64, calls inlined = 272, statements flattened = 4173 [2024-11-09 16:08:48,885 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-09 16:08:48,886 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-09 16:08:48,886 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-09 16:08:48,886 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-09 16:08:48,897 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:48,897 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:48,909 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:48,959 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-09 16:08:48,959 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:48,960 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:49,012 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:49,049 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:49,057 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:49,069 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:49,091 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-09 16:08:49,092 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-09 16:08:49,092 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-09 16:08:49,092 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-09 16:08:49,093 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (1/1) ... [2024-11-09 16:08:49,099 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:08:49,116 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:08:49,135 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:08:49,139 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-09 16:08:49,190 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-09 16:08:49,191 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-09 16:08:49,191 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-09 16:08:49,191 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-09 16:08:49,342 INFO L238 CfgBuilder]: Building ICFG [2024-11-09 16:08:49,345 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-09 16:08:52,146 INFO L? ?]: Removed 886 outVars from TransFormulas that were not future-live. [2024-11-09 16:08:52,146 INFO L287 CfgBuilder]: Performing block encoding [2024-11-09 16:08:52,206 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-09 16:08:52,207 INFO L316 CfgBuilder]: Removed 15 assume(true) statements. [2024-11-09 16:08:52,207 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:08:52 BoogieIcfgContainer [2024-11-09 16:08:52,207 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-09 16:08:52,208 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-09 16:08:52,208 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-09 16:08:52,212 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-09 16:08:52,213 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:08:52,213 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 04:08:48" (1/3) ... [2024-11-09 16:08:52,214 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62b55a4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:08:52, skipping insertion in model container [2024-11-09 16:08:52,216 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:08:52,216 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:08:48" (2/3) ... [2024-11-09 16:08:52,217 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62b55a4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:08:52, skipping insertion in model container [2024-11-09 16:08:52,217 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:08:52,217 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:08:52" (3/3) ... [2024-11-09 16:08:52,220 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2024-11-09 16:08:52,338 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-09 16:08:52,338 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-09 16:08:52,338 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-09 16:08:52,338 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-09 16:08:52,339 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-09 16:08:52,339 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-09 16:08:52,339 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-09 16:08:52,339 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-09 16:08:52,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:52,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1644 [2024-11-09 16:08:52,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:52,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:52,467 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:52,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:52,467 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-09 16:08:52,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:52,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1644 [2024-11-09 16:08:52,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:52,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:52,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:52,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:52,508 INFO L745 eck$LassoCheckResult]: Stem: 135#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1716#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 657#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1711#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1369#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1480#L848-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 436#L853-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 308#L858-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2#L863-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 753#L868-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 842#L873-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1612#L878-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1578#L883-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1663#L888-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 387#L893-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 776#L898-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1788#L903-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 703#L908-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 411#L1201true assume !(0 == ~M_E~0); 1189#L1201-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1609#L1206-1true assume !(0 == ~T2_E~0); 1161#L1211-1true assume !(0 == ~T3_E~0); 1311#L1216-1true assume !(0 == ~T4_E~0); 296#L1221-1true assume !(0 == ~T5_E~0); 1253#L1226-1true assume !(0 == ~T6_E~0); 99#L1231-1true assume !(0 == ~T7_E~0); 1392#L1236-1true assume !(0 == ~T8_E~0); 1234#L1241-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 321#L1246-1true assume !(0 == ~T10_E~0); 409#L1251-1true assume !(0 == ~T11_E~0); 876#L1256-1true assume !(0 == ~T12_E~0); 6#L1261-1true assume !(0 == ~E_M~0); 1582#L1266-1true assume !(0 == ~E_1~0); 1521#L1271-1true assume !(0 == ~E_2~0); 830#L1276-1true assume !(0 == ~E_3~0); 1516#L1281-1true assume 0 == ~E_4~0;~E_4~0 := 1; 788#L1286-1true assume !(0 == ~E_5~0); 237#L1291-1true assume !(0 == ~E_6~0); 1607#L1296-1true assume !(0 == ~E_7~0); 614#L1301-1true assume !(0 == ~E_8~0); 1104#L1306-1true assume !(0 == ~E_9~0); 1078#L1311-1true assume !(0 == ~E_10~0); 212#L1316-1true assume !(0 == ~E_11~0); 1465#L1321-1true assume 0 == ~E_12~0;~E_12~0 := 1; 628#L1326-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745#L593true assume 1 == ~m_pc~0; 862#L594true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1479#L604true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 545#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 796#L1492true assume !(0 != activate_threads_~tmp~1#1); 1236#L1492-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1127#L612true assume !(1 == ~t1_pc~0); 1671#L612-2true is_transmit1_triggered_~__retres1~1#1 := 0; 1547#L623true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 925#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 149#L1500true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 443#L1500-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 395#L631true assume 1 == ~t2_pc~0; 353#L632true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41#L642true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 219#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 523#L1508true assume !(0 != activate_threads_~tmp___1~0#1); 1317#L1508-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 188#L650true assume !(1 == ~t3_pc~0); 962#L650-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1226#L661true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 903#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22#L1516true assume !(0 != activate_threads_~tmp___2~0#1); 972#L1516-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 772#L669true assume 1 == ~t4_pc~0; 1279#L670true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1797#L680true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 115#L1524true assume !(0 != activate_threads_~tmp___3~0#1); 244#L1524-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 988#L688true assume !(1 == ~t5_pc~0); 125#L688-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1478#L699true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1453#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 671#L1532true assume !(0 != activate_threads_~tmp___4~0#1); 782#L1532-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1301#L707true assume 1 == ~t6_pc~0; 1349#L708true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 502#L718true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1375#L1540true assume !(0 != activate_threads_~tmp___5~0#1); 732#L1540-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 410#L726true assume 1 == ~t7_pc~0; 346#L727true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 915#L737true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1734#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1312#L1548true assume !(0 != activate_threads_~tmp___6~0#1); 56#L1548-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 293#L745true assume !(1 == ~t8_pc~0); 1114#L745-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1201#L756true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1396#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 550#L1556true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1025#L1556-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1802#L764true assume 1 == ~t9_pc~0; 407#L765true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 799#L775true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 255#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1439#L1564true assume !(0 != activate_threads_~tmp___8~0#1); 68#L1564-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1394#L783true assume !(1 == ~t10_pc~0); 93#L783-2true is_transmit10_triggered_~__retres1~10#1 := 0; 191#L794true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1217#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 382#L1572true assume !(0 != activate_threads_~tmp___9~0#1); 1177#L1572-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1282#L802true assume 1 == ~t11_pc~0; 1148#L803true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39#L813true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1310#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 297#L1580true assume !(0 != activate_threads_~tmp___10~0#1); 365#L1580-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 533#L821true assume !(1 == ~t12_pc~0); 605#L821-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1339#L832true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1252#L1588true assume !(0 != activate_threads_~tmp___11~0#1); 1257#L1588-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 805#L1339true assume !(1 == ~M_E~0); 1462#L1339-2true assume !(1 == ~T1_E~0); 1322#L1344-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1736#L1349-1true assume !(1 == ~T3_E~0); 624#L1354-1true assume !(1 == ~T4_E~0); 995#L1359-1true assume !(1 == ~T5_E~0); 1557#L1364-1true assume !(1 == ~T6_E~0); 272#L1369-1true assume !(1 == ~T7_E~0); 965#L1374-1true assume !(1 == ~T8_E~0); 626#L1379-1true assume !(1 == ~T9_E~0); 700#L1384-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1776#L1389-1true assume !(1 == ~T11_E~0); 1241#L1394-1true assume !(1 == ~T12_E~0); 1638#L1399-1true assume !(1 == ~E_M~0); 1442#L1404-1true assume !(1 == ~E_1~0); 324#L1409-1true assume !(1 == ~E_2~0); 1410#L1414-1true assume !(1 == ~E_3~0); 863#L1419-1true assume !(1 == ~E_4~0); 120#L1424-1true assume 1 == ~E_5~0;~E_5~0 := 2; 632#L1429-1true assume !(1 == ~E_6~0); 1269#L1434-1true assume !(1 == ~E_7~0); 1614#L1439-1true assume !(1 == ~E_8~0); 142#L1444-1true assume !(1 == ~E_9~0); 818#L1449-1true assume !(1 == ~E_10~0); 357#L1454-1true assume !(1 == ~E_11~0); 1309#L1459-1true assume !(1 == ~E_12~0); 730#L1464-1true assume { :end_inline_reset_delta_events } true; 492#L1810-2true [2024-11-09 16:08:52,515 INFO L747 eck$LassoCheckResult]: Loop: 492#L1810-2true assume !false; 1346#L1811true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 877#L1176-1true assume false; 496#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 325#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1058#L1201-3true assume 0 == ~M_E~0;~M_E~0 := 1; 822#L1201-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1611#L1206-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 728#L1211-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 186#L1216-3true assume !(0 == ~T4_E~0); 470#L1221-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1023#L1226-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 230#L1231-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 373#L1236-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1786#L1241-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1345#L1246-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1152#L1251-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 807#L1256-3true assume !(0 == ~T12_E~0); 196#L1261-3true assume 0 == ~E_M~0;~E_M~0 := 1; 517#L1266-3true assume 0 == ~E_1~0;~E_1~0 := 1; 226#L1271-3true assume 0 == ~E_2~0;~E_2~0 := 1; 490#L1276-3true assume 0 == ~E_3~0;~E_3~0 := 1; 456#L1281-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1211#L1286-3true assume 0 == ~E_5~0;~E_5~0 := 1; 860#L1291-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1624#L1296-3true assume !(0 == ~E_7~0); 1548#L1301-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1429#L1306-3true assume 0 == ~E_9~0;~E_9~0 := 1; 528#L1311-3true assume 0 == ~E_10~0;~E_10~0 := 1; 154#L1316-3true assume 0 == ~E_11~0;~E_11~0 := 1; 197#L1321-3true assume 0 == ~E_12~0;~E_12~0 := 1; 604#L1326-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1221#L593-42true assume !(1 == ~m_pc~0); 734#L593-44true is_master_triggered_~__retres1~0#1 := 0; 1771#L604-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 388#is_master_triggered_returnLabel#15true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1733#L1492-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 102#L1492-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 690#L612-42true assume !(1 == ~t1_pc~0); 1099#L612-44true is_transmit1_triggered_~__retres1~1#1 := 0; 1595#L623-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1625#is_transmit1_triggered_returnLabel#15true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 148#L1500-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1767#L1500-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 577#L631-42true assume 1 == ~t2_pc~0; 34#L632-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 566#L642-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 570#is_transmit2_triggered_returnLabel#15true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 489#L1508-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1645#L1508-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239#L650-42true assume !(1 == ~t3_pc~0); 130#L650-44true is_transmit3_triggered_~__retres1~3#1 := 0; 1729#L661-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 890#is_transmit3_triggered_returnLabel#15true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 352#L1516-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1379#L1516-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1278#L669-42true assume !(1 == ~t4_pc~0); 18#L669-44true is_transmit4_triggered_~__retres1~4#1 := 0; 1000#L680-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 974#is_transmit4_triggered_returnLabel#15true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 872#L1524-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 781#L1524-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 859#L688-42true assume !(1 == ~t5_pc~0); 1106#L688-44true is_transmit5_triggered_~__retres1~5#1 := 0; 1358#L699-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 617#is_transmit5_triggered_returnLabel#15true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 114#L1532-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1436#L1532-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31#L707-42true assume 1 == ~t6_pc~0; 1447#L708-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1705#L718-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 193#is_transmit6_triggered_returnLabel#15true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1300#L1540-42true assume !(0 != activate_threads_~tmp___5~0#1); 756#L1540-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1033#L726-42true assume !(1 == ~t7_pc~0); 1801#L726-44true is_transmit7_triggered_~__retres1~7#1 := 0; 1075#L737-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 634#is_transmit7_triggered_returnLabel#15true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 531#L1548-42true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 608#L1548-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1197#L745-42true assume 1 == ~t8_pc~0; 638#L746-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1433#L756-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 773#is_transmit8_triggered_returnLabel#15true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26#L1556-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 428#L1556-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 514#L764-42true assume !(1 == ~t9_pc~0); 1297#L764-44true is_transmit9_triggered_~__retres1~9#1 := 0; 794#L775-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1651#is_transmit9_triggered_returnLabel#15true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 161#L1564-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 192#L1564-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 243#L783-42true assume 1 == ~t10_pc~0; 7#L784-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 316#L794-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 768#is_transmit10_triggered_returnLabel#15true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1550#L1572-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1528#L1572-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 959#L802-42true assume 1 == ~t11_pc~0; 276#L803-14true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 71#L813-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1366#is_transmit11_triggered_returnLabel#15true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46#L1580-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1565#L1580-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 803#L821-42true assume 1 == ~t12_pc~0; 1703#L822-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1010#L832-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 602#is_transmit12_triggered_returnLabel#15true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1165#L1588-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 557#L1588-44true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 549#L1339-3true assume 1 == ~M_E~0;~M_E~0 := 2; 673#L1339-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 810#L1344-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 771#L1349-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 344#L1354-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 778#L1359-3true assume !(1 == ~T5_E~0); 1620#L1364-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1512#L1369-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1267#L1374-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 241#L1379-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1156#L1384-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 343#L1389-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 482#L1394-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1719#L1399-3true assume !(1 == ~E_M~0); 1288#L1404-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1233#L1409-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1344#L1414-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1363#L1419-3true assume 1 == ~E_4~0;~E_4~0 := 2; 963#L1424-3true assume 1 == ~E_5~0;~E_5~0 := 2; 171#L1429-3true assume 1 == ~E_6~0;~E_6~0 := 2; 777#L1434-3true assume 1 == ~E_7~0;~E_7~0 := 2; 930#L1439-3true assume !(1 == ~E_8~0); 136#L1444-3true assume 1 == ~E_9~0;~E_9~0 := 2; 201#L1449-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1428#L1454-3true assume 1 == ~E_11~0;~E_11~0 := 2; 774#L1459-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1785#L1464-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 503#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1740#L988-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 189#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1464#L1829true assume !(0 == start_simulation_~tmp~3#1); 82#L1829-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1040#L921-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 552#L988-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 789#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1559#L1791true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1239#stop_simulation_returnLabel#1true start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 218#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 492#L1810-2true [2024-11-09 16:08:52,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:52,531 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 1 times [2024-11-09 16:08:52,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:52,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1284379105] [2024-11-09 16:08:52,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:52,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:52,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:52,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:52,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:52,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1284379105] [2024-11-09 16:08:52,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1284379105] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:52,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:52,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:52,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654305081] [2024-11-09 16:08:52,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:52,908 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:52,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:52,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1251295423, now seen corresponding path program 1 times [2024-11-09 16:08:52,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:52,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554985130] [2024-11-09 16:08:52,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:52,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:52,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:52,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:52,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:52,973 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554985130] [2024-11-09 16:08:52,973 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [554985130] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:52,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:52,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:08:52,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136035429] [2024-11-09 16:08:52,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:52,976 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:52,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:53,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-09 16:08:53,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-09 16:08:53,019 INFO L87 Difference]: Start difference. First operand has 1811 states, 1810 states have (on average 1.4950276243093923) internal successors, (2706), 1810 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 74.5) internal successors, (149), 2 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:53,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:53,098 INFO L93 Difference]: Finished difference Result 1807 states and 2670 transitions. [2024-11-09 16:08:53,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1807 states and 2670 transitions. [2024-11-09 16:08:53,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:53,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1807 states to 1801 states and 2664 transitions. [2024-11-09 16:08:53,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:53,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:53,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2664 transitions. [2024-11-09 16:08:53,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:53,146 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2024-11-09 16:08:53,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2664 transitions. [2024-11-09 16:08:53,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:53,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4791782343142699) internal successors, (2664), 1800 states have internal predecessors, (2664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:53,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2664 transitions. [2024-11-09 16:08:53,248 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2024-11-09 16:08:53,249 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-09 16:08:53,252 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2664 transitions. [2024-11-09 16:08:53,253 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-09 16:08:53,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2664 transitions. [2024-11-09 16:08:53,263 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:53,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:53,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:53,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:53,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:53,268 INFO L745 eck$LassoCheckResult]: Stem: 3915#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 3916#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4760#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4761#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5347#L848 assume !(1 == ~m_i~0);~m_st~0 := 2; 5348#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4441#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4230#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3627#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3628#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4872#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4971#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5409#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5410#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4366#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4367#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4898#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4823#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4403#L1201 assume !(0 == ~M_E~0); 4404#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5256#L1206-1 assume !(0 == ~T2_E~0); 5239#L1211-1 assume !(0 == ~T3_E~0); 5240#L1216-1 assume !(0 == ~T4_E~0); 4211#L1221-1 assume !(0 == ~T5_E~0); 4212#L1226-1 assume !(0 == ~T6_E~0); 3841#L1231-1 assume !(0 == ~T7_E~0); 3842#L1236-1 assume !(0 == ~T8_E~0); 5280#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4251#L1246-1 assume !(0 == ~T10_E~0); 4252#L1251-1 assume !(0 == ~T11_E~0); 4401#L1256-1 assume !(0 == ~T12_E~0); 3636#L1261-1 assume !(0 == ~E_M~0); 3637#L1266-1 assume !(0 == ~E_1~0); 5394#L1271-1 assume !(0 == ~E_2~0); 4955#L1276-1 assume !(0 == ~E_3~0); 4956#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4910#L1286-1 assume !(0 == ~E_5~0); 4107#L1291-1 assume !(0 == ~E_6~0); 4108#L1296-1 assume !(0 == ~E_7~0); 4696#L1301-1 assume !(0 == ~E_8~0); 4697#L1306-1 assume !(0 == ~E_9~0); 5175#L1311-1 assume !(0 == ~E_10~0); 4058#L1316-1 assume !(0 == ~E_11~0); 4059#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 4715#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4716#L593 assume 1 == ~m_pc~0; 4865#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3940#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4604#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4605#L1492 assume !(0 != activate_threads_~tmp~1#1); 4920#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5208#L612 assume !(1 == ~t1_pc~0); 5209#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5343#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5053#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3943#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3944#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4382#L631 assume 1 == ~t2_pc~0; 4309#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3717#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4072#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 4568#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4019#L650 assume !(1 == ~t3_pc~0); 4020#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4738#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5032#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3674#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 3675#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4891#L669 assume 1 == ~t4_pc~0; 4892#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5247#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3757#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3758#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 3878#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4117#L688 assume !(1 == ~t5_pc~0); 3897#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3898#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5375#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4780#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 4781#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4905#L707 assume 1 == ~t6_pc~0; 5314#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4537#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4060#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4061#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 4851#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4402#L726 assume 1 == ~t7_pc~0; 4297#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3984#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5044#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5318#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 3747#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3748#L745 assume !(1 == ~t8_pc~0); 4204#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4224#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5262#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4613#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4614#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5132#L764 assume 1 == ~t9_pc~0; 4400#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4234#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4133#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4134#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 3773#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3774#L783 assume !(1 == ~t10_pc~0); 3828#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3829#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4026#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4356#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 4357#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5249#L802 assume 1 == ~t11_pc~0; 5231#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3714#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3715#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4213#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 4214#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4331#L821 assume !(1 == ~t12_pc~0); 4582#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4688#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3721#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3722#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 5291#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4928#L1339 assume !(1 == ~M_E~0); 4929#L1339-2 assume !(1 == ~T1_E~0); 5321#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5322#L1349-1 assume !(1 == ~T3_E~0); 4708#L1354-1 assume !(1 == ~T4_E~0); 4709#L1359-1 assume !(1 == ~T5_E~0); 5108#L1364-1 assume !(1 == ~T6_E~0); 4165#L1369-1 assume !(1 == ~T7_E~0); 4166#L1374-1 assume !(1 == ~T8_E~0); 4711#L1379-1 assume !(1 == ~T9_E~0); 4712#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4820#L1389-1 assume !(1 == ~T11_E~0); 5285#L1394-1 assume !(1 == ~T12_E~0); 5286#L1399-1 assume !(1 == ~E_M~0); 5367#L1404-1 assume !(1 == ~E_1~0); 4258#L1409-1 assume !(1 == ~E_2~0); 4259#L1414-1 assume !(1 == ~E_3~0); 4991#L1419-1 assume !(1 == ~E_4~0); 3887#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3888#L1429-1 assume !(1 == ~E_6~0); 4723#L1434-1 assume !(1 == ~E_7~0); 5303#L1439-1 assume !(1 == ~E_8~0); 3929#L1444-1 assume !(1 == ~E_9~0); 3930#L1449-1 assume !(1 == ~E_10~0); 4315#L1454-1 assume !(1 == ~E_11~0); 4316#L1459-1 assume !(1 == ~E_12~0); 4850#L1464-1 assume { :end_inline_reset_delta_events } true; 4071#L1810-2 [2024-11-09 16:08:53,270 INFO L747 eck$LassoCheckResult]: Loop: 4071#L1810-2 assume !false; 4521#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4619#L1176-1 assume !false; 5001#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4565#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3755#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 5055#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5226#L1003 assume !(0 != eval_~tmp~0#1); 4528#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4260#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4261#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4945#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4946#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4848#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4014#L1216-3 assume !(0 == ~T4_E~0); 4015#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4493#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4093#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4094#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4345#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5334#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5234#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4933#L1256-3 assume !(0 == ~T12_E~0); 4034#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4035#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4085#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4086#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4469#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4470#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4988#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4989#L1296-3 assume !(0 == ~E_7~0); 5406#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5364#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4573#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3954#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3955#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4036#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4687#L593-42 assume 1 == ~m_pc~0; 5074#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4853#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4368#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4369#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3848#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3849#L612-42 assume !(1 == ~t1_pc~0); 4807#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 5188#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5415#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3941#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3942#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4650#L631-42 assume 1 == ~t2_pc~0; 3701#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3702#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4635#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4519#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4520#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4112#L650-42 assume 1 == ~t3_pc~0; 3666#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3667#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5021#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4307#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4308#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5305#L669-42 assume !(1 == ~t4_pc~0); 3664#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 3665#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5090#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4999#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4903#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4904#L688-42 assume 1 == ~t5_pc~0; 4986#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5191#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4699#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3876#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3877#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3694#L707-42 assume 1 == ~t6_pc~0; 3696#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5370#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4028#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4029#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 4874#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4875#L726-42 assume 1 == ~t7_pc~0; 5141#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5172#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4726#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4577#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4578#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4691#L745-42 assume 1 == ~t8_pc~0; 4729#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4731#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4894#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3682#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3683#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4428#L764-42 assume 1 == ~t9_pc~0; 4556#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4917#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4918#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3966#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3967#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4027#L783-42 assume 1 == ~t10_pc~0; 3638#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3639#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4243#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4886#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5397#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5080#L802-42 assume 1 == ~t11_pc~0; 4174#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3780#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3781#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3727#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3728#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4925#L821-42 assume !(1 == ~t12_pc~0); 4283#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4284#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4684#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4685#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4621#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4611#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4612#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4784#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4890#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4293#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4294#L1359-3 assume !(1 == ~T5_E~0); 4900#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5391#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5301#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4114#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4115#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4291#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4292#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4507#L1399-3 assume !(1 == ~E_M~0); 5310#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5278#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5279#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5333#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5083#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3988#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3989#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4899#L1439-3 assume !(1 == ~E_8~0); 3917#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3918#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4039#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4895#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4896#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4538#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3820#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4022#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4023#L1829 assume !(0 == start_simulation_~tmp~3#1); 3802#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3803#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4617#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3707#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 3708#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4911#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5284#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4070#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4071#L1810-2 [2024-11-09 16:08:53,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:53,271 INFO L85 PathProgramCache]: Analyzing trace with hash -1818030166, now seen corresponding path program 2 times [2024-11-09 16:08:53,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:53,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63756415] [2024-11-09 16:08:53,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:53,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:53,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:53,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:53,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:53,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63756415] [2024-11-09 16:08:53,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63756415] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:53,365 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:53,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:53,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874821535] [2024-11-09 16:08:53,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:53,366 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:53,367 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:53,370 INFO L85 PathProgramCache]: Analyzing trace with hash 1042690776, now seen corresponding path program 1 times [2024-11-09 16:08:53,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:53,371 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143930251] [2024-11-09 16:08:53,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:53,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:53,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:53,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:53,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:53,572 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143930251] [2024-11-09 16:08:53,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143930251] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:53,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:53,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:53,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445595989] [2024-11-09 16:08:53,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:53,576 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:53,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:53,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:53,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:53,579 INFO L87 Difference]: Start difference. First operand 1801 states and 2664 transitions. cyclomatic complexity: 864 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:53,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:53,628 INFO L93 Difference]: Finished difference Result 1801 states and 2663 transitions. [2024-11-09 16:08:53,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2663 transitions. [2024-11-09 16:08:53,643 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:53,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2663 transitions. [2024-11-09 16:08:53,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:53,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:53,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2663 transitions. [2024-11-09 16:08:53,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:53,665 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2024-11-09 16:08:53,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2663 transitions. [2024-11-09 16:08:53,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:53,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.478622987229317) internal successors, (2663), 1800 states have internal predecessors, (2663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:53,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2663 transitions. [2024-11-09 16:08:53,703 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2024-11-09 16:08:53,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:53,705 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2663 transitions. [2024-11-09 16:08:53,708 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-09 16:08:53,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2663 transitions. [2024-11-09 16:08:53,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:53,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:53,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:53,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:53,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:53,727 INFO L745 eck$LassoCheckResult]: Stem: 7524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 7525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 8369#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8370#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8956#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 8957#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8050#L853-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7839#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7236#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7237#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8481#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8580#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9018#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9019#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7975#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7976#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8507#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8432#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8012#L1201 assume !(0 == ~M_E~0); 8013#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8865#L1206-1 assume !(0 == ~T2_E~0); 8848#L1211-1 assume !(0 == ~T3_E~0); 8849#L1216-1 assume !(0 == ~T4_E~0); 7820#L1221-1 assume !(0 == ~T5_E~0); 7821#L1226-1 assume !(0 == ~T6_E~0); 7450#L1231-1 assume !(0 == ~T7_E~0); 7451#L1236-1 assume !(0 == ~T8_E~0); 8889#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7860#L1246-1 assume !(0 == ~T10_E~0); 7861#L1251-1 assume !(0 == ~T11_E~0); 8010#L1256-1 assume !(0 == ~T12_E~0); 7245#L1261-1 assume !(0 == ~E_M~0); 7246#L1266-1 assume !(0 == ~E_1~0); 9003#L1271-1 assume !(0 == ~E_2~0); 8564#L1276-1 assume !(0 == ~E_3~0); 8565#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8519#L1286-1 assume !(0 == ~E_5~0); 7716#L1291-1 assume !(0 == ~E_6~0); 7717#L1296-1 assume !(0 == ~E_7~0); 8305#L1301-1 assume !(0 == ~E_8~0); 8306#L1306-1 assume !(0 == ~E_9~0); 8784#L1311-1 assume !(0 == ~E_10~0); 7667#L1316-1 assume !(0 == ~E_11~0); 7668#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 8324#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8325#L593 assume 1 == ~m_pc~0; 8474#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7549#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8213#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8214#L1492 assume !(0 != activate_threads_~tmp~1#1); 8529#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8817#L612 assume !(1 == ~t1_pc~0); 8818#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8952#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8662#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7552#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7553#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7991#L631 assume 1 == ~t2_pc~0; 7918#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7326#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7327#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7681#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 8177#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7628#L650 assume !(1 == ~t3_pc~0); 7629#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8347#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8641#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7283#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 7284#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8500#L669 assume 1 == ~t4_pc~0; 8501#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8856#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7367#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 7487#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7726#L688 assume !(1 == ~t5_pc~0); 7506#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7507#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8984#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8389#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 8390#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8514#L707 assume 1 == ~t6_pc~0; 8923#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8146#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7669#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7670#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 8460#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8011#L726 assume 1 == ~t7_pc~0; 7906#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7593#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8927#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 7356#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7357#L745 assume !(1 == ~t8_pc~0); 7813#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7833#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8871#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8222#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8223#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8741#L764 assume 1 == ~t9_pc~0; 8009#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7843#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7742#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7743#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 7382#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7383#L783 assume !(1 == ~t10_pc~0); 7437#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7438#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7635#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7965#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 7966#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8858#L802 assume 1 == ~t11_pc~0; 8840#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7323#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7324#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7822#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 7823#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7940#L821 assume !(1 == ~t12_pc~0); 8191#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8297#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7330#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7331#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 8900#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8537#L1339 assume !(1 == ~M_E~0); 8538#L1339-2 assume !(1 == ~T1_E~0); 8930#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8931#L1349-1 assume !(1 == ~T3_E~0); 8317#L1354-1 assume !(1 == ~T4_E~0); 8318#L1359-1 assume !(1 == ~T5_E~0); 8717#L1364-1 assume !(1 == ~T6_E~0); 7774#L1369-1 assume !(1 == ~T7_E~0); 7775#L1374-1 assume !(1 == ~T8_E~0); 8320#L1379-1 assume !(1 == ~T9_E~0); 8321#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8429#L1389-1 assume !(1 == ~T11_E~0); 8894#L1394-1 assume !(1 == ~T12_E~0); 8895#L1399-1 assume !(1 == ~E_M~0); 8976#L1404-1 assume !(1 == ~E_1~0); 7867#L1409-1 assume !(1 == ~E_2~0); 7868#L1414-1 assume !(1 == ~E_3~0); 8600#L1419-1 assume !(1 == ~E_4~0); 7496#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7497#L1429-1 assume !(1 == ~E_6~0); 8332#L1434-1 assume !(1 == ~E_7~0); 8912#L1439-1 assume !(1 == ~E_8~0); 7538#L1444-1 assume !(1 == ~E_9~0); 7539#L1449-1 assume !(1 == ~E_10~0); 7924#L1454-1 assume !(1 == ~E_11~0); 7925#L1459-1 assume !(1 == ~E_12~0); 8459#L1464-1 assume { :end_inline_reset_delta_events } true; 7680#L1810-2 [2024-11-09 16:08:53,728 INFO L747 eck$LassoCheckResult]: Loop: 7680#L1810-2 assume !false; 8130#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8228#L1176-1 assume !false; 8610#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8174#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7364#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8664#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8835#L1003 assume !(0 != eval_~tmp~0#1); 8137#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7869#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7870#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8554#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8555#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8457#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7623#L1216-3 assume !(0 == ~T4_E~0); 7624#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8102#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7702#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7703#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7954#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8943#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8843#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8542#L1256-3 assume !(0 == ~T12_E~0); 7643#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7644#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7694#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7695#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8078#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8079#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8597#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8598#L1296-3 assume !(0 == ~E_7~0); 9015#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8973#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8182#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7563#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7564#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7645#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8296#L593-42 assume 1 == ~m_pc~0; 8683#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8462#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7977#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7978#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7457#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7458#L612-42 assume !(1 == ~t1_pc~0); 8416#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 8797#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9024#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7550#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7551#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8259#L631-42 assume !(1 == ~t2_pc~0); 7312#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 7311#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8244#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8128#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8129#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7721#L650-42 assume 1 == ~t3_pc~0; 7275#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7276#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8630#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7916#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7917#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8914#L669-42 assume 1 == ~t4_pc~0; 8196#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7274#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8699#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8608#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8512#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8513#L688-42 assume 1 == ~t5_pc~0; 8595#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8800#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8308#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7485#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7486#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7303#L707-42 assume !(1 == ~t6_pc~0); 7304#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 8979#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7637#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7638#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 8483#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8484#L726-42 assume 1 == ~t7_pc~0; 8750#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8781#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8335#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8186#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8187#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8300#L745-42 assume 1 == ~t8_pc~0; 8338#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8340#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8503#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7291#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7292#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8037#L764-42 assume 1 == ~t9_pc~0; 8165#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8526#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8527#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7575#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7576#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7636#L783-42 assume !(1 == ~t10_pc~0); 7249#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 7248#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7852#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8495#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9006#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8689#L802-42 assume 1 == ~t11_pc~0; 7783#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7389#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7390#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7336#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7337#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8534#L821-42 assume !(1 == ~t12_pc~0); 7892#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 7893#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8293#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8294#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8230#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8220#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8221#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8393#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8499#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7902#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7903#L1359-3 assume !(1 == ~T5_E~0); 8509#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9000#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8910#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7723#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7724#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7900#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7901#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8116#L1399-3 assume !(1 == ~E_M~0); 8919#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8887#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8888#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8942#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8692#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7597#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7598#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8508#L1439-3 assume !(1 == ~E_8~0); 7526#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7527#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7648#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8504#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8505#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8147#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7429#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7631#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7632#L1829 assume !(0 == start_simulation_~tmp~3#1); 7411#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7412#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8226#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7316#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7317#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8520#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8893#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7679#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 7680#L1810-2 [2024-11-09 16:08:53,729 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:53,729 INFO L85 PathProgramCache]: Analyzing trace with hash -494851220, now seen corresponding path program 1 times [2024-11-09 16:08:53,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:53,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420899171] [2024-11-09 16:08:53,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:53,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:53,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:53,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:53,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:53,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420899171] [2024-11-09 16:08:53,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420899171] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:53,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:53,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:53,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299660337] [2024-11-09 16:08:53,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:53,827 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:53,828 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:53,828 INFO L85 PathProgramCache]: Analyzing trace with hash 1913226970, now seen corresponding path program 1 times [2024-11-09 16:08:53,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:53,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875425344] [2024-11-09 16:08:53,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:53,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:53,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:53,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:53,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:53,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875425344] [2024-11-09 16:08:53,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875425344] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:53,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:53,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:53,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444105269] [2024-11-09 16:08:53,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:53,928 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:53,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:53,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:53,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:53,929 INFO L87 Difference]: Start difference. First operand 1801 states and 2663 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:53,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:53,964 INFO L93 Difference]: Finished difference Result 1801 states and 2662 transitions. [2024-11-09 16:08:53,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2662 transitions. [2024-11-09 16:08:53,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:53,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2662 transitions. [2024-11-09 16:08:53,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:53,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:53,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2662 transitions. [2024-11-09 16:08:53,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:53,991 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2024-11-09 16:08:53,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2662 transitions. [2024-11-09 16:08:54,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:54,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4780677401443643) internal successors, (2662), 1800 states have internal predecessors, (2662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:54,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2662 transitions. [2024-11-09 16:08:54,024 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2024-11-09 16:08:54,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:54,027 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2662 transitions. [2024-11-09 16:08:54,027 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-09 16:08:54,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2662 transitions. [2024-11-09 16:08:54,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:54,038 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:54,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:54,042 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:54,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:54,045 INFO L745 eck$LassoCheckResult]: Stem: 11133#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 11134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11978#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11979#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12565#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12566#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11659#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11448#L858-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10845#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10846#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12090#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12189#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12627#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12628#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11584#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11585#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12116#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12041#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11621#L1201 assume !(0 == ~M_E~0); 11622#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12474#L1206-1 assume !(0 == ~T2_E~0); 12457#L1211-1 assume !(0 == ~T3_E~0); 12458#L1216-1 assume !(0 == ~T4_E~0); 11429#L1221-1 assume !(0 == ~T5_E~0); 11430#L1226-1 assume !(0 == ~T6_E~0); 11059#L1231-1 assume !(0 == ~T7_E~0); 11060#L1236-1 assume !(0 == ~T8_E~0); 12498#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11469#L1246-1 assume !(0 == ~T10_E~0); 11470#L1251-1 assume !(0 == ~T11_E~0); 11619#L1256-1 assume !(0 == ~T12_E~0); 10854#L1261-1 assume !(0 == ~E_M~0); 10855#L1266-1 assume !(0 == ~E_1~0); 12612#L1271-1 assume !(0 == ~E_2~0); 12173#L1276-1 assume !(0 == ~E_3~0); 12174#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 12128#L1286-1 assume !(0 == ~E_5~0); 11325#L1291-1 assume !(0 == ~E_6~0); 11326#L1296-1 assume !(0 == ~E_7~0); 11914#L1301-1 assume !(0 == ~E_8~0); 11915#L1306-1 assume !(0 == ~E_9~0); 12393#L1311-1 assume !(0 == ~E_10~0); 11276#L1316-1 assume !(0 == ~E_11~0); 11277#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 11933#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11934#L593 assume 1 == ~m_pc~0; 12083#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11158#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11822#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11823#L1492 assume !(0 != activate_threads_~tmp~1#1); 12138#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12426#L612 assume !(1 == ~t1_pc~0); 12427#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12561#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11161#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11162#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11600#L631 assume 1 == ~t2_pc~0; 11527#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10935#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10936#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11290#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 11786#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11237#L650 assume !(1 == ~t3_pc~0); 11238#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11956#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12250#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10892#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 10893#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12109#L669 assume 1 == ~t4_pc~0; 12110#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12465#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10976#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 11096#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11335#L688 assume !(1 == ~t5_pc~0); 11115#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11116#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12593#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11998#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 11999#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12123#L707 assume 1 == ~t6_pc~0; 12532#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11755#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11278#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11279#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 12069#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11620#L726 assume 1 == ~t7_pc~0; 11515#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11202#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12262#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12536#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 10965#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10966#L745 assume !(1 == ~t8_pc~0); 11422#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11442#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12480#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11831#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11832#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12350#L764 assume 1 == ~t9_pc~0; 11618#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11452#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11351#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11352#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 10991#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10992#L783 assume !(1 == ~t10_pc~0); 11046#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11047#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11244#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11574#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 11575#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12467#L802 assume 1 == ~t11_pc~0; 12449#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10932#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10933#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11431#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 11432#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11549#L821 assume !(1 == ~t12_pc~0); 11800#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11906#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10939#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10940#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 12509#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12146#L1339 assume !(1 == ~M_E~0); 12147#L1339-2 assume !(1 == ~T1_E~0); 12539#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12540#L1349-1 assume !(1 == ~T3_E~0); 11926#L1354-1 assume !(1 == ~T4_E~0); 11927#L1359-1 assume !(1 == ~T5_E~0); 12326#L1364-1 assume !(1 == ~T6_E~0); 11383#L1369-1 assume !(1 == ~T7_E~0); 11384#L1374-1 assume !(1 == ~T8_E~0); 11929#L1379-1 assume !(1 == ~T9_E~0); 11930#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12038#L1389-1 assume !(1 == ~T11_E~0); 12503#L1394-1 assume !(1 == ~T12_E~0); 12504#L1399-1 assume !(1 == ~E_M~0); 12585#L1404-1 assume !(1 == ~E_1~0); 11476#L1409-1 assume !(1 == ~E_2~0); 11477#L1414-1 assume !(1 == ~E_3~0); 12209#L1419-1 assume !(1 == ~E_4~0); 11105#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11106#L1429-1 assume !(1 == ~E_6~0); 11941#L1434-1 assume !(1 == ~E_7~0); 12521#L1439-1 assume !(1 == ~E_8~0); 11147#L1444-1 assume !(1 == ~E_9~0); 11148#L1449-1 assume !(1 == ~E_10~0); 11533#L1454-1 assume !(1 == ~E_11~0); 11534#L1459-1 assume !(1 == ~E_12~0); 12068#L1464-1 assume { :end_inline_reset_delta_events } true; 11289#L1810-2 [2024-11-09 16:08:54,045 INFO L747 eck$LassoCheckResult]: Loop: 11289#L1810-2 assume !false; 11739#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11837#L1176-1 assume !false; 12219#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11783#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10973#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 12273#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12444#L1003 assume !(0 != eval_~tmp~0#1); 11746#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11479#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12163#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12164#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12066#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11232#L1216-3 assume !(0 == ~T4_E~0); 11233#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11711#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11311#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11312#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11563#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12552#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12452#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12151#L1256-3 assume !(0 == ~T12_E~0); 11252#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11253#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11303#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11304#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11687#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11688#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12206#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12207#L1296-3 assume !(0 == ~E_7~0); 12624#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12582#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11791#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11172#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11173#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11254#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11905#L593-42 assume 1 == ~m_pc~0; 12292#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12071#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11586#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11587#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11066#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11067#L612-42 assume !(1 == ~t1_pc~0); 12025#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 12406#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12633#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11159#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11160#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11868#L631-42 assume 1 == ~t2_pc~0; 10919#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10920#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11853#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11737#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11738#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11330#L650-42 assume 1 == ~t3_pc~0; 10884#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10885#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12239#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11525#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11526#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12523#L669-42 assume !(1 == ~t4_pc~0); 10882#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 10883#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12308#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12217#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12121#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12122#L688-42 assume 1 == ~t5_pc~0; 12204#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12409#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11917#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11094#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11095#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10912#L707-42 assume !(1 == ~t6_pc~0); 10913#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 12588#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11246#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11247#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 12092#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12093#L726-42 assume 1 == ~t7_pc~0; 12359#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12390#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11944#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11795#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11796#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11909#L745-42 assume 1 == ~t8_pc~0; 11947#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11949#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12112#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10900#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10901#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11646#L764-42 assume 1 == ~t9_pc~0; 11774#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12135#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12136#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11184#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11185#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11245#L783-42 assume 1 == ~t10_pc~0; 10856#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10857#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11461#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12104#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12615#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12298#L802-42 assume 1 == ~t11_pc~0; 11392#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10998#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10999#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10945#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10946#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12143#L821-42 assume 1 == ~t12_pc~0; 12144#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11502#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11902#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11903#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11839#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11829#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11830#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12002#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12108#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11511#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11512#L1359-3 assume !(1 == ~T5_E~0); 12118#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12609#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12519#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11332#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11333#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11509#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11510#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11725#L1399-3 assume !(1 == ~E_M~0); 12528#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12496#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12497#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12551#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12301#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11206#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11207#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12117#L1439-3 assume !(1 == ~E_8~0); 11135#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11136#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 11257#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12113#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12114#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11756#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11038#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11240#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11241#L1829 assume !(0 == start_simulation_~tmp~3#1); 11020#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11021#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11835#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10925#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 10926#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12129#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12502#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11288#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11289#L1810-2 [2024-11-09 16:08:54,046 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:54,046 INFO L85 PathProgramCache]: Analyzing trace with hash -833138770, now seen corresponding path program 1 times [2024-11-09 16:08:54,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:54,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482074128] [2024-11-09 16:08:54,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:54,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:54,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:54,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:54,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:54,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482074128] [2024-11-09 16:08:54,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482074128] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:54,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:54,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:54,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609917606] [2024-11-09 16:08:54,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:54,104 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:54,104 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:54,104 INFO L85 PathProgramCache]: Analyzing trace with hash -918804904, now seen corresponding path program 1 times [2024-11-09 16:08:54,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:54,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493964638] [2024-11-09 16:08:54,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:54,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:54,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:54,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:54,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:54,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493964638] [2024-11-09 16:08:54,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493964638] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:54,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:54,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:54,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640219459] [2024-11-09 16:08:54,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:54,182 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:54,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:54,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:54,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:54,183 INFO L87 Difference]: Start difference. First operand 1801 states and 2662 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:54,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:54,248 INFO L93 Difference]: Finished difference Result 1801 states and 2661 transitions. [2024-11-09 16:08:54,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2661 transitions. [2024-11-09 16:08:54,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:54,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2661 transitions. [2024-11-09 16:08:54,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:54,271 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:54,271 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2661 transitions. [2024-11-09 16:08:54,273 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:54,273 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2024-11-09 16:08:54,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2661 transitions. [2024-11-09 16:08:54,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:54,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4775124930594115) internal successors, (2661), 1800 states have internal predecessors, (2661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:54,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2661 transitions. [2024-11-09 16:08:54,306 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2024-11-09 16:08:54,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:54,307 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2661 transitions. [2024-11-09 16:08:54,307 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-09 16:08:54,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2661 transitions. [2024-11-09 16:08:54,318 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:54,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:54,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:54,321 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:54,323 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:54,323 INFO L745 eck$LassoCheckResult]: Stem: 14742#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 14743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15587#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15588#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16174#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 16175#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15268#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15057#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14454#L863-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14455#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15699#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15798#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16236#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16237#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15193#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15194#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15725#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15650#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15230#L1201 assume !(0 == ~M_E~0); 15231#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16083#L1206-1 assume !(0 == ~T2_E~0); 16066#L1211-1 assume !(0 == ~T3_E~0); 16067#L1216-1 assume !(0 == ~T4_E~0); 15038#L1221-1 assume !(0 == ~T5_E~0); 15039#L1226-1 assume !(0 == ~T6_E~0); 14668#L1231-1 assume !(0 == ~T7_E~0); 14669#L1236-1 assume !(0 == ~T8_E~0); 16107#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15078#L1246-1 assume !(0 == ~T10_E~0); 15079#L1251-1 assume !(0 == ~T11_E~0); 15228#L1256-1 assume !(0 == ~T12_E~0); 14463#L1261-1 assume !(0 == ~E_M~0); 14464#L1266-1 assume !(0 == ~E_1~0); 16221#L1271-1 assume !(0 == ~E_2~0); 15782#L1276-1 assume !(0 == ~E_3~0); 15783#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 15737#L1286-1 assume !(0 == ~E_5~0); 14934#L1291-1 assume !(0 == ~E_6~0); 14935#L1296-1 assume !(0 == ~E_7~0); 15523#L1301-1 assume !(0 == ~E_8~0); 15524#L1306-1 assume !(0 == ~E_9~0); 16002#L1311-1 assume !(0 == ~E_10~0); 14885#L1316-1 assume !(0 == ~E_11~0); 14886#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 15542#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15543#L593 assume 1 == ~m_pc~0; 15692#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14767#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15431#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15432#L1492 assume !(0 != activate_threads_~tmp~1#1); 15747#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16035#L612 assume !(1 == ~t1_pc~0); 16036#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16170#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15880#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14770#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14771#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15209#L631 assume 1 == ~t2_pc~0; 15136#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14544#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14545#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14899#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 15395#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14846#L650 assume !(1 == ~t3_pc~0); 14847#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15565#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15859#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14501#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 14502#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15718#L669 assume 1 == ~t4_pc~0; 15719#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16074#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14584#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14585#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 14705#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14944#L688 assume !(1 == ~t5_pc~0); 14724#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14725#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16202#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15607#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 15608#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15732#L707 assume 1 == ~t6_pc~0; 16141#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15364#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14887#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14888#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 15678#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15229#L726 assume 1 == ~t7_pc~0; 15124#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14811#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15871#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16145#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 14574#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14575#L745 assume !(1 == ~t8_pc~0); 15031#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 15051#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16089#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15440#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15441#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15959#L764 assume 1 == ~t9_pc~0; 15227#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15061#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14960#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14961#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 14600#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14601#L783 assume !(1 == ~t10_pc~0); 14655#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 14656#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14853#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15183#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 15184#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16076#L802 assume 1 == ~t11_pc~0; 16058#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14541#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14542#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15040#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 15041#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15158#L821 assume !(1 == ~t12_pc~0); 15409#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 15515#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14548#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14549#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 16118#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15755#L1339 assume !(1 == ~M_E~0); 15756#L1339-2 assume !(1 == ~T1_E~0); 16148#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16149#L1349-1 assume !(1 == ~T3_E~0); 15535#L1354-1 assume !(1 == ~T4_E~0); 15536#L1359-1 assume !(1 == ~T5_E~0); 15935#L1364-1 assume !(1 == ~T6_E~0); 14992#L1369-1 assume !(1 == ~T7_E~0); 14993#L1374-1 assume !(1 == ~T8_E~0); 15538#L1379-1 assume !(1 == ~T9_E~0); 15539#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15647#L1389-1 assume !(1 == ~T11_E~0); 16112#L1394-1 assume !(1 == ~T12_E~0); 16113#L1399-1 assume !(1 == ~E_M~0); 16194#L1404-1 assume !(1 == ~E_1~0); 15085#L1409-1 assume !(1 == ~E_2~0); 15086#L1414-1 assume !(1 == ~E_3~0); 15818#L1419-1 assume !(1 == ~E_4~0); 14714#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14715#L1429-1 assume !(1 == ~E_6~0); 15550#L1434-1 assume !(1 == ~E_7~0); 16130#L1439-1 assume !(1 == ~E_8~0); 14756#L1444-1 assume !(1 == ~E_9~0); 14757#L1449-1 assume !(1 == ~E_10~0); 15142#L1454-1 assume !(1 == ~E_11~0); 15143#L1459-1 assume !(1 == ~E_12~0); 15677#L1464-1 assume { :end_inline_reset_delta_events } true; 14898#L1810-2 [2024-11-09 16:08:54,324 INFO L747 eck$LassoCheckResult]: Loop: 14898#L1810-2 assume !false; 15348#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15446#L1176-1 assume !false; 15828#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15392#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14582#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15882#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16053#L1003 assume !(0 != eval_~tmp~0#1); 15355#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15087#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15088#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15772#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15773#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15675#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14841#L1216-3 assume !(0 == ~T4_E~0); 14842#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15320#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14920#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14921#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15172#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16161#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16061#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15760#L1256-3 assume !(0 == ~T12_E~0); 14861#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14862#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14912#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14913#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15296#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15297#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15815#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15816#L1296-3 assume !(0 == ~E_7~0); 16233#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16191#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15400#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14781#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14782#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14863#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15514#L593-42 assume 1 == ~m_pc~0; 15901#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15680#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15195#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15196#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14675#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14676#L612-42 assume !(1 == ~t1_pc~0); 15634#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 16015#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16242#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14768#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14769#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15477#L631-42 assume 1 == ~t2_pc~0; 14528#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14529#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15462#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15346#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15347#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14939#L650-42 assume 1 == ~t3_pc~0; 14493#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14494#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15848#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15134#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15135#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16132#L669-42 assume 1 == ~t4_pc~0; 15414#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14492#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15917#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15826#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15730#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15731#L688-42 assume 1 == ~t5_pc~0; 15813#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16018#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15526#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14703#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14704#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14521#L707-42 assume !(1 == ~t6_pc~0); 14522#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 16197#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14855#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14856#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 15701#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15702#L726-42 assume 1 == ~t7_pc~0; 15968#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15999#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15553#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15404#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15405#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15518#L745-42 assume 1 == ~t8_pc~0; 15556#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15558#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15721#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14509#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14510#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15255#L764-42 assume 1 == ~t9_pc~0; 15383#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15744#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15745#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14793#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14794#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14854#L783-42 assume 1 == ~t10_pc~0; 14465#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14466#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15070#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15713#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16224#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15907#L802-42 assume 1 == ~t11_pc~0; 15001#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14607#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14608#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14554#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14555#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 15752#L821-42 assume !(1 == ~t12_pc~0); 15110#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 15111#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15511#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 15512#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 15448#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15438#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15439#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15611#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15717#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15120#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15121#L1359-3 assume !(1 == ~T5_E~0); 15727#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16218#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16128#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14941#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14942#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15118#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15119#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15334#L1399-3 assume !(1 == ~E_M~0); 16137#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16105#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16106#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16160#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15910#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14815#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14816#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15726#L1439-3 assume !(1 == ~E_8~0); 14744#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 14745#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 14866#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 15722#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 15723#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15365#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14647#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14849#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 14850#L1829 assume !(0 == start_simulation_~tmp~3#1); 14629#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 14630#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15444#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14534#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 14535#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15738#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16111#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 14897#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 14898#L1810-2 [2024-11-09 16:08:54,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:54,325 INFO L85 PathProgramCache]: Analyzing trace with hash -1259693268, now seen corresponding path program 1 times [2024-11-09 16:08:54,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:54,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045806983] [2024-11-09 16:08:54,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:54,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:54,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:54,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:54,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:54,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045806983] [2024-11-09 16:08:54,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1045806983] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:54,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:54,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:54,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635588779] [2024-11-09 16:08:54,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:54,376 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:54,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:54,376 INFO L85 PathProgramCache]: Analyzing trace with hash 1385499736, now seen corresponding path program 1 times [2024-11-09 16:08:54,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:54,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430711812] [2024-11-09 16:08:54,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:54,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:54,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:54,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:54,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:54,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430711812] [2024-11-09 16:08:54,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430711812] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:54,442 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:54,442 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:54,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039706239] [2024-11-09 16:08:54,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:54,443 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:54,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:54,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:54,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:54,444 INFO L87 Difference]: Start difference. First operand 1801 states and 2661 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:54,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:54,474 INFO L93 Difference]: Finished difference Result 1801 states and 2660 transitions. [2024-11-09 16:08:54,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2660 transitions. [2024-11-09 16:08:54,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:54,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2660 transitions. [2024-11-09 16:08:54,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:54,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:54,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2660 transitions. [2024-11-09 16:08:54,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:54,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2024-11-09 16:08:54,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2660 transitions. [2024-11-09 16:08:54,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:54,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4769572459744587) internal successors, (2660), 1800 states have internal predecessors, (2660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:54,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2660 transitions. [2024-11-09 16:08:54,530 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2024-11-09 16:08:54,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:54,533 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2660 transitions. [2024-11-09 16:08:54,533 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-09 16:08:54,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2660 transitions. [2024-11-09 16:08:54,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:54,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:54,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:54,542 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:54,542 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:54,542 INFO L745 eck$LassoCheckResult]: Stem: 18351#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 18352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 19197#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19198#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19783#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 19784#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18878#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18666#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18063#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18064#L868-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19308#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19408#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19845#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19846#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18802#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18803#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19334#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19259#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18839#L1201 assume !(0 == ~M_E~0); 18840#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19692#L1206-1 assume !(0 == ~T2_E~0); 19675#L1211-1 assume !(0 == ~T3_E~0); 19676#L1216-1 assume !(0 == ~T4_E~0); 18650#L1221-1 assume !(0 == ~T5_E~0); 18651#L1226-1 assume !(0 == ~T6_E~0); 18277#L1231-1 assume !(0 == ~T7_E~0); 18278#L1236-1 assume !(0 == ~T8_E~0); 19716#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18690#L1246-1 assume !(0 == ~T10_E~0); 18691#L1251-1 assume !(0 == ~T11_E~0); 18837#L1256-1 assume !(0 == ~T12_E~0); 18072#L1261-1 assume !(0 == ~E_M~0); 18073#L1266-1 assume !(0 == ~E_1~0); 19830#L1271-1 assume !(0 == ~E_2~0); 19391#L1276-1 assume !(0 == ~E_3~0); 19392#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 19346#L1286-1 assume !(0 == ~E_5~0); 18543#L1291-1 assume !(0 == ~E_6~0); 18544#L1296-1 assume !(0 == ~E_7~0); 19132#L1301-1 assume !(0 == ~E_8~0); 19133#L1306-1 assume !(0 == ~E_9~0); 19611#L1311-1 assume !(0 == ~E_10~0); 18494#L1316-1 assume !(0 == ~E_11~0); 18495#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 19151#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19152#L593 assume 1 == ~m_pc~0; 19301#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18376#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19040#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19041#L1492 assume !(0 != activate_threads_~tmp~1#1); 19356#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19644#L612 assume !(1 == ~t1_pc~0); 19645#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19779#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19490#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18379#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18380#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18818#L631 assume 1 == ~t2_pc~0; 18745#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18153#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18154#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18508#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 19004#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18457#L650 assume !(1 == ~t3_pc~0); 18458#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19174#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19468#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18110#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 18111#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19327#L669 assume 1 == ~t4_pc~0; 19328#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19684#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18197#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18198#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 18314#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18553#L688 assume !(1 == ~t5_pc~0); 18333#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 18334#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19811#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19218#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 19219#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19344#L707 assume 1 == ~t6_pc~0; 19750#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18973#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18496#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18497#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 19289#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18838#L726 assume 1 == ~t7_pc~0; 18735#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18420#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19481#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19755#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 18183#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18184#L745 assume !(1 == ~t8_pc~0); 18640#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 18660#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19049#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19050#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19568#L764 assume 1 == ~t9_pc~0; 18836#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18670#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18569#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18570#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 18209#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18210#L783 assume !(1 == ~t10_pc~0); 18264#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 18265#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18462#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18797#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 18798#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19685#L802 assume 1 == ~t11_pc~0; 19667#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18150#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18151#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18647#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 18648#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18767#L821 assume !(1 == ~t12_pc~0); 19018#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 19124#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18157#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18158#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 19727#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19364#L1339 assume !(1 == ~M_E~0); 19365#L1339-2 assume !(1 == ~T1_E~0); 19757#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19758#L1349-1 assume !(1 == ~T3_E~0); 19144#L1354-1 assume !(1 == ~T4_E~0); 19145#L1359-1 assume !(1 == ~T5_E~0); 19544#L1364-1 assume !(1 == ~T6_E~0); 18601#L1369-1 assume !(1 == ~T7_E~0); 18602#L1374-1 assume !(1 == ~T8_E~0); 19147#L1379-1 assume !(1 == ~T9_E~0); 19148#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19256#L1389-1 assume !(1 == ~T11_E~0); 19721#L1394-1 assume !(1 == ~T12_E~0); 19722#L1399-1 assume !(1 == ~E_M~0); 19803#L1404-1 assume !(1 == ~E_1~0); 18694#L1409-1 assume !(1 == ~E_2~0); 18695#L1414-1 assume !(1 == ~E_3~0); 19427#L1419-1 assume !(1 == ~E_4~0); 18323#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18324#L1429-1 assume !(1 == ~E_6~0); 19159#L1434-1 assume !(1 == ~E_7~0); 19739#L1439-1 assume !(1 == ~E_8~0); 18365#L1444-1 assume !(1 == ~E_9~0); 18366#L1449-1 assume !(1 == ~E_10~0); 18751#L1454-1 assume !(1 == ~E_11~0); 18752#L1459-1 assume !(1 == ~E_12~0); 19286#L1464-1 assume { :end_inline_reset_delta_events } true; 18507#L1810-2 [2024-11-09 16:08:54,543 INFO L747 eck$LassoCheckResult]: Loop: 18507#L1810-2 assume !false; 18957#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19055#L1176-1 assume !false; 19437#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19001#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18191#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19491#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19662#L1003 assume !(0 != eval_~tmp~0#1); 18964#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18696#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18697#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19381#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19382#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19284#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18450#L1216-3 assume !(0 == ~T4_E~0); 18451#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18929#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18529#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18530#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18781#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19770#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19670#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19369#L1256-3 assume !(0 == ~T12_E~0); 18470#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18471#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18521#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18522#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18905#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18906#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19424#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19425#L1296-3 assume !(0 == ~E_7~0); 19842#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19800#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19009#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18390#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18391#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 18472#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19123#L593-42 assume 1 == ~m_pc~0; 19510#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19288#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18804#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18805#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18284#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18285#L612-42 assume !(1 == ~t1_pc~0); 19243#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 19624#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19851#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18377#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18378#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19086#L631-42 assume 1 == ~t2_pc~0; 18137#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18138#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19071#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18955#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18956#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18548#L650-42 assume 1 == ~t3_pc~0; 18102#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18103#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19457#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18743#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18744#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19741#L669-42 assume !(1 == ~t4_pc~0); 18100#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 18101#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19526#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19435#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19339#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19340#L688-42 assume 1 == ~t5_pc~0; 19422#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19627#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19135#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18312#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18313#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18130#L707-42 assume !(1 == ~t6_pc~0); 18131#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 19806#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18464#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18465#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 19310#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19311#L726-42 assume 1 == ~t7_pc~0; 19577#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19608#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19162#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19013#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19014#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19127#L745-42 assume 1 == ~t8_pc~0; 19165#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19167#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19330#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18118#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18119#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18864#L764-42 assume 1 == ~t9_pc~0; 18992#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19353#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19354#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18402#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18403#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18463#L783-42 assume 1 == ~t10_pc~0; 18074#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18075#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18679#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19322#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19833#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19516#L802-42 assume 1 == ~t11_pc~0; 18610#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18216#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18217#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18163#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18164#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19361#L821-42 assume 1 == ~t12_pc~0; 19362#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18720#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19120#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19121#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 19057#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19047#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19048#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19220#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19326#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18729#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18730#L1359-3 assume !(1 == ~T5_E~0); 19336#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19827#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19737#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18550#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18551#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18727#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18728#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18943#L1399-3 assume !(1 == ~E_M~0); 19746#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19714#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19715#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19769#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19519#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18424#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18425#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19335#L1439-3 assume !(1 == ~E_8~0); 18353#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18354#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18475#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19331#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19332#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18974#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18256#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 18456#L1829 assume !(0 == start_simulation_~tmp~3#1); 18238#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18239#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 19053#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18143#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 18144#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19347#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19720#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18506#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18507#L1810-2 [2024-11-09 16:08:54,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:54,544 INFO L85 PathProgramCache]: Analyzing trace with hash -719263762, now seen corresponding path program 1 times [2024-11-09 16:08:54,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:54,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034486807] [2024-11-09 16:08:54,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:54,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:54,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:54,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:54,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:54,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034486807] [2024-11-09 16:08:54,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2034486807] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:54,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:54,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:54,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752645265] [2024-11-09 16:08:54,607 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:54,607 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:54,607 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:54,608 INFO L85 PathProgramCache]: Analyzing trace with hash -918804904, now seen corresponding path program 2 times [2024-11-09 16:08:54,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:54,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004788009] [2024-11-09 16:08:54,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:54,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:54,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:54,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:54,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:54,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004788009] [2024-11-09 16:08:54,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1004788009] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:54,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:54,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:54,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414814614] [2024-11-09 16:08:54,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:54,675 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:54,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:54,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:54,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:54,676 INFO L87 Difference]: Start difference. First operand 1801 states and 2660 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:54,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:54,705 INFO L93 Difference]: Finished difference Result 1801 states and 2659 transitions. [2024-11-09 16:08:54,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2659 transitions. [2024-11-09 16:08:54,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:54,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2659 transitions. [2024-11-09 16:08:54,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:54,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:54,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2659 transitions. [2024-11-09 16:08:54,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:54,733 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2024-11-09 16:08:54,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2659 transitions. [2024-11-09 16:08:54,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:54,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4764019988895059) internal successors, (2659), 1800 states have internal predecessors, (2659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:54,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2659 transitions. [2024-11-09 16:08:54,772 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2024-11-09 16:08:54,772 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:54,773 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2659 transitions. [2024-11-09 16:08:54,773 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-09 16:08:54,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2659 transitions. [2024-11-09 16:08:54,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:54,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:54,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:54,807 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:54,807 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:54,807 INFO L745 eck$LassoCheckResult]: Stem: 21960#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 21961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22805#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22806#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23392#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 23393#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22487#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22275#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21672#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21673#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22917#L873-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23017#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23454#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23455#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22411#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22412#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22943#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22868#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22448#L1201 assume !(0 == ~M_E~0); 22449#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23301#L1206-1 assume !(0 == ~T2_E~0); 23284#L1211-1 assume !(0 == ~T3_E~0); 23285#L1216-1 assume !(0 == ~T4_E~0); 22257#L1221-1 assume !(0 == ~T5_E~0); 22258#L1226-1 assume !(0 == ~T6_E~0); 21886#L1231-1 assume !(0 == ~T7_E~0); 21887#L1236-1 assume !(0 == ~T8_E~0); 23325#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22299#L1246-1 assume !(0 == ~T10_E~0); 22300#L1251-1 assume !(0 == ~T11_E~0); 22446#L1256-1 assume !(0 == ~T12_E~0); 21681#L1261-1 assume !(0 == ~E_M~0); 21682#L1266-1 assume !(0 == ~E_1~0); 23439#L1271-1 assume !(0 == ~E_2~0); 23000#L1276-1 assume !(0 == ~E_3~0); 23001#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 22955#L1286-1 assume !(0 == ~E_5~0); 22152#L1291-1 assume !(0 == ~E_6~0); 22153#L1296-1 assume !(0 == ~E_7~0); 22741#L1301-1 assume !(0 == ~E_8~0); 22742#L1306-1 assume !(0 == ~E_9~0); 23220#L1311-1 assume !(0 == ~E_10~0); 22103#L1316-1 assume !(0 == ~E_11~0); 22104#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 22760#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22761#L593 assume 1 == ~m_pc~0; 22910#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21985#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22649#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22650#L1492 assume !(0 != activate_threads_~tmp~1#1); 22965#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23253#L612 assume !(1 == ~t1_pc~0); 23254#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23388#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23098#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21988#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21989#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22427#L631 assume 1 == ~t2_pc~0; 22354#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21762#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22117#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 22613#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22066#L650 assume !(1 == ~t3_pc~0); 22067#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22783#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21719#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 21720#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22936#L669 assume 1 == ~t4_pc~0; 22937#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23293#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21806#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21807#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 21923#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22162#L688 assume !(1 == ~t5_pc~0); 21942#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21943#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23420#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22825#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 22826#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22953#L707 assume 1 == ~t6_pc~0; 23359#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22582#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22105#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22106#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 22898#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22447#L726 assume 1 == ~t7_pc~0; 22344#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22029#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23090#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23363#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 21792#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21793#L745 assume !(1 == ~t8_pc~0); 22249#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22269#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23307#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22658#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22659#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23177#L764 assume 1 == ~t9_pc~0; 22445#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22279#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22178#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22179#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 21818#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21819#L783 assume !(1 == ~t10_pc~0); 21873#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 21874#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22406#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 22407#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23294#L802 assume 1 == ~t11_pc~0; 23276#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21759#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21760#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22259#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 22260#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22376#L821 assume !(1 == ~t12_pc~0); 22627#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22733#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21768#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21769#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 23336#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22973#L1339 assume !(1 == ~M_E~0); 22974#L1339-2 assume !(1 == ~T1_E~0); 23366#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23367#L1349-1 assume !(1 == ~T3_E~0); 22754#L1354-1 assume !(1 == ~T4_E~0); 22755#L1359-1 assume !(1 == ~T5_E~0); 23155#L1364-1 assume !(1 == ~T6_E~0); 22210#L1369-1 assume !(1 == ~T7_E~0); 22211#L1374-1 assume !(1 == ~T8_E~0); 22756#L1379-1 assume !(1 == ~T9_E~0); 22757#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22865#L1389-1 assume !(1 == ~T11_E~0); 23330#L1394-1 assume !(1 == ~T12_E~0); 23331#L1399-1 assume !(1 == ~E_M~0); 23412#L1404-1 assume !(1 == ~E_1~0); 22303#L1409-1 assume !(1 == ~E_2~0); 22304#L1414-1 assume !(1 == ~E_3~0); 23036#L1419-1 assume !(1 == ~E_4~0); 21932#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 21933#L1429-1 assume !(1 == ~E_6~0); 22768#L1434-1 assume !(1 == ~E_7~0); 23348#L1439-1 assume !(1 == ~E_8~0); 21974#L1444-1 assume !(1 == ~E_9~0); 21975#L1449-1 assume !(1 == ~E_10~0); 22362#L1454-1 assume !(1 == ~E_11~0); 22363#L1459-1 assume !(1 == ~E_12~0); 22895#L1464-1 assume { :end_inline_reset_delta_events } true; 22116#L1810-2 [2024-11-09 16:08:54,808 INFO L747 eck$LassoCheckResult]: Loop: 22116#L1810-2 assume !false; 22566#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22664#L1176-1 assume !false; 23046#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22612#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21800#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 23100#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23273#L1003 assume !(0 != eval_~tmp~0#1); 22573#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22305#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22306#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22990#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22991#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22893#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22059#L1216-3 assume !(0 == ~T4_E~0); 22060#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22538#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22140#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22141#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22391#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23379#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23279#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22978#L1256-3 assume !(0 == ~T12_E~0); 22079#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22080#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22130#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22131#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22514#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22515#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23034#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23035#L1296-3 assume !(0 == ~E_7~0); 23451#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23409#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22618#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21999#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22000#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 22081#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22732#L593-42 assume !(1 == ~m_pc~0); 22896#L593-44 is_master_triggered_~__retres1~0#1 := 0; 22897#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22413#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22414#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21890#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21891#L612-42 assume !(1 == ~t1_pc~0); 22850#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 23232#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23460#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21986#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21987#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22694#L631-42 assume 1 == ~t2_pc~0; 21746#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21747#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22680#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22564#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22565#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22157#L650-42 assume !(1 == ~t3_pc~0); 21713#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 21712#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23066#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22352#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22353#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23350#L669-42 assume 1 == ~t4_pc~0; 22632#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21708#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23135#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23044#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22948#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22949#L688-42 assume 1 == ~t5_pc~0; 23031#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23236#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22744#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21918#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21919#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21739#L707-42 assume !(1 == ~t6_pc~0); 21740#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 23415#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22073#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22074#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 22919#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22920#L726-42 assume 1 == ~t7_pc~0; 23186#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23217#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22771#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22622#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22623#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22736#L745-42 assume 1 == ~t8_pc~0; 22773#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22775#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22939#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21727#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21728#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22471#L764-42 assume 1 == ~t9_pc~0; 22601#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22962#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22963#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22011#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22012#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22072#L783-42 assume 1 == ~t10_pc~0; 21683#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21684#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22288#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22931#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23442#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23125#L802-42 assume 1 == ~t11_pc~0; 22219#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21825#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21826#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21772#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21773#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22970#L821-42 assume !(1 == ~t12_pc~0); 22328#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 22329#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22729#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22730#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22666#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22656#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22657#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22829#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22935#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22338#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22339#L1359-3 assume !(1 == ~T5_E~0); 22945#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23436#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23346#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22158#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22159#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22336#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22337#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22552#L1399-3 assume !(1 == ~E_M~0); 23355#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23323#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23324#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23378#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23128#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22033#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22034#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22944#L1439-3 assume !(1 == ~E_8~0); 21962#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21963#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22084#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 22940#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 22941#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22583#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21865#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22064#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22065#L1829 assume !(0 == start_simulation_~tmp~3#1); 21847#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21848#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22662#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 21753#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22956#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23329#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 22115#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 22116#L1810-2 [2024-11-09 16:08:54,808 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:54,808 INFO L85 PathProgramCache]: Analyzing trace with hash -563283220, now seen corresponding path program 1 times [2024-11-09 16:08:54,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:54,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944705228] [2024-11-09 16:08:54,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:54,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:54,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:54,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:54,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:54,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944705228] [2024-11-09 16:08:54,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944705228] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:54,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:54,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:54,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190440407] [2024-11-09 16:08:54,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:54,868 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:54,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:54,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1307554790, now seen corresponding path program 1 times [2024-11-09 16:08:54,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:54,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028644331] [2024-11-09 16:08:54,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:54,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:54,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:54,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:54,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:54,953 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028644331] [2024-11-09 16:08:54,954 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028644331] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:54,954 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:54,954 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:54,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106082367] [2024-11-09 16:08:54,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:54,955 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:54,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:54,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:54,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:54,956 INFO L87 Difference]: Start difference. First operand 1801 states and 2659 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:54,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:54,988 INFO L93 Difference]: Finished difference Result 1801 states and 2658 transitions. [2024-11-09 16:08:54,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2658 transitions. [2024-11-09 16:08:54,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2658 transitions. [2024-11-09 16:08:55,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:55,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:55,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2658 transitions. [2024-11-09 16:08:55,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:55,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2024-11-09 16:08:55,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2658 transitions. [2024-11-09 16:08:55,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:55,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.475846751804553) internal successors, (2658), 1800 states have internal predecessors, (2658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2658 transitions. [2024-11-09 16:08:55,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2024-11-09 16:08:55,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:55,048 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2658 transitions. [2024-11-09 16:08:55,049 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-09 16:08:55,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2658 transitions. [2024-11-09 16:08:55,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:55,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:55,058 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,058 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,059 INFO L745 eck$LassoCheckResult]: Stem: 25569#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 25570#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26414#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26415#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27001#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 27002#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26096#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25884#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25281#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25282#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26526#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26626#L878-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27063#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27064#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26020#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26021#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26552#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26477#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26057#L1201 assume !(0 == ~M_E~0); 26058#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26910#L1206-1 assume !(0 == ~T2_E~0); 26893#L1211-1 assume !(0 == ~T3_E~0); 26894#L1216-1 assume !(0 == ~T4_E~0); 25866#L1221-1 assume !(0 == ~T5_E~0); 25867#L1226-1 assume !(0 == ~T6_E~0); 25495#L1231-1 assume !(0 == ~T7_E~0); 25496#L1236-1 assume !(0 == ~T8_E~0); 26934#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25905#L1246-1 assume !(0 == ~T10_E~0); 25906#L1251-1 assume !(0 == ~T11_E~0); 26055#L1256-1 assume !(0 == ~T12_E~0); 25290#L1261-1 assume !(0 == ~E_M~0); 25291#L1266-1 assume !(0 == ~E_1~0); 27048#L1271-1 assume !(0 == ~E_2~0); 26609#L1276-1 assume !(0 == ~E_3~0); 26610#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 26564#L1286-1 assume !(0 == ~E_5~0); 25761#L1291-1 assume !(0 == ~E_6~0); 25762#L1296-1 assume !(0 == ~E_7~0); 26350#L1301-1 assume !(0 == ~E_8~0); 26351#L1306-1 assume !(0 == ~E_9~0); 26829#L1311-1 assume !(0 == ~E_10~0); 25712#L1316-1 assume !(0 == ~E_11~0); 25713#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 26369#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26370#L593 assume 1 == ~m_pc~0; 26519#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25594#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26258#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26259#L1492 assume !(0 != activate_threads_~tmp~1#1); 26574#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26862#L612 assume !(1 == ~t1_pc~0); 26863#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26997#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26707#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25597#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25598#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26036#L631 assume 1 == ~t2_pc~0; 25963#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25371#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25726#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 26222#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25675#L650 assume !(1 == ~t3_pc~0); 25676#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26392#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26686#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25328#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 25329#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26545#L669 assume 1 == ~t4_pc~0; 26546#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26902#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25415#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25416#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 25532#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25771#L688 assume !(1 == ~t5_pc~0); 25551#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25552#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27029#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26434#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 26435#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26562#L707 assume 1 == ~t6_pc~0; 26968#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26191#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25714#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25715#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 26505#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26056#L726 assume 1 == ~t7_pc~0; 25953#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25638#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26699#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26972#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 25401#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25402#L745 assume !(1 == ~t8_pc~0); 25858#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25878#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26916#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26267#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26268#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26786#L764 assume 1 == ~t9_pc~0; 26054#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25888#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25787#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25788#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 25427#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25428#L783 assume !(1 == ~t10_pc~0); 25482#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25483#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25680#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26015#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 26016#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26903#L802 assume 1 == ~t11_pc~0; 26885#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25368#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25369#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25868#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 25869#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25985#L821 assume !(1 == ~t12_pc~0); 26236#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26342#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25377#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25378#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 26945#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26582#L1339 assume !(1 == ~M_E~0); 26583#L1339-2 assume !(1 == ~T1_E~0); 26975#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26976#L1349-1 assume !(1 == ~T3_E~0); 26363#L1354-1 assume !(1 == ~T4_E~0); 26364#L1359-1 assume !(1 == ~T5_E~0); 26762#L1364-1 assume !(1 == ~T6_E~0); 25819#L1369-1 assume !(1 == ~T7_E~0); 25820#L1374-1 assume !(1 == ~T8_E~0); 26365#L1379-1 assume !(1 == ~T9_E~0); 26366#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26474#L1389-1 assume !(1 == ~T11_E~0); 26939#L1394-1 assume !(1 == ~T12_E~0); 26940#L1399-1 assume !(1 == ~E_M~0); 27021#L1404-1 assume !(1 == ~E_1~0); 25912#L1409-1 assume !(1 == ~E_2~0); 25913#L1414-1 assume !(1 == ~E_3~0); 26645#L1419-1 assume !(1 == ~E_4~0); 25541#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 25542#L1429-1 assume !(1 == ~E_6~0); 26377#L1434-1 assume !(1 == ~E_7~0); 26957#L1439-1 assume !(1 == ~E_8~0); 25583#L1444-1 assume !(1 == ~E_9~0); 25584#L1449-1 assume !(1 == ~E_10~0); 25971#L1454-1 assume !(1 == ~E_11~0); 25972#L1459-1 assume !(1 == ~E_12~0); 26504#L1464-1 assume { :end_inline_reset_delta_events } true; 25725#L1810-2 [2024-11-09 16:08:55,059 INFO L747 eck$LassoCheckResult]: Loop: 25725#L1810-2 assume !false; 26175#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26273#L1176-1 assume !false; 26655#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26220#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25409#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26709#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26882#L1003 assume !(0 != eval_~tmp~0#1); 26182#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25914#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25915#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26599#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26600#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26502#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25668#L1216-3 assume !(0 == ~T4_E~0); 25669#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26147#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25747#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25748#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26000#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26988#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26888#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26587#L1256-3 assume !(0 == ~T12_E~0); 25688#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25689#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25739#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25740#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26123#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26124#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26643#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26644#L1296-3 assume !(0 == ~E_7~0); 27060#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27018#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26227#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25608#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25609#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25690#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26341#L593-42 assume 1 == ~m_pc~0; 26729#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26507#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26024#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26025#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25505#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25506#L612-42 assume !(1 == ~t1_pc~0); 26461#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 26843#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27069#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25595#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25596#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26304#L631-42 assume !(1 == ~t2_pc~0); 25360#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 25359#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26289#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26173#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26174#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25766#L650-42 assume 1 == ~t3_pc~0; 25323#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25324#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26675#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25961#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25962#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26959#L669-42 assume 1 == ~t4_pc~0; 26244#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25319#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26744#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26653#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26557#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26558#L688-42 assume 1 == ~t5_pc~0; 26640#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26845#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26352#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25527#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25528#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25341#L707-42 assume !(1 == ~t6_pc~0); 25342#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 27024#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25682#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25683#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 26528#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26529#L726-42 assume 1 == ~t7_pc~0; 26792#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26826#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26380#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26231#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26232#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26345#L745-42 assume 1 == ~t8_pc~0; 26382#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26384#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26548#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25336#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25337#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26080#L764-42 assume 1 == ~t9_pc~0; 26210#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26571#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26572#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25620#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25621#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25681#L783-42 assume 1 == ~t10_pc~0; 25292#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25293#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25895#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26540#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27051#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26734#L802-42 assume 1 == ~t11_pc~0; 25828#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25434#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25435#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25381#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25382#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26579#L821-42 assume !(1 == ~t12_pc~0); 25937#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 25938#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26338#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26339#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26275#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26262#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26263#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26438#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26544#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25947#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25948#L1359-3 assume !(1 == ~T5_E~0); 26554#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27045#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26955#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25767#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25768#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25945#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25946#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26161#L1399-3 assume !(1 == ~E_M~0); 26964#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26932#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26933#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26987#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26737#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25642#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25643#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26553#L1439-3 assume !(1 == ~E_8~0); 25571#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25572#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25693#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26549#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 26550#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26192#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 25474#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25673#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 25674#L1829 assume !(0 == start_simulation_~tmp~3#1); 25456#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25457#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26271#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 25362#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26565#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26938#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25724#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 25725#L1810-2 [2024-11-09 16:08:55,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:55,060 INFO L85 PathProgramCache]: Analyzing trace with hash -973893586, now seen corresponding path program 1 times [2024-11-09 16:08:55,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:55,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894108584] [2024-11-09 16:08:55,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:55,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:55,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:55,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:55,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:55,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894108584] [2024-11-09 16:08:55,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894108584] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:55,112 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:55,112 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:55,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265685718] [2024-11-09 16:08:55,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:55,113 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:55,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:55,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1672959641, now seen corresponding path program 1 times [2024-11-09 16:08:55,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:55,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980343164] [2024-11-09 16:08:55,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:55,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:55,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:55,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:55,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:55,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980343164] [2024-11-09 16:08:55,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1980343164] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:55,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:55,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:55,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748211647] [2024-11-09 16:08:55,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:55,177 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:55,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:55,178 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:55,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:55,178 INFO L87 Difference]: Start difference. First operand 1801 states and 2658 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:55,210 INFO L93 Difference]: Finished difference Result 1801 states and 2657 transitions. [2024-11-09 16:08:55,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2657 transitions. [2024-11-09 16:08:55,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2657 transitions. [2024-11-09 16:08:55,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:55,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:55,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2657 transitions. [2024-11-09 16:08:55,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:55,235 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2024-11-09 16:08:55,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2657 transitions. [2024-11-09 16:08:55,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:55,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4752915047196002) internal successors, (2657), 1800 states have internal predecessors, (2657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2657 transitions. [2024-11-09 16:08:55,273 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2024-11-09 16:08:55,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:55,276 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2657 transitions. [2024-11-09 16:08:55,276 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-09 16:08:55,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2657 transitions. [2024-11-09 16:08:55,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:55,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:55,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,287 INFO L745 eck$LassoCheckResult]: Stem: 29178#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 29179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 30023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30610#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 30611#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29704#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29493#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28890#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28891#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30135#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30234#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30672#L883-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30673#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29629#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29630#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30161#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30086#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29666#L1201 assume !(0 == ~M_E~0); 29667#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30519#L1206-1 assume !(0 == ~T2_E~0); 30502#L1211-1 assume !(0 == ~T3_E~0); 30503#L1216-1 assume !(0 == ~T4_E~0); 29474#L1221-1 assume !(0 == ~T5_E~0); 29475#L1226-1 assume !(0 == ~T6_E~0); 29104#L1231-1 assume !(0 == ~T7_E~0); 29105#L1236-1 assume !(0 == ~T8_E~0); 30543#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29514#L1246-1 assume !(0 == ~T10_E~0); 29515#L1251-1 assume !(0 == ~T11_E~0); 29664#L1256-1 assume !(0 == ~T12_E~0); 28899#L1261-1 assume !(0 == ~E_M~0); 28900#L1266-1 assume !(0 == ~E_1~0); 30657#L1271-1 assume !(0 == ~E_2~0); 30218#L1276-1 assume !(0 == ~E_3~0); 30219#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 30173#L1286-1 assume !(0 == ~E_5~0); 29370#L1291-1 assume !(0 == ~E_6~0); 29371#L1296-1 assume !(0 == ~E_7~0); 29959#L1301-1 assume !(0 == ~E_8~0); 29960#L1306-1 assume !(0 == ~E_9~0); 30438#L1311-1 assume !(0 == ~E_10~0); 29321#L1316-1 assume !(0 == ~E_11~0); 29322#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 29978#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29979#L593 assume 1 == ~m_pc~0; 30128#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29203#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29867#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29868#L1492 assume !(0 != activate_threads_~tmp~1#1); 30183#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30471#L612 assume !(1 == ~t1_pc~0); 30472#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30606#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30316#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29206#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29207#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29645#L631 assume 1 == ~t2_pc~0; 29572#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28980#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28981#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29335#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 29831#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29284#L650 assume !(1 == ~t3_pc~0); 29285#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30001#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30295#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28937#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 28938#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30154#L669 assume 1 == ~t4_pc~0; 30155#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30510#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29022#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29023#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 29141#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29380#L688 assume !(1 == ~t5_pc~0); 29160#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29161#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30638#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30043#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 30044#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30168#L707 assume 1 == ~t6_pc~0; 30577#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29800#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29323#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29324#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 30114#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29665#L726 assume 1 == ~t7_pc~0; 29560#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29247#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30307#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30581#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 29010#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29011#L745 assume !(1 == ~t8_pc~0); 29467#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 29487#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30525#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29876#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29877#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30395#L764 assume 1 == ~t9_pc~0; 29663#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29497#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29396#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29397#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 29036#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29037#L783 assume !(1 == ~t10_pc~0); 29091#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29092#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29289#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29619#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 29620#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30512#L802 assume 1 == ~t11_pc~0; 30494#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28977#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28978#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29476#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 29477#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29594#L821 assume !(1 == ~t12_pc~0); 29845#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29951#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28986#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28987#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 30554#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30191#L1339 assume !(1 == ~M_E~0); 30192#L1339-2 assume !(1 == ~T1_E~0); 30584#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30585#L1349-1 assume !(1 == ~T3_E~0); 29971#L1354-1 assume !(1 == ~T4_E~0); 29972#L1359-1 assume !(1 == ~T5_E~0); 30371#L1364-1 assume !(1 == ~T6_E~0); 29428#L1369-1 assume !(1 == ~T7_E~0); 29429#L1374-1 assume !(1 == ~T8_E~0); 29974#L1379-1 assume !(1 == ~T9_E~0); 29975#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30083#L1389-1 assume !(1 == ~T11_E~0); 30548#L1394-1 assume !(1 == ~T12_E~0); 30549#L1399-1 assume !(1 == ~E_M~0); 30630#L1404-1 assume !(1 == ~E_1~0); 29521#L1409-1 assume !(1 == ~E_2~0); 29522#L1414-1 assume !(1 == ~E_3~0); 30254#L1419-1 assume !(1 == ~E_4~0); 29150#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 29151#L1429-1 assume !(1 == ~E_6~0); 29986#L1434-1 assume !(1 == ~E_7~0); 30566#L1439-1 assume !(1 == ~E_8~0); 29192#L1444-1 assume !(1 == ~E_9~0); 29193#L1449-1 assume !(1 == ~E_10~0); 29578#L1454-1 assume !(1 == ~E_11~0); 29579#L1459-1 assume !(1 == ~E_12~0); 30113#L1464-1 assume { :end_inline_reset_delta_events } true; 29334#L1810-2 [2024-11-09 16:08:55,288 INFO L747 eck$LassoCheckResult]: Loop: 29334#L1810-2 assume !false; 29784#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29882#L1176-1 assume !false; 30264#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29828#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29018#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30318#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30489#L1003 assume !(0 != eval_~tmp~0#1); 29791#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29523#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29524#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30208#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30209#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30111#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29277#L1216-3 assume !(0 == ~T4_E~0); 29278#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29756#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29356#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29357#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29609#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30597#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30497#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30196#L1256-3 assume !(0 == ~T12_E~0); 29297#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29298#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29348#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29349#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29732#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29733#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30252#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30253#L1296-3 assume !(0 == ~E_7~0); 30669#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30627#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29836#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29217#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 29218#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29299#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29950#L593-42 assume 1 == ~m_pc~0; 30338#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30116#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29631#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29632#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29111#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29112#L612-42 assume !(1 == ~t1_pc~0); 30070#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 30451#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30678#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29204#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29205#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29913#L631-42 assume 1 == ~t2_pc~0; 28967#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28968#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29898#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29782#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29783#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29375#L650-42 assume 1 == ~t3_pc~0; 28932#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28933#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30284#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29570#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29571#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30568#L669-42 assume 1 == ~t4_pc~0; 29853#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28928#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30353#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30262#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30166#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30167#L688-42 assume 1 == ~t5_pc~0; 30249#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30454#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29962#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29139#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29140#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28957#L707-42 assume !(1 == ~t6_pc~0); 28958#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 30635#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29291#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29292#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 30137#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30138#L726-42 assume 1 == ~t7_pc~0; 30404#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30435#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29989#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29840#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29841#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29954#L745-42 assume 1 == ~t8_pc~0; 29995#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29997#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30157#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28945#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28946#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29691#L764-42 assume 1 == ~t9_pc~0; 29819#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30180#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30181#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29229#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29230#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29290#L783-42 assume 1 == ~t10_pc~0; 28901#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28902#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29504#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30149#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30660#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30343#L802-42 assume 1 == ~t11_pc~0; 29437#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29043#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29044#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28990#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28991#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30188#L821-42 assume !(1 == ~t12_pc~0); 29546#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 29547#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29947#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29948#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29884#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29871#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29872#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30047#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30153#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29556#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29557#L1359-3 assume !(1 == ~T5_E~0); 30163#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30654#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30564#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29376#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29377#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29554#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29555#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29770#L1399-3 assume !(1 == ~E_M~0); 30573#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30541#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30542#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30596#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30346#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29251#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29252#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 30162#L1439-3 assume !(1 == ~E_8~0); 29180#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29181#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29302#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 30158#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 30159#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29801#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29083#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 29282#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29283#L1829 assume !(0 == start_simulation_~tmp~3#1); 29065#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 29066#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29880#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28970#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 28971#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30174#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30547#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29333#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 29334#L1810-2 [2024-11-09 16:08:55,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:55,288 INFO L85 PathProgramCache]: Analyzing trace with hash 813976236, now seen corresponding path program 1 times [2024-11-09 16:08:55,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:55,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196096683] [2024-11-09 16:08:55,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:55,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:55,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:55,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:55,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:55,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196096683] [2024-11-09 16:08:55,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196096683] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:55,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:55,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:55,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996863703] [2024-11-09 16:08:55,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:55,332 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:55,332 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:55,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1385499736, now seen corresponding path program 2 times [2024-11-09 16:08:55,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:55,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776281278] [2024-11-09 16:08:55,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:55,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:55,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:55,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:55,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:55,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776281278] [2024-11-09 16:08:55,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776281278] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:55,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:55,442 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:55,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896470255] [2024-11-09 16:08:55,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:55,442 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:55,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:55,443 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:55,443 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:55,443 INFO L87 Difference]: Start difference. First operand 1801 states and 2657 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:55,471 INFO L93 Difference]: Finished difference Result 1801 states and 2656 transitions. [2024-11-09 16:08:55,472 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2656 transitions. [2024-11-09 16:08:55,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2656 transitions. [2024-11-09 16:08:55,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:55,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:55,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2656 transitions. [2024-11-09 16:08:55,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:55,491 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2024-11-09 16:08:55,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2656 transitions. [2024-11-09 16:08:55,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:55,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4747362576346474) internal successors, (2656), 1800 states have internal predecessors, (2656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2656 transitions. [2024-11-09 16:08:55,519 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2024-11-09 16:08:55,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:55,520 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2656 transitions. [2024-11-09 16:08:55,520 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-09 16:08:55,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2656 transitions. [2024-11-09 16:08:55,526 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:55,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:55,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,528 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,529 INFO L745 eck$LassoCheckResult]: Stem: 32787#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 32788#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33633#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34219#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 34220#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33313#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33102#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32499#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32500#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33744#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33843#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34281#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34282#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33238#L893-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33239#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33770#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33695#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33275#L1201 assume !(0 == ~M_E~0); 33276#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34128#L1206-1 assume !(0 == ~T2_E~0); 34111#L1211-1 assume !(0 == ~T3_E~0); 34112#L1216-1 assume !(0 == ~T4_E~0); 33083#L1221-1 assume !(0 == ~T5_E~0); 33084#L1226-1 assume !(0 == ~T6_E~0); 32713#L1231-1 assume !(0 == ~T7_E~0); 32714#L1236-1 assume !(0 == ~T8_E~0); 34152#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33123#L1246-1 assume !(0 == ~T10_E~0); 33124#L1251-1 assume !(0 == ~T11_E~0); 33273#L1256-1 assume !(0 == ~T12_E~0); 32508#L1261-1 assume !(0 == ~E_M~0); 32509#L1266-1 assume !(0 == ~E_1~0); 34266#L1271-1 assume !(0 == ~E_2~0); 33827#L1276-1 assume !(0 == ~E_3~0); 33828#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 33782#L1286-1 assume !(0 == ~E_5~0); 32979#L1291-1 assume !(0 == ~E_6~0); 32980#L1296-1 assume !(0 == ~E_7~0); 33568#L1301-1 assume !(0 == ~E_8~0); 33569#L1306-1 assume !(0 == ~E_9~0); 34047#L1311-1 assume !(0 == ~E_10~0); 32930#L1316-1 assume !(0 == ~E_11~0); 32931#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 33587#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33588#L593 assume 1 == ~m_pc~0; 33737#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32812#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33476#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33477#L1492 assume !(0 != activate_threads_~tmp~1#1); 33792#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34080#L612 assume !(1 == ~t1_pc~0); 34081#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34215#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33925#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32815#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32816#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33254#L631 assume 1 == ~t2_pc~0; 33181#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32589#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32590#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32944#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 33440#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32891#L650 assume !(1 == ~t3_pc~0); 32892#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33610#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33904#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32546#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 32547#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33763#L669 assume 1 == ~t4_pc~0; 33764#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34119#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32629#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32630#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 32750#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32989#L688 assume !(1 == ~t5_pc~0); 32769#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32770#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34247#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33652#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 33653#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33777#L707 assume 1 == ~t6_pc~0; 34186#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33409#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32932#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32933#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 33723#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33274#L726 assume 1 == ~t7_pc~0; 33169#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32856#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33916#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34190#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 32619#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32620#L745 assume !(1 == ~t8_pc~0); 33076#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 33096#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34134#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33485#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33486#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34004#L764 assume 1 == ~t9_pc~0; 33272#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33106#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33005#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33006#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 32645#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32646#L783 assume !(1 == ~t10_pc~0); 32700#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32701#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32898#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33228#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 33229#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34121#L802 assume 1 == ~t11_pc~0; 34103#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32586#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32587#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33085#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 33086#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33203#L821 assume !(1 == ~t12_pc~0); 33454#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33560#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32593#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32594#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 34163#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33800#L1339 assume !(1 == ~M_E~0); 33801#L1339-2 assume !(1 == ~T1_E~0); 34193#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34194#L1349-1 assume !(1 == ~T3_E~0); 33580#L1354-1 assume !(1 == ~T4_E~0); 33581#L1359-1 assume !(1 == ~T5_E~0); 33980#L1364-1 assume !(1 == ~T6_E~0); 33037#L1369-1 assume !(1 == ~T7_E~0); 33038#L1374-1 assume !(1 == ~T8_E~0); 33583#L1379-1 assume !(1 == ~T9_E~0); 33584#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33692#L1389-1 assume !(1 == ~T11_E~0); 34157#L1394-1 assume !(1 == ~T12_E~0); 34158#L1399-1 assume !(1 == ~E_M~0); 34239#L1404-1 assume !(1 == ~E_1~0); 33130#L1409-1 assume !(1 == ~E_2~0); 33131#L1414-1 assume !(1 == ~E_3~0); 33863#L1419-1 assume !(1 == ~E_4~0); 32759#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 32760#L1429-1 assume !(1 == ~E_6~0); 33595#L1434-1 assume !(1 == ~E_7~0); 34175#L1439-1 assume !(1 == ~E_8~0); 32801#L1444-1 assume !(1 == ~E_9~0); 32802#L1449-1 assume !(1 == ~E_10~0); 33187#L1454-1 assume !(1 == ~E_11~0); 33188#L1459-1 assume !(1 == ~E_12~0); 33722#L1464-1 assume { :end_inline_reset_delta_events } true; 32943#L1810-2 [2024-11-09 16:08:55,529 INFO L747 eck$LassoCheckResult]: Loop: 32943#L1810-2 assume !false; 33393#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33491#L1176-1 assume !false; 33873#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33437#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32627#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33927#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34098#L1003 assume !(0 != eval_~tmp~0#1); 33400#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33132#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33133#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33817#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33818#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33720#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32886#L1216-3 assume !(0 == ~T4_E~0); 32887#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33365#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32965#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32966#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33217#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34206#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34106#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33805#L1256-3 assume !(0 == ~T12_E~0); 32906#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32907#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32957#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32958#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33341#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33342#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33860#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33861#L1296-3 assume !(0 == ~E_7~0); 34278#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34236#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33445#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32826#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32827#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32908#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33559#L593-42 assume 1 == ~m_pc~0; 33946#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33725#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33240#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33241#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32720#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32721#L612-42 assume 1 == ~t1_pc~0; 33680#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34060#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34287#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32813#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32814#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33522#L631-42 assume 1 == ~t2_pc~0; 32573#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32574#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33507#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33391#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33392#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32984#L650-42 assume 1 == ~t3_pc~0; 32538#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32539#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33893#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33179#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33180#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34177#L669-42 assume 1 == ~t4_pc~0; 33459#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32537#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33962#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33871#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33775#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33776#L688-42 assume 1 == ~t5_pc~0; 33858#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34063#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33571#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32748#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32749#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32566#L707-42 assume !(1 == ~t6_pc~0); 32567#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 34242#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32900#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32901#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 33746#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33747#L726-42 assume 1 == ~t7_pc~0; 34013#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34044#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33598#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33449#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33450#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33563#L745-42 assume 1 == ~t8_pc~0; 33601#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33603#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33766#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32554#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32555#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33300#L764-42 assume 1 == ~t9_pc~0; 33428#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33789#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33790#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32838#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32839#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32899#L783-42 assume !(1 == ~t10_pc~0); 32512#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 32511#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33115#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33758#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34269#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33952#L802-42 assume 1 == ~t11_pc~0; 33046#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32652#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32653#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32599#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32600#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33797#L821-42 assume !(1 == ~t12_pc~0); 33155#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 33156#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33556#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33557#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33493#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33483#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33484#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33656#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33762#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33165#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33166#L1359-3 assume !(1 == ~T5_E~0); 33772#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34263#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34173#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32986#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32987#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33163#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33164#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33379#L1399-3 assume !(1 == ~E_M~0); 34182#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34150#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34151#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34205#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33955#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32860#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32861#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33771#L1439-3 assume !(1 == ~E_8~0); 32789#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32790#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32911#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33767#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33768#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 33410#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 32692#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32894#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32895#L1829 assume !(0 == start_simulation_~tmp~3#1); 32674#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32675#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33489#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32579#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 32580#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33783#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34156#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32942#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 32943#L1810-2 [2024-11-09 16:08:55,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:55,530 INFO L85 PathProgramCache]: Analyzing trace with hash -1345107858, now seen corresponding path program 1 times [2024-11-09 16:08:55,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:55,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22580511] [2024-11-09 16:08:55,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:55,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:55,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:55,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:55,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:55,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [22580511] [2024-11-09 16:08:55,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [22580511] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:55,572 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:55,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:55,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44461840] [2024-11-09 16:08:55,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:55,573 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:55,573 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:55,573 INFO L85 PathProgramCache]: Analyzing trace with hash 900687640, now seen corresponding path program 1 times [2024-11-09 16:08:55,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:55,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505173487] [2024-11-09 16:08:55,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:55,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:55,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:55,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:55,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:55,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [505173487] [2024-11-09 16:08:55,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [505173487] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:55,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:55,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:55,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [323104895] [2024-11-09 16:08:55,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:55,633 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:55,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:55,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:55,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:55,634 INFO L87 Difference]: Start difference. First operand 1801 states and 2656 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:55,662 INFO L93 Difference]: Finished difference Result 1801 states and 2655 transitions. [2024-11-09 16:08:55,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2655 transitions. [2024-11-09 16:08:55,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,683 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2655 transitions. [2024-11-09 16:08:55,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:55,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:55,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2655 transitions. [2024-11-09 16:08:55,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:55,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2024-11-09 16:08:55,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2655 transitions. [2024-11-09 16:08:55,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:55,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4741810105496946) internal successors, (2655), 1800 states have internal predecessors, (2655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2655 transitions. [2024-11-09 16:08:55,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2024-11-09 16:08:55,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:55,719 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2655 transitions. [2024-11-09 16:08:55,720 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-09 16:08:55,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2655 transitions. [2024-11-09 16:08:55,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:55,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:55,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,729 INFO L745 eck$LassoCheckResult]: Stem: 36396#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 36397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37241#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37242#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37828#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 37829#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36922#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36711#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36108#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36109#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37353#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37452#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37890#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37891#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36847#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36848#L898-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37379#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37304#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36884#L1201 assume !(0 == ~M_E~0); 36885#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37737#L1206-1 assume !(0 == ~T2_E~0); 37720#L1211-1 assume !(0 == ~T3_E~0); 37721#L1216-1 assume !(0 == ~T4_E~0); 36692#L1221-1 assume !(0 == ~T5_E~0); 36693#L1226-1 assume !(0 == ~T6_E~0); 36322#L1231-1 assume !(0 == ~T7_E~0); 36323#L1236-1 assume !(0 == ~T8_E~0); 37761#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36732#L1246-1 assume !(0 == ~T10_E~0); 36733#L1251-1 assume !(0 == ~T11_E~0); 36882#L1256-1 assume !(0 == ~T12_E~0); 36117#L1261-1 assume !(0 == ~E_M~0); 36118#L1266-1 assume !(0 == ~E_1~0); 37875#L1271-1 assume !(0 == ~E_2~0); 37436#L1276-1 assume !(0 == ~E_3~0); 37437#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 37391#L1286-1 assume !(0 == ~E_5~0); 36588#L1291-1 assume !(0 == ~E_6~0); 36589#L1296-1 assume !(0 == ~E_7~0); 37177#L1301-1 assume !(0 == ~E_8~0); 37178#L1306-1 assume !(0 == ~E_9~0); 37656#L1311-1 assume !(0 == ~E_10~0); 36539#L1316-1 assume !(0 == ~E_11~0); 36540#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 37196#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37197#L593 assume 1 == ~m_pc~0; 37346#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 36421#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37085#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37086#L1492 assume !(0 != activate_threads_~tmp~1#1); 37401#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37689#L612 assume !(1 == ~t1_pc~0); 37690#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37824#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36424#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36425#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36863#L631 assume 1 == ~t2_pc~0; 36790#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36198#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36199#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36553#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 37049#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36500#L650 assume !(1 == ~t3_pc~0); 36501#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37219#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37513#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36155#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 36156#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37372#L669 assume 1 == ~t4_pc~0; 37373#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37728#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36238#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36239#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 36359#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36598#L688 assume !(1 == ~t5_pc~0); 36378#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36379#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37856#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37261#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 37262#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37386#L707 assume 1 == ~t6_pc~0; 37795#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37018#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36542#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 37332#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36883#L726 assume 1 == ~t7_pc~0; 36778#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36465#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37525#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37799#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 36228#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36229#L745 assume !(1 == ~t8_pc~0); 36685#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 36705#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37743#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37094#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37095#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37613#L764 assume 1 == ~t9_pc~0; 36881#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36715#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36614#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36615#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 36254#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36255#L783 assume !(1 == ~t10_pc~0); 36309#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36310#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36507#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36837#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 36838#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37730#L802 assume 1 == ~t11_pc~0; 37712#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36195#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36196#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36694#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 36695#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 36812#L821 assume !(1 == ~t12_pc~0); 37063#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37169#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36202#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36203#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 37772#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37409#L1339 assume !(1 == ~M_E~0); 37410#L1339-2 assume !(1 == ~T1_E~0); 37802#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37803#L1349-1 assume !(1 == ~T3_E~0); 37189#L1354-1 assume !(1 == ~T4_E~0); 37190#L1359-1 assume !(1 == ~T5_E~0); 37589#L1364-1 assume !(1 == ~T6_E~0); 36646#L1369-1 assume !(1 == ~T7_E~0); 36647#L1374-1 assume !(1 == ~T8_E~0); 37192#L1379-1 assume !(1 == ~T9_E~0); 37193#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37301#L1389-1 assume !(1 == ~T11_E~0); 37766#L1394-1 assume !(1 == ~T12_E~0); 37767#L1399-1 assume !(1 == ~E_M~0); 37848#L1404-1 assume !(1 == ~E_1~0); 36739#L1409-1 assume !(1 == ~E_2~0); 36740#L1414-1 assume !(1 == ~E_3~0); 37472#L1419-1 assume !(1 == ~E_4~0); 36368#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 36369#L1429-1 assume !(1 == ~E_6~0); 37204#L1434-1 assume !(1 == ~E_7~0); 37784#L1439-1 assume !(1 == ~E_8~0); 36410#L1444-1 assume !(1 == ~E_9~0); 36411#L1449-1 assume !(1 == ~E_10~0); 36796#L1454-1 assume !(1 == ~E_11~0); 36797#L1459-1 assume !(1 == ~E_12~0); 37331#L1464-1 assume { :end_inline_reset_delta_events } true; 36552#L1810-2 [2024-11-09 16:08:55,730 INFO L747 eck$LassoCheckResult]: Loop: 36552#L1810-2 assume !false; 37002#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37100#L1176-1 assume !false; 37482#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37046#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36236#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37536#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37707#L1003 assume !(0 != eval_~tmp~0#1); 37009#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36741#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36742#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37426#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37427#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37329#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36495#L1216-3 assume !(0 == ~T4_E~0); 36496#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36974#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36574#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36575#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36826#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37815#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37715#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37414#L1256-3 assume !(0 == ~T12_E~0); 36515#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36516#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36566#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36567#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36950#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36951#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37469#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37470#L1296-3 assume !(0 == ~E_7~0); 37887#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37845#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37054#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36435#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36436#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36517#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37168#L593-42 assume 1 == ~m_pc~0; 37555#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37334#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36849#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36850#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36329#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36330#L612-42 assume !(1 == ~t1_pc~0); 37288#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 37669#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37896#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36422#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36423#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37131#L631-42 assume 1 == ~t2_pc~0; 36182#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36183#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37116#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37000#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37001#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36593#L650-42 assume 1 == ~t3_pc~0; 36147#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36148#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37502#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36788#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36789#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37786#L669-42 assume !(1 == ~t4_pc~0); 36145#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 36146#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37571#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37480#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37384#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37385#L688-42 assume 1 == ~t5_pc~0; 37467#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37672#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37180#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36357#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36358#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36175#L707-42 assume !(1 == ~t6_pc~0); 36176#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 37851#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36509#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36510#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 37355#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37356#L726-42 assume 1 == ~t7_pc~0; 37622#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37653#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37207#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37058#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37059#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37172#L745-42 assume 1 == ~t8_pc~0; 37210#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37212#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37375#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36163#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36164#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36909#L764-42 assume 1 == ~t9_pc~0; 37037#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37398#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37399#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36447#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36448#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36508#L783-42 assume 1 == ~t10_pc~0; 36119#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36120#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36724#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37367#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37878#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37561#L802-42 assume !(1 == ~t11_pc~0); 36656#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 36261#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36262#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36208#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36209#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37406#L821-42 assume !(1 == ~t12_pc~0); 36764#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 36765#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37165#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37166#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37102#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37092#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37093#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37265#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37371#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36774#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36775#L1359-3 assume !(1 == ~T5_E~0); 37381#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37872#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37782#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36595#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36596#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36772#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36773#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36988#L1399-3 assume !(1 == ~E_M~0); 37791#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37759#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37760#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37814#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37564#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36469#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36470#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37380#L1439-3 assume !(1 == ~E_8~0); 36398#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36399#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 36520#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37376#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37377#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37019#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 36301#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36503#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36504#L1829 assume !(0 == start_simulation_~tmp~3#1); 36283#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 36284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37098#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 36188#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 36189#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37392#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37765#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36551#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 36552#L1810-2 [2024-11-09 16:08:55,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:55,730 INFO L85 PathProgramCache]: Analyzing trace with hash -1762996560, now seen corresponding path program 1 times [2024-11-09 16:08:55,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:55,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [323299572] [2024-11-09 16:08:55,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:55,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:55,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:55,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:55,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:55,773 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [323299572] [2024-11-09 16:08:55,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [323299572] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:55,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:55,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:55,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876609753] [2024-11-09 16:08:55,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:55,774 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:55,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:55,775 INFO L85 PathProgramCache]: Analyzing trace with hash 401843482, now seen corresponding path program 1 times [2024-11-09 16:08:55,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:55,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077345691] [2024-11-09 16:08:55,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:55,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:55,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:55,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:55,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:55,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077345691] [2024-11-09 16:08:55,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077345691] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:55,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:55,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:55,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236331967] [2024-11-09 16:08:55,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:55,850 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:55,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:55,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:55,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:55,852 INFO L87 Difference]: Start difference. First operand 1801 states and 2655 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:55,881 INFO L93 Difference]: Finished difference Result 1801 states and 2654 transitions. [2024-11-09 16:08:55,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2654 transitions. [2024-11-09 16:08:55,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2654 transitions. [2024-11-09 16:08:55,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:55,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:55,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2654 transitions. [2024-11-09 16:08:55,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:55,943 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2024-11-09 16:08:55,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2654 transitions. [2024-11-09 16:08:55,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:55,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.4736257634647418) internal successors, (2654), 1800 states have internal predecessors, (2654), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:55,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2654 transitions. [2024-11-09 16:08:55,988 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2024-11-09 16:08:55,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:55,989 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2654 transitions. [2024-11-09 16:08:55,989 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-09 16:08:55,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2654 transitions. [2024-11-09 16:08:55,996 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:55,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:55,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:55,999 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:55,999 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,000 INFO L745 eck$LassoCheckResult]: Stem: 40005#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 40006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 40850#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40851#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41437#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 41438#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40531#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40320#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39717#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39718#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40962#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41061#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41499#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41500#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40456#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 40457#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40988#L903-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40913#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40493#L1201 assume !(0 == ~M_E~0); 40494#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41346#L1206-1 assume !(0 == ~T2_E~0); 41329#L1211-1 assume !(0 == ~T3_E~0); 41330#L1216-1 assume !(0 == ~T4_E~0); 40301#L1221-1 assume !(0 == ~T5_E~0); 40302#L1226-1 assume !(0 == ~T6_E~0); 39931#L1231-1 assume !(0 == ~T7_E~0); 39932#L1236-1 assume !(0 == ~T8_E~0); 41370#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40341#L1246-1 assume !(0 == ~T10_E~0); 40342#L1251-1 assume !(0 == ~T11_E~0); 40491#L1256-1 assume !(0 == ~T12_E~0); 39726#L1261-1 assume !(0 == ~E_M~0); 39727#L1266-1 assume !(0 == ~E_1~0); 41484#L1271-1 assume !(0 == ~E_2~0); 41045#L1276-1 assume !(0 == ~E_3~0); 41046#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 41000#L1286-1 assume !(0 == ~E_5~0); 40197#L1291-1 assume !(0 == ~E_6~0); 40198#L1296-1 assume !(0 == ~E_7~0); 40786#L1301-1 assume !(0 == ~E_8~0); 40787#L1306-1 assume !(0 == ~E_9~0); 41265#L1311-1 assume !(0 == ~E_10~0); 40148#L1316-1 assume !(0 == ~E_11~0); 40149#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 40805#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40806#L593 assume 1 == ~m_pc~0; 40955#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40030#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40694#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40695#L1492 assume !(0 != activate_threads_~tmp~1#1); 41010#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41298#L612 assume !(1 == ~t1_pc~0); 41299#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 41433#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40033#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40034#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40472#L631 assume 1 == ~t2_pc~0; 40399#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39807#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39808#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40162#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 40658#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40109#L650 assume !(1 == ~t3_pc~0); 40110#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40828#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41122#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39764#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 39765#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40981#L669 assume 1 == ~t4_pc~0; 40982#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41337#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39847#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39848#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 39968#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40207#L688 assume !(1 == ~t5_pc~0); 39987#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39988#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41465#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40870#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 40871#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40995#L707 assume 1 == ~t6_pc~0; 41404#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40627#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40151#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 40941#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40492#L726 assume 1 == ~t7_pc~0; 40387#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 40074#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41134#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41408#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 39837#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39838#L745 assume !(1 == ~t8_pc~0); 40294#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 40314#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41352#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40703#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40704#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41222#L764 assume 1 == ~t9_pc~0; 40490#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40324#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40223#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40224#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 39863#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39864#L783 assume !(1 == ~t10_pc~0); 39918#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 39919#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40116#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40446#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 40447#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41339#L802 assume 1 == ~t11_pc~0; 41321#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39804#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39805#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40303#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 40304#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 40421#L821 assume !(1 == ~t12_pc~0); 40672#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 40778#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39811#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39812#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 41381#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41018#L1339 assume !(1 == ~M_E~0); 41019#L1339-2 assume !(1 == ~T1_E~0); 41411#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41412#L1349-1 assume !(1 == ~T3_E~0); 40798#L1354-1 assume !(1 == ~T4_E~0); 40799#L1359-1 assume !(1 == ~T5_E~0); 41198#L1364-1 assume !(1 == ~T6_E~0); 40255#L1369-1 assume !(1 == ~T7_E~0); 40256#L1374-1 assume !(1 == ~T8_E~0); 40801#L1379-1 assume !(1 == ~T9_E~0); 40802#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40910#L1389-1 assume !(1 == ~T11_E~0); 41375#L1394-1 assume !(1 == ~T12_E~0); 41376#L1399-1 assume !(1 == ~E_M~0); 41457#L1404-1 assume !(1 == ~E_1~0); 40348#L1409-1 assume !(1 == ~E_2~0); 40349#L1414-1 assume !(1 == ~E_3~0); 41081#L1419-1 assume !(1 == ~E_4~0); 39977#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 39978#L1429-1 assume !(1 == ~E_6~0); 40813#L1434-1 assume !(1 == ~E_7~0); 41393#L1439-1 assume !(1 == ~E_8~0); 40019#L1444-1 assume !(1 == ~E_9~0); 40020#L1449-1 assume !(1 == ~E_10~0); 40405#L1454-1 assume !(1 == ~E_11~0); 40406#L1459-1 assume !(1 == ~E_12~0); 40940#L1464-1 assume { :end_inline_reset_delta_events } true; 40161#L1810-2 [2024-11-09 16:08:56,000 INFO L747 eck$LassoCheckResult]: Loop: 40161#L1810-2 assume !false; 40611#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40709#L1176-1 assume !false; 41091#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40655#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39845#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41145#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 41316#L1003 assume !(0 != eval_~tmp~0#1); 40618#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40350#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40351#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41035#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41036#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40938#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40104#L1216-3 assume !(0 == ~T4_E~0); 40105#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40583#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40183#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40184#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40435#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41424#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41324#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41023#L1256-3 assume !(0 == ~T12_E~0); 40124#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40125#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40175#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40176#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40559#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40560#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41078#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41079#L1296-3 assume !(0 == ~E_7~0); 41496#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41454#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40663#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40044#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40045#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40126#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40777#L593-42 assume 1 == ~m_pc~0; 41164#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40943#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40458#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40459#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39938#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39939#L612-42 assume !(1 == ~t1_pc~0); 40897#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 41278#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41505#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40031#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40032#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40740#L631-42 assume !(1 == ~t2_pc~0); 39793#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 39792#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40725#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40609#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40610#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40202#L650-42 assume 1 == ~t3_pc~0; 39756#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39757#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41111#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40397#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40398#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41395#L669-42 assume 1 == ~t4_pc~0; 40677#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39755#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41180#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41089#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40993#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40994#L688-42 assume 1 == ~t5_pc~0; 41076#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41281#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40789#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39966#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39967#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39784#L707-42 assume !(1 == ~t6_pc~0); 39785#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 41460#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40118#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40119#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 40964#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40965#L726-42 assume !(1 == ~t7_pc~0); 41232#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 41262#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40816#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40667#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40668#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40781#L745-42 assume 1 == ~t8_pc~0; 40819#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40821#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40984#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39772#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39773#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40518#L764-42 assume 1 == ~t9_pc~0; 40646#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41007#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41008#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40056#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40057#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40117#L783-42 assume 1 == ~t10_pc~0; 39728#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39729#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40333#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40976#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41487#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41170#L802-42 assume 1 == ~t11_pc~0; 40264#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39870#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39871#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39817#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39818#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41015#L821-42 assume !(1 == ~t12_pc~0); 40373#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 40374#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40774#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40775#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 40711#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40701#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40702#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40874#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40980#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40383#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40384#L1359-3 assume !(1 == ~T5_E~0); 40990#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41481#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41391#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40204#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40205#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40381#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40382#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40597#L1399-3 assume !(1 == ~E_M~0); 41400#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41368#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41369#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41423#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41173#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40078#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40079#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40989#L1439-3 assume !(1 == ~E_8~0); 40007#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40008#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 40129#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40985#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40986#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 40628#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 39910#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40112#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40113#L1829 assume !(0 == start_simulation_~tmp~3#1); 39892#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39893#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40707#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 39797#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 39798#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41001#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41374#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40160#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 40161#L1810-2 [2024-11-09 16:08:56,001 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1133017134, now seen corresponding path program 1 times [2024-11-09 16:08:56,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169594659] [2024-11-09 16:08:56,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [169594659] [2024-11-09 16:08:56,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [169594659] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:56,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808291839] [2024-11-09 16:08:56,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,054 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:56,055 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1814059162, now seen corresponding path program 1 times [2024-11-09 16:08:56,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155308570] [2024-11-09 16:08:56,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,120 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155308570] [2024-11-09 16:08:56,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155308570] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,121 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,121 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:56,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1875294607] [2024-11-09 16:08:56,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,122 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:56,122 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:56,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:56,123 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:56,123 INFO L87 Difference]: Start difference. First operand 1801 states and 2654 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:56,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:56,156 INFO L93 Difference]: Finished difference Result 1801 states and 2653 transitions. [2024-11-09 16:08:56,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2653 transitions. [2024-11-09 16:08:56,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:56,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2653 transitions. [2024-11-09 16:08:56,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:56,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:56,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2653 transitions. [2024-11-09 16:08:56,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:56,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2024-11-09 16:08:56,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2653 transitions. [2024-11-09 16:08:56,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:56,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.473070516379789) internal successors, (2653), 1800 states have internal predecessors, (2653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:56,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2653 transitions. [2024-11-09 16:08:56,211 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2024-11-09 16:08:56,211 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:56,212 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2653 transitions. [2024-11-09 16:08:56,212 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-09 16:08:56,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2653 transitions. [2024-11-09 16:08:56,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:56,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:56,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:56,221 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,221 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,221 INFO L745 eck$LassoCheckResult]: Stem: 43614#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 43615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45046#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 45047#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44140#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43929#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43326#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43327#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44571#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44670#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45108#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45109#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44065#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44066#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44597#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44522#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44102#L1201 assume !(0 == ~M_E~0); 44103#L1201-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44955#L1206-1 assume !(0 == ~T2_E~0); 44938#L1211-1 assume !(0 == ~T3_E~0); 44939#L1216-1 assume !(0 == ~T4_E~0); 43910#L1221-1 assume !(0 == ~T5_E~0); 43911#L1226-1 assume !(0 == ~T6_E~0); 43540#L1231-1 assume !(0 == ~T7_E~0); 43541#L1236-1 assume !(0 == ~T8_E~0); 44979#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43950#L1246-1 assume !(0 == ~T10_E~0); 43951#L1251-1 assume !(0 == ~T11_E~0); 44100#L1256-1 assume !(0 == ~T12_E~0); 43335#L1261-1 assume !(0 == ~E_M~0); 43336#L1266-1 assume !(0 == ~E_1~0); 45093#L1271-1 assume !(0 == ~E_2~0); 44654#L1276-1 assume !(0 == ~E_3~0); 44655#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 44609#L1286-1 assume !(0 == ~E_5~0); 43806#L1291-1 assume !(0 == ~E_6~0); 43807#L1296-1 assume !(0 == ~E_7~0); 44395#L1301-1 assume !(0 == ~E_8~0); 44396#L1306-1 assume !(0 == ~E_9~0); 44874#L1311-1 assume !(0 == ~E_10~0); 43757#L1316-1 assume !(0 == ~E_11~0); 43758#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 44414#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44415#L593 assume 1 == ~m_pc~0; 44564#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43639#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44303#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44304#L1492 assume !(0 != activate_threads_~tmp~1#1); 44619#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44907#L612 assume !(1 == ~t1_pc~0); 44908#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45042#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44752#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43642#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43643#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44081#L631 assume 1 == ~t2_pc~0; 44008#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43416#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43417#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43771#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 44267#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43718#L650 assume !(1 == ~t3_pc~0); 43719#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44437#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44731#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43373#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 43374#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44590#L669 assume 1 == ~t4_pc~0; 44591#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44946#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43456#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43457#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 43577#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43816#L688 assume !(1 == ~t5_pc~0); 43596#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43597#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45074#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44479#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 44480#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44604#L707 assume 1 == ~t6_pc~0; 45013#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44236#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43759#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43760#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 44550#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44101#L726 assume 1 == ~t7_pc~0; 43996#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43683#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44743#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45017#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 43446#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43447#L745 assume !(1 == ~t8_pc~0); 43903#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 43923#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44961#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44312#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44313#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44831#L764 assume 1 == ~t9_pc~0; 44099#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43933#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43832#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43833#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 43472#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43473#L783 assume !(1 == ~t10_pc~0); 43527#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 43528#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43725#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44055#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 44056#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44948#L802 assume 1 == ~t11_pc~0; 44930#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43413#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43414#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43912#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 43913#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44030#L821 assume !(1 == ~t12_pc~0); 44281#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 44387#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43420#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43421#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 44990#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44627#L1339 assume !(1 == ~M_E~0); 44628#L1339-2 assume !(1 == ~T1_E~0); 45020#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45021#L1349-1 assume !(1 == ~T3_E~0); 44407#L1354-1 assume !(1 == ~T4_E~0); 44408#L1359-1 assume !(1 == ~T5_E~0); 44807#L1364-1 assume !(1 == ~T6_E~0); 43864#L1369-1 assume !(1 == ~T7_E~0); 43865#L1374-1 assume !(1 == ~T8_E~0); 44410#L1379-1 assume !(1 == ~T9_E~0); 44411#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44519#L1389-1 assume !(1 == ~T11_E~0); 44984#L1394-1 assume !(1 == ~T12_E~0); 44985#L1399-1 assume !(1 == ~E_M~0); 45066#L1404-1 assume !(1 == ~E_1~0); 43957#L1409-1 assume !(1 == ~E_2~0); 43958#L1414-1 assume !(1 == ~E_3~0); 44690#L1419-1 assume !(1 == ~E_4~0); 43586#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 43587#L1429-1 assume !(1 == ~E_6~0); 44422#L1434-1 assume !(1 == ~E_7~0); 45002#L1439-1 assume !(1 == ~E_8~0); 43628#L1444-1 assume !(1 == ~E_9~0); 43629#L1449-1 assume !(1 == ~E_10~0); 44014#L1454-1 assume !(1 == ~E_11~0); 44015#L1459-1 assume !(1 == ~E_12~0); 44549#L1464-1 assume { :end_inline_reset_delta_events } true; 43770#L1810-2 [2024-11-09 16:08:56,222 INFO L747 eck$LassoCheckResult]: Loop: 43770#L1810-2 assume !false; 44220#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44318#L1176-1 assume !false; 44700#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44264#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43454#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44754#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44925#L1003 assume !(0 != eval_~tmp~0#1); 44227#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43959#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43960#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44644#L1201-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44645#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44547#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43713#L1216-3 assume !(0 == ~T4_E~0); 43714#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44192#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43792#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43793#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44044#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45033#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44933#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44632#L1256-3 assume !(0 == ~T12_E~0); 43733#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 43734#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43784#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43785#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44168#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44169#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44687#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44688#L1296-3 assume !(0 == ~E_7~0); 45105#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45063#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44272#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 43653#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43654#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 43735#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44386#L593-42 assume 1 == ~m_pc~0; 44773#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44552#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44067#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44068#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43547#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43548#L612-42 assume !(1 == ~t1_pc~0); 44506#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 44887#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45114#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43640#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43641#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44349#L631-42 assume 1 == ~t2_pc~0; 43400#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43401#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44334#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44218#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44219#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43811#L650-42 assume 1 == ~t3_pc~0; 43365#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43366#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44720#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44006#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44007#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45004#L669-42 assume !(1 == ~t4_pc~0); 43363#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43364#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44789#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44698#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44602#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44603#L688-42 assume 1 == ~t5_pc~0; 44685#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44890#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44398#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43575#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43576#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43393#L707-42 assume !(1 == ~t6_pc~0); 43394#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 45069#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43727#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43728#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 44573#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44574#L726-42 assume 1 == ~t7_pc~0; 44840#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44871#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44425#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44276#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44277#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44390#L745-42 assume 1 == ~t8_pc~0; 44428#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44430#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44593#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43381#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43382#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44127#L764-42 assume !(1 == ~t9_pc~0); 44256#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 44616#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44617#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43665#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43666#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43726#L783-42 assume 1 == ~t10_pc~0; 43337#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43338#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43942#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44585#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45096#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44779#L802-42 assume 1 == ~t11_pc~0; 43873#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43479#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43480#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43426#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43427#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44624#L821-42 assume 1 == ~t12_pc~0; 44625#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43983#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44383#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44384#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44320#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44310#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44311#L1339-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44483#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44589#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43992#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43993#L1359-3 assume !(1 == ~T5_E~0); 44599#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45090#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45000#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43813#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 43814#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43990#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43991#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44206#L1399-3 assume !(1 == ~E_M~0); 45009#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44977#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44978#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45032#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44782#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43687#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43688#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44598#L1439-3 assume !(1 == ~E_8~0); 43616#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43617#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43738#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44594#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44595#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44237#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 43519#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43721#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43722#L1829 assume !(0 == start_simulation_~tmp~3#1); 43501#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 43502#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44316#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 43406#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 43407#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44610#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44983#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 43769#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 43770#L1810-2 [2024-11-09 16:08:56,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,222 INFO L85 PathProgramCache]: Analyzing trace with hash -1544509712, now seen corresponding path program 1 times [2024-11-09 16:08:56,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141601164] [2024-11-09 16:08:56,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,284 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [141601164] [2024-11-09 16:08:56,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [141601164] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,285 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:08:56,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728335340] [2024-11-09 16:08:56,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,285 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:56,285 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,286 INFO L85 PathProgramCache]: Analyzing trace with hash -341876263, now seen corresponding path program 1 times [2024-11-09 16:08:56,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380694869] [2024-11-09 16:08:56,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,341 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,341 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [380694869] [2024-11-09 16:08:56,341 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [380694869] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,341 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,341 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:56,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713375470] [2024-11-09 16:08:56,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,342 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:56,342 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:56,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:56,342 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:56,342 INFO L87 Difference]: Start difference. First operand 1801 states and 2653 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:56,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:56,378 INFO L93 Difference]: Finished difference Result 1801 states and 2648 transitions. [2024-11-09 16:08:56,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1801 states and 2648 transitions. [2024-11-09 16:08:56,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:56,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1801 states to 1801 states and 2648 transitions. [2024-11-09 16:08:56,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1801 [2024-11-09 16:08:56,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1801 [2024-11-09 16:08:56,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1801 states and 2648 transitions. [2024-11-09 16:08:56,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:56,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2024-11-09 16:08:56,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1801 states and 2648 transitions. [2024-11-09 16:08:56,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1801 to 1801. [2024-11-09 16:08:56,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1801 states, 1801 states have (on average 1.470294280955025) internal successors, (2648), 1800 states have internal predecessors, (2648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:56,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1801 states to 1801 states and 2648 transitions. [2024-11-09 16:08:56,427 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2024-11-09 16:08:56,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:56,431 INFO L425 stractBuchiCegarLoop]: Abstraction has 1801 states and 2648 transitions. [2024-11-09 16:08:56,431 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-09 16:08:56,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1801 states and 2648 transitions. [2024-11-09 16:08:56,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1638 [2024-11-09 16:08:56,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:56,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:56,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,440 INFO L745 eck$LassoCheckResult]: Stem: 47223#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 47224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48068#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48069#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48655#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 48656#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47749#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47538#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46935#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46936#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48180#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48279#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48717#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48718#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47674#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47675#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48206#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48131#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47711#L1201 assume !(0 == ~M_E~0); 47712#L1201-2 assume !(0 == ~T1_E~0); 48564#L1206-1 assume !(0 == ~T2_E~0); 48547#L1211-1 assume !(0 == ~T3_E~0); 48548#L1216-1 assume !(0 == ~T4_E~0); 47519#L1221-1 assume !(0 == ~T5_E~0); 47520#L1226-1 assume !(0 == ~T6_E~0); 47149#L1231-1 assume !(0 == ~T7_E~0); 47150#L1236-1 assume !(0 == ~T8_E~0); 48588#L1241-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47559#L1246-1 assume !(0 == ~T10_E~0); 47560#L1251-1 assume !(0 == ~T11_E~0); 47709#L1256-1 assume !(0 == ~T12_E~0); 46944#L1261-1 assume !(0 == ~E_M~0); 46945#L1266-1 assume !(0 == ~E_1~0); 48702#L1271-1 assume !(0 == ~E_2~0); 48263#L1276-1 assume !(0 == ~E_3~0); 48264#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 48218#L1286-1 assume !(0 == ~E_5~0); 47415#L1291-1 assume !(0 == ~E_6~0); 47416#L1296-1 assume !(0 == ~E_7~0); 48004#L1301-1 assume !(0 == ~E_8~0); 48005#L1306-1 assume !(0 == ~E_9~0); 48483#L1311-1 assume !(0 == ~E_10~0); 47366#L1316-1 assume !(0 == ~E_11~0); 47367#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 48023#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48024#L593 assume 1 == ~m_pc~0; 48173#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47248#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47912#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47913#L1492 assume !(0 != activate_threads_~tmp~1#1); 48228#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48516#L612 assume !(1 == ~t1_pc~0); 48517#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48651#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48361#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47251#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47252#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47690#L631 assume 1 == ~t2_pc~0; 47617#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47025#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47026#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47380#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 47876#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47327#L650 assume !(1 == ~t3_pc~0); 47328#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48046#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48340#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46982#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 46983#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48199#L669 assume 1 == ~t4_pc~0; 48200#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48555#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47065#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47066#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 47186#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47425#L688 assume !(1 == ~t5_pc~0); 47205#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 47206#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48683#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48088#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 48089#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48213#L707 assume 1 == ~t6_pc~0; 48622#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47845#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47368#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47369#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 48159#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47710#L726 assume 1 == ~t7_pc~0; 47605#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47292#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48352#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 48626#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 47055#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47056#L745 assume !(1 == ~t8_pc~0); 47512#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 47532#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48570#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47921#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47922#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48440#L764 assume 1 == ~t9_pc~0; 47708#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47542#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47441#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47442#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 47081#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47082#L783 assume !(1 == ~t10_pc~0); 47136#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 47137#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47334#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47664#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 47665#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48557#L802 assume 1 == ~t11_pc~0; 48539#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47022#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47023#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47521#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 47522#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47639#L821 assume !(1 == ~t12_pc~0); 47890#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 47996#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47029#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47030#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 48599#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48236#L1339 assume !(1 == ~M_E~0); 48237#L1339-2 assume !(1 == ~T1_E~0); 48629#L1344-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48630#L1349-1 assume !(1 == ~T3_E~0); 48016#L1354-1 assume !(1 == ~T4_E~0); 48017#L1359-1 assume !(1 == ~T5_E~0); 48416#L1364-1 assume !(1 == ~T6_E~0); 47473#L1369-1 assume !(1 == ~T7_E~0); 47474#L1374-1 assume !(1 == ~T8_E~0); 48019#L1379-1 assume !(1 == ~T9_E~0); 48020#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48128#L1389-1 assume !(1 == ~T11_E~0); 48593#L1394-1 assume !(1 == ~T12_E~0); 48594#L1399-1 assume !(1 == ~E_M~0); 48675#L1404-1 assume !(1 == ~E_1~0); 47566#L1409-1 assume !(1 == ~E_2~0); 47567#L1414-1 assume !(1 == ~E_3~0); 48299#L1419-1 assume !(1 == ~E_4~0); 47195#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 47196#L1429-1 assume !(1 == ~E_6~0); 48031#L1434-1 assume !(1 == ~E_7~0); 48611#L1439-1 assume !(1 == ~E_8~0); 47237#L1444-1 assume !(1 == ~E_9~0); 47238#L1449-1 assume !(1 == ~E_10~0); 47623#L1454-1 assume !(1 == ~E_11~0); 47624#L1459-1 assume !(1 == ~E_12~0); 48158#L1464-1 assume { :end_inline_reset_delta_events } true; 47379#L1810-2 [2024-11-09 16:08:56,440 INFO L747 eck$LassoCheckResult]: Loop: 47379#L1810-2 assume !false; 47829#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47927#L1176-1 assume !false; 48309#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47873#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47063#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48363#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48534#L1003 assume !(0 != eval_~tmp~0#1); 47836#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47568#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47569#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48253#L1201-5 assume !(0 == ~T1_E~0); 48254#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48156#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47322#L1216-3 assume !(0 == ~T4_E~0); 47323#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47801#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47401#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47402#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47653#L1241-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48642#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 48542#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48241#L1256-3 assume !(0 == ~T12_E~0); 47342#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47343#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47393#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47394#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47777#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47778#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 48296#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48297#L1296-3 assume !(0 == ~E_7~0); 48714#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 48672#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47881#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47262#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47263#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 47344#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47995#L593-42 assume !(1 == ~m_pc~0); 48160#L593-44 is_master_triggered_~__retres1~0#1 := 0; 48161#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47676#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47677#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47156#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47157#L612-42 assume !(1 == ~t1_pc~0); 48115#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 48496#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48723#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47249#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47250#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47958#L631-42 assume 1 == ~t2_pc~0; 47009#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47010#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47943#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47827#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47828#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47420#L650-42 assume !(1 == ~t3_pc~0); 46976#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 46975#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48329#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47615#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47616#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48613#L669-42 assume 1 == ~t4_pc~0; 47895#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46973#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48398#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48307#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48211#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48212#L688-42 assume 1 == ~t5_pc~0; 48294#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48499#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48007#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47184#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47185#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47002#L707-42 assume !(1 == ~t6_pc~0); 47003#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 48678#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47336#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47337#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 48182#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48183#L726-42 assume 1 == ~t7_pc~0; 48449#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 48480#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48034#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47885#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47886#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47999#L745-42 assume 1 == ~t8_pc~0; 48037#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48039#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48202#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46990#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46991#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47736#L764-42 assume 1 == ~t9_pc~0; 47864#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48225#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48226#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47274#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47275#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47335#L783-42 assume 1 == ~t10_pc~0; 46946#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46947#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47551#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48194#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48705#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48388#L802-42 assume 1 == ~t11_pc~0; 47482#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47088#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47089#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47035#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47036#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48233#L821-42 assume !(1 == ~t12_pc~0); 47591#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 47592#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47992#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47993#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47929#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47919#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47920#L1339-5 assume !(1 == ~T1_E~0); 48092#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48198#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47601#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47602#L1359-3 assume !(1 == ~T5_E~0); 48208#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48699#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48609#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47422#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47423#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47599#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47600#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47815#L1399-3 assume !(1 == ~E_M~0); 48618#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48586#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48587#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48641#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48391#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47296#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47297#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 48207#L1439-3 assume !(1 == ~E_8~0); 47225#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47226#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47347#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48203#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48204#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47846#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47128#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47330#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47331#L1829 assume !(0 == start_simulation_~tmp~3#1); 47110#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 47111#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 47925#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 47015#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47016#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48219#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48592#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 47378#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 47379#L1810-2 [2024-11-09 16:08:56,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,440 INFO L85 PathProgramCache]: Analyzing trace with hash -2089382286, now seen corresponding path program 1 times [2024-11-09 16:08:56,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258601762] [2024-11-09 16:08:56,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1258601762] [2024-11-09 16:08:56,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1258601762] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,517 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,518 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:56,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727317355] [2024-11-09 16:08:56,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,518 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:56,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1910359590, now seen corresponding path program 1 times [2024-11-09 16:08:56,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,519 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244708998] [2024-11-09 16:08:56,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244708998] [2024-11-09 16:08:56,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [244708998] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,598 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,598 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:56,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645420831] [2024-11-09 16:08:56,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,599 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:56,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:56,600 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:56,600 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:56,601 INFO L87 Difference]: Start difference. First operand 1801 states and 2648 transitions. cyclomatic complexity: 848 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:56,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:56,739 INFO L93 Difference]: Finished difference Result 3463 states and 5084 transitions. [2024-11-09 16:08:56,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3463 states and 5084 transitions. [2024-11-09 16:08:56,758 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3276 [2024-11-09 16:08:56,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3463 states to 3463 states and 5084 transitions. [2024-11-09 16:08:56,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3463 [2024-11-09 16:08:56,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3463 [2024-11-09 16:08:56,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3463 states and 5084 transitions. [2024-11-09 16:08:56,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:56,790 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2024-11-09 16:08:56,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3463 states and 5084 transitions. [2024-11-09 16:08:56,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3463 to 3463. [2024-11-09 16:08:56,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3463 states, 3463 states have (on average 1.4680912503609587) internal successors, (5084), 3462 states have internal predecessors, (5084), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:56,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3463 states to 3463 states and 5084 transitions. [2024-11-09 16:08:56,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2024-11-09 16:08:56,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:08:56,856 INFO L425 stractBuchiCegarLoop]: Abstraction has 3463 states and 5084 transitions. [2024-11-09 16:08:56,856 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-09 16:08:56,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3463 states and 5084 transitions. [2024-11-09 16:08:56,867 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3276 [2024-11-09 16:08:56,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:56,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:56,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:56,870 INFO L745 eck$LassoCheckResult]: Stem: 52497#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 52498#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 53347#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53943#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 53944#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53025#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52813#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52209#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52210#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53460#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53561#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54015#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54016#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52949#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52950#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53486#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 53409#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52986#L1201 assume !(0 == ~M_E~0); 52987#L1201-2 assume !(0 == ~T1_E~0); 53847#L1206-1 assume !(0 == ~T2_E~0); 53830#L1211-1 assume !(0 == ~T3_E~0); 53831#L1216-1 assume !(0 == ~T4_E~0); 52795#L1221-1 assume !(0 == ~T5_E~0); 52796#L1226-1 assume !(0 == ~T6_E~0); 52423#L1231-1 assume !(0 == ~T7_E~0); 52424#L1236-1 assume !(0 == ~T8_E~0); 53873#L1241-1 assume !(0 == ~T9_E~0); 52837#L1246-1 assume !(0 == ~T10_E~0); 52838#L1251-1 assume !(0 == ~T11_E~0); 52984#L1256-1 assume !(0 == ~T12_E~0); 52218#L1261-1 assume !(0 == ~E_M~0); 52219#L1266-1 assume !(0 == ~E_1~0); 53997#L1271-1 assume !(0 == ~E_2~0); 53544#L1276-1 assume !(0 == ~E_3~0); 53545#L1281-1 assume 0 == ~E_4~0;~E_4~0 := 1; 53498#L1286-1 assume !(0 == ~E_5~0); 52689#L1291-1 assume !(0 == ~E_6~0); 52690#L1296-1 assume !(0 == ~E_7~0); 53281#L1301-1 assume !(0 == ~E_8~0); 53282#L1306-1 assume !(0 == ~E_9~0); 53765#L1311-1 assume !(0 == ~E_10~0); 52640#L1316-1 assume !(0 == ~E_11~0); 52641#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 53301#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53302#L593 assume 1 == ~m_pc~0; 53452#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 52522#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53188#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53189#L1492 assume !(0 != activate_threads_~tmp~1#1); 53508#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53798#L612 assume !(1 == ~t1_pc~0); 53799#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53939#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52525#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52526#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52965#L631 assume 1 == ~t2_pc~0; 52892#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52299#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52300#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52654#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 53152#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52603#L650 assume !(1 == ~t3_pc~0); 52604#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53324#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53621#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52256#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 52257#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53479#L669 assume 1 == ~t4_pc~0; 53480#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53839#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52343#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52344#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 52460#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52700#L688 assume !(1 == ~t5_pc~0); 52479#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52480#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53975#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53368#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 53369#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53496#L707 assume 1 == ~t6_pc~0; 53908#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53121#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52642#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52643#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 53440#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52985#L726 assume 1 == ~t7_pc~0; 52882#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52566#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53634#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53914#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 52329#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52330#L745 assume !(1 == ~t8_pc~0); 52787#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 52807#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53853#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53197#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53198#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53721#L764 assume 1 == ~t9_pc~0; 52983#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52817#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52716#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52717#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 52355#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52356#L783 assume !(1 == ~t10_pc~0); 52410#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52411#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52608#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52944#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 52945#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53840#L802 assume 1 == ~t11_pc~0; 53822#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52296#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52297#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52797#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 52798#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52914#L821 assume !(1 == ~t12_pc~0); 53166#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 53272#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52305#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52306#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 53885#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53516#L1339 assume !(1 == ~M_E~0); 53517#L1339-2 assume !(1 == ~T1_E~0); 53916#L1344-1 assume !(1 == ~T2_E~0); 53917#L1349-1 assume !(1 == ~T3_E~0); 53294#L1354-1 assume !(1 == ~T4_E~0); 53295#L1359-1 assume !(1 == ~T5_E~0); 53699#L1364-1 assume !(1 == ~T6_E~0); 52748#L1369-1 assume !(1 == ~T7_E~0); 52749#L1374-1 assume !(1 == ~T8_E~0); 53298#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53299#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54132#L1389-1 assume !(1 == ~T11_E~0); 54131#L1394-1 assume !(1 == ~T12_E~0); 54130#L1399-1 assume !(1 == ~E_M~0); 54129#L1404-1 assume !(1 == ~E_1~0); 54127#L1409-1 assume !(1 == ~E_2~0); 54125#L1414-1 assume !(1 == ~E_3~0); 54123#L1419-1 assume !(1 == ~E_4~0); 54121#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54118#L1429-1 assume !(1 == ~E_6~0); 54116#L1434-1 assume !(1 == ~E_7~0); 54114#L1439-1 assume !(1 == ~E_8~0); 54112#L1444-1 assume !(1 == ~E_9~0); 54110#L1449-1 assume !(1 == ~E_10~0); 54092#L1454-1 assume !(1 == ~E_11~0); 54084#L1459-1 assume !(1 == ~E_12~0); 53437#L1464-1 assume { :end_inline_reset_delta_events } true; 52653#L1810-2 [2024-11-09 16:08:56,872 INFO L747 eck$LassoCheckResult]: Loop: 52653#L1810-2 assume !false; 53105#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53203#L1176-1 assume !false; 53590#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 53151#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52337#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 53644#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53819#L1003 assume !(0 != eval_~tmp~0#1); 53112#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52844#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53534#L1201-5 assume !(0 == ~T1_E~0); 53535#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54042#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55102#L1216-3 assume !(0 == ~T4_E~0); 55101#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55100#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55099#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55098#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55096#L1241-3 assume !(0 == ~T9_E~0); 55093#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 55091#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55089#L1256-3 assume !(0 == ~T12_E~0); 55087#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55085#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55083#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55080#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55078#L1281-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55076#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55074#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55072#L1296-3 assume !(0 == ~E_7~0); 55070#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 55067#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 55065#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 55063#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55061#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 55059#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55057#L593-42 assume 1 == ~m_pc~0; 55053#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 55051#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55049#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 55047#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55045#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55043#L612-42 assume 1 == ~t1_pc~0; 55040#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55037#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55035#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55033#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55031#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55029#L631-42 assume 1 == ~t2_pc~0; 55025#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55023#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55021#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55019#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55017#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55015#L650-42 assume !(1 == ~t3_pc~0); 55011#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 55009#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55007#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55005#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55003#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55001#L669-42 assume 1 == ~t4_pc~0; 54997#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54995#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54993#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54991#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54989#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54987#L688-42 assume !(1 == ~t5_pc~0); 54983#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 54981#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54979#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54977#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54975#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54973#L707-42 assume 1 == ~t6_pc~0; 54969#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54967#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54965#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54963#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 54961#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54959#L726-42 assume 1 == ~t7_pc~0; 54955#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54953#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54951#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54949#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54947#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54945#L745-42 assume !(1 == ~t8_pc~0); 54941#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 54939#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54937#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54935#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54933#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54931#L764-42 assume !(1 == ~t9_pc~0); 54928#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 54925#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54923#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54921#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54919#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54915#L783-42 assume !(1 == ~t10_pc~0); 54912#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 54910#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54909#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54908#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54905#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54904#L802-42 assume 1 == ~t11_pc~0; 54902#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54901#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54900#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54899#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54898#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54897#L821-42 assume 1 == ~t12_pc~0; 54896#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54894#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54893#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54892#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54891#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54890#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54889#L1339-5 assume !(1 == ~T1_E~0); 54888#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53525#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54887#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54886#L1359-3 assume !(1 == ~T5_E~0); 54885#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54884#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54883#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54882#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52696#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54881#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54880#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54879#L1399-3 assume !(1 == ~E_M~0); 54878#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54877#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54876#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54875#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54874#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54873#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54872#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54871#L1439-3 assume !(1 == ~E_8~0); 54870#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54869#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54868#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54867#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54866#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54865#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54852#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54851#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 54771#L1829 assume !(0 == start_simulation_~tmp~3#1); 54770#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54286#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54109#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54108#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 54107#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54012#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53877#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 52652#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 52653#L1810-2 [2024-11-09 16:08:56,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,873 INFO L85 PathProgramCache]: Analyzing trace with hash 907144632, now seen corresponding path program 1 times [2024-11-09 16:08:56,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273668297] [2024-11-09 16:08:56,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:56,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:56,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:56,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [273668297] [2024-11-09 16:08:56,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [273668297] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:56,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:56,941 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:56,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784669855] [2024-11-09 16:08:56,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:56,942 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:56,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:56,943 INFO L85 PathProgramCache]: Analyzing trace with hash -770929124, now seen corresponding path program 1 times [2024-11-09 16:08:56,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:56,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476363903] [2024-11-09 16:08:56,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:56,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:56,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:57,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:57,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:57,002 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476363903] [2024-11-09 16:08:57,002 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476363903] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:57,002 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:57,002 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:57,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1103227584] [2024-11-09 16:08:57,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:57,002 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:57,002 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:57,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:57,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:57,003 INFO L87 Difference]: Start difference. First operand 3463 states and 5084 transitions. cyclomatic complexity: 1623 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:57,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:57,228 INFO L93 Difference]: Finished difference Result 6581 states and 9651 transitions. [2024-11-09 16:08:57,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6581 states and 9651 transitions. [2024-11-09 16:08:57,278 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6366 [2024-11-09 16:08:57,305 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6581 states to 6581 states and 9651 transitions. [2024-11-09 16:08:57,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6581 [2024-11-09 16:08:57,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6581 [2024-11-09 16:08:57,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6581 states and 9651 transitions. [2024-11-09 16:08:57,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:57,323 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6581 states and 9651 transitions. [2024-11-09 16:08:57,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6581 states and 9651 transitions. [2024-11-09 16:08:57,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6581 to 6579. [2024-11-09 16:08:57,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6579 states, 6579 states have (on average 1.4666362669098647) internal successors, (9649), 6578 states have internal predecessors, (9649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:57,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6579 states to 6579 states and 9649 transitions. [2024-11-09 16:08:57,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6579 states and 9649 transitions. [2024-11-09 16:08:57,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:08:57,536 INFO L425 stractBuchiCegarLoop]: Abstraction has 6579 states and 9649 transitions. [2024-11-09 16:08:57,536 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-09 16:08:57,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6579 states and 9649 transitions. [2024-11-09 16:08:57,562 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6366 [2024-11-09 16:08:57,562 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:57,562 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:57,564 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:57,564 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:57,565 INFO L745 eck$LassoCheckResult]: Stem: 62551#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 62552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 63420#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63421#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64064#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 64065#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63086#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62871#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62263#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62264#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63534#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63637#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64147#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64148#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63010#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63011#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63560#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 63484#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63048#L1201 assume !(0 == ~M_E~0); 63049#L1201-2 assume !(0 == ~T1_E~0); 63961#L1206-1 assume !(0 == ~T2_E~0); 63940#L1211-1 assume !(0 == ~T3_E~0); 63941#L1216-1 assume !(0 == ~T4_E~0); 62852#L1221-1 assume !(0 == ~T5_E~0); 62853#L1226-1 assume !(0 == ~T6_E~0); 62477#L1231-1 assume !(0 == ~T7_E~0); 62478#L1236-1 assume !(0 == ~T8_E~0); 63987#L1241-1 assume !(0 == ~T9_E~0); 62892#L1246-1 assume !(0 == ~T10_E~0); 62893#L1251-1 assume !(0 == ~T11_E~0); 63046#L1256-1 assume !(0 == ~T12_E~0); 62272#L1261-1 assume !(0 == ~E_M~0); 62273#L1266-1 assume !(0 == ~E_1~0); 64124#L1271-1 assume !(0 == ~E_2~0); 63621#L1276-1 assume !(0 == ~E_3~0); 63622#L1281-1 assume !(0 == ~E_4~0); 63572#L1286-1 assume !(0 == ~E_5~0); 62744#L1291-1 assume !(0 == ~E_6~0); 62745#L1296-1 assume !(0 == ~E_7~0); 63354#L1301-1 assume !(0 == ~E_8~0); 63355#L1306-1 assume !(0 == ~E_9~0); 63866#L1311-1 assume !(0 == ~E_10~0); 62695#L1316-1 assume !(0 == ~E_11~0); 62696#L1321-1 assume 0 == ~E_12~0;~E_12~0 := 1; 63375#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63376#L593 assume 1 == ~m_pc~0; 63527#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62576#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63258#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63259#L1492 assume !(0 != activate_threads_~tmp~1#1); 63582#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63903#L612 assume !(1 == ~t1_pc~0); 63904#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 64059#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63724#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62579#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62580#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63026#L631 assume 1 == ~t2_pc~0; 62950#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62353#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62354#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62709#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 63219#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62656#L650 assume !(1 == ~t3_pc~0); 62657#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63398#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63700#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62310#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 62311#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63553#L669 assume 1 == ~t4_pc~0; 63554#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63950#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62393#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62394#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 62514#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62755#L688 assume !(1 == ~t5_pc~0); 62533#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 62534#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64097#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63440#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 63441#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63567#L707 assume 1 == ~t6_pc~0; 64023#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63187#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62697#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 62698#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 63513#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 63047#L726 assume 1 == ~t7_pc~0; 62938#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 62621#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63714#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64030#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 62383#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62384#L745 assume !(1 == ~t8_pc~0); 62845#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 62865#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63969#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63267#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63268#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63817#L764 assume 1 == ~t9_pc~0; 63045#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62875#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62773#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62774#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 62409#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62410#L783 assume !(1 == ~t10_pc~0); 62464#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 62465#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 62999#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 63000#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63952#L802 assume 1 == ~t11_pc~0; 63926#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62350#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62351#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 62854#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 62855#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62973#L821 assume !(1 == ~t12_pc~0); 63235#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 63345#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 62357#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 62358#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 63998#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63592#L1339 assume !(1 == ~M_E~0); 63593#L1339-2 assume !(1 == ~T1_E~0); 64033#L1344-1 assume !(1 == ~T2_E~0); 64034#L1349-1 assume !(1 == ~T3_E~0); 63367#L1354-1 assume !(1 == ~T4_E~0); 63368#L1359-1 assume !(1 == ~T5_E~0); 63790#L1364-1 assume !(1 == ~T6_E~0); 64139#L1369-1 assume !(1 == ~T7_E~0); 64492#L1374-1 assume !(1 == ~T8_E~0); 63370#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63371#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64409#L1389-1 assume !(1 == ~T11_E~0); 64407#L1394-1 assume !(1 == ~T12_E~0); 64404#L1399-1 assume !(1 == ~E_M~0); 64402#L1404-1 assume !(1 == ~E_1~0); 64400#L1409-1 assume !(1 == ~E_2~0); 64399#L1414-1 assume !(1 == ~E_3~0); 64349#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 64347#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 64345#L1429-1 assume !(1 == ~E_6~0); 64331#L1434-1 assume !(1 == ~E_7~0); 64329#L1439-1 assume !(1 == ~E_8~0); 64287#L1444-1 assume !(1 == ~E_9~0); 64256#L1449-1 assume !(1 == ~E_10~0); 64239#L1454-1 assume !(1 == ~E_11~0); 64230#L1459-1 assume !(1 == ~E_12~0); 64222#L1464-1 assume { :end_inline_reset_delta_events } true; 64215#L1810-2 [2024-11-09 16:08:57,565 INFO L747 eck$LassoCheckResult]: Loop: 64215#L1810-2 assume !false; 64211#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64210#L1176-1 assume !false; 64209#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64206#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64195#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64194#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 64192#L1003 assume !(0 != eval_~tmp~0#1); 64191#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64190#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64189#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 64188#L1201-5 assume !(0 == ~T1_E~0); 64186#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64187#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66079#L1216-3 assume !(0 == ~T4_E~0); 66069#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66062#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 66055#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66047#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 66036#L1241-3 assume !(0 == ~T9_E~0); 66034#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66032#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 66030#L1256-3 assume !(0 == ~T12_E~0); 66027#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66025#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66023#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66021#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66019#L1281-3 assume !(0 == ~E_4~0); 66017#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66014#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 66013#L1296-3 assume !(0 == ~E_7~0); 66011#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66009#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 66007#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 66006#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66004#L1321-3 assume 0 == ~E_12~0;~E_12~0 := 1; 66002#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66000#L593-42 assume !(1 == ~m_pc~0); 65999#L593-44 is_master_triggered_~__retres1~0#1 := 0; 65997#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65995#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65993#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65937#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65935#L612-42 assume 1 == ~t1_pc~0; 65933#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65930#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65928#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65926#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65924#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65923#L631-42 assume 1 == ~t2_pc~0; 65921#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65919#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65917#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65915#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65913#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65911#L650-42 assume 1 == ~t3_pc~0; 65909#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65906#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65904#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65817#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65816#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65813#L669-42 assume !(1 == ~t4_pc~0); 65811#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 65808#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65806#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65804#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65802#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65800#L688-42 assume !(1 == ~t5_pc~0); 65797#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 65795#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65793#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65791#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65789#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65750#L707-42 assume 1 == ~t6_pc~0; 65683#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65681#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65679#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65614#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 65611#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65609#L726-42 assume !(1 == ~t7_pc~0); 65607#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 65604#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65602#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65600#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65599#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65598#L745-42 assume 1 == ~t8_pc~0; 65597#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65593#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65591#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65589#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65587#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65487#L764-42 assume 1 == ~t9_pc~0; 65483#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65481#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65479#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65477#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65475#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65473#L783-42 assume !(1 == ~t10_pc~0); 65470#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 65422#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65420#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65368#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65367#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65366#L802-42 assume 1 == ~t11_pc~0; 65323#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65321#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65213#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65211#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65209#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65207#L821-42 assume !(1 == ~t12_pc~0); 64830#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 64828#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64826#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64824#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64822#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64820#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 64818#L1339-5 assume !(1 == ~T1_E~0); 64816#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63601#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64682#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64680#L1359-3 assume !(1 == ~T5_E~0); 64678#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64676#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64672#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64670#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62752#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64626#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 64624#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64622#L1399-3 assume !(1 == ~E_M~0); 64620#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 64562#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64517#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64465#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64398#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64396#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 64394#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 64392#L1439-3 assume !(1 == ~E_8~0); 64390#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64388#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 64386#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 64348#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 64346#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64344#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64330#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64328#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 64323#L1829 assume !(0 == start_simulation_~tmp~3#1); 64321#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64284#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64271#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64255#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 64251#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64238#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64229#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 64221#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 64215#L1810-2 [2024-11-09 16:08:57,566 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:57,566 INFO L85 PathProgramCache]: Analyzing trace with hash -1065863428, now seen corresponding path program 1 times [2024-11-09 16:08:57,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:57,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059154417] [2024-11-09 16:08:57,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:57,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:57,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:57,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:57,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:57,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1059154417] [2024-11-09 16:08:57,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1059154417] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:57,635 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:57,636 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:57,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162214335] [2024-11-09 16:08:57,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:57,636 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:57,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:57,637 INFO L85 PathProgramCache]: Analyzing trace with hash -1007106657, now seen corresponding path program 1 times [2024-11-09 16:08:57,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:57,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150389935] [2024-11-09 16:08:57,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:57,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:57,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:57,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:57,689 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:57,689 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150389935] [2024-11-09 16:08:57,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150389935] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:57,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:57,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:57,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946290379] [2024-11-09 16:08:57,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:57,691 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:57,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:57,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:08:57,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:08:57,691 INFO L87 Difference]: Start difference. First operand 6579 states and 9649 transitions. cyclomatic complexity: 3074 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:57,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:57,910 INFO L93 Difference]: Finished difference Result 12589 states and 18436 transitions. [2024-11-09 16:08:57,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12589 states and 18436 transitions. [2024-11-09 16:08:57,982 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12360 [2024-11-09 16:08:58,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12589 states to 12589 states and 18436 transitions. [2024-11-09 16:08:58,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12589 [2024-11-09 16:08:58,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12589 [2024-11-09 16:08:58,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12589 states and 18436 transitions. [2024-11-09 16:08:58,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:58,063 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12589 states and 18436 transitions. [2024-11-09 16:08:58,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12589 states and 18436 transitions. [2024-11-09 16:08:58,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12589 to 12585. [2024-11-09 16:08:58,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12585 states, 12585 states have (on average 1.464600715137068) internal successors, (18432), 12584 states have internal predecessors, (18432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:58,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12585 states to 12585 states and 18432 transitions. [2024-11-09 16:08:58,400 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12585 states and 18432 transitions. [2024-11-09 16:08:58,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:08:58,401 INFO L425 stractBuchiCegarLoop]: Abstraction has 12585 states and 18432 transitions. [2024-11-09 16:08:58,401 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-09 16:08:58,401 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12585 states and 18432 transitions. [2024-11-09 16:08:58,443 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12360 [2024-11-09 16:08:58,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:08:58,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:08:58,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:58,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:08:58,446 INFO L745 eck$LassoCheckResult]: Stem: 81729#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 81730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 82582#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82583#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83200#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 83201#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82261#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82049#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81441#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81442#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82696#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82797#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83270#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83271#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82185#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 82186#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82722#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82646#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82223#L1201 assume !(0 == ~M_E~0); 82224#L1201-2 assume !(0 == ~T1_E~0); 83100#L1206-1 assume !(0 == ~T2_E~0); 83080#L1211-1 assume !(0 == ~T3_E~0); 83081#L1216-1 assume !(0 == ~T4_E~0); 82030#L1221-1 assume !(0 == ~T5_E~0); 82031#L1226-1 assume !(0 == ~T6_E~0); 81655#L1231-1 assume !(0 == ~T7_E~0); 81656#L1236-1 assume !(0 == ~T8_E~0); 83126#L1241-1 assume !(0 == ~T9_E~0); 82070#L1246-1 assume !(0 == ~T10_E~0); 82071#L1251-1 assume !(0 == ~T11_E~0); 82221#L1256-1 assume !(0 == ~T12_E~0); 81450#L1261-1 assume !(0 == ~E_M~0); 81451#L1266-1 assume !(0 == ~E_1~0); 83253#L1271-1 assume !(0 == ~E_2~0); 82780#L1276-1 assume !(0 == ~E_3~0); 82781#L1281-1 assume !(0 == ~E_4~0); 82734#L1286-1 assume !(0 == ~E_5~0); 81923#L1291-1 assume !(0 == ~E_6~0); 81924#L1296-1 assume !(0 == ~E_7~0); 82517#L1301-1 assume !(0 == ~E_8~0); 82518#L1306-1 assume !(0 == ~E_9~0); 83012#L1311-1 assume !(0 == ~E_10~0); 81874#L1316-1 assume !(0 == ~E_11~0); 81875#L1321-1 assume !(0 == ~E_12~0); 82536#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82537#L593 assume 1 == ~m_pc~0; 82689#L594 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 81754#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82425#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 82426#L1492 assume !(0 != activate_threads_~tmp~1#1); 82744#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83049#L612 assume !(1 == ~t1_pc~0); 83050#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 83196#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82882#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81757#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81758#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82201#L631 assume 1 == ~t2_pc~0; 82128#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 81531#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81532#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81888#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 82389#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81835#L650 assume !(1 == ~t3_pc~0); 81836#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82560#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82860#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81488#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 81489#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82715#L669 assume 1 == ~t4_pc~0; 82716#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83089#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81571#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 81572#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 81692#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81934#L688 assume !(1 == ~t5_pc~0); 81711#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81712#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83232#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82602#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 82603#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82729#L707 assume 1 == ~t6_pc~0; 83162#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82358#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81876#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81877#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 82674#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82222#L726 assume 1 == ~t7_pc~0; 82116#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 81799#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82872#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83167#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 81561#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81562#L745 assume !(1 == ~t8_pc~0); 82023#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 82043#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83107#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82434#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82435#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82968#L764 assume 1 == ~t9_pc~0; 82220#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82053#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81952#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81953#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 81587#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81588#L783 assume !(1 == ~t10_pc~0); 81642#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81643#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81842#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82175#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 82176#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83091#L802 assume 1 == ~t11_pc~0; 83072#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 81528#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81529#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82032#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 82033#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 82150#L821 assume !(1 == ~t12_pc~0); 82403#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 82509#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81535#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 81536#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 83137#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82752#L1339 assume !(1 == ~M_E~0); 82753#L1339-2 assume !(1 == ~T1_E~0); 83171#L1344-1 assume !(1 == ~T2_E~0); 83172#L1349-1 assume !(1 == ~T3_E~0); 82529#L1354-1 assume !(1 == ~T4_E~0); 82530#L1359-1 assume !(1 == ~T5_E~0); 82942#L1364-1 assume !(1 == ~T6_E~0); 81984#L1369-1 assume !(1 == ~T7_E~0); 81985#L1374-1 assume !(1 == ~T8_E~0); 82917#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83561#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83559#L1389-1 assume !(1 == ~T11_E~0); 83557#L1394-1 assume !(1 == ~T12_E~0); 83555#L1399-1 assume !(1 == ~E_M~0); 83552#L1404-1 assume !(1 == ~E_1~0); 83550#L1409-1 assume !(1 == ~E_2~0); 83214#L1414-1 assume !(1 == ~E_3~0); 83215#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 83477#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 83475#L1429-1 assume !(1 == ~E_6~0); 83473#L1434-1 assume !(1 == ~E_7~0); 83421#L1439-1 assume !(1 == ~E_8~0); 83394#L1444-1 assume !(1 == ~E_9~0); 83374#L1449-1 assume !(1 == ~E_10~0); 83357#L1454-1 assume !(1 == ~E_11~0); 83346#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 83338#L1464-1 assume { :end_inline_reset_delta_events } true; 83331#L1810-2 [2024-11-09 16:08:58,447 INFO L747 eck$LassoCheckResult]: Loop: 83331#L1810-2 assume !false; 83327#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83326#L1176-1 assume !false; 83325#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83322#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83311#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83310#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 83308#L1003 assume !(0 != eval_~tmp~0#1); 83307#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83306#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83305#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 83304#L1201-5 assume !(0 == ~T1_E~0); 83302#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83303#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88279#L1216-3 assume !(0 == ~T4_E~0); 88275#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88271#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88268#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88265#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 88262#L1241-3 assume !(0 == ~T9_E~0); 88259#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88256#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 88252#L1256-3 assume !(0 == ~T12_E~0); 88249#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 88246#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88243#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88240#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88237#L1281-3 assume !(0 == ~E_4~0); 88233#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88230#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88227#L1296-3 assume !(0 == ~E_7~0); 88224#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 88221#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 88218#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88214#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 88211#L1321-3 assume !(0 == ~E_12~0); 88208#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88205#L593-42 assume 1 == ~m_pc~0; 88201#L594-14 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 88198#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88194#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88191#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88188#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88185#L612-42 assume !(1 == ~t1_pc~0); 88181#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 88178#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88173#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88170#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88167#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88164#L631-42 assume !(1 == ~t2_pc~0); 88161#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 88157#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88152#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88149#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88146#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88143#L650-42 assume !(1 == ~t3_pc~0); 88139#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 88136#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88131#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 88128#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88125#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88122#L669-42 assume !(1 == ~t4_pc~0); 88119#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 88115#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88110#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 88107#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88104#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88101#L688-42 assume !(1 == ~t5_pc~0); 88097#L688-44 is_transmit5_triggered_~__retres1~5#1 := 0; 88094#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88089#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88086#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88083#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88080#L707-42 assume !(1 == ~t6_pc~0); 88077#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 88073#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88068#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88065#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 88062#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88059#L726-42 assume 1 == ~t7_pc~0; 88055#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88053#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88050#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 88048#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 88046#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88043#L745-42 assume 1 == ~t8_pc~0; 88041#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 88037#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 88035#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88032#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 88028#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 88025#L764-42 assume 1 == ~t9_pc~0; 88021#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88017#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88014#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 88011#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 88007#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88004#L783-42 assume 1 == ~t10_pc~0; 88001#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 87996#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 87993#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 87990#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 87986#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 87983#L802-42 assume 1 == ~t11_pc~0; 87979#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 87975#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 87972#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 87969#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 87965#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84083#L821-42 assume !(1 == ~t12_pc~0); 83957#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 83955#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83953#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 83951#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83949#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83847#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 83845#L1339-5 assume !(1 == ~T1_E~0); 83843#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82761#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83840#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83838#L1359-3 assume !(1 == ~T5_E~0); 83836#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 83834#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 83832#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83729#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83725#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83723#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 83721#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 83719#L1399-3 assume !(1 == ~E_M~0); 83717#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83715#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 83713#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 83648#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83644#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 83642#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 83640#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 83638#L1439-3 assume !(1 == ~E_8~0); 83636#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 83634#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 83569#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 83567#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 83563#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83490#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83476#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83474#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 83434#L1829 assume !(0 == start_simulation_~tmp~3#1); 83432#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83406#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83395#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83393#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 83373#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83356#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83345#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 83337#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 83331#L1810-2 [2024-11-09 16:08:58,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:58,447 INFO L85 PathProgramCache]: Analyzing trace with hash 1087243328, now seen corresponding path program 1 times [2024-11-09 16:08:58,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:58,448 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554665683] [2024-11-09 16:08:58,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:58,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:58,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:58,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:58,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:58,493 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554665683] [2024-11-09 16:08:58,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [554665683] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:58,494 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:58,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:08:58,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [687120525] [2024-11-09 16:08:58,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:58,494 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:08:58,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:08:58,495 INFO L85 PathProgramCache]: Analyzing trace with hash -1726191326, now seen corresponding path program 1 times [2024-11-09 16:08:58,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:08:58,495 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615233740] [2024-11-09 16:08:58,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:08:58,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:08:58,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:08:58,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:08:58,538 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:08:58,538 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615233740] [2024-11-09 16:08:58,538 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [615233740] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:08:58,538 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:08:58,538 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:08:58,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1875711349] [2024-11-09 16:08:58,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:08:58,539 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:08:58,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:08:58,540 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:08:58,540 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:08:58,540 INFO L87 Difference]: Start difference. First operand 12585 states and 18432 transitions. cyclomatic complexity: 5855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:58,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:08:58,733 INFO L93 Difference]: Finished difference Result 24792 states and 36094 transitions. [2024-11-09 16:08:58,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24792 states and 36094 transitions. [2024-11-09 16:08:59,056 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24552 [2024-11-09 16:08:59,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24792 states to 24792 states and 36094 transitions. [2024-11-09 16:08:59,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24792 [2024-11-09 16:08:59,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24792 [2024-11-09 16:08:59,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24792 states and 36094 transitions. [2024-11-09 16:08:59,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:08:59,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24792 states and 36094 transitions. [2024-11-09 16:08:59,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24792 states and 36094 transitions. [2024-11-09 16:08:59,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24792 to 24072. [2024-11-09 16:08:59,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24072 states, 24072 states have (on average 1.4572116982386174) internal successors, (35078), 24071 states have internal predecessors, (35078), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:08:59,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24072 states to 24072 states and 35078 transitions. [2024-11-09 16:08:59,937 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24072 states and 35078 transitions. [2024-11-09 16:08:59,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:08:59,938 INFO L425 stractBuchiCegarLoop]: Abstraction has 24072 states and 35078 transitions. [2024-11-09 16:08:59,938 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-09 16:08:59,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24072 states and 35078 transitions. [2024-11-09 16:09:00,010 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23832 [2024-11-09 16:09:00,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:00,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:00,013 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:00,013 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:00,013 INFO L745 eck$LassoCheckResult]: Stem: 119114#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 119115#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 120032#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 120033#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 120864#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 120865#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119666#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119443#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118825#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118826#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120167#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 120284#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 121011#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 121012#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 119586#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 119587#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 120195#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 120107#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119624#L1201 assume !(0 == ~M_E~0); 119625#L1201-2 assume !(0 == ~T1_E~0); 120678#L1206-1 assume !(0 == ~T2_E~0); 120645#L1211-1 assume !(0 == ~T3_E~0); 120646#L1216-1 assume !(0 == ~T4_E~0); 119422#L1221-1 assume !(0 == ~T5_E~0); 119423#L1226-1 assume !(0 == ~T6_E~0); 119038#L1231-1 assume !(0 == ~T7_E~0); 119039#L1236-1 assume !(0 == ~T8_E~0); 120726#L1241-1 assume !(0 == ~T9_E~0); 119465#L1246-1 assume !(0 == ~T10_E~0); 119466#L1251-1 assume !(0 == ~T11_E~0); 119622#L1256-1 assume !(0 == ~T12_E~0); 118833#L1261-1 assume !(0 == ~E_M~0); 118834#L1266-1 assume !(0 == ~E_1~0); 120974#L1271-1 assume !(0 == ~E_2~0); 120267#L1276-1 assume !(0 == ~E_3~0); 120268#L1281-1 assume !(0 == ~E_4~0); 120211#L1286-1 assume !(0 == ~E_5~0); 119311#L1291-1 assume !(0 == ~E_6~0); 119312#L1296-1 assume !(0 == ~E_7~0); 119956#L1301-1 assume !(0 == ~E_8~0); 119957#L1306-1 assume !(0 == ~E_9~0); 120554#L1311-1 assume !(0 == ~E_10~0); 119260#L1316-1 assume !(0 == ~E_11~0); 119261#L1321-1 assume !(0 == ~E_12~0); 119979#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119980#L593 assume !(1 == ~m_pc~0); 119138#L593-2 is_master_triggered_~__retres1~0#1 := 0; 119139#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119850#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119851#L1492 assume !(0 != activate_threads_~tmp~1#1); 120224#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120602#L612 assume !(1 == ~t1_pc~0); 120603#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 120860#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120391#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 119142#L1500 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119143#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119603#L631 assume 1 == ~t2_pc~0; 119524#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 118914#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118915#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119276#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 119809#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119218#L650 assume !(1 == ~t3_pc~0); 119219#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 120005#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 118871#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 118872#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120188#L669 assume 1 == ~t4_pc~0; 120189#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 120662#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118954#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118955#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 119075#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119322#L688 assume !(1 == ~t5_pc~0); 119094#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 119095#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 120928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 120055#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 120056#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 120204#L707 assume 1 == ~t6_pc~0; 120792#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 119775#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119262#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119263#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 120139#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119623#L726 assume 1 == ~t7_pc~0; 119512#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 119183#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 120379#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 120802#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 118944#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118945#L745 assume !(1 == ~t8_pc~0); 119415#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 119436#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 120690#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 119861#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 119862#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 120500#L764 assume 1 == ~t9_pc~0; 119621#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 119448#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119341#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 119342#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 118970#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 118971#L783 assume !(1 == ~t10_pc~0); 119026#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 119027#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 119225#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 119574#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 119575#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 120665#L802 assume 1 == ~t11_pc~0; 120633#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 118911#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 118912#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 119424#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 119425#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 119547#L821 assume !(1 == ~t12_pc~0); 119825#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 119945#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 118918#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 118919#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 120744#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 120232#L1339 assume !(1 == ~M_E~0); 120233#L1339-2 assume !(1 == ~T1_E~0); 120807#L1344-1 assume !(1 == ~T2_E~0); 120808#L1349-1 assume !(1 == ~T3_E~0); 119972#L1354-1 assume !(1 == ~T4_E~0); 119973#L1359-1 assume !(1 == ~T5_E~0); 120467#L1364-1 assume !(1 == ~T6_E~0); 119376#L1369-1 assume !(1 == ~T7_E~0); 119377#L1374-1 assume !(1 == ~T8_E~0); 120437#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 122303#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 122301#L1389-1 assume !(1 == ~T11_E~0); 122259#L1394-1 assume !(1 == ~T12_E~0); 122257#L1399-1 assume !(1 == ~E_M~0); 122256#L1404-1 assume !(1 == ~E_1~0); 119472#L1409-1 assume !(1 == ~E_2~0); 119473#L1414-1 assume !(1 == ~E_3~0); 122172#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 122170#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 122167#L1429-1 assume !(1 == ~E_6~0); 122165#L1434-1 assume !(1 == ~E_7~0); 122149#L1439-1 assume !(1 == ~E_8~0); 122133#L1444-1 assume !(1 == ~E_9~0); 122120#L1449-1 assume !(1 == ~E_10~0); 122118#L1454-1 assume !(1 == ~E_11~0); 122108#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 122100#L1464-1 assume { :end_inline_reset_delta_events } true; 122093#L1810-2 [2024-11-09 16:09:00,014 INFO L747 eck$LassoCheckResult]: Loop: 122093#L1810-2 assume !false; 122089#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 122088#L1176-1 assume !false; 122087#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 122084#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 122073#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 122072#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 122071#L1003 assume !(0 != eval_~tmp~0#1); 122070#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 122069#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 122068#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 122067#L1201-5 assume !(0 == ~T1_E~0); 122064#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 122065#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 126621#L1216-3 assume !(0 == ~T4_E~0); 126619#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 126617#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 126615#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 126613#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 126611#L1241-3 assume !(0 == ~T9_E~0); 126609#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 126607#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 126605#L1256-3 assume !(0 == ~T12_E~0); 126603#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 126601#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 126599#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 126597#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 126595#L1281-3 assume !(0 == ~E_4~0); 126593#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 126591#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 126589#L1296-3 assume !(0 == ~E_7~0); 126587#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 126585#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 126583#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 126581#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 126579#L1321-3 assume !(0 == ~E_12~0); 126577#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126575#L593-42 assume !(1 == ~m_pc~0); 126573#L593-44 is_master_triggered_~__retres1~0#1 := 0; 126571#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126569#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126567#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 126565#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126563#L612-42 assume 1 == ~t1_pc~0; 126561#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 126558#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126556#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126553#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 126551#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126549#L631-42 assume !(1 == ~t2_pc~0); 126547#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 126544#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126542#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126539#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 126537#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126535#L650-42 assume 1 == ~t3_pc~0; 126533#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 126530#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126528#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126525#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 126523#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126521#L669-42 assume !(1 == ~t4_pc~0); 126519#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 126516#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126514#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 126511#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126509#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126507#L688-42 assume 1 == ~t5_pc~0; 126505#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126502#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126500#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126497#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 126495#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 126493#L707-42 assume !(1 == ~t6_pc~0); 126491#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 126488#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 126486#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 126483#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 126481#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126479#L726-42 assume !(1 == ~t7_pc~0); 126477#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 126474#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 126472#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 126469#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 126467#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 126465#L745-42 assume 1 == ~t8_pc~0; 126463#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 126460#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 126458#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 126455#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 126453#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 126451#L764-42 assume !(1 == ~t9_pc~0); 126449#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 126446#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 126444#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126441#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 126439#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 126437#L783-42 assume 1 == ~t10_pc~0; 126435#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 126432#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 126430#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126427#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 126425#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126423#L802-42 assume !(1 == ~t11_pc~0); 126421#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 126418#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126416#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 126413#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 126411#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126409#L821-42 assume 1 == ~t12_pc~0; 126403#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 126395#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 126391#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 126387#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 126383#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126379#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 126375#L1339-5 assume !(1 == ~T1_E~0); 126371#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121856#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 126364#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126360#L1359-3 assume !(1 == ~T5_E~0); 126356#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 126352#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 126348#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 126344#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 126338#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 126336#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 126334#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 126332#L1399-3 assume !(1 == ~E_M~0); 126330#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 126328#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 126326#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 126323#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 126319#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 126317#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 126315#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 126313#L1439-3 assume !(1 == ~E_8~0); 126311#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 126309#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 126308#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 122297#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 122293#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 122252#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 122238#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 122236#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 122233#L1829 assume !(0 == start_simulation_~tmp~3#1); 122229#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 122199#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 122164#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 122148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 122132#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 122117#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122107#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 122099#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 122093#L1810-2 [2024-11-09 16:09:00,014 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:00,015 INFO L85 PathProgramCache]: Analyzing trace with hash 1374703233, now seen corresponding path program 1 times [2024-11-09 16:09:00,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:00,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987529706] [2024-11-09 16:09:00,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:00,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:00,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:00,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:00,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:00,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987529706] [2024-11-09 16:09:00,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987529706] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:00,083 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:00,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:00,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194766595] [2024-11-09 16:09:00,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:00,084 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:00,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:00,084 INFO L85 PathProgramCache]: Analyzing trace with hash 52712866, now seen corresponding path program 1 times [2024-11-09 16:09:00,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:00,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689128907] [2024-11-09 16:09:00,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:00,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:00,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:00,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:00,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:00,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [689128907] [2024-11-09 16:09:00,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [689128907] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:00,220 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:00,220 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:00,220 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703472954] [2024-11-09 16:09:00,220 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:00,220 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:00,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:00,221 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:00,221 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:00,221 INFO L87 Difference]: Start difference. First operand 24072 states and 35078 transitions. cyclomatic complexity: 11022 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:00,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:00,593 INFO L93 Difference]: Finished difference Result 24723 states and 35729 transitions. [2024-11-09 16:09:00,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24723 states and 35729 transitions. [2024-11-09 16:09:00,718 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24480 [2024-11-09 16:09:00,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24723 states to 24723 states and 35729 transitions. [2024-11-09 16:09:00,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24723 [2024-11-09 16:09:00,812 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24723 [2024-11-09 16:09:00,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24723 states and 35729 transitions. [2024-11-09 16:09:00,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:00,838 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24723 states and 35729 transitions. [2024-11-09 16:09:00,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24723 states and 35729 transitions. [2024-11-09 16:09:01,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24723 to 24723. [2024-11-09 16:09:01,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24723 states, 24723 states have (on average 1.4451725114266067) internal successors, (35729), 24722 states have internal predecessors, (35729), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:01,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24723 states to 24723 states and 35729 transitions. [2024-11-09 16:09:01,338 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24723 states and 35729 transitions. [2024-11-09 16:09:01,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:01,339 INFO L425 stractBuchiCegarLoop]: Abstraction has 24723 states and 35729 transitions. [2024-11-09 16:09:01,339 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-09 16:09:01,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24723 states and 35729 transitions. [2024-11-09 16:09:01,554 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24480 [2024-11-09 16:09:01,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:01,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:01,558 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:01,558 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:01,559 INFO L745 eck$LassoCheckResult]: Stem: 167916#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 167917#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 168814#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 168815#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169527#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 169528#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 168464#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 168245#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 167629#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 167630#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 168946#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 169056#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 169638#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 169639#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 168386#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 168387#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 168974#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 168889#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 168425#L1201 assume !(0 == ~M_E~0); 168426#L1201-2 assume !(0 == ~T1_E~0); 169398#L1206-1 assume !(0 == ~T2_E~0); 169367#L1211-1 assume !(0 == ~T3_E~0); 169368#L1216-1 assume !(0 == ~T4_E~0); 168222#L1221-1 assume !(0 == ~T5_E~0); 168223#L1226-1 assume !(0 == ~T6_E~0); 167842#L1231-1 assume !(0 == ~T7_E~0); 167843#L1236-1 assume !(0 == ~T8_E~0); 169434#L1241-1 assume !(0 == ~T9_E~0); 168266#L1246-1 assume !(0 == ~T10_E~0); 168267#L1251-1 assume !(0 == ~T11_E~0); 168423#L1256-1 assume !(0 == ~T12_E~0); 167637#L1261-1 assume !(0 == ~E_M~0); 167638#L1266-1 assume !(0 == ~E_1~0); 169611#L1271-1 assume !(0 == ~E_2~0); 169039#L1276-1 assume !(0 == ~E_3~0); 169040#L1281-1 assume !(0 == ~E_4~0); 168990#L1286-1 assume !(0 == ~E_5~0); 168112#L1291-1 assume !(0 == ~E_6~0); 168113#L1296-1 assume !(0 == ~E_7~0); 168745#L1301-1 assume !(0 == ~E_8~0); 168746#L1306-1 assume !(0 == ~E_9~0); 169287#L1311-1 assume !(0 == ~E_10~0); 168063#L1316-1 assume !(0 == ~E_11~0); 168064#L1321-1 assume !(0 == ~E_12~0); 168766#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168767#L593 assume !(1 == ~m_pc~0); 167940#L593-2 is_master_triggered_~__retres1~0#1 := 0; 167941#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 168639#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 168640#L1492 assume !(0 != activate_threads_~tmp~1#1); 169001#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169328#L612 assume !(1 == ~t1_pc~0); 169329#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169630#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169149#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 167944#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 167945#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 168403#L631 assume 1 == ~t2_pc~0; 168324#L632 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 167718#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 167719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 168077#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 168599#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168021#L650 assume !(1 == ~t3_pc~0); 168022#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 168789#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169125#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 167675#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 167676#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168967#L669 assume 1 == ~t4_pc~0; 168968#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 169381#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 167758#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 167759#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 167879#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 168125#L688 assume !(1 == ~t5_pc~0); 167898#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 167899#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169574#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 168837#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 168838#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 168984#L707 assume 1 == ~t6_pc~0; 169476#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 168567#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168065#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 168066#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 168919#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 168424#L726 assume 1 == ~t7_pc~0; 168312#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 167986#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169138#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 169483#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 167748#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 167749#L745 assume !(1 == ~t8_pc~0); 168215#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 168238#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 169406#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 168648#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 168649#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 169241#L764 assume 1 == ~t9_pc~0; 168422#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 168249#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 168143#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 168144#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 167774#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 167775#L783 assume !(1 == ~t10_pc~0); 167830#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 167831#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 168028#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 168375#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 168376#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 169384#L802 assume 1 == ~t11_pc~0; 169355#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 167715#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 167716#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168224#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 168225#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168347#L821 assume !(1 == ~t12_pc~0); 168614#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 168736#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 167722#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 167723#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 169445#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169009#L1339 assume !(1 == ~M_E~0); 169010#L1339-2 assume !(1 == ~T1_E~0); 169487#L1344-1 assume !(1 == ~T2_E~0); 169488#L1349-1 assume !(1 == ~T3_E~0); 168759#L1354-1 assume !(1 == ~T4_E~0); 168760#L1359-1 assume !(1 == ~T5_E~0); 169214#L1364-1 assume !(1 == ~T6_E~0); 179624#L1369-1 assume !(1 == ~T7_E~0); 179621#L1374-1 assume !(1 == ~T8_E~0); 179619#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 168885#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 168886#L1389-1 assume !(1 == ~T11_E~0); 169439#L1394-1 assume !(1 == ~T12_E~0); 169440#L1399-1 assume !(1 == ~E_M~0); 169564#L1404-1 assume !(1 == ~E_1~0); 168273#L1409-1 assume !(1 == ~E_2~0); 168274#L1414-1 assume !(1 == ~E_3~0); 169076#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 169077#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 182921#L1429-1 assume !(1 == ~E_6~0); 182919#L1434-1 assume !(1 == ~E_7~0); 182917#L1439-1 assume !(1 == ~E_8~0); 182915#L1444-1 assume !(1 == ~E_9~0); 182913#L1449-1 assume !(1 == ~E_10~0); 182911#L1454-1 assume !(1 == ~E_11~0); 182907#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 182904#L1464-1 assume { :end_inline_reset_delta_events } true; 182902#L1810-2 [2024-11-09 16:09:01,559 INFO L747 eck$LassoCheckResult]: Loop: 182902#L1810-2 assume !false; 181546#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179226#L1176-1 assume !false; 179223#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 179219#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 179207#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 179203#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 179198#L1003 assume !(0 != eval_~tmp~0#1); 179199#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 192315#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 192313#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 192311#L1201-5 assume !(0 == ~T1_E~0); 192309#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 192307#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 192305#L1216-3 assume !(0 == ~T4_E~0); 192304#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 192303#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 192302#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 192301#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 192300#L1241-3 assume !(0 == ~T9_E~0); 192299#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 192298#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 192297#L1256-3 assume !(0 == ~T12_E~0); 192296#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 192295#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 192294#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 168547#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 168495#L1281-3 assume !(0 == ~E_4~0); 168496#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 169073#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 169074#L1296-3 assume !(0 == ~E_7~0); 169631#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 169554#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 168605#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 167955#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 167956#L1321-3 assume !(0 == ~E_12~0); 191991#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 191990#L593-42 assume !(1 == ~m_pc~0); 191989#L593-44 is_master_triggered_~__retres1~0#1 := 0; 191988#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 191987#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 191986#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 191985#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191984#L612-42 assume 1 == ~t1_pc~0; 191982#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 191980#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191978#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 191976#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 191975#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191974#L631-42 assume 1 == ~t2_pc~0; 191972#L632-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 191971#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191970#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 191969#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 191968#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 191967#L650-42 assume 1 == ~t3_pc~0; 191966#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 191964#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191963#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 191962#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 191961#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 191960#L669-42 assume 1 == ~t4_pc~0; 191958#L670-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 191957#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 191956#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 191955#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 191954#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 191953#L688-42 assume 1 == ~t5_pc~0; 191952#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 191950#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 191949#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 191948#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 191947#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 191946#L707-42 assume 1 == ~t6_pc~0; 191944#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 191943#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191942#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 191941#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 191940#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 191939#L726-42 assume !(1 == ~t7_pc~0); 191938#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 191936#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 170876#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 170875#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 170873#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 170874#L745-42 assume !(1 == ~t8_pc~0); 170867#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 170868#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 191933#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 191932#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 191931#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 191930#L764-42 assume 1 == ~t9_pc~0; 191928#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 191927#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 191926#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 191925#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 191924#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 191923#L783-42 assume !(1 == ~t10_pc~0); 170806#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 170807#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 191840#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 191839#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 191838#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 191837#L802-42 assume 1 == ~t11_pc~0; 191835#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 191834#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 191833#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 191832#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 191831#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 191830#L821-42 assume !(1 == ~t12_pc~0); 191828#L821-44 is_transmit12_triggered_~__retres1~12#1 := 0; 191827#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 168731#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 168732#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 191436#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 191422#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 191420#L1339-5 assume !(1 == ~T1_E~0); 191418#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 169018#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 168308#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 168309#L1359-3 assume !(1 == ~T5_E~0); 191413#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 189328#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 189279#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 189278#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 168122#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 189277#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 189276#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 189275#L1399-3 assume !(1 == ~E_M~0); 189274#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 189273#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 189272#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 189271#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 188642#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189270#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189269#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 189268#L1439-3 assume !(1 == ~E_8~0); 189267#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 189266#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 189264#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 189261#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 185076#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 189258#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 189244#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 168024#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 168025#L1829 assume !(0 == start_simulation_~tmp~3#1); 184470#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 182959#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 182947#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 182945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 182943#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 182940#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 182938#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 182903#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 182902#L1810-2 [2024-11-09 16:09:01,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:01,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1568878845, now seen corresponding path program 1 times [2024-11-09 16:09:01,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:01,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266485029] [2024-11-09 16:09:01,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:01,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:01,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:01,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:01,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:01,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266485029] [2024-11-09 16:09:01,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266485029] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:01,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:01,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:01,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754104405] [2024-11-09 16:09:01,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:01,629 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:01,630 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:01,630 INFO L85 PathProgramCache]: Analyzing trace with hash -783594848, now seen corresponding path program 1 times [2024-11-09 16:09:01,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:01,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529149651] [2024-11-09 16:09:01,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:01,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:01,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:01,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:01,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:01,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529149651] [2024-11-09 16:09:01,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529149651] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:01,699 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:01,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:01,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139870391] [2024-11-09 16:09:01,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:01,701 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:01,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:01,702 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:01,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:01,702 INFO L87 Difference]: Start difference. First operand 24723 states and 35729 transitions. cyclomatic complexity: 11022 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:01,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:01,982 INFO L93 Difference]: Finished difference Result 47474 states and 68320 transitions. [2024-11-09 16:09:01,982 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47474 states and 68320 transitions. [2024-11-09 16:09:02,344 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 47184 [2024-11-09 16:09:02,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47474 states to 47474 states and 68320 transitions. [2024-11-09 16:09:02,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47474 [2024-11-09 16:09:02,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47474 [2024-11-09 16:09:02,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47474 states and 68320 transitions. [2024-11-09 16:09:02,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:02,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 47474 states and 68320 transitions. [2024-11-09 16:09:02,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47474 states and 68320 transitions. [2024-11-09 16:09:03,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47474 to 47442. [2024-11-09 16:09:03,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47442 states, 47442 states have (on average 1.4393996880401332) internal successors, (68288), 47441 states have internal predecessors, (68288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:03,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47442 states to 47442 states and 68288 transitions. [2024-11-09 16:09:03,290 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47442 states and 68288 transitions. [2024-11-09 16:09:03,290 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:03,291 INFO L425 stractBuchiCegarLoop]: Abstraction has 47442 states and 68288 transitions. [2024-11-09 16:09:03,292 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-09 16:09:03,292 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47442 states and 68288 transitions. [2024-11-09 16:09:03,609 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 47152 [2024-11-09 16:09:03,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:03,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:03,612 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:03,612 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:03,613 INFO L745 eck$LassoCheckResult]: Stem: 240120#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 240121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 241020#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 241021#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 241747#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 241748#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 240673#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 240453#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 239833#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 239834#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 241147#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 241267#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 241900#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 241901#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 240596#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 240597#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 241178#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 241089#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 240634#L1201 assume !(0 == ~M_E~0); 240635#L1201-2 assume !(0 == ~T1_E~0); 241608#L1206-1 assume !(0 == ~T2_E~0); 241582#L1211-1 assume !(0 == ~T3_E~0); 241583#L1216-1 assume !(0 == ~T4_E~0); 240435#L1221-1 assume !(0 == ~T5_E~0); 240436#L1226-1 assume !(0 == ~T6_E~0); 240044#L1231-1 assume !(0 == ~T7_E~0); 240045#L1236-1 assume !(0 == ~T8_E~0); 241639#L1241-1 assume !(0 == ~T9_E~0); 240479#L1246-1 assume !(0 == ~T10_E~0); 240480#L1251-1 assume !(0 == ~T11_E~0); 240632#L1256-1 assume !(0 == ~T12_E~0); 239841#L1261-1 assume !(0 == ~E_M~0); 239842#L1266-1 assume !(0 == ~E_1~0); 241858#L1271-1 assume !(0 == ~E_2~0); 241250#L1276-1 assume !(0 == ~E_3~0); 241251#L1281-1 assume !(0 == ~E_4~0); 241191#L1286-1 assume !(0 == ~E_5~0); 240318#L1291-1 assume !(0 == ~E_6~0); 240319#L1296-1 assume !(0 == ~E_7~0); 240947#L1301-1 assume !(0 == ~E_8~0); 240948#L1306-1 assume !(0 == ~E_9~0); 241505#L1311-1 assume !(0 == ~E_10~0); 240268#L1316-1 assume !(0 == ~E_11~0); 240269#L1321-1 assume !(0 == ~E_12~0); 240972#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 240973#L593 assume !(1 == ~m_pc~0); 240144#L593-2 is_master_triggered_~__retres1~0#1 := 0; 240145#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 240845#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 240846#L1492 assume !(0 != activate_threads_~tmp~1#1); 241205#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 241547#L612 assume !(1 == ~t1_pc~0); 241548#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 241882#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 241363#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 240148#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 240149#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 240612#L631 assume !(1 == ~t2_pc~0); 240613#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 239921#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 240282#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 240806#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240228#L650 assume !(1 == ~t3_pc~0); 240229#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 240995#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 239879#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 239880#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 241171#L669 assume 1 == ~t4_pc~0; 241172#L670 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 241596#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 239965#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 239966#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 240081#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 240334#L688 assume !(1 == ~t5_pc~0); 240102#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 240103#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 241812#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 241042#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 241043#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 241188#L707 assume 1 == ~t6_pc~0; 241690#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 240775#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 240270#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 240271#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 241124#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 240633#L726 assume 1 == ~t7_pc~0; 240527#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 240191#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 241351#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 241698#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 239951#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 239952#L745 assume !(1 == ~t8_pc~0); 240427#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 240447#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 241614#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 240854#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 240855#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 241457#L764 assume 1 == ~t9_pc~0; 240631#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 240457#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 240352#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 240353#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 239977#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 239978#L783 assume !(1 == ~t10_pc~0); 240032#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 240033#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 240233#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 240590#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 240591#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 241597#L802 assume 1 == ~t11_pc~0; 241571#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 239918#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 239919#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 240437#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 240438#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 240559#L821 assume !(1 == ~t12_pc~0); 240822#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 240937#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 239927#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 239928#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 241653#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 241217#L1339 assume !(1 == ~M_E~0); 241218#L1339-2 assume !(1 == ~T1_E~0); 241701#L1344-1 assume !(1 == ~T2_E~0); 241702#L1349-1 assume !(1 == ~T3_E~0); 246251#L1354-1 assume !(1 == ~T4_E~0); 246250#L1359-1 assume !(1 == ~T5_E~0); 241884#L1364-1 assume !(1 == ~T6_E~0); 241885#L1369-1 assume !(1 == ~T7_E~0); 246085#L1374-1 assume !(1 == ~T8_E~0); 240969#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 240970#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 241084#L1389-1 assume !(1 == ~T11_E~0); 245916#L1394-1 assume !(1 == ~T12_E~0); 245914#L1399-1 assume !(1 == ~E_M~0); 245912#L1404-1 assume !(1 == ~E_1~0); 245910#L1409-1 assume !(1 == ~E_2~0); 245873#L1414-1 assume !(1 == ~E_3~0); 245868#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 245866#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 245814#L1429-1 assume !(1 == ~E_6~0); 245800#L1434-1 assume !(1 == ~E_7~0); 245760#L1439-1 assume !(1 == ~E_8~0); 245746#L1444-1 assume !(1 == ~E_9~0); 245722#L1449-1 assume !(1 == ~E_10~0); 245705#L1454-1 assume !(1 == ~E_11~0); 245694#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 245686#L1464-1 assume { :end_inline_reset_delta_events } true; 245679#L1810-2 [2024-11-09 16:09:03,613 INFO L747 eck$LassoCheckResult]: Loop: 245679#L1810-2 assume !false; 245675#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 245674#L1176-1 assume !false; 245673#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 245670#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 245659#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 245658#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 245656#L1003 assume !(0 != eval_~tmp~0#1); 245655#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 245654#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 245653#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 245652#L1201-5 assume !(0 == ~T1_E~0); 245649#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 245650#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 248842#L1216-3 assume !(0 == ~T4_E~0); 248510#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 248431#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 248429#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 248427#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 248425#L1241-3 assume !(0 == ~T9_E~0); 248423#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 248421#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 248419#L1256-3 assume !(0 == ~T12_E~0); 248417#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 248355#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 248294#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 248292#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 248291#L1281-3 assume !(0 == ~E_4~0); 248289#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 248228#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 248226#L1296-3 assume !(0 == ~E_7~0); 248224#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 248221#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 248219#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 248200#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 248191#L1321-3 assume !(0 == ~E_12~0); 248061#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 248059#L593-42 assume !(1 == ~m_pc~0); 248057#L593-44 is_master_triggered_~__retres1~0#1 := 0; 248055#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 248052#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 248050#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 248048#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 248046#L612-42 assume 1 == ~t1_pc~0; 248043#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 248041#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 248039#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247852#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 247849#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247847#L631-42 assume !(1 == ~t2_pc~0); 247845#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 247843#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247495#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247493#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 247490#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247488#L650-42 assume 1 == ~t3_pc~0; 247485#L651-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 247483#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247482#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 247481#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247480#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247479#L669-42 assume !(1 == ~t4_pc~0); 247478#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 247476#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247474#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 247472#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 247470#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247468#L688-42 assume 1 == ~t5_pc~0; 247466#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 247463#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247460#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 247253#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 247251#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 247249#L707-42 assume !(1 == ~t6_pc~0); 247246#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 247243#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247241#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 247239#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 247237#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 247235#L726-42 assume !(1 == ~t7_pc~0); 247232#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 247229#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 247227#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 247225#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 247223#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247221#L745-42 assume 1 == ~t8_pc~0; 247218#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 247215#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 247213#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 247211#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 247209#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 247207#L764-42 assume 1 == ~t9_pc~0; 247203#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 246819#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 246817#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 246815#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 246813#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 246811#L783-42 assume !(1 == ~t10_pc~0); 246807#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 246805#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 246573#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 246571#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 246569#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 246568#L802-42 assume !(1 == ~t11_pc~0); 246566#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 246563#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 246560#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 246558#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 246556#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 246554#L821-42 assume 1 == ~t12_pc~0; 246353#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 246350#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 246348#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 246346#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 246344#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 246342#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 246340#L1339-5 assume !(1 == ~T1_E~0); 246338#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 241227#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 246335#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 246333#L1359-3 assume !(1 == ~T5_E~0); 246330#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 246328#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 246326#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 246191#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 246187#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 246185#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 246026#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 246024#L1399-3 assume !(1 == ~E_M~0); 246022#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 246020#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 246018#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 246017#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 246013#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 246011#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 245926#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 245922#L1439-3 assume !(1 == ~E_8~0); 245920#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 245918#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 245874#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 245872#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 245815#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 245813#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 245799#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 245798#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 245795#L1829 assume !(0 == start_simulation_~tmp~3#1); 245792#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 245757#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 245723#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 245721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 245717#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 245704#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 245693#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 245685#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 245679#L1810-2 [2024-11-09 16:09:03,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:03,614 INFO L85 PathProgramCache]: Analyzing trace with hash -451693884, now seen corresponding path program 1 times [2024-11-09 16:09:03,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:03,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816282826] [2024-11-09 16:09:03,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:03,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:03,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:03,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:03,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:03,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816282826] [2024-11-09 16:09:03,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816282826] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:03,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:03,680 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:03,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889264855] [2024-11-09 16:09:03,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:03,681 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:03,681 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:03,682 INFO L85 PathProgramCache]: Analyzing trace with hash -283948446, now seen corresponding path program 1 times [2024-11-09 16:09:03,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:03,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757866144] [2024-11-09 16:09:03,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:03,682 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:03,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:03,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:03,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:03,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757866144] [2024-11-09 16:09:03,744 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757866144] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:03,744 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:03,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:03,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464400792] [2024-11-09 16:09:03,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:03,745 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:03,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:03,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:03,746 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:03,746 INFO L87 Difference]: Start difference. First operand 47442 states and 68288 transitions. cyclomatic complexity: 20878 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:04,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:04,304 INFO L93 Difference]: Finished difference Result 91201 states and 130769 transitions. [2024-11-09 16:09:04,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91201 states and 130769 transitions. [2024-11-09 16:09:04,770 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 90784 [2024-11-09 16:09:05,006 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91201 states to 91201 states and 130769 transitions. [2024-11-09 16:09:05,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91201 [2024-11-09 16:09:05,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91201 [2024-11-09 16:09:05,207 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91201 states and 130769 transitions. [2024-11-09 16:09:05,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:05,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91201 states and 130769 transitions. [2024-11-09 16:09:05,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91201 states and 130769 transitions. [2024-11-09 16:09:06,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91201 to 91137. [2024-11-09 16:09:06,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91137 states, 91137 states have (on average 1.434159561978121) internal successors, (130705), 91136 states have internal predecessors, (130705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:06,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91137 states to 91137 states and 130705 transitions. [2024-11-09 16:09:06,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 91137 states and 130705 transitions. [2024-11-09 16:09:06,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:06,946 INFO L425 stractBuchiCegarLoop]: Abstraction has 91137 states and 130705 transitions. [2024-11-09 16:09:06,947 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-09 16:09:06,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91137 states and 130705 transitions. [2024-11-09 16:09:07,176 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 90720 [2024-11-09 16:09:07,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:07,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:07,180 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:07,180 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:07,180 INFO L745 eck$LassoCheckResult]: Stem: 378769#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 378770#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 379645#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 379646#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 380353#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 380354#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 379307#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 379091#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 378483#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 378484#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 379775#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 379881#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 380458#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 380459#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 379227#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 379228#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 379802#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 379718#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 379268#L1201 assume !(0 == ~M_E~0); 379269#L1201-2 assume !(0 == ~T1_E~0); 380212#L1206-1 assume !(0 == ~T2_E~0); 380184#L1211-1 assume !(0 == ~T3_E~0); 380185#L1216-1 assume !(0 == ~T4_E~0); 379071#L1221-1 assume !(0 == ~T5_E~0); 379072#L1226-1 assume !(0 == ~T6_E~0); 378695#L1231-1 assume !(0 == ~T7_E~0); 378696#L1236-1 assume !(0 == ~T8_E~0); 380254#L1241-1 assume !(0 == ~T9_E~0); 379112#L1246-1 assume !(0 == ~T10_E~0); 379113#L1251-1 assume !(0 == ~T11_E~0); 379266#L1256-1 assume !(0 == ~T12_E~0); 378492#L1261-1 assume !(0 == ~E_M~0); 378493#L1266-1 assume !(0 == ~E_1~0); 380430#L1271-1 assume !(0 == ~E_2~0); 379864#L1276-1 assume !(0 == ~E_3~0); 379865#L1281-1 assume !(0 == ~E_4~0); 379815#L1286-1 assume !(0 == ~E_5~0); 378963#L1291-1 assume !(0 == ~E_6~0); 378964#L1296-1 assume !(0 == ~E_7~0); 379582#L1301-1 assume !(0 == ~E_8~0); 379583#L1306-1 assume !(0 == ~E_9~0); 380110#L1311-1 assume !(0 == ~E_10~0); 378913#L1316-1 assume !(0 == ~E_11~0); 378914#L1321-1 assume !(0 == ~E_12~0); 379601#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 379602#L593 assume !(1 == ~m_pc~0); 378793#L593-2 is_master_triggered_~__retres1~0#1 := 0; 378794#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 379477#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 379478#L1492 assume !(0 != activate_threads_~tmp~1#1); 379827#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 380151#L612 assume !(1 == ~t1_pc~0); 380152#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 380446#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 379969#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 378797#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 378798#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 379244#L631 assume !(1 == ~t2_pc~0); 379245#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 378572#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 378573#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 378927#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 379438#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 378874#L650 assume !(1 == ~t3_pc~0); 378875#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 379625#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 379949#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 378530#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 378531#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 379796#L669 assume !(1 == ~t4_pc~0); 379797#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 380197#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 378612#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 378613#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 378732#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 378974#L688 assume !(1 == ~t5_pc~0); 378751#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 378752#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 380398#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 379667#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 379668#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 379809#L707 assume 1 == ~t6_pc~0; 380303#L708 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 379407#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 378915#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 378916#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 379748#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379267#L726 assume 1 == ~t7_pc~0; 379158#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 378839#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 379960#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 380309#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 378602#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 378603#L745 assume !(1 == ~t8_pc~0); 379064#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 379085#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 380224#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 379486#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 379487#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 380062#L764 assume 1 == ~t9_pc~0; 379265#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 379095#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 378992#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 378993#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 378628#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 378629#L783 assume !(1 == ~t10_pc~0); 378683#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 378684#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 378881#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 379216#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 379217#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 380199#L802 assume 1 == ~t11_pc~0; 380176#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 378569#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 378570#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 379073#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 379074#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 379191#L821 assume !(1 == ~t12_pc~0); 379453#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 379570#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 378576#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 378577#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 380267#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 379835#L1339 assume !(1 == ~M_E~0); 379836#L1339-2 assume !(1 == ~T1_E~0); 380315#L1344-1 assume !(1 == ~T2_E~0); 380316#L1349-1 assume !(1 == ~T3_E~0); 398141#L1354-1 assume !(1 == ~T4_E~0); 398139#L1359-1 assume !(1 == ~T5_E~0); 398137#L1364-1 assume !(1 == ~T6_E~0); 398134#L1369-1 assume !(1 == ~T7_E~0); 398132#L1374-1 assume !(1 == ~T8_E~0); 398129#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 398127#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 398125#L1389-1 assume !(1 == ~T11_E~0); 398123#L1394-1 assume !(1 == ~T12_E~0); 398120#L1399-1 assume !(1 == ~E_M~0); 398118#L1404-1 assume !(1 == ~E_1~0); 398116#L1409-1 assume !(1 == ~E_2~0); 398114#L1414-1 assume !(1 == ~E_3~0); 398111#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 398112#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 399039#L1429-1 assume !(1 == ~E_6~0); 397011#L1434-1 assume !(1 == ~E_7~0); 397008#L1439-1 assume !(1 == ~E_8~0); 397005#L1444-1 assume !(1 == ~E_9~0); 396894#L1449-1 assume !(1 == ~E_10~0); 396874#L1454-1 assume !(1 == ~E_11~0); 396863#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 379746#L1464-1 assume { :end_inline_reset_delta_events } true; 379747#L1810-2 [2024-11-09 16:09:07,181 INFO L747 eck$LassoCheckResult]: Loop: 379747#L1810-2 assume !false; 417163#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 417159#L1176-1 assume !false; 417157#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 417128#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 417117#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 414056#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 414008#L1003 assume !(0 != eval_~tmp~0#1); 414009#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 419125#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 419122#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 419118#L1201-5 assume !(0 == ~T1_E~0); 419115#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 419112#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 419108#L1216-3 assume !(0 == ~T4_E~0); 419104#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 419097#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 419094#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 419092#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 419090#L1241-3 assume !(0 == ~T9_E~0); 419088#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 419086#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 419084#L1256-3 assume !(0 == ~T12_E~0); 419082#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 419080#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 419078#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 419075#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 419073#L1281-3 assume !(0 == ~E_4~0); 419071#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 419069#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 419067#L1296-3 assume !(0 == ~E_7~0); 419065#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 419062#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 419059#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 419056#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 419053#L1321-3 assume !(0 == ~E_12~0); 419050#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 419047#L593-42 assume !(1 == ~m_pc~0); 419043#L593-44 is_master_triggered_~__retres1~0#1 := 0; 419039#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 419035#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 419031#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 419027#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 419024#L612-42 assume !(1 == ~t1_pc~0); 419020#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 419016#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 419012#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 419008#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 419004#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 419002#L631-42 assume !(1 == ~t2_pc~0); 419000#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 418997#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 418995#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 418993#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 418990#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 418987#L650-42 assume !(1 == ~t3_pc~0); 418983#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 418978#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 418974#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 418969#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 418964#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 418958#L669-42 assume !(1 == ~t4_pc~0); 418952#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 418945#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 418938#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 418932#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 418925#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 418918#L688-42 assume 1 == ~t5_pc~0; 418912#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 418904#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 418898#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 418892#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 418886#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 418879#L707-42 assume 1 == ~t6_pc~0; 418872#L708-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 418865#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 418858#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 418850#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 418841#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 418832#L726-42 assume 1 == ~t7_pc~0; 418823#L727-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 418815#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 418808#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 418801#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 418792#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 418783#L745-42 assume !(1 == ~t8_pc~0); 418774#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 418765#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 418757#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 418749#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 418741#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 418733#L764-42 assume !(1 == ~t9_pc~0); 418726#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 418717#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 418709#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 418701#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 418692#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 418685#L783-42 assume !(1 == ~t10_pc~0); 418678#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 418672#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 418665#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 418658#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 418650#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 418643#L802-42 assume !(1 == ~t11_pc~0); 418636#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 418628#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 418620#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 418612#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 418603#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 418595#L821-42 assume 1 == ~t12_pc~0; 418588#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 418579#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 418570#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 418561#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 418551#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 418543#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 418536#L1339-5 assume !(1 == ~T1_E~0); 418529#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 398528#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 418514#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 418505#L1359-3 assume !(1 == ~T5_E~0); 418497#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 418490#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 418482#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 418474#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 409564#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 418458#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 418451#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 418445#L1399-3 assume !(1 == ~E_M~0); 418438#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 418431#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 418424#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 418413#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 411937#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 418400#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 418391#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 418385#L1439-3 assume !(1 == ~E_8~0); 418380#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 418374#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 418367#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 418360#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 398475#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 418198#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 418181#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 418177#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 418173#L1829 assume !(0 == start_simulation_~tmp~3#1); 418168#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 417302#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 417290#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 417288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 417191#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 417187#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 417185#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 417183#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 379747#L1810-2 [2024-11-09 16:09:07,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:07,182 INFO L85 PathProgramCache]: Analyzing trace with hash 1008300037, now seen corresponding path program 1 times [2024-11-09 16:09:07,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:07,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256927016] [2024-11-09 16:09:07,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:07,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:07,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:07,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:07,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:07,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256927016] [2024-11-09 16:09:07,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256927016] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:07,235 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:07,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:07,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799191497] [2024-11-09 16:09:07,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:07,235 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:07,236 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:07,236 INFO L85 PathProgramCache]: Analyzing trace with hash 597135206, now seen corresponding path program 1 times [2024-11-09 16:09:07,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:07,236 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488954685] [2024-11-09 16:09:07,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:07,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:07,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:07,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:07,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:07,284 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [488954685] [2024-11-09 16:09:07,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [488954685] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:07,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:07,285 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:07,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324086014] [2024-11-09 16:09:07,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:07,285 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:07,286 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:07,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:07,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:07,287 INFO L87 Difference]: Start difference. First operand 91137 states and 130705 transitions. cyclomatic complexity: 39632 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:08,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:08,154 INFO L93 Difference]: Finished difference Result 175200 states and 250358 transitions. [2024-11-09 16:09:08,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 175200 states and 250358 transitions. [2024-11-09 16:09:08,731 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 174464 [2024-11-09 16:09:09,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 175200 states to 175200 states and 250358 transitions. [2024-11-09 16:09:09,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 175200 [2024-11-09 16:09:09,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 175200 [2024-11-09 16:09:09,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 175200 states and 250358 transitions. [2024-11-09 16:09:09,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:09,665 INFO L218 hiAutomatonCegarLoop]: Abstraction has 175200 states and 250358 transitions. [2024-11-09 16:09:09,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175200 states and 250358 transitions. [2024-11-09 16:09:11,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175200 to 175072. [2024-11-09 16:09:11,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 175072 states, 175072 states have (on average 1.4292976603911534) internal successors, (250230), 175071 states have internal predecessors, (250230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:12,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175072 states to 175072 states and 250230 transitions. [2024-11-09 16:09:12,158 INFO L240 hiAutomatonCegarLoop]: Abstraction has 175072 states and 250230 transitions. [2024-11-09 16:09:12,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:12,158 INFO L425 stractBuchiCegarLoop]: Abstraction has 175072 states and 250230 transitions. [2024-11-09 16:09:12,158 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-09 16:09:12,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 175072 states and 250230 transitions. [2024-11-09 16:09:13,149 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 174336 [2024-11-09 16:09:13,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:13,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:13,154 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,154 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,154 INFO L745 eck$LassoCheckResult]: Stem: 645116#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 645117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 645999#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 646000#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 646713#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 646714#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 645658#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 645438#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 644827#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 644828#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 646127#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 646237#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 646811#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 646812#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 645576#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 645577#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 646155#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 646068#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 645614#L1201 assume !(0 == ~M_E~0); 645615#L1201-2 assume !(0 == ~T1_E~0); 646577#L1206-1 assume !(0 == ~T2_E~0); 646554#L1211-1 assume !(0 == ~T3_E~0); 646555#L1216-1 assume !(0 == ~T4_E~0); 645419#L1221-1 assume !(0 == ~T5_E~0); 645420#L1226-1 assume !(0 == ~T6_E~0); 645040#L1231-1 assume !(0 == ~T7_E~0); 645041#L1236-1 assume !(0 == ~T8_E~0); 646611#L1241-1 assume !(0 == ~T9_E~0); 645462#L1246-1 assume !(0 == ~T10_E~0); 645463#L1251-1 assume !(0 == ~T11_E~0); 645612#L1256-1 assume !(0 == ~T12_E~0); 644835#L1261-1 assume !(0 == ~E_M~0); 644836#L1266-1 assume !(0 == ~E_1~0); 646785#L1271-1 assume !(0 == ~E_2~0); 646219#L1276-1 assume !(0 == ~E_3~0); 646220#L1281-1 assume !(0 == ~E_4~0); 646167#L1286-1 assume !(0 == ~E_5~0); 645309#L1291-1 assume !(0 == ~E_6~0); 645310#L1296-1 assume !(0 == ~E_7~0); 645932#L1301-1 assume !(0 == ~E_8~0); 645933#L1306-1 assume !(0 == ~E_9~0); 646475#L1311-1 assume !(0 == ~E_10~0); 645260#L1316-1 assume !(0 == ~E_11~0); 645261#L1321-1 assume !(0 == ~E_12~0); 645952#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 645953#L593 assume !(1 == ~m_pc~0); 645140#L593-2 is_master_triggered_~__retres1~0#1 := 0; 645141#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 645827#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 645828#L1492 assume !(0 != activate_threads_~tmp~1#1); 646178#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 646518#L612 assume !(1 == ~t1_pc~0); 646519#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 646805#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 646324#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 645144#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 645145#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 645592#L631 assume !(1 == ~t2_pc~0); 645593#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 644915#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 644916#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 645274#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 645788#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 645223#L650 assume !(1 == ~t3_pc~0); 645224#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 645975#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 646300#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 644873#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 644874#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 646149#L669 assume !(1 == ~t4_pc~0); 646150#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 646565#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 644959#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 644960#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 645077#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 645320#L688 assume !(1 == ~t5_pc~0); 645098#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 645099#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 646752#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 646021#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 646022#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 646165#L707 assume !(1 == ~t6_pc~0); 646401#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 645755#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 645262#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 645263#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 646103#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 645613#L726 assume 1 == ~t7_pc~0; 645508#L727 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 645185#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 646315#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 646670#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 644945#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 644946#L745 assume !(1 == ~t8_pc~0); 645411#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 645432#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 646585#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 645836#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 645837#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 646420#L764 assume 1 == ~t9_pc~0; 645611#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 645442#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 645339#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 645340#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 644971#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 644972#L783 assume !(1 == ~t10_pc~0); 645027#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 645028#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 645228#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 645571#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 645572#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 646566#L802 assume 1 == ~t11_pc~0; 646542#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 644912#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 644913#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 645421#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 645422#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 645539#L821 assume !(1 == ~t12_pc~0); 645803#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 645923#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 644921#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 644922#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 646624#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 646188#L1339 assume !(1 == ~M_E~0); 646189#L1339-2 assume !(1 == ~T1_E~0); 646674#L1344-1 assume !(1 == ~T2_E~0); 646675#L1349-1 assume !(1 == ~T3_E~0); 645946#L1354-1 assume !(1 == ~T4_E~0); 645947#L1359-1 assume !(1 == ~T5_E~0); 655381#L1364-1 assume !(1 == ~T6_E~0); 655378#L1369-1 assume !(1 == ~T7_E~0); 655376#L1374-1 assume !(1 == ~T8_E~0); 655373#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 655374#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 663083#L1389-1 assume !(1 == ~T11_E~0); 663081#L1394-1 assume !(1 == ~T12_E~0); 663079#L1399-1 assume !(1 == ~E_M~0); 663076#L1404-1 assume !(1 == ~E_1~0); 663072#L1409-1 assume !(1 == ~E_2~0); 663070#L1414-1 assume !(1 == ~E_3~0); 663069#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 645088#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 645089#L1429-1 assume !(1 == ~E_6~0); 645960#L1434-1 assume !(1 == ~E_7~0); 646639#L1439-1 assume !(1 == ~E_8~0); 646826#L1444-1 assume !(1 == ~E_9~0); 664743#L1449-1 assume !(1 == ~E_10~0); 664740#L1454-1 assume !(1 == ~E_11~0); 646667#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 646668#L1464-1 assume { :end_inline_reset_delta_events } true; 664696#L1810-2 [2024-11-09 16:09:13,155 INFO L747 eck$LassoCheckResult]: Loop: 664696#L1810-2 assume !false; 664604#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 664602#L1176-1 assume !false; 664600#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 664596#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 664583#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 664531#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 664522#L1003 assume !(0 != eval_~tmp~0#1); 664523#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 666771#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 666769#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 666767#L1201-5 assume !(0 == ~T1_E~0); 666765#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 666762#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 666760#L1216-3 assume !(0 == ~T4_E~0); 666758#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 666756#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 666754#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 666738#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 666733#L1241-3 assume !(0 == ~T9_E~0); 666728#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 666724#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 666720#L1256-3 assume !(0 == ~T12_E~0); 666716#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 666712#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 666707#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 666703#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 666699#L1281-3 assume !(0 == ~E_4~0); 666695#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 666691#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 666688#L1296-3 assume !(0 == ~E_7~0); 666685#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 666680#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 666676#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 666672#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 666668#L1321-3 assume !(0 == ~E_12~0); 666664#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 666660#L593-42 assume !(1 == ~m_pc~0); 666656#L593-44 is_master_triggered_~__retres1~0#1 := 0; 666652#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 666648#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 666644#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 666640#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 666636#L612-42 assume 1 == ~t1_pc~0; 666630#L613-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 666625#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 666620#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 666615#L1500-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 666611#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 666607#L631-42 assume !(1 == ~t2_pc~0); 666602#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 666598#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 666594#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 666590#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 666586#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 666582#L650-42 assume !(1 == ~t3_pc~0); 666576#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 666572#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 666567#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 666562#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 666557#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 666552#L669-42 assume !(1 == ~t4_pc~0); 666547#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 666543#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 666539#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 666535#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 666531#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 666526#L688-42 assume 1 == ~t5_pc~0; 666520#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 666514#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 666508#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 666504#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 666500#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 666496#L707-42 assume !(1 == ~t6_pc~0); 666491#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 666488#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 666485#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 666482#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 666479#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 666475#L726-42 assume !(1 == ~t7_pc~0); 666472#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 666468#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 666464#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 666461#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 666457#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 666453#L745-42 assume !(1 == ~t8_pc~0); 666448#L745-44 is_transmit8_triggered_~__retres1~8#1 := 0; 666444#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 666440#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 666436#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 666432#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 666426#L764-42 assume 1 == ~t9_pc~0; 666420#L765-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 666415#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 666409#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 666405#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 666401#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 666397#L783-42 assume !(1 == ~t10_pc~0); 666392#L783-44 is_transmit10_triggered_~__retres1~10#1 := 0; 666388#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 666383#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 666379#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 666375#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 666369#L802-42 assume 1 == ~t11_pc~0; 666364#L803-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 666360#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 666355#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 666351#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 666347#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 666342#L821-42 assume 1 == ~t12_pc~0; 666338#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 666333#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 666328#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 666324#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 666320#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 666314#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 666310#L1339-5 assume !(1 == ~T1_E~0); 666306#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 655672#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 666296#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 666291#L1359-3 assume !(1 == ~T5_E~0); 666285#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 666280#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 666275#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 666268#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 660050#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 666255#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 666246#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 666239#L1399-3 assume !(1 == ~E_M~0); 666233#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 666228#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 666221#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 666007#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 665945#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 665939#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 665931#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 665921#L1439-3 assume !(1 == ~E_8~0); 665913#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 665906#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 665899#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 665892#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 665885#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 665524#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 665503#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 665494#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 665489#L1829 assume !(0 == start_simulation_~tmp~3#1); 665488#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 664735#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 664723#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 664721#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 664719#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 664716#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 664707#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 664700#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 664696#L1810-2 [2024-11-09 16:09:13,155 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,155 INFO L85 PathProgramCache]: Analyzing trace with hash 2145928902, now seen corresponding path program 1 times [2024-11-09 16:09:13,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [783609854] [2024-11-09 16:09:13,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [783609854] [2024-11-09 16:09:13,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [783609854] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:13,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651695802] [2024-11-09 16:09:13,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,328 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:13,328 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,328 INFO L85 PathProgramCache]: Analyzing trace with hash 843954979, now seen corresponding path program 1 times [2024-11-09 16:09:13,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149045163] [2024-11-09 16:09:13,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149045163] [2024-11-09 16:09:13,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149045163] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:13,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719491158] [2024-11-09 16:09:13,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,429 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:13,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:13,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:13,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:13,430 INFO L87 Difference]: Start difference. First operand 175072 states and 250230 transitions. cyclomatic complexity: 75286 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:15,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:15,504 INFO L93 Difference]: Finished difference Result 495454 states and 702928 transitions. [2024-11-09 16:09:15,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 495454 states and 702928 transitions. [2024-11-09 16:09:18,403 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 492672 [2024-11-09 16:09:19,992 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 495454 states to 495454 states and 702928 transitions. [2024-11-09 16:09:19,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 495454 [2024-11-09 16:09:20,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 495454 [2024-11-09 16:09:20,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 495454 states and 702928 transitions. [2024-11-09 16:09:20,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:20,401 INFO L218 hiAutomatonCegarLoop]: Abstraction has 495454 states and 702928 transitions. [2024-11-09 16:09:20,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495454 states and 702928 transitions. [2024-11-09 16:09:24,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495454 to 489182. [2024-11-09 16:09:26,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 489182 states, 489182 states have (on average 1.4196761123671762) internal successors, (694480), 489181 states have internal predecessors, (694480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:27,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489182 states to 489182 states and 694480 transitions. [2024-11-09 16:09:27,856 INFO L240 hiAutomatonCegarLoop]: Abstraction has 489182 states and 694480 transitions. [2024-11-09 16:09:27,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:27,857 INFO L425 stractBuchiCegarLoop]: Abstraction has 489182 states and 694480 transitions. [2024-11-09 16:09:27,857 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-09 16:09:27,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489182 states and 694480 transitions. [2024-11-09 16:09:29,905 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 487168 [2024-11-09 16:09:29,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:29,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:29,907 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:29,907 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:29,907 INFO L745 eck$LassoCheckResult]: Stem: 1315650#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1315651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1316531#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1316532#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1317272#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 1317273#L848-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1316190#L853-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1315972#L858-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1315363#L863-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1315364#L868-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1316664#L873-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1316776#L878-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1317391#L883-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1317392#L888-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1316110#L893-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1316111#L898-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1316690#L903-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1316603#L908-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1316149#L1201 assume !(0 == ~M_E~0); 1316150#L1201-2 assume !(0 == ~T1_E~0); 1317129#L1206-1 assume !(0 == ~T2_E~0); 1317105#L1211-1 assume !(0 == ~T3_E~0); 1317106#L1216-1 assume !(0 == ~T4_E~0); 1315954#L1221-1 assume !(0 == ~T5_E~0); 1315955#L1226-1 assume !(0 == ~T6_E~0); 1315574#L1231-1 assume !(0 == ~T7_E~0); 1315575#L1236-1 assume !(0 == ~T8_E~0); 1317173#L1241-1 assume !(0 == ~T9_E~0); 1315997#L1246-1 assume !(0 == ~T10_E~0); 1315998#L1251-1 assume !(0 == ~T11_E~0); 1316147#L1256-1 assume !(0 == ~T12_E~0); 1315372#L1261-1 assume !(0 == ~E_M~0); 1315373#L1266-1 assume !(0 == ~E_1~0); 1317359#L1271-1 assume !(0 == ~E_2~0); 1316755#L1276-1 assume !(0 == ~E_3~0); 1316756#L1281-1 assume !(0 == ~E_4~0); 1316704#L1286-1 assume !(0 == ~E_5~0); 1315842#L1291-1 assume !(0 == ~E_6~0); 1315843#L1296-1 assume !(0 == ~E_7~0); 1316462#L1301-1 assume !(0 == ~E_8~0); 1316463#L1306-1 assume !(0 == ~E_9~0); 1317026#L1311-1 assume !(0 == ~E_10~0); 1315793#L1316-1 assume !(0 == ~E_11~0); 1315794#L1321-1 assume !(0 == ~E_12~0); 1316482#L1326-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1316483#L593 assume !(1 == ~m_pc~0); 1315674#L593-2 is_master_triggered_~__retres1~0#1 := 0; 1315675#L604 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1316365#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1316366#L1492 assume !(0 != activate_threads_~tmp~1#1); 1316715#L1492-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1317070#L612 assume !(1 == ~t1_pc~0); 1317071#L612-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1317381#L623 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1316873#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1315678#L1500 assume !(0 != activate_threads_~tmp___0~0#1); 1315679#L1500-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1316126#L631 assume !(1 == ~t2_pc~0); 1316127#L631-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1315451#L642 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1315452#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1315807#L1508 assume !(0 != activate_threads_~tmp___1~0#1); 1316325#L1508-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1315756#L650 assume !(1 == ~t3_pc~0); 1315757#L650-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1316907#L661 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1316848#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1315409#L1516 assume !(0 != activate_threads_~tmp___2~0#1); 1315410#L1516-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1316684#L669 assume !(1 == ~t4_pc~0); 1316685#L669-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1317118#L680 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1315495#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1315496#L1524 assume !(0 != activate_threads_~tmp___3~0#1); 1315611#L1524-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1315854#L688 assume !(1 == ~t5_pc~0); 1315630#L688-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1315631#L699 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1317321#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1316554#L1532 assume !(0 != activate_threads_~tmp___4~0#1); 1316555#L1532-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1316702#L707 assume !(1 == ~t6_pc~0); 1316953#L707-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1316291#L718 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1315795#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1315796#L1540 assume !(0 != activate_threads_~tmp___5~0#1); 1316643#L1540-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1316148#L726 assume !(1 == ~t7_pc~0); 1315717#L726-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1315718#L737 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1316862#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1317225#L1548 assume !(0 != activate_threads_~tmp___6~0#1); 1315481#L1548-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1315482#L745 assume !(1 == ~t8_pc~0); 1315946#L745-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1315966#L756 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1317141#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1316373#L1556 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1316374#L1556-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1316975#L764 assume 1 == ~t9_pc~0; 1316146#L765 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1315976#L775 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1315874#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1315875#L1564 assume !(0 != activate_threads_~tmp___8~0#1); 1315507#L1564-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1315508#L783 assume !(1 == ~t10_pc~0); 1315562#L783-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1315563#L794 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1315760#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1316105#L1572 assume !(0 != activate_threads_~tmp___9~0#1); 1316106#L1572-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1317119#L802 assume 1 == ~t11_pc~0; 1317093#L803 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1315448#L813 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1315449#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1315956#L1580 assume !(0 != activate_threads_~tmp___10~0#1); 1315957#L1580-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1316074#L821 assume !(1 == ~t12_pc~0); 1316340#L821-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1316452#L832 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1315457#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1315458#L1588 assume !(0 != activate_threads_~tmp___11~0#1); 1317186#L1588-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316723#L1339 assume !(1 == ~M_E~0); 1316724#L1339-2 assume !(1 == ~T1_E~0); 1317228#L1344-1 assume !(1 == ~T2_E~0); 1317229#L1349-1 assume !(1 == ~T3_E~0); 1509642#L1354-1 assume !(1 == ~T4_E~0); 1509640#L1359-1 assume !(1 == ~T5_E~0); 1509638#L1364-1 assume !(1 == ~T6_E~0); 1509636#L1369-1 assume !(1 == ~T7_E~0); 1509634#L1374-1 assume !(1 == ~T8_E~0); 1509632#L1379-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1509630#L1384-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1509628#L1389-1 assume !(1 == ~T11_E~0); 1509627#L1394-1 assume !(1 == ~T12_E~0); 1509625#L1399-1 assume !(1 == ~E_M~0); 1509619#L1404-1 assume !(1 == ~E_1~0); 1509617#L1409-1 assume !(1 == ~E_2~0); 1509615#L1414-1 assume !(1 == ~E_3~0); 1509612#L1419-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1509613#L1424-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1527249#L1429-1 assume !(1 == ~E_6~0); 1527247#L1434-1 assume !(1 == ~E_7~0); 1527245#L1439-1 assume !(1 == ~E_8~0); 1527243#L1444-1 assume !(1 == ~E_9~0); 1527241#L1449-1 assume !(1 == ~E_10~0); 1527239#L1454-1 assume !(1 == ~E_11~0); 1527238#L1459-1 assume 1 == ~E_12~0;~E_12~0 := 2; 1317222#L1464-1 assume { :end_inline_reset_delta_events } true; 1534294#L1810-2 [2024-11-09 16:09:29,908 INFO L747 eck$LassoCheckResult]: Loop: 1534294#L1810-2 assume !false; 1534283#L1811 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1534276#L1176-1 assume !false; 1534269#L999 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1534026#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1534011#L988 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1534004#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1533998#L1003 assume !(0 != eval_~tmp~0#1); 1533999#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1539863#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1539861#L1201-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1539859#L1201-5 assume !(0 == ~T1_E~0); 1539857#L1206-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1539855#L1211-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1539853#L1216-3 assume !(0 == ~T4_E~0); 1539851#L1221-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1539849#L1226-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1539847#L1231-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1539845#L1236-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1539843#L1241-3 assume !(0 == ~T9_E~0); 1539841#L1246-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1539839#L1251-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1539836#L1256-3 assume !(0 == ~T12_E~0); 1539834#L1261-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1539832#L1266-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1539830#L1271-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1539828#L1276-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1539826#L1281-3 assume !(0 == ~E_4~0); 1539824#L1286-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1539822#L1291-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1539820#L1296-3 assume !(0 == ~E_7~0); 1539818#L1301-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1539816#L1306-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1539814#L1311-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1539812#L1316-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1539810#L1321-3 assume !(0 == ~E_12~0); 1539808#L1326-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1539806#L593-42 assume !(1 == ~m_pc~0); 1539804#L593-44 is_master_triggered_~__retres1~0#1 := 0; 1538507#L604-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1538434#is_master_triggered_returnLabel#15 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1538334#L1492-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1538312#L1492-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1538306#L612-42 assume !(1 == ~t1_pc~0); 1538301#L612-44 is_transmit1_triggered_~__retres1~1#1 := 0; 1538295#L623-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1538289#is_transmit1_triggered_returnLabel#15 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1538283#L1500-42 assume !(0 != activate_threads_~tmp___0~0#1); 1538277#L1500-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1538273#L631-42 assume !(1 == ~t2_pc~0); 1538269#L631-44 is_transmit2_triggered_~__retres1~2#1 := 0; 1538264#L642-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1538259#is_transmit2_triggered_returnLabel#15 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1538254#L1508-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1538249#L1508-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1538245#L650-42 assume !(1 == ~t3_pc~0); 1538240#L650-44 is_transmit3_triggered_~__retres1~3#1 := 0; 1538235#L661-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1538230#is_transmit3_triggered_returnLabel#15 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1538224#L1516-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1538218#L1516-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1538213#L669-42 assume !(1 == ~t4_pc~0); 1538207#L669-44 is_transmit4_triggered_~__retres1~4#1 := 0; 1538203#L680-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1538199#is_transmit4_triggered_returnLabel#15 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1538194#L1524-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1538193#L1524-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1538192#L688-42 assume 1 == ~t5_pc~0; 1538191#L689-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1538189#L699-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1538188#is_transmit5_triggered_returnLabel#15 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1538186#L1532-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1538184#L1532-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1538182#L707-42 assume !(1 == ~t6_pc~0); 1538180#L707-44 is_transmit6_triggered_~__retres1~6#1 := 0; 1538178#L718-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1538177#is_transmit6_triggered_returnLabel#15 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1538173#L1540-42 assume !(0 != activate_threads_~tmp___5~0#1); 1538169#L1540-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1538164#L726-42 assume !(1 == ~t7_pc~0); 1538159#L726-44 is_transmit7_triggered_~__retres1~7#1 := 0; 1538154#L737-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1538149#is_transmit7_triggered_returnLabel#15 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1538143#L1548-42 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1538137#L1548-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1538130#L745-42 assume 1 == ~t8_pc~0; 1538122#L746-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1538115#L756-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1538108#is_transmit8_triggered_returnLabel#15 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1538101#L1556-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1538096#L1556-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1538091#L764-42 assume !(1 == ~t9_pc~0); 1538086#L764-44 is_transmit9_triggered_~__retres1~9#1 := 0; 1538080#L775-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1538075#is_transmit9_triggered_returnLabel#15 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1538069#L1564-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1538064#L1564-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1538059#L783-42 assume 1 == ~t10_pc~0; 1538054#L784-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1538048#L794-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1538043#is_transmit10_triggered_returnLabel#15 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1538037#L1572-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1538032#L1572-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1538027#L802-42 assume !(1 == ~t11_pc~0); 1538021#L802-44 is_transmit11_triggered_~__retres1~11#1 := 0; 1538015#L813-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1538010#is_transmit11_triggered_returnLabel#15 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1538003#L1580-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1537998#L1580-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1537992#L821-42 assume 1 == ~t12_pc~0; 1537986#L822-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1537980#L832-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1537975#is_transmit12_triggered_returnLabel#15 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1537969#L1588-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1537964#L1588-44 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1537959#L1339-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1537947#L1339-5 assume !(1 == ~T1_E~0); 1537943#L1344-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1493649#L1349-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1537938#L1354-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1537936#L1359-3 assume !(1 == ~T5_E~0); 1537934#L1364-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1537932#L1369-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1537930#L1374-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1537928#L1379-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1537924#L1384-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1537922#L1389-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1537919#L1394-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1537917#L1399-3 assume !(1 == ~E_M~0); 1537915#L1404-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1537913#L1409-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1537911#L1414-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1537909#L1419-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1526267#L1424-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1537905#L1429-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1537903#L1434-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1537901#L1439-3 assume !(1 == ~E_8~0); 1537892#L1444-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1537887#L1449-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1537883#L1454-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1537878#L1459-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1527290#L1464-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1537813#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1537799#L988-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1537798#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1537784#L1829 assume !(0 == start_simulation_~tmp~3#1); 1537782#L1829-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1535011#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1534999#L988-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1534997#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1534995#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1534993#L1791 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1534359#stop_simulation_returnLabel#1 start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1534308#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 1534294#L1810-2 [2024-11-09 16:09:29,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:29,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1572109753, now seen corresponding path program 1 times [2024-11-09 16:09:29,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:29,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772183119] [2024-11-09 16:09:29,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:29,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:29,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:29,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:29,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:29,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772183119] [2024-11-09 16:09:29,967 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772183119] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:29,967 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:29,967 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:29,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191865836] [2024-11-09 16:09:29,967 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:29,968 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:29,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:29,968 INFO L85 PathProgramCache]: Analyzing trace with hash 820332454, now seen corresponding path program 1 times [2024-11-09 16:09:29,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:29,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992300694] [2024-11-09 16:09:29,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:29,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:29,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:30,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:30,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:30,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992300694] [2024-11-09 16:09:30,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992300694] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:30,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:30,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:30,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357161815] [2024-11-09 16:09:30,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:30,010 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:30,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:30,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:30,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:30,010 INFO L87 Difference]: Start difference. First operand 489182 states and 694480 transitions. cyclomatic complexity: 205554 Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:32,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:32,152 INFO L93 Difference]: Finished difference Result 502049 states and 707347 transitions. [2024-11-09 16:09:32,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 502049 states and 707347 transitions. [2024-11-09 16:09:35,026 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 500032 [2024-11-09 16:09:36,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 502049 states to 502049 states and 707347 transitions. [2024-11-09 16:09:36,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 502049 [2024-11-09 16:09:37,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 502049 [2024-11-09 16:09:37,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 502049 states and 707347 transitions. [2024-11-09 16:09:37,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:37,227 INFO L218 hiAutomatonCegarLoop]: Abstraction has 502049 states and 707347 transitions. [2024-11-09 16:09:37,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 502049 states and 707347 transitions.