./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c7c6ca5d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.2.5-?-c7c6ca5-m [2024-11-09 16:09:07,266 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-09 16:09:07,314 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-09 16:09:07,319 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-09 16:09:07,319 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-09 16:09:07,342 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-09 16:09:07,342 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-09 16:09:07,343 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-09 16:09:07,343 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-09 16:09:07,343 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-09 16:09:07,344 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-09 16:09:07,344 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-09 16:09:07,344 INFO L153 SettingsManager]: * Use SBE=true [2024-11-09 16:09:07,347 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-09 16:09:07,347 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-09 16:09:07,347 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-09 16:09:07,347 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-09 16:09:07,347 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-09 16:09:07,348 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-09 16:09:07,348 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-09 16:09:07,348 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-09 16:09:07,348 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-09 16:09:07,348 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-09 16:09:07,349 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-09 16:09:07,350 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-09 16:09:07,350 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-09 16:09:07,350 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-09 16:09:07,350 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-09 16:09:07,350 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-09 16:09:07,351 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-09 16:09:07,351 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-09 16:09:07,351 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-09 16:09:07,351 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-09 16:09:07,351 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-09 16:09:07,351 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-09 16:09:07,352 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-09 16:09:07,352 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-09 16:09:07,352 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-09 16:09:07,353 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-09 16:09:07,353 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2024-11-09 16:09:07,569 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-09 16:09:07,586 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-09 16:09:07,588 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-09 16:09:07,590 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-09 16:09:07,590 INFO L274 PluginConnector]: CDTParser initialized [2024-11-09 16:09:07,591 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.01.cil.c [2024-11-09 16:09:08,718 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-09 16:09:08,883 INFO L384 CDTParser]: Found 1 translation units. [2024-11-09 16:09:08,884 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c [2024-11-09 16:09:08,890 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5f1f74f54/0223bead8ca14cf5b52d8f5316952aa5/FLAG11084f5a6 [2024-11-09 16:09:09,285 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5f1f74f54/0223bead8ca14cf5b52d8f5316952aa5 [2024-11-09 16:09:09,287 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-09 16:09:09,289 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-09 16:09:09,290 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-09 16:09:09,290 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-09 16:09:09,298 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-09 16:09:09,299 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,299 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c7564ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09, skipping insertion in model container [2024-11-09 16:09:09,299 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,330 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-09 16:09:09,472 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:09:09,481 INFO L200 MainTranslator]: Completed pre-run [2024-11-09 16:09:09,505 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:09:09,519 INFO L204 MainTranslator]: Completed translation [2024-11-09 16:09:09,520 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09 WrapperNode [2024-11-09 16:09:09,520 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-09 16:09:09,521 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-09 16:09:09,521 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-09 16:09:09,521 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-09 16:09:09,526 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,531 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,550 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 361 [2024-11-09 16:09:09,550 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-09 16:09:09,551 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-09 16:09:09,551 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-09 16:09:09,551 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-09 16:09:09,559 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,559 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,566 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,576 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-09 16:09:09,577 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,577 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,580 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,586 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,587 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,588 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,594 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-09 16:09:09,595 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-09 16:09:09,595 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-09 16:09:09,595 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-09 16:09:09,596 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (1/1) ... [2024-11-09 16:09:09,603 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:09,612 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:09,626 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:09,628 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-09 16:09:09,664 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-09 16:09:09,664 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-09 16:09:09,664 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-09 16:09:09,664 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-09 16:09:09,743 INFO L238 CfgBuilder]: Building ICFG [2024-11-09 16:09:09,745 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-09 16:09:10,091 INFO L? ?]: Removed 60 outVars from TransFormulas that were not future-live. [2024-11-09 16:09:10,092 INFO L287 CfgBuilder]: Performing block encoding [2024-11-09 16:09:10,109 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-09 16:09:10,111 INFO L316 CfgBuilder]: Removed 5 assume(true) statements. [2024-11-09 16:09:10,111 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:09:10 BoogieIcfgContainer [2024-11-09 16:09:10,111 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-09 16:09:10,112 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-09 16:09:10,112 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-09 16:09:10,116 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-09 16:09:10,116 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:09:10,117 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 04:09:09" (1/3) ... [2024-11-09 16:09:10,117 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@fdcd410 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:09:10, skipping insertion in model container [2024-11-09 16:09:10,118 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:09:10,118 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:09" (2/3) ... [2024-11-09 16:09:10,118 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@fdcd410 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:09:10, skipping insertion in model container [2024-11-09 16:09:10,118 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:09:10,118 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:09:10" (3/3) ... [2024-11-09 16:09:10,120 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2024-11-09 16:09:10,162 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-09 16:09:10,163 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-09 16:09:10,163 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-09 16:09:10,163 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-09 16:09:10,163 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-09 16:09:10,163 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-09 16:09:10,164 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-09 16:09:10,164 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-09 16:09:10,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2024-11-09 16:09:10,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:10,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:10,196 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,196 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,196 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-09 16:09:10,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2024-11-09 16:09:10,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:10,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:10,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,210 INFO L745 eck$LassoCheckResult]: Stem: 31#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 48#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 134#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13#L161true assume !(1 == ~m_i~0);~m_st~0 := 2; 5#L161-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 80#L166-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89#L250true assume !(0 == ~M_E~0); 108#L250-2true assume !(0 == ~T1_E~0); 39#L255-1true assume !(0 == ~E_1~0); 81#L260-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55#L115true assume !(1 == ~m_pc~0); 59#L115-2true is_master_triggered_~__retres1~0#1 := 0; 69#L126true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8#is_master_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 66#L300true assume !(0 != activate_threads_~tmp~1#1); 107#L300-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L134true assume 1 == ~t1_pc~0; 109#L135true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57#L145true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10#L308true assume !(0 != activate_threads_~tmp___0~0#1); 62#L308-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60#L273true assume !(1 == ~M_E~0); 113#L273-2true assume !(1 == ~T1_E~0); 102#L278-1true assume !(1 == ~E_1~0); 72#L283-1true assume { :end_inline_reset_delta_events } true; 58#L404-2true [2024-11-09 16:09:10,211 INFO L747 eck$LassoCheckResult]: Loop: 58#L404-2true assume !false; 82#L405true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96#L225-1true assume false; 85#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120#L250-3true assume 0 == ~M_E~0;~M_E~0 := 1; 98#L250-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 104#L255-3true assume 0 == ~E_1~0;~E_1~0 := 1; 6#L260-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49#L115-6true assume 1 == ~m_pc~0; 116#L116-2true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 135#L126-2true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54#is_master_triggered_returnLabel#3true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 74#L300-6true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 118#L300-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133#L134-6true assume !(1 == ~t1_pc~0); 32#L134-8true is_transmit1_triggered_~__retres1~1#1 := 0; 53#L145-2true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125#is_transmit1_triggered_returnLabel#3true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 50#L308-6true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7#L308-8true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130#L273-3true assume 1 == ~M_E~0;~M_E~0 := 2; 45#L273-5true assume !(1 == ~T1_E~0); 33#L278-3true assume 1 == ~E_1~0;~E_1~0 := 2; 95#L283-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 76#L179-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 114#L191-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 100#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 19#L423true assume !(0 == start_simulation_~tmp~3#1); 18#L423-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 22#L179-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 73#L191-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 16#L378true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17#L385true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136#stop_simulation_returnLabel#1true start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 44#L436true assume !(0 != start_simulation_~tmp___0~1#1); 58#L404-2true [2024-11-09 16:09:10,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,215 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2024-11-09 16:09:10,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212646658] [2024-11-09 16:09:10,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:10,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:10,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:10,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212646658] [2024-11-09 16:09:10,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212646658] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:10,349 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:10,349 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:10,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844518993] [2024-11-09 16:09:10,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:10,354 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:10,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,357 INFO L85 PathProgramCache]: Analyzing trace with hash 1288992519, now seen corresponding path program 1 times [2024-11-09 16:09:10,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965114713] [2024-11-09 16:09:10,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:10,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:10,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:10,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965114713] [2024-11-09 16:09:10,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965114713] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:10,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:10,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:10,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100032262] [2024-11-09 16:09:10,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:10,391 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:10,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:10,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:10,419 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:10,420 INFO L87 Difference]: Start difference. First operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:10,441 INFO L93 Difference]: Finished difference Result 134 states and 190 transitions. [2024-11-09 16:09:10,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134 states and 190 transitions. [2024-11-09 16:09:10,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2024-11-09 16:09:10,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134 states to 128 states and 184 transitions. [2024-11-09 16:09:10,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2024-11-09 16:09:10,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2024-11-09 16:09:10,451 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 184 transitions. [2024-11-09 16:09:10,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:10,452 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 184 transitions. [2024-11-09 16:09:10,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 184 transitions. [2024-11-09 16:09:10,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2024-11-09 16:09:10,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.4375) internal successors, (184), 127 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 184 transitions. [2024-11-09 16:09:10,480 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 184 transitions. [2024-11-09 16:09:10,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:10,484 INFO L425 stractBuchiCegarLoop]: Abstraction has 128 states and 184 transitions. [2024-11-09 16:09:10,484 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-09 16:09:10,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 184 transitions. [2024-11-09 16:09:10,485 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2024-11-09 16:09:10,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:10,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:10,487 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,487 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,487 INFO L745 eck$LassoCheckResult]: Stem: 329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 352#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 298#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 283#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 284#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 381#L250 assume !(0 == ~M_E~0); 390#L250-2 assume !(0 == ~T1_E~0); 342#L255-1 assume !(0 == ~E_1~0); 343#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 359#L115 assume !(1 == ~m_pc~0); 325#L115-2 is_master_triggered_~__retres1~0#1 := 0; 326#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 289#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 290#L300 assume !(0 != activate_threads_~tmp~1#1); 368#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L134 assume 1 == ~t1_pc~0; 401#L135 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 361#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 341#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 292#L308 assume !(0 != activate_threads_~tmp___0~0#1); 293#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363#L273 assume !(1 == ~M_E~0); 364#L273-2 assume !(1 == ~T1_E~0); 398#L278-1 assume !(1 == ~E_1~0); 372#L283-1 assume { :end_inline_reset_delta_events } true; 347#L404-2 [2024-11-09 16:09:10,487 INFO L747 eck$LassoCheckResult]: Loop: 347#L404-2 assume !false; 362#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 380#L225-1 assume !false; 386#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 387#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 328#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 299#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 300#L206 assume !(0 != eval_~tmp~0#1); 338#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 405#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 395#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 396#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 285#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286#L115-6 assume !(1 == ~m_pc~0); 353#L115-8 is_master_triggered_~__retres1~0#1 := 0; 404#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 357#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 358#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 373#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406#L134-6 assume !(1 == ~t1_pc~0); 331#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 332#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 356#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 355#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 287#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 288#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 349#L273-5 assume !(1 == ~T1_E~0); 333#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 334#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 375#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 376#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 309#L423 assume !(0 == start_simulation_~tmp~3#1); 307#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 308#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 313#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 340#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 301#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 302#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 346#L436 assume !(0 != start_simulation_~tmp___0~1#1); 347#L404-2 [2024-11-09 16:09:10,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,488 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2024-11-09 16:09:10,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574392551] [2024-11-09 16:09:10,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:10,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:10,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:10,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574392551] [2024-11-09 16:09:10,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574392551] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:10,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:10,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:10,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506091552] [2024-11-09 16:09:10,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:10,554 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:10,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,555 INFO L85 PathProgramCache]: Analyzing trace with hash 487194975, now seen corresponding path program 1 times [2024-11-09 16:09:10,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571778812] [2024-11-09 16:09:10,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:10,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:10,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:10,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1571778812] [2024-11-09 16:09:10,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1571778812] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:10,622 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:10,622 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:10,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456375631] [2024-11-09 16:09:10,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:10,623 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:10,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:10,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:10,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:10,626 INFO L87 Difference]: Start difference. First operand 128 states and 184 transitions. cyclomatic complexity: 57 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:10,663 INFO L93 Difference]: Finished difference Result 222 states and 313 transitions. [2024-11-09 16:09:10,663 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 222 states and 313 transitions. [2024-11-09 16:09:10,665 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 192 [2024-11-09 16:09:10,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 222 states to 222 states and 313 transitions. [2024-11-09 16:09:10,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 222 [2024-11-09 16:09:10,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 222 [2024-11-09 16:09:10,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 222 states and 313 transitions. [2024-11-09 16:09:10,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:10,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 222 states and 313 transitions. [2024-11-09 16:09:10,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states and 313 transitions. [2024-11-09 16:09:10,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 218. [2024-11-09 16:09:10,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 218 states, 218 states have (on average 1.4128440366972477) internal successors, (308), 217 states have internal predecessors, (308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 308 transitions. [2024-11-09 16:09:10,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 218 states and 308 transitions. [2024-11-09 16:09:10,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:10,684 INFO L425 stractBuchiCegarLoop]: Abstraction has 218 states and 308 transitions. [2024-11-09 16:09:10,684 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-09 16:09:10,684 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 218 states and 308 transitions. [2024-11-09 16:09:10,685 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2024-11-09 16:09:10,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:10,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:10,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,686 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,687 INFO L745 eck$LassoCheckResult]: Stem: 688#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 689#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 712#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 708#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 655#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 640#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 641#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 746#L250 assume !(0 == ~M_E~0); 762#L250-2 assume !(0 == ~T1_E~0); 702#L255-1 assume !(0 == ~E_1~0); 703#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 720#L115 assume !(1 == ~m_pc~0); 683#L115-2 is_master_triggered_~__retres1~0#1 := 0; 684#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 646#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 647#L300 assume !(0 != activate_threads_~tmp~1#1); 730#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 770#L134 assume !(1 == ~t1_pc~0); 728#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 721#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 700#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 651#L308 assume !(0 != activate_threads_~tmp___0~0#1); 652#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 724#L273 assume !(1 == ~M_E~0); 725#L273-2 assume !(1 == ~T1_E~0); 768#L278-1 assume !(1 == ~E_1~0); 736#L283-1 assume { :end_inline_reset_delta_events } true; 722#L404-2 [2024-11-09 16:09:10,687 INFO L747 eck$LassoCheckResult]: Loop: 722#L404-2 assume !false; 723#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 814#L225-1 assume !false; 813#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 811#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 810#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 809#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 808#L206 assume !(0 != eval_~tmp~0#1); 806#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 803#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 801#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 799#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 797#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 794#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 792#L115-6 assume 1 == ~m_pc~0; 775#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 776#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 717#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 718#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 737#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783#L134-6 assume !(1 == ~t1_pc~0); 784#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 850#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 849#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 848#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 846#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 842#L273-5 assume !(1 == ~T1_E~0); 841#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 840#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 838#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 836#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 834#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 832#L423 assume !(0 == start_simulation_~tmp~3#1); 831#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 670#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 671#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 829#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 828#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 827#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 826#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 825#L436 assume !(0 != start_simulation_~tmp___0~1#1); 722#L404-2 [2024-11-09 16:09:10,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,688 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2024-11-09 16:09:10,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109210205] [2024-11-09 16:09:10,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:10,702 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:10,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:10,735 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:10,736 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,736 INFO L85 PathProgramCache]: Analyzing trace with hash 795633984, now seen corresponding path program 1 times [2024-11-09 16:09:10,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032023356] [2024-11-09 16:09:10,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:10,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:10,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:10,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1032023356] [2024-11-09 16:09:10,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1032023356] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:10,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:10,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:10,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273891225] [2024-11-09 16:09:10,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:10,793 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:10,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:10,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:10,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:10,794 INFO L87 Difference]: Start difference. First operand 218 states and 308 transitions. cyclomatic complexity: 92 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:10,814 INFO L93 Difference]: Finished difference Result 270 states and 380 transitions. [2024-11-09 16:09:10,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 380 transitions. [2024-11-09 16:09:10,815 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 225 [2024-11-09 16:09:10,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 380 transitions. [2024-11-09 16:09:10,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2024-11-09 16:09:10,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2024-11-09 16:09:10,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 380 transitions. [2024-11-09 16:09:10,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:10,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 380 transitions. [2024-11-09 16:09:10,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 380 transitions. [2024-11-09 16:09:10,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2024-11-09 16:09:10,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 270 states, 270 states have (on average 1.4074074074074074) internal successors, (380), 269 states have internal predecessors, (380), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 380 transitions. [2024-11-09 16:09:10,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 270 states and 380 transitions. [2024-11-09 16:09:10,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:10,827 INFO L425 stractBuchiCegarLoop]: Abstraction has 270 states and 380 transitions. [2024-11-09 16:09:10,827 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-09 16:09:10,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 380 transitions. [2024-11-09 16:09:10,829 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 225 [2024-11-09 16:09:10,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:10,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:10,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,829 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,830 INFO L745 eck$LassoCheckResult]: Stem: 1181#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1182#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1207#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1201#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1149#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1134#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1135#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1242#L250 assume !(0 == ~M_E~0); 1254#L250-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1264#L255-1 assume !(0 == ~E_1~0); 1383#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1382#L115 assume !(1 == ~m_pc~0); 1380#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1378#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1288#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1287#L300 assume !(0 != activate_threads_~tmp~1#1); 1286#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1285#L134 assume !(1 == ~t1_pc~0); 1284#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1283#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1281#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1279#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1221#L273 assume !(1 == ~M_E~0); 1222#L273-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1260#L278-1 assume !(1 == ~E_1~0); 1233#L283-1 assume { :end_inline_reset_delta_events } true; 1200#L404-2 [2024-11-09 16:09:10,830 INFO L747 eck$LassoCheckResult]: Loop: 1200#L404-2 assume !false; 1220#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1241#L225-1 assume !false; 1247#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1248#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1179#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1150#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1151#L206 assume !(0 != eval_~tmp~0#1); 1190#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1244#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1269#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1257#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1258#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1399#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1398#L115-6 assume !(1 == ~m_pc~0); 1396#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1395#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1394#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1393#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1392#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1391#L134-6 assume !(1 == ~t1_pc~0); 1390#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1212#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1213#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1210#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1138#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1139#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1202#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1185#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1186#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1236#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1237#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1256#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1160#L423 assume !(0 == start_simulation_~tmp~3#1); 1158#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1159#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1164#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1193#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1155#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1156#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1157#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1199#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1200#L404-2 [2024-11-09 16:09:10,830 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,831 INFO L85 PathProgramCache]: Analyzing trace with hash 784287684, now seen corresponding path program 1 times [2024-11-09 16:09:10,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788775617] [2024-11-09 16:09:10,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:10,871 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:10,871 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:10,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788775617] [2024-11-09 16:09:10,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788775617] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:10,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:10,872 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:10,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729198908] [2024-11-09 16:09:10,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:10,873 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:10,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,874 INFO L85 PathProgramCache]: Analyzing trace with hash 1767058653, now seen corresponding path program 1 times [2024-11-09 16:09:10,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515550111] [2024-11-09 16:09:10,874 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:10,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:10,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:10,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515550111] [2024-11-09 16:09:10,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515550111] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:10,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:10,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:10,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324502673] [2024-11-09 16:09:10,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:10,952 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:10,952 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:10,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:10,952 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:10,953 INFO L87 Difference]: Start difference. First operand 270 states and 380 transitions. cyclomatic complexity: 112 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:10,965 INFO L93 Difference]: Finished difference Result 218 states and 300 transitions. [2024-11-09 16:09:10,965 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 300 transitions. [2024-11-09 16:09:10,967 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2024-11-09 16:09:10,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 218 states and 300 transitions. [2024-11-09 16:09:10,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 218 [2024-11-09 16:09:10,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 218 [2024-11-09 16:09:10,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218 states and 300 transitions. [2024-11-09 16:09:10,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:10,968 INFO L218 hiAutomatonCegarLoop]: Abstraction has 218 states and 300 transitions. [2024-11-09 16:09:10,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states and 300 transitions. [2024-11-09 16:09:10,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 218. [2024-11-09 16:09:10,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 218 states, 218 states have (on average 1.3761467889908257) internal successors, (300), 217 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:10,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 300 transitions. [2024-11-09 16:09:10,978 INFO L240 hiAutomatonCegarLoop]: Abstraction has 218 states and 300 transitions. [2024-11-09 16:09:10,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:10,981 INFO L425 stractBuchiCegarLoop]: Abstraction has 218 states and 300 transitions. [2024-11-09 16:09:10,983 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-09 16:09:10,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 218 states and 300 transitions. [2024-11-09 16:09:10,984 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2024-11-09 16:09:10,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:10,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:10,985 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,985 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:10,985 INFO L745 eck$LassoCheckResult]: Stem: 1680#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1646#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1631#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1632#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1737#L250 assume !(0 == ~M_E~0); 1750#L250-2 assume !(0 == ~T1_E~0); 1694#L255-1 assume !(0 == ~E_1~0); 1695#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1714#L115 assume !(1 == ~m_pc~0); 1674#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1675#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1637#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1638#L300 assume !(0 != activate_threads_~tmp~1#1); 1724#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1757#L134 assume !(1 == ~t1_pc~0); 1722#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1716#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1640#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1641#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1718#L273 assume !(1 == ~M_E~0); 1719#L273-2 assume !(1 == ~T1_E~0); 1755#L278-1 assume !(1 == ~E_1~0); 1727#L283-1 assume { :end_inline_reset_delta_events } true; 1728#L404-2 [2024-11-09 16:09:10,985 INFO L747 eck$LassoCheckResult]: Loop: 1728#L404-2 assume !false; 1802#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1800#L225-1 assume !false; 1798#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1794#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1791#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1789#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L206 assume !(0 != eval_~tmp~0#1); 1739#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1740#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1762#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1753#L250-5 assume !(0 == ~T1_E~0); 1754#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1633#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1634#L115-6 assume !(1 == ~m_pc~0); 1831#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1829#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1712#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1713#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1729#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1763#L134-6 assume !(1 == ~t1_pc~0); 1682#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1683#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1711#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1710#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1635#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1636#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1701#L273-5 assume !(1 == ~T1_E~0); 1684#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1685#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1731#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1732#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1752#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1657#L423 assume !(0 == start_simulation_~tmp~3#1); 1658#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1827#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1825#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1824#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1652#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1653#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1654#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1765#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1728#L404-2 [2024-11-09 16:09:10,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:10,986 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2024-11-09 16:09:10,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:10,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903785569] [2024-11-09 16:09:10,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:10,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:10,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:10,996 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:10,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,004 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:11,005 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,005 INFO L85 PathProgramCache]: Analyzing trace with hash 1188794849, now seen corresponding path program 1 times [2024-11-09 16:09:11,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286114553] [2024-11-09 16:09:11,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:11,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:11,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:11,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286114553] [2024-11-09 16:09:11,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286114553] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:11,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:11,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:11,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892311450] [2024-11-09 16:09:11,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:11,062 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:11,062 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:11,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:11,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:11,063 INFO L87 Difference]: Start difference. First operand 218 states and 300 transitions. cyclomatic complexity: 84 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:11,115 INFO L93 Difference]: Finished difference Result 232 states and 314 transitions. [2024-11-09 16:09:11,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 232 states and 314 transitions. [2024-11-09 16:09:11,116 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 204 [2024-11-09 16:09:11,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 232 states to 232 states and 314 transitions. [2024-11-09 16:09:11,117 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232 [2024-11-09 16:09:11,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232 [2024-11-09 16:09:11,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 232 states and 314 transitions. [2024-11-09 16:09:11,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:11,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 232 states and 314 transitions. [2024-11-09 16:09:11,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states and 314 transitions. [2024-11-09 16:09:11,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 224. [2024-11-09 16:09:11,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224 states, 224 states have (on average 1.3660714285714286) internal successors, (306), 223 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 306 transitions. [2024-11-09 16:09:11,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224 states and 306 transitions. [2024-11-09 16:09:11,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:11,126 INFO L425 stractBuchiCegarLoop]: Abstraction has 224 states and 306 transitions. [2024-11-09 16:09:11,126 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-09 16:09:11,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224 states and 306 transitions. [2024-11-09 16:09:11,127 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 196 [2024-11-09 16:09:11,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:11,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:11,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:11,128 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:11,128 INFO L745 eck$LassoCheckResult]: Stem: 2139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2161#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2157#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2105#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2089#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2090#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2192#L250 assume !(0 == ~M_E~0); 2207#L250-2 assume !(0 == ~T1_E~0); 2151#L255-1 assume !(0 == ~E_1~0); 2152#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2168#L115 assume !(1 == ~m_pc~0); 2132#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2133#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2095#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2096#L300 assume !(0 != activate_threads_~tmp~1#1); 2177#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2215#L134 assume !(1 == ~t1_pc~0); 2176#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2170#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2150#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2099#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2100#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2172#L273 assume !(1 == ~M_E~0); 2173#L273-2 assume !(1 == ~T1_E~0); 2213#L278-1 assume !(1 == ~E_1~0); 2182#L283-1 assume { :end_inline_reset_delta_events } true; 2156#L404-2 [2024-11-09 16:09:11,128 INFO L747 eck$LassoCheckResult]: Loop: 2156#L404-2 assume !false; 2171#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2255#L225-1 assume !false; 2254#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2253#L179 assume !(0 == ~m_st~0); 2252#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2251#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2250#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2249#L206 assume !(0 != eval_~tmp~0#1); 2248#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2247#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2246#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2211#L250-5 assume !(0 == ~T1_E~0); 2212#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2091#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2092#L115-6 assume !(1 == ~m_pc~0); 2162#L115-8 is_master_triggered_~__retres1~0#1 := 0; 2220#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2166#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2167#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2183#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2222#L134-6 assume !(1 == ~t1_pc~0); 2225#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2308#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2307#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2306#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2305#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2304#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2303#L273-5 assume !(1 == ~T1_E~0); 2302#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2297#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2295#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2292#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2209#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2116#L423 assume !(0 == start_simulation_~tmp~3#1); 2114#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2115#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2120#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2149#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2108#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2109#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2113#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2155#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2156#L404-2 [2024-11-09 16:09:11,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,129 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2024-11-09 16:09:11,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100418294] [2024-11-09 16:09:11,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,134 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:11,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,142 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:11,143 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,143 INFO L85 PathProgramCache]: Analyzing trace with hash 1260103574, now seen corresponding path program 1 times [2024-11-09 16:09:11,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714770208] [2024-11-09 16:09:11,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:11,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:11,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:11,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714770208] [2024-11-09 16:09:11,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714770208] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:11,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:11,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:11,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1456829814] [2024-11-09 16:09:11,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:11,206 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:11,206 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:11,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:11,207 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:11,207 INFO L87 Difference]: Start difference. First operand 224 states and 306 transitions. cyclomatic complexity: 84 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:11,259 INFO L93 Difference]: Finished difference Result 245 states and 327 transitions. [2024-11-09 16:09:11,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 327 transitions. [2024-11-09 16:09:11,261 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 214 [2024-11-09 16:09:11,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 245 states and 327 transitions. [2024-11-09 16:09:11,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2024-11-09 16:09:11,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2024-11-09 16:09:11,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 245 states and 327 transitions. [2024-11-09 16:09:11,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:11,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 245 states and 327 transitions. [2024-11-09 16:09:11,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states and 327 transitions. [2024-11-09 16:09:11,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 245. [2024-11-09 16:09:11,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245 states, 245 states have (on average 1.3346938775510204) internal successors, (327), 244 states have internal predecessors, (327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 327 transitions. [2024-11-09 16:09:11,266 INFO L240 hiAutomatonCegarLoop]: Abstraction has 245 states and 327 transitions. [2024-11-09 16:09:11,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:11,267 INFO L425 stractBuchiCegarLoop]: Abstraction has 245 states and 327 transitions. [2024-11-09 16:09:11,268 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-09 16:09:11,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245 states and 327 transitions. [2024-11-09 16:09:11,269 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 214 [2024-11-09 16:09:11,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:11,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:11,269 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:11,269 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:11,269 INFO L745 eck$LassoCheckResult]: Stem: 2615#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2638#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2632#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2581#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2566#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2567#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2669#L250 assume !(0 == ~M_E~0); 2679#L250-2 assume !(0 == ~T1_E~0); 2628#L255-1 assume !(0 == ~E_1~0); 2629#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2646#L115 assume !(1 == ~m_pc~0); 2608#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2650#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2572#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2573#L300 assume !(0 != activate_threads_~tmp~1#1); 2656#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2691#L134 assume !(1 == ~t1_pc~0); 2653#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2648#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2627#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2575#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2576#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2651#L273 assume !(1 == ~M_E~0); 2652#L273-2 assume !(1 == ~T1_E~0); 2687#L278-1 assume !(1 == ~E_1~0); 2660#L283-1 assume { :end_inline_reset_delta_events } true; 2634#L404-2 [2024-11-09 16:09:11,270 INFO L747 eck$LassoCheckResult]: Loop: 2634#L404-2 assume !false; 2649#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2668#L225-1 assume !false; 2673#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2674#L179 assume !(0 == ~m_st~0); 2610#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2612#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2796#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2794#L206 assume !(0 != eval_~tmp~0#1); 2671#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2672#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2698#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2684#L250-5 assume !(0 == ~T1_E~0); 2685#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2568#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2569#L115-6 assume 1 == ~m_pc~0; 2640#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2697#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2802#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2801#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2661#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2699#L134-6 assume !(1 == ~t1_pc~0); 2702#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2804#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2803#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2799#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2570#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2571#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2635#L273-5 assume !(1 == ~T1_E~0); 2619#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2620#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2663#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2664#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2592#L423 assume !(0 == start_simulation_~tmp~3#1); 2590#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2591#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2596#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2626#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2587#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2588#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2589#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2633#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2634#L404-2 [2024-11-09 16:09:11,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,273 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 4 times [2024-11-09 16:09:11,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968413064] [2024-11-09 16:09:11,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,280 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:11,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,291 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:11,291 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,292 INFO L85 PathProgramCache]: Analyzing trace with hash 1568542583, now seen corresponding path program 1 times [2024-11-09 16:09:11,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189147248] [2024-11-09 16:09:11,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:11,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:11,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:11,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189147248] [2024-11-09 16:09:11,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189147248] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:11,350 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:11,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:11,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911087476] [2024-11-09 16:09:11,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:11,350 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:11,350 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:11,351 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:11,351 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:11,351 INFO L87 Difference]: Start difference. First operand 245 states and 327 transitions. cyclomatic complexity: 84 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:11,416 INFO L93 Difference]: Finished difference Result 254 states and 332 transitions. [2024-11-09 16:09:11,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 254 states and 332 transitions. [2024-11-09 16:09:11,418 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 223 [2024-11-09 16:09:11,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 254 states to 254 states and 332 transitions. [2024-11-09 16:09:11,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 254 [2024-11-09 16:09:11,420 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 254 [2024-11-09 16:09:11,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 254 states and 332 transitions. [2024-11-09 16:09:11,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:11,420 INFO L218 hiAutomatonCegarLoop]: Abstraction has 254 states and 332 transitions. [2024-11-09 16:09:11,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254 states and 332 transitions. [2024-11-09 16:09:11,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254 to 254. [2024-11-09 16:09:11,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 254 states, 254 states have (on average 1.3070866141732282) internal successors, (332), 253 states have internal predecessors, (332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 332 transitions. [2024-11-09 16:09:11,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 254 states and 332 transitions. [2024-11-09 16:09:11,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:11,425 INFO L425 stractBuchiCegarLoop]: Abstraction has 254 states and 332 transitions. [2024-11-09 16:09:11,426 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-09 16:09:11,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 254 states and 332 transitions. [2024-11-09 16:09:11,427 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 223 [2024-11-09 16:09:11,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:11,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:11,427 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:11,428 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:11,428 INFO L745 eck$LassoCheckResult]: Stem: 3123#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 3124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3147#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3139#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3088#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 3073#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3074#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3181#L250 assume !(0 == ~M_E~0); 3191#L250-2 assume !(0 == ~T1_E~0); 3135#L255-1 assume !(0 == ~E_1~0); 3136#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3154#L115 assume !(1 == ~m_pc~0); 3116#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3158#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3079#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3080#L300 assume !(0 != activate_threads_~tmp~1#1); 3166#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3203#L134 assume !(1 == ~t1_pc~0); 3161#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3156#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3134#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3082#L308 assume !(0 != activate_threads_~tmp___0~0#1); 3083#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3159#L273 assume !(1 == ~M_E~0); 3160#L273-2 assume !(1 == ~T1_E~0); 3200#L278-1 assume !(1 == ~E_1~0); 3170#L283-1 assume { :end_inline_reset_delta_events } true; 3171#L404-2 [2024-11-09 16:09:11,428 INFO L747 eck$LassoCheckResult]: Loop: 3171#L404-2 assume !false; 3281#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3280#L225-1 assume !false; 3279#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3278#L179 assume !(0 == ~m_st~0); 3118#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 3120#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3276#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3277#L206 assume !(0 != eval_~tmp~0#1); 3183#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3184#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3208#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3197#L250-5 assume !(0 == ~T1_E~0); 3198#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3075#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3076#L115-6 assume !(1 == ~m_pc~0); 3148#L115-8 is_master_triggered_~__retres1~0#1 := 0; 3212#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3152#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3153#L300-6 assume !(0 != activate_threads_~tmp~1#1); 3172#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3209#L134-6 assume !(1 == ~t1_pc~0); 3125#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 3126#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3294#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3293#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 3292#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3291#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3290#L273-5 assume !(1 == ~T1_E~0); 3289#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3287#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3174#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3175#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3199#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 3099#L423 assume !(0 == start_simulation_~tmp~3#1); 3100#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3300#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3299#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3297#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 3295#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3286#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3285#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3284#L436 assume !(0 != start_simulation_~tmp___0~1#1); 3171#L404-2 [2024-11-09 16:09:11,430 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,431 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 5 times [2024-11-09 16:09:11,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103322500] [2024-11-09 16:09:11,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,438 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:11,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,446 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:11,446 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,446 INFO L85 PathProgramCache]: Analyzing trace with hash -868054638, now seen corresponding path program 1 times [2024-11-09 16:09:11,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,446 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879063889] [2024-11-09 16:09:11,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:11,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:11,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:11,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879063889] [2024-11-09 16:09:11,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879063889] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:11,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:11,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:11,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [662216424] [2024-11-09 16:09:11,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:11,489 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:11,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:11,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:11,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:11,491 INFO L87 Difference]: Start difference. First operand 254 states and 332 transitions. cyclomatic complexity: 80 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:11,520 INFO L93 Difference]: Finished difference Result 405 states and 515 transitions. [2024-11-09 16:09:11,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 515 transitions. [2024-11-09 16:09:11,522 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 374 [2024-11-09 16:09:11,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 405 states and 515 transitions. [2024-11-09 16:09:11,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 405 [2024-11-09 16:09:11,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 405 [2024-11-09 16:09:11,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 405 states and 515 transitions. [2024-11-09 16:09:11,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:11,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 405 states and 515 transitions. [2024-11-09 16:09:11,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states and 515 transitions. [2024-11-09 16:09:11,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 381. [2024-11-09 16:09:11,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 381 states, 381 states have (on average 1.2808398950131235) internal successors, (488), 380 states have internal predecessors, (488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:11,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 488 transitions. [2024-11-09 16:09:11,531 INFO L240 hiAutomatonCegarLoop]: Abstraction has 381 states and 488 transitions. [2024-11-09 16:09:11,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:11,532 INFO L425 stractBuchiCegarLoop]: Abstraction has 381 states and 488 transitions. [2024-11-09 16:09:11,532 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-09 16:09:11,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 381 states and 488 transitions. [2024-11-09 16:09:11,535 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 350 [2024-11-09 16:09:11,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:11,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:11,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:11,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:11,536 INFO L745 eck$LassoCheckResult]: Stem: 3786#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 3787#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3813#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3805#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3753#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 3738#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3739#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3850#L250 assume !(0 == ~M_E~0); 3862#L250-2 assume !(0 == ~T1_E~0); 3799#L255-1 assume !(0 == ~E_1~0); 3800#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3822#L115 assume !(1 == ~m_pc~0); 3780#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3827#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3744#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3745#L300 assume !(0 != activate_threads_~tmp~1#1); 3834#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3880#L134 assume !(1 == ~t1_pc~0); 3830#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3825#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3798#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3747#L308 assume !(0 != activate_threads_~tmp___0~0#1); 3748#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3828#L273 assume !(1 == ~M_E~0); 3829#L273-2 assume !(1 == ~T1_E~0); 3873#L278-1 assume !(1 == ~E_1~0); 3840#L283-1 assume { :end_inline_reset_delta_events } true; 3841#L404-2 [2024-11-09 16:09:11,537 INFO L747 eck$LassoCheckResult]: Loop: 3841#L404-2 assume !false; 3956#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3954#L225-1 assume !false; 3856#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3857#L179 assume !(0 == ~m_st~0); 3922#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 3908#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3909#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3904#L206 assume !(0 != eval_~tmp~0#1); 3905#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3921#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3920#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3869#L250-5 assume !(0 == ~T1_E~0); 3870#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3740#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3741#L115-6 assume 1 == ~m_pc~0; 3918#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3916#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3914#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3911#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3912#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4020#L134-6 assume !(1 == ~t1_pc~0); 4018#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 4015#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4013#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4011#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 4010#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4009#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4007#L273-5 assume !(1 == ~T1_E~0); 4004#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4002#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3999#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3994#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3992#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 3974#L423 assume !(0 == start_simulation_~tmp~3#1); 3972#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3971#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3970#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3969#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 3968#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3967#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3964#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3962#L436 assume !(0 != start_simulation_~tmp___0~1#1); 3841#L404-2 [2024-11-09 16:09:11,540 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,540 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 6 times [2024-11-09 16:09:11,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411798274] [2024-11-09 16:09:11,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,546 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:11,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,553 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:11,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,554 INFO L85 PathProgramCache]: Analyzing trace with hash -425602123, now seen corresponding path program 1 times [2024-11-09 16:09:11,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159923582] [2024-11-09 16:09:11,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:11,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:11,569 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:11,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:11,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1027369614, now seen corresponding path program 1 times [2024-11-09 16:09:11,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:11,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511645814] [2024-11-09 16:09:11,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:11,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:11,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:11,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:11,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:11,611 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511645814] [2024-11-09 16:09:11,611 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511645814] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:11,612 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:11,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:11,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555371025] [2024-11-09 16:09:11,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:11,864 INFO L204 LassoAnalysis]: Preferences: [2024-11-09 16:09:11,864 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-09 16:09:11,865 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-09 16:09:11,865 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-09 16:09:11,865 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-09 16:09:11,865 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:11,865 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-09 16:09:11,865 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-09 16:09:11,865 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.01.cil.c_Iteration9_Loop [2024-11-09 16:09:11,865 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-09 16:09:11,865 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-09 16:09:11,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,895 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,903 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,905 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,908 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,912 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,915 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,919 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,922 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,930 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,933 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,937 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,938 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,940 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:11,946 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,096 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-09 16:09:12,097 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-09 16:09:12,098 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,098 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,100 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,101 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-09 16:09:12,102 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,102 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,117 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:09:12,117 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:09:12,132 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-09 16:09:12,134 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,134 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,136 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,137 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-09 16:09:12,138 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,138 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,153 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:09:12,153 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:09:12,164 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,164 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,165 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,166 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,167 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-09 16:09:12,172 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,172 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,184 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:09:12,184 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:09:12,195 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,195 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,195 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,196 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,197 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-09 16:09:12,199 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,199 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,213 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:09:12,213 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:09:12,224 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-09 16:09:12,225 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,225 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,226 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,238 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-09 16:09:12,242 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,242 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,253 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:09:12,253 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:09:12,263 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,263 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,264 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,264 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,265 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-09 16:09:12,266 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,266 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,277 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:09:12,277 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~2#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:09:12,287 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,288 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,289 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,290 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-09 16:09:12,294 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,294 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,306 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:09:12,307 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:09:12,317 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,317 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,317 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,318 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,319 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-09 16:09:12,319 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,319 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,337 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:09:12,337 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:09:12,348 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,348 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,349 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,350 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-09 16:09:12,350 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:09:12,351 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,373 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-09 16:09:12,374 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,374 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,375 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,376 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-09 16:09:12,378 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-09 16:09:12,378 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:09:12,391 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-09 16:09:12,401 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,402 INFO L204 LassoAnalysis]: Preferences: [2024-11-09 16:09:12,402 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-09 16:09:12,402 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-09 16:09:12,402 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-09 16:09:12,402 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-09 16:09:12,402 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,402 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-09 16:09:12,402 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-09 16:09:12,402 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.01.cil.c_Iteration9_Loop [2024-11-09 16:09:12,402 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-09 16:09:12,402 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-09 16:09:12,404 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,409 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,412 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,415 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,417 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,419 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,428 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,430 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,435 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,451 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,455 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,463 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,464 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,465 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,467 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,471 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,477 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:09:12,603 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-09 16:09:12,607 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-09 16:09:12,608 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,608 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,609 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,610 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-09 16:09:12,612 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,623 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,623 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,624 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,624 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:09:12,624 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,625 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:09:12,626 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,627 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:09:12,638 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-09 16:09:12,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,638 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,639 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,641 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-09 16:09:12,645 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,656 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,656 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,656 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,656 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:09:12,656 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,657 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:09:12,657 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,659 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:09:12,669 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,670 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,670 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,671 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,672 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-09 16:09:12,674 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,684 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,684 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,684 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,684 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:09:12,684 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,686 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:09:12,686 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,687 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:09:12,699 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-09 16:09:12,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,699 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,701 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,702 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-09 16:09:12,703 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,713 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,713 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,713 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,714 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:09:12,714 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,714 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:09:12,714 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,715 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:09:12,733 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,733 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,733 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,734 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,736 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-09 16:09:12,736 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,746 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,747 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,747 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,747 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:09:12,747 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,747 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:09:12,747 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,748 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:09:12,759 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,759 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,759 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,761 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,762 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-09 16:09:12,763 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,773 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,774 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,774 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,774 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:09:12,774 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,774 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:09:12,774 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,776 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:09:12,787 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-09 16:09:12,787 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,787 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,790 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,791 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-09 16:09:12,792 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,803 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,803 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,804 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,804 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:09:12,804 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,804 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:09:12,804 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,805 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:09:12,816 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,817 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,817 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,818 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,820 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-09 16:09:12,822 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,832 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,832 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,832 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,832 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:09:12,832 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,837 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:09:12,837 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,842 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:09:12,853 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,854 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,854 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,855 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,856 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-09 16:09:12,857 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:09:12,867 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:09:12,867 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:09:12,867 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:09:12,867 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:09:12,867 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:09:12,869 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:09:12,869 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:09:12,874 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-09 16:09:12,880 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-09 16:09:12,880 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-09 16:09:12,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:12,882 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:12,898 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:12,899 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-09 16:09:12,900 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-09 16:09:12,900 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-09 16:09:12,900 INFO L474 LassoAnalysis]: Proved termination. [2024-11-09 16:09:12,901 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2024-11-09 16:09:12,911 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2024-11-09 16:09:12,914 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-09 16:09:12,937 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:12,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:12,954 INFO L255 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-09 16:09:12,954 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-09 16:09:12,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:12,997 INFO L255 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-09 16:09:12,997 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-09 16:09:13,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,090 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-09 16:09:13,092 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 381 states and 488 transitions. cyclomatic complexity: 109 Second operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,151 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 381 states and 488 transitions. cyclomatic complexity: 109. Second operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 911 states and 1167 transitions. Complement of second has 5 states. [2024-11-09 16:09:13,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-09 16:09:13,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 150 transitions. [2024-11-09 16:09:13,154 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 150 transitions. Stem has 27 letters. Loop has 43 letters. [2024-11-09 16:09:13,155 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:09:13,155 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 150 transitions. Stem has 70 letters. Loop has 43 letters. [2024-11-09 16:09:13,156 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:09:13,156 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 150 transitions. Stem has 27 letters. Loop has 86 letters. [2024-11-09 16:09:13,158 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:09:13,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 911 states and 1167 transitions. [2024-11-09 16:09:13,163 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 608 [2024-11-09 16:09:13,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 911 states to 911 states and 1167 transitions. [2024-11-09 16:09:13,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 640 [2024-11-09 16:09:13,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 647 [2024-11-09 16:09:13,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 911 states and 1167 transitions. [2024-11-09 16:09:13,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-09 16:09:13,166 INFO L218 hiAutomatonCegarLoop]: Abstraction has 911 states and 1167 transitions. [2024-11-09 16:09:13,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 911 states and 1167 transitions. [2024-11-09 16:09:13,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 911 to 904. [2024-11-09 16:09:13,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 904 states, 904 states have (on average 1.2765486725663717) internal successors, (1154), 903 states have internal predecessors, (1154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 904 states to 904 states and 1154 transitions. [2024-11-09 16:09:13,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 904 states and 1154 transitions. [2024-11-09 16:09:13,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:13,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:13,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:13,177 INFO L87 Difference]: Start difference. First operand 904 states and 1154 transitions. Second operand has 3 states, 3 states have (on average 23.333333333333332) internal successors, (70), 3 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:13,198 INFO L93 Difference]: Finished difference Result 976 states and 1211 transitions. [2024-11-09 16:09:13,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 976 states and 1211 transitions. [2024-11-09 16:09:13,201 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 656 [2024-11-09 16:09:13,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 976 states to 976 states and 1211 transitions. [2024-11-09 16:09:13,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-09 16:09:13,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-09 16:09:13,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 976 states and 1211 transitions. [2024-11-09 16:09:13,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-09 16:09:13,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 976 states and 1211 transitions. [2024-11-09 16:09:13,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 976 states and 1211 transitions. [2024-11-09 16:09:13,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 976 to 904. [2024-11-09 16:09:13,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 904 states, 904 states have (on average 1.25) internal successors, (1130), 903 states have internal predecessors, (1130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 904 states to 904 states and 1130 transitions. [2024-11-09 16:09:13,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 904 states and 1130 transitions. [2024-11-09 16:09:13,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:13,215 INFO L425 stractBuchiCegarLoop]: Abstraction has 904 states and 1130 transitions. [2024-11-09 16:09:13,216 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-09 16:09:13,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 904 states and 1130 transitions. [2024-11-09 16:09:13,218 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 608 [2024-11-09 16:09:13,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:13,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:13,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,219 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,219 INFO L745 eck$LassoCheckResult]: Stem: 7225#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 7226#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 7272#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7258#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7168#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 7144#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7145#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7335#L250 assume !(0 == ~M_E~0); 7353#L250-2 assume !(0 == ~T1_E~0); 7247#L255-1 assume !(0 == ~E_1~0); 7248#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7290#L115 assume !(1 == ~m_pc~0); 7214#L115-2 is_master_triggered_~__retres1~0#1 := 0; 7298#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7552#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7307#L300 assume !(0 != activate_threads_~tmp~1#1); 7308#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7379#L134 assume !(1 == ~t1_pc~0); 7301#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7295#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7246#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7158#L308 assume !(0 != activate_threads_~tmp___0~0#1); 7159#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7299#L273 assume !(1 == ~M_E~0); 7300#L273-2 assume !(1 == ~T1_E~0); 7371#L278-1 assume !(1 == ~E_1~0); 7315#L283-1 assume { :end_inline_reset_delta_events } true; 7316#L404-2 assume !false; 7296#L405 [2024-11-09 16:09:13,219 INFO L747 eck$LassoCheckResult]: Loop: 7296#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7332#L225-1 assume !false; 7342#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7343#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 7403#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7639#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7635#L206 assume 0 != eval_~tmp~0#1; 7636#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 7914#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 7912#L41 assume !(0 == ~m_pc~0); 7910#L44 assume 1 == ~m_pc~0; 7901#$Ultimate##91 assume !false; 7312#L61 ~m_pc~0 := 1;~m_st~0 := 2; 7313#master_returnLabel#1 assume { :end_inline_master } true; 7164#L214-2 havoc eval_~tmp_ndt_1~0#1; 7165#L211-1 assume !(0 == ~t1_st~0); 7382#L225-1 assume !false; 7603#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7601#L179 assume !(0 == ~m_st~0); 7216#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 7218#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7329#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7584#L206 assume !(0 != eval_~tmp~0#1); 7585#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7928#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7927#L250-3 assume !(0 == ~M_E~0); 7926#L250-5 assume !(0 == ~T1_E~0); 7925#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7924#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7923#L115-6 assume 1 == ~m_pc~0; 7922#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7917#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7918#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 7983#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7392#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7393#L134-6 assume !(1 == ~t1_pc~0); 7413#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 7991#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7989#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7987#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 7986#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7985#L273-3 assume !(1 == ~M_E~0); 7984#L273-5 assume !(1 == ~T1_E~0); 7982#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7981#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7980#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 7979#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7978#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 7872#L423 assume !(0 == start_simulation_~tmp~3#1); 7593#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7194#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 7195#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7244#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 7179#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7180#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7183#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 7259#L436 assume !(0 != start_simulation_~tmp___0~1#1); 7260#L404-2 assume !false; 7296#L405 [2024-11-09 16:09:13,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,219 INFO L85 PathProgramCache]: Analyzing trace with hash 2020492972, now seen corresponding path program 1 times [2024-11-09 16:09:13,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981842975] [2024-11-09 16:09:13,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,224 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,228 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,228 INFO L85 PathProgramCache]: Analyzing trace with hash -1382120805, now seen corresponding path program 1 times [2024-11-09 16:09:13,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149083248] [2024-11-09 16:09:13,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,264 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-09 16:09:13,265 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149083248] [2024-11-09 16:09:13,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1149083248] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:13,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206347294] [2024-11-09 16:09:13,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,269 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:13,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:13,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:13,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:13,269 INFO L87 Difference]: Start difference. First operand 904 states and 1130 transitions. cyclomatic complexity: 232 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:13,294 INFO L93 Difference]: Finished difference Result 1232 states and 1501 transitions. [2024-11-09 16:09:13,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1232 states and 1501 transitions. [2024-11-09 16:09:13,299 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 632 [2024-11-09 16:09:13,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1232 states to 1162 states and 1417 transitions. [2024-11-09 16:09:13,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 795 [2024-11-09 16:09:13,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 795 [2024-11-09 16:09:13,303 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1162 states and 1417 transitions. [2024-11-09 16:09:13,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-09 16:09:13,303 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1162 states and 1417 transitions. [2024-11-09 16:09:13,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1162 states and 1417 transitions. [2024-11-09 16:09:13,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1162 to 1133. [2024-11-09 16:09:13,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1133 states, 1133 states have (on average 1.2224183583406885) internal successors, (1385), 1132 states have internal predecessors, (1385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1133 states to 1133 states and 1385 transitions. [2024-11-09 16:09:13,316 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1133 states and 1385 transitions. [2024-11-09 16:09:13,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:13,316 INFO L425 stractBuchiCegarLoop]: Abstraction has 1133 states and 1385 transitions. [2024-11-09 16:09:13,316 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-09 16:09:13,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1133 states and 1385 transitions. [2024-11-09 16:09:13,338 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 615 [2024-11-09 16:09:13,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:13,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:13,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,343 INFO L745 eck$LassoCheckResult]: Stem: 9367#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 9368#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 9417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9405#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9315#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 9286#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9287#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9477#L250 assume 0 == ~M_E~0;~M_E~0 := 1; 9500#L250-2 assume !(0 == ~T1_E~0); 9391#L255-1 assume !(0 == ~E_1~0); 9392#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9478#L115 assume !(1 == ~m_pc~0); 9444#L115-2 is_master_triggered_~__retres1~0#1 := 0; 9445#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9296#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9297#L300 assume !(0 != activate_threads_~tmp~1#1); 9456#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9537#L134 assume !(1 == ~t1_pc~0); 9538#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9561#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9560#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9305#L308 assume !(0 != activate_threads_~tmp___0~0#1); 9306#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9446#L273 assume 1 == ~M_E~0;~M_E~0 := 2; 9447#L273-2 assume !(1 == ~T1_E~0); 9512#L278-1 assume !(1 == ~E_1~0); 9460#L283-1 assume { :end_inline_reset_delta_events } true; 9461#L404-2 assume !false; 9610#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10018#L225-1 [2024-11-09 16:09:13,343 INFO L747 eck$LassoCheckResult]: Loop: 10018#L225-1 assume !false; 10016#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10014#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10012#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10010#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10008#L206 assume 0 != eval_~tmp~0#1; 10006#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10003#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 10004#L214-2 havoc eval_~tmp_ndt_1~0#1; 10024#L211-1 assume !(0 == ~t1_st~0); 10018#L225-1 [2024-11-09 16:09:13,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,343 INFO L85 PathProgramCache]: Analyzing trace with hash -2065340210, now seen corresponding path program 1 times [2024-11-09 16:09:13,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769759422] [2024-11-09 16:09:13,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,346 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-09 16:09:13,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769759422] [2024-11-09 16:09:13,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769759422] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:13,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624201627] [2024-11-09 16:09:13,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,362 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:13,362 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,362 INFO L85 PathProgramCache]: Analyzing trace with hash 722519487, now seen corresponding path program 1 times [2024-11-09 16:09:13,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616028359] [2024-11-09 16:09:13,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,365 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,367 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,396 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:13,397 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:13,397 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:13,397 INFO L87 Difference]: Start difference. First operand 1133 states and 1385 transitions. cyclomatic complexity: 261 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:13,421 INFO L93 Difference]: Finished difference Result 699 states and 844 transitions. [2024-11-09 16:09:13,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 699 states and 844 transitions. [2024-11-09 16:09:13,423 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 428 [2024-11-09 16:09:13,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 699 states to 506 states and 610 transitions. [2024-11-09 16:09:13,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 506 [2024-11-09 16:09:13,425 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 506 [2024-11-09 16:09:13,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 506 states and 610 transitions. [2024-11-09 16:09:13,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:13,425 INFO L218 hiAutomatonCegarLoop]: Abstraction has 506 states and 610 transitions. [2024-11-09 16:09:13,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states and 610 transitions. [2024-11-09 16:09:13,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 312. [2024-11-09 16:09:13,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 312 states, 312 states have (on average 1.1987179487179487) internal successors, (374), 311 states have internal predecessors, (374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 374 transitions. [2024-11-09 16:09:13,429 INFO L240 hiAutomatonCegarLoop]: Abstraction has 312 states and 374 transitions. [2024-11-09 16:09:13,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:13,430 INFO L425 stractBuchiCegarLoop]: Abstraction has 312 states and 374 transitions. [2024-11-09 16:09:13,430 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-09 16:09:13,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 312 states and 374 transitions. [2024-11-09 16:09:13,431 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 284 [2024-11-09 16:09:13,431 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:13,431 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:13,431 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,431 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,432 INFO L745 eck$LassoCheckResult]: Stem: 11172#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 11173#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 11199#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11192#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11137#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 11122#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11123#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11236#L250 assume !(0 == ~M_E~0); 11247#L250-2 assume !(0 == ~T1_E~0); 11185#L255-1 assume !(0 == ~E_1~0); 11186#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11208#L115 assume !(1 == ~m_pc~0); 11167#L115-2 is_master_triggered_~__retres1~0#1 := 0; 11212#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11128#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11129#L300 assume !(0 != activate_threads_~tmp~1#1); 11219#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11260#L134 assume !(1 == ~t1_pc~0); 11215#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11210#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11184#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11131#L308 assume !(0 != activate_threads_~tmp___0~0#1); 11132#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11213#L273 assume !(1 == ~M_E~0); 11214#L273-2 assume !(1 == ~T1_E~0); 11258#L278-1 assume !(1 == ~E_1~0); 11225#L283-1 assume { :end_inline_reset_delta_events } true; 11226#L404-2 [2024-11-09 16:09:13,432 INFO L747 eck$LassoCheckResult]: Loop: 11226#L404-2 assume !false; 11410#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11408#L225-1 assume !false; 11406#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11405#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11403#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11402#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11180#L206 assume 0 != eval_~tmp~0#1; 11181#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 11238#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 11162#L41 assume !(0 == ~m_pc~0); 11163#L44 assume 1 == ~m_pc~0; 11187#$Ultimate##91 assume !false; 11223#L61 ~m_pc~0 := 1;~m_st~0 := 2; 11224#master_returnLabel#1 assume { :end_inline_master } true; 11237#L214-2 havoc eval_~tmp_ndt_1~0#1; 11388#L211-1 assume !(0 == ~t1_st~0); 11389#L225-1 assume !false; 11401#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11400#L179 assume !(0 == ~m_st~0); 11168#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 11170#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11138#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11139#L206 assume !(0 != eval_~tmp~0#1); 11320#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11318#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11314#L250-3 assume !(0 == ~M_E~0); 11312#L250-5 assume !(0 == ~T1_E~0); 11300#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11299#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11200#L115-6 assume !(1 == ~m_pc~0); 11201#L115-8 is_master_triggered_~__retres1~0#1 := 0; 11271#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11206#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11207#L300-6 assume !(0 != activate_threads_~tmp~1#1); 11228#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11265#L134-6 assume !(1 == ~t1_pc~0); 11277#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 11425#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11424#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11423#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 11422#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11421#L273-3 assume !(1 == ~M_E~0); 11420#L273-5 assume !(1 == ~T1_E~0); 11419#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11253#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11229#L179-1 assume !(0 == ~m_st~0); 11230#L183-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11315#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11313#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 11309#L423 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 11221#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11222#L115-9 assume 1 == ~m_pc~0; 11250#L116-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11251#L126-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11279#is_master_triggered_returnLabel#4 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11310#L300-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11311#L300-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11379#L134-9 assume !(1 == ~t1_pc~0); 11380#L134-11 is_transmit1_triggered_~__retres1~1#1 := 0; 11372#L145-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11373#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11364#L308-9 assume !(0 != activate_threads_~tmp___0~0#1); 11365#L308-11 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 11351#L341 assume 1 == ~M_E~0;~M_E~0 := 2; 11352#L341-2 assume !(1 == ~T1_E~0); 11341#L346-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11342#L351-1 assume { :end_inline_reset_time_events } true; 11147#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11148#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11429#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11428#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 11427#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11145#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11146#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 11418#L436 assume !(0 != start_simulation_~tmp___0~1#1); 11226#L404-2 [2024-11-09 16:09:13,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,433 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 7 times [2024-11-09 16:09:13,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205150141] [2024-11-09 16:09:13,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,436 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,440 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,440 INFO L85 PathProgramCache]: Analyzing trace with hash 896165013, now seen corresponding path program 1 times [2024-11-09 16:09:13,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [237256540] [2024-11-09 16:09:13,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,463 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [237256540] [2024-11-09 16:09:13,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [237256540] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,463 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,463 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:13,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570436455] [2024-11-09 16:09:13,463 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,463 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:13,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:13,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:13,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:13,464 INFO L87 Difference]: Start difference. First operand 312 states and 374 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:13,482 INFO L93 Difference]: Finished difference Result 386 states and 455 transitions. [2024-11-09 16:09:13,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 386 states and 455 transitions. [2024-11-09 16:09:13,483 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 269 [2024-11-09 16:09:13,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 386 states to 386 states and 455 transitions. [2024-11-09 16:09:13,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 386 [2024-11-09 16:09:13,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 386 [2024-11-09 16:09:13,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 386 states and 455 transitions. [2024-11-09 16:09:13,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:13,485 INFO L218 hiAutomatonCegarLoop]: Abstraction has 386 states and 455 transitions. [2024-11-09 16:09:13,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 386 states and 455 transitions. [2024-11-09 16:09:13,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 386 to 354. [2024-11-09 16:09:13,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 354 states, 354 states have (on average 1.1864406779661016) internal successors, (420), 353 states have internal predecessors, (420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 420 transitions. [2024-11-09 16:09:13,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 354 states and 420 transitions. [2024-11-09 16:09:13,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:13,490 INFO L425 stractBuchiCegarLoop]: Abstraction has 354 states and 420 transitions. [2024-11-09 16:09:13,490 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-09 16:09:13,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 354 states and 420 transitions. [2024-11-09 16:09:13,491 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 269 [2024-11-09 16:09:13,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:13,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:13,492 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,492 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,492 INFO L745 eck$LassoCheckResult]: Stem: 11872#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 11873#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 11898#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11890#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11841#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 11826#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11827#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11931#L250 assume !(0 == ~M_E~0); 11942#L250-2 assume !(0 == ~T1_E~0); 11884#L255-1 assume !(0 == ~E_1~0); 11885#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11904#L115 assume 1 == ~m_pc~0; 11867#L116 assume !(1 == ~M_E~0); 11868#L115-2 is_master_triggered_~__retres1~0#1 := 0; 11909#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11832#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11833#L300 assume !(0 != activate_threads_~tmp~1#1); 11916#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11954#L134 assume !(1 == ~t1_pc~0); 11912#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11907#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11883#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11835#L308 assume !(0 != activate_threads_~tmp___0~0#1); 11836#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11910#L273 assume !(1 == ~M_E~0); 11911#L273-2 assume !(1 == ~T1_E~0); 11950#L278-1 assume !(1 == ~E_1~0); 11951#L283-1 assume { :end_inline_reset_delta_events } true; 12144#L404-2 [2024-11-09 16:09:13,492 INFO L747 eck$LassoCheckResult]: Loop: 12144#L404-2 assume !false; 12141#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12110#L225-1 assume !false; 12111#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12104#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12105#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12098#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12099#L206 assume 0 != eval_~tmp~0#1; 12092#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12093#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 12086#L41 assume !(0 == ~m_pc~0); 12085#L44 assume 1 == ~m_pc~0; 12083#$Ultimate##91 assume !false; 11919#L61 ~m_pc~0 := 1;~m_st~0 := 2; 11920#master_returnLabel#1 assume { :end_inline_master } true; 11932#L214-2 havoc eval_~tmp_ndt_1~0#1; 12019#L211-1 assume !(0 == ~t1_st~0); 12020#L225-1 assume !false; 12075#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12074#L179 assume !(0 == ~m_st~0); 11869#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 11871#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12063#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12062#L206 assume !(0 != eval_~tmp~0#1); 11934#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11935#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11961#L250-3 assume !(0 == ~M_E~0); 11947#L250-5 assume !(0 == ~T1_E~0); 11948#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11828#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11829#L115-6 assume 1 == ~m_pc~0; 11899#L116-2 assume !(1 == ~M_E~0); 11960#L115-8 is_master_triggered_~__retres1~0#1 := 0; 11966#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11902#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11903#L300-6 assume !(0 != activate_threads_~tmp~1#1); 11924#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11962#L134-6 assume !(1 == ~t1_pc~0); 11874#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 11875#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11901#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11900#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 11830#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11831#L273-3 assume !(1 == ~M_E~0); 11893#L273-5 assume !(1 == ~T1_E~0); 11876#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11877#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11925#L179-1 assume !(0 == ~m_st~0); 11926#L183-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11943#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11949#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 11853#L423 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 11855#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11918#L115-9 assume 1 == ~m_pc~0; 11944#L116-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11945#L126-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11856#is_master_triggered_returnLabel#4 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11857#L300-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11863#L300-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11864#L134-9 assume !(1 == ~t1_pc~0); 11955#L134-11 is_transmit1_triggered_~__retres1~1#1 := 0; 12172#L145-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12171#is_transmit1_triggered_returnLabel#4 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12170#L308-9 assume !(0 != activate_threads_~tmp___0~0#1); 12169#L308-11 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 12168#L341 assume 1 == ~M_E~0;~M_E~0 := 2; 12167#L341-2 assume !(1 == ~T1_E~0); 12166#L346-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12165#L351-1 assume { :end_inline_reset_time_events } true; 12164#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12163#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12162#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12161#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 12160#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11849#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11850#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 12145#L436 assume !(0 != start_simulation_~tmp___0~1#1); 12144#L404-2 [2024-11-09 16:09:13,493 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,493 INFO L85 PathProgramCache]: Analyzing trace with hash -831988783, now seen corresponding path program 1 times [2024-11-09 16:09:13,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888456625] [2024-11-09 16:09:13,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,507 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888456625] [2024-11-09 16:09:13,507 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888456625] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,507 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,507 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:13,507 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [329170047] [2024-11-09 16:09:13,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,508 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:13,508 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,508 INFO L85 PathProgramCache]: Analyzing trace with hash -1714249558, now seen corresponding path program 1 times [2024-11-09 16:09:13,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178895457] [2024-11-09 16:09:13,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,527 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178895457] [2024-11-09 16:09:13,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178895457] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,527 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:13,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019975241] [2024-11-09 16:09:13,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,528 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:13,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:13,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:13,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:13,528 INFO L87 Difference]: Start difference. First operand 354 states and 420 transitions. cyclomatic complexity: 70 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 2 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:13,540 INFO L93 Difference]: Finished difference Result 340 states and 400 transitions. [2024-11-09 16:09:13,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 340 states and 400 transitions. [2024-11-09 16:09:13,541 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 269 [2024-11-09 16:09:13,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 340 states to 340 states and 400 transitions. [2024-11-09 16:09:13,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 340 [2024-11-09 16:09:13,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 340 [2024-11-09 16:09:13,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 400 transitions. [2024-11-09 16:09:13,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:13,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 400 transitions. [2024-11-09 16:09:13,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 400 transitions. [2024-11-09 16:09:13,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 336. [2024-11-09 16:09:13,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 336 states, 336 states have (on average 1.1785714285714286) internal successors, (396), 335 states have internal predecessors, (396), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 336 states to 336 states and 396 transitions. [2024-11-09 16:09:13,546 INFO L240 hiAutomatonCegarLoop]: Abstraction has 336 states and 396 transitions. [2024-11-09 16:09:13,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:13,547 INFO L425 stractBuchiCegarLoop]: Abstraction has 336 states and 396 transitions. [2024-11-09 16:09:13,547 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-09 16:09:13,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 336 states and 396 transitions. [2024-11-09 16:09:13,548 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 269 [2024-11-09 16:09:13,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:13,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:13,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,549 INFO L745 eck$LassoCheckResult]: Stem: 12573#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 12574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 12600#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12594#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12544#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 12527#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12528#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12634#L250 assume !(0 == ~M_E~0); 12648#L250-2 assume !(0 == ~T1_E~0); 12586#L255-1 assume !(0 == ~E_1~0); 12587#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12608#L115 assume !(1 == ~m_pc~0); 12609#L115-2 is_master_triggered_~__retres1~0#1 := 0; 12613#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12533#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 12534#L300 assume !(0 != activate_threads_~tmp~1#1); 12622#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12662#L134 assume !(1 == ~t1_pc~0); 12619#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12611#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12585#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12538#L308 assume !(0 != activate_threads_~tmp___0~0#1); 12539#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12614#L273 assume !(1 == ~M_E~0); 12615#L273-2 assume !(1 == ~T1_E~0); 12656#L278-1 assume !(1 == ~E_1~0); 12625#L283-1 assume { :end_inline_reset_delta_events } true; 12626#L404-2 assume !false; 12726#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12716#L225-1 [2024-11-09 16:09:13,549 INFO L747 eck$LassoCheckResult]: Loop: 12716#L225-1 assume !false; 12725#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12724#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12723#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12722#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12721#L206 assume 0 != eval_~tmp~0#1; 12720#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12718#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 12717#L214-2 havoc eval_~tmp_ndt_1~0#1; 12715#L211-1 assume !(0 == ~t1_st~0); 12716#L225-1 [2024-11-09 16:09:13,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 1 times [2024-11-09 16:09:13,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308293076] [2024-11-09 16:09:13,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,553 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,557 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,557 INFO L85 PathProgramCache]: Analyzing trace with hash 722519487, now seen corresponding path program 2 times [2024-11-09 16:09:13,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511814026] [2024-11-09 16:09:13,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,560 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,561 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,562 INFO L85 PathProgramCache]: Analyzing trace with hash -1929671224, now seen corresponding path program 1 times [2024-11-09 16:09:13,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396982540] [2024-11-09 16:09:13,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396982540] [2024-11-09 16:09:13,581 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396982540] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:13,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339450516] [2024-11-09 16:09:13,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:13,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:13,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:13,603 INFO L87 Difference]: Start difference. First operand 336 states and 396 transitions. cyclomatic complexity: 64 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:13,622 INFO L93 Difference]: Finished difference Result 583 states and 673 transitions. [2024-11-09 16:09:13,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 583 states and 673 transitions. [2024-11-09 16:09:13,624 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 397 [2024-11-09 16:09:13,625 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 583 states to 583 states and 673 transitions. [2024-11-09 16:09:13,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 583 [2024-11-09 16:09:13,626 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 583 [2024-11-09 16:09:13,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 583 states and 673 transitions. [2024-11-09 16:09:13,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:13,626 INFO L218 hiAutomatonCegarLoop]: Abstraction has 583 states and 673 transitions. [2024-11-09 16:09:13,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 583 states and 673 transitions. [2024-11-09 16:09:13,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 583 to 509. [2024-11-09 16:09:13,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 509 states, 509 states have (on average 1.163064833005894) internal successors, (592), 508 states have internal predecessors, (592), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 509 states to 509 states and 592 transitions. [2024-11-09 16:09:13,631 INFO L240 hiAutomatonCegarLoop]: Abstraction has 509 states and 592 transitions. [2024-11-09 16:09:13,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:13,632 INFO L425 stractBuchiCegarLoop]: Abstraction has 509 states and 592 transitions. [2024-11-09 16:09:13,632 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-09 16:09:13,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 509 states and 592 transitions. [2024-11-09 16:09:13,634 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 374 [2024-11-09 16:09:13,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:13,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:13,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,634 INFO L745 eck$LassoCheckResult]: Stem: 13499#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 13500#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 13524#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13519#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13472#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 13454#L161-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 13455#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13825#L250 assume !(0 == ~M_E~0); 13823#L250-2 assume !(0 == ~T1_E~0); 13821#L255-1 assume !(0 == ~E_1~0); 13819#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13817#L115 assume !(1 == ~m_pc~0); 13816#L115-2 is_master_triggered_~__retres1~0#1 := 0; 13815#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13814#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 13813#L300 assume !(0 != activate_threads_~tmp~1#1); 13812#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13811#L134 assume !(1 == ~t1_pc~0); 13810#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13809#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13808#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13807#L308 assume !(0 != activate_threads_~tmp___0~0#1); 13806#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13805#L273 assume !(1 == ~M_E~0); 13804#L273-2 assume !(1 == ~T1_E~0); 13803#L278-1 assume !(1 == ~E_1~0); 13801#L283-1 assume { :end_inline_reset_delta_events } true; 13799#L404-2 assume !false; 13794#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13792#L225-1 [2024-11-09 16:09:13,634 INFO L747 eck$LassoCheckResult]: Loop: 13792#L225-1 assume !false; 13790#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13789#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 13788#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 13786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13784#L206 assume 0 != eval_~tmp~0#1; 13782#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 13779#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 13780#L214-2 havoc eval_~tmp_ndt_1~0#1; 13795#L211-1 assume !(0 == ~t1_st~0); 13792#L225-1 [2024-11-09 16:09:13,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,635 INFO L85 PathProgramCache]: Analyzing trace with hash -1923240696, now seen corresponding path program 1 times [2024-11-09 16:09:13,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767771740] [2024-11-09 16:09:13,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:13,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:13,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:13,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767771740] [2024-11-09 16:09:13,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1767771740] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:13,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:13,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:13,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683875390] [2024-11-09 16:09:13,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:13,646 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:13,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,646 INFO L85 PathProgramCache]: Analyzing trace with hash 722519487, now seen corresponding path program 3 times [2024-11-09 16:09:13,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305429744] [2024-11-09 16:09:13,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,648 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:13,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:13,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:13,670 INFO L87 Difference]: Start difference. First operand 509 states and 592 transitions. cyclomatic complexity: 88 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:13,674 INFO L93 Difference]: Finished difference Result 344 states and 404 transitions. [2024-11-09 16:09:13,674 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 344 states and 404 transitions. [2024-11-09 16:09:13,675 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 262 [2024-11-09 16:09:13,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 344 states to 344 states and 404 transitions. [2024-11-09 16:09:13,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 344 [2024-11-09 16:09:13,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 344 [2024-11-09 16:09:13,676 INFO L73 IsDeterministic]: Start isDeterministic. Operand 344 states and 404 transitions. [2024-11-09 16:09:13,677 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:13,677 INFO L218 hiAutomatonCegarLoop]: Abstraction has 344 states and 404 transitions. [2024-11-09 16:09:13,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states and 404 transitions. [2024-11-09 16:09:13,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 344. [2024-11-09 16:09:13,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 344 states, 344 states have (on average 1.1744186046511629) internal successors, (404), 343 states have internal predecessors, (404), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:13,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 404 transitions. [2024-11-09 16:09:13,680 INFO L240 hiAutomatonCegarLoop]: Abstraction has 344 states and 404 transitions. [2024-11-09 16:09:13,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:13,681 INFO L425 stractBuchiCegarLoop]: Abstraction has 344 states and 404 transitions. [2024-11-09 16:09:13,681 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-09 16:09:13,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 344 states and 404 transitions. [2024-11-09 16:09:13,682 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 262 [2024-11-09 16:09:13,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:13,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:13,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,682 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:13,682 INFO L745 eck$LassoCheckResult]: Stem: 14356#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 14357#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 14381#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14374#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14328#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 14313#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14314#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14416#L250 assume !(0 == ~M_E~0); 14427#L250-2 assume !(0 == ~T1_E~0); 14368#L255-1 assume !(0 == ~E_1~0); 14369#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14388#L115 assume !(1 == ~m_pc~0); 14389#L115-2 is_master_triggered_~__retres1~0#1 := 0; 14393#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14319#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 14320#L300 assume !(0 != activate_threads_~tmp~1#1); 14401#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14439#L134 assume !(1 == ~t1_pc~0); 14396#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14390#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14367#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14322#L308 assume !(0 != activate_threads_~tmp___0~0#1); 14323#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14394#L273 assume !(1 == ~M_E~0); 14395#L273-2 assume !(1 == ~T1_E~0); 14435#L278-1 assume !(1 == ~E_1~0); 14406#L283-1 assume { :end_inline_reset_delta_events } true; 14391#L404-2 assume !false; 14392#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14415#L225-1 [2024-11-09 16:09:13,682 INFO L747 eck$LassoCheckResult]: Loop: 14415#L225-1 assume !false; 14421#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 14422#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 14413#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 14329#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14330#L206 assume 0 != eval_~tmp~0#1; 14364#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 14418#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 14326#L214-2 havoc eval_~tmp_ndt_1~0#1; 14327#L211-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 14425#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 14414#L228-2 havoc eval_~tmp_ndt_2~0#1; 14415#L225-1 [2024-11-09 16:09:13,683 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,683 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 2 times [2024-11-09 16:09:13,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596560805] [2024-11-09 16:09:13,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,687 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,690 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,690 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,691 INFO L85 PathProgramCache]: Analyzing trace with hash -1443506858, now seen corresponding path program 1 times [2024-11-09 16:09:13,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861075190] [2024-11-09 16:09:13,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,693 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,694 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,694 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:13,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1011793695, now seen corresponding path program 1 times [2024-11-09 16:09:13,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:13,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780672918] [2024-11-09 16:09:13,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:13,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:13,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,698 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,702 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:13,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:13,958 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:13,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:14,023 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 09.11 04:09:14 BoogieIcfgContainer [2024-11-09 16:09:14,023 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-09 16:09:14,023 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-09 16:09:14,023 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-09 16:09:14,024 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-09 16:09:14,024 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:09:10" (3/4) ... [2024-11-09 16:09:14,026 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-09 16:09:14,081 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-09 16:09:14,081 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-09 16:09:14,081 INFO L158 Benchmark]: Toolchain (without parser) took 4792.91ms. Allocated memory was 186.6MB in the beginning and 224.4MB in the end (delta: 37.7MB). Free memory was 152.9MB in the beginning and 160.2MB in the end (delta: -7.3MB). Peak memory consumption was 29.0MB. Max. memory is 16.1GB. [2024-11-09 16:09:14,081 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 102.8MB. Free memory is still 74.0MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-09 16:09:14,082 INFO L158 Benchmark]: CACSL2BoogieTranslator took 230.28ms. Allocated memory is still 186.6MB. Free memory was 152.9MB in the beginning and 138.2MB in the end (delta: 14.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-11-09 16:09:14,082 INFO L158 Benchmark]: Boogie Procedure Inliner took 29.70ms. Allocated memory is still 186.6MB. Free memory was 138.2MB in the beginning and 136.1MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-09 16:09:14,082 INFO L158 Benchmark]: Boogie Preprocessor took 43.35ms. Allocated memory is still 186.6MB. Free memory was 136.1MB in the beginning and 133.4MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-09 16:09:14,082 INFO L158 Benchmark]: RCFGBuilder took 516.68ms. Allocated memory is still 186.6MB. Free memory was 133.4MB in the beginning and 139.7MB in the end (delta: -6.3MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-09 16:09:14,082 INFO L158 Benchmark]: BuchiAutomizer took 3910.67ms. Allocated memory was 186.6MB in the beginning and 224.4MB in the end (delta: 37.7MB). Free memory was 139.7MB in the beginning and 163.3MB in the end (delta: -23.6MB). Peak memory consumption was 16.1MB. Max. memory is 16.1GB. [2024-11-09 16:09:14,082 INFO L158 Benchmark]: Witness Printer took 57.68ms. Allocated memory is still 224.4MB. Free memory was 163.3MB in the beginning and 160.2MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-09 16:09:14,084 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 102.8MB. Free memory is still 74.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 230.28ms. Allocated memory is still 186.6MB. Free memory was 152.9MB in the beginning and 138.2MB in the end (delta: 14.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 29.70ms. Allocated memory is still 186.6MB. Free memory was 138.2MB in the beginning and 136.1MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 43.35ms. Allocated memory is still 186.6MB. Free memory was 136.1MB in the beginning and 133.4MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 516.68ms. Allocated memory is still 186.6MB. Free memory was 133.4MB in the beginning and 139.7MB in the end (delta: -6.3MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 3910.67ms. Allocated memory was 186.6MB in the beginning and 224.4MB in the end (delta: 37.7MB). Free memory was 139.7MB in the beginning and 163.3MB in the end (delta: -23.6MB). Peak memory consumption was 16.1MB. Max. memory is 16.1GB. * Witness Printer took 57.68ms. Allocated memory is still 224.4MB. Free memory was 163.3MB in the beginning and 160.2MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (15 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * M_E) + 1) and consists of 3 locations. 15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 344 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.8s and 16 iterations. TraceHistogramMax:2. Analysis of lassos took 2.7s. Construction of modules took 0.2s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 3. Minimization of det autom 13. Minimization of nondet autom 3. Automata minimization 0.1s AutomataMinimizationTime, 16 MinimizatonAttempts, 448 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1525 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1524 mSDsluCounter, 5512 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2629 mSDsCounter, 99 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 326 IncrementalHoareTripleChecker+Invalid, 425 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 99 mSolverCounterUnsat, 2883 mSDtfsCounter, 326 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc1 concLT1 SILN2 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital40 mio100 ax100 hnf100 lsp25 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 25ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 8 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 201]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 201]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-09 16:09:14,108 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)