./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.09.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c7c6ca5d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.09.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 --- Real Ultimate output --- This is Ultimate 0.2.5-?-c7c6ca5-m [2024-11-09 16:09:20,075 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-09 16:09:20,145 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-09 16:09:20,152 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-09 16:09:20,152 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-09 16:09:20,174 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-09 16:09:20,174 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-09 16:09:20,175 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-09 16:09:20,175 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-09 16:09:20,175 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-09 16:09:20,176 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-09 16:09:20,176 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-09 16:09:20,176 INFO L153 SettingsManager]: * Use SBE=true [2024-11-09 16:09:20,176 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-09 16:09:20,177 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-09 16:09:20,177 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-09 16:09:20,177 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-09 16:09:20,177 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-09 16:09:20,177 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-09 16:09:20,178 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-09 16:09:20,178 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-09 16:09:20,182 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-09 16:09:20,182 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-09 16:09:20,182 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-09 16:09:20,182 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-09 16:09:20,182 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-09 16:09:20,182 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-09 16:09:20,183 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-09 16:09:20,183 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-09 16:09:20,183 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-09 16:09:20,183 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-09 16:09:20,183 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-09 16:09:20,183 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-09 16:09:20,184 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-09 16:09:20,184 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-09 16:09:20,184 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-09 16:09:20,184 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-09 16:09:20,184 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-09 16:09:20,185 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-09 16:09:20,185 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 [2024-11-09 16:09:20,404 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-09 16:09:20,422 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-09 16:09:20,425 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-09 16:09:20,426 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-09 16:09:20,427 INFO L274 PluginConnector]: CDTParser initialized [2024-11-09 16:09:20,428 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.09.cil.c [2024-11-09 16:09:21,729 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-09 16:09:21,935 INFO L384 CDTParser]: Found 1 translation units. [2024-11-09 16:09:21,936 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.09.cil.c [2024-11-09 16:09:21,957 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/54d013c91/3062be89b8c247039b3ad3e53c4891f1/FLAG5bd907bdb [2024-11-09 16:09:21,972 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/54d013c91/3062be89b8c247039b3ad3e53c4891f1 [2024-11-09 16:09:21,976 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-09 16:09:21,977 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-09 16:09:21,980 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-09 16:09:21,980 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-09 16:09:21,989 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-09 16:09:22,004 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:09:21" (1/1) ... [2024-11-09 16:09:22,007 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5c6c3ef8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22, skipping insertion in model container [2024-11-09 16:09:22,007 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:09:21" (1/1) ... [2024-11-09 16:09:22,056 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-09 16:09:22,279 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:09:22,292 INFO L200 MainTranslator]: Completed pre-run [2024-11-09 16:09:22,349 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:09:22,367 INFO L204 MainTranslator]: Completed translation [2024-11-09 16:09:22,367 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22 WrapperNode [2024-11-09 16:09:22,367 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-09 16:09:22,368 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-09 16:09:22,368 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-09 16:09:22,369 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-09 16:09:22,374 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,382 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,452 INFO L138 Inliner]: procedures = 46, calls = 58, calls flagged for inlining = 53, calls inlined = 171, statements flattened = 2601 [2024-11-09 16:09:22,452 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-09 16:09:22,453 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-09 16:09:22,453 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-09 16:09:22,453 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-09 16:09:22,462 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,462 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,477 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,500 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-09 16:09:22,500 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,500 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,520 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,554 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,558 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,564 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,573 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-09 16:09:22,574 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-09 16:09:22,574 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-09 16:09:22,574 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-09 16:09:22,575 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (1/1) ... [2024-11-09 16:09:22,580 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:09:22,590 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:09:22,604 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:09:22,607 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-09 16:09:22,645 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-09 16:09:22,645 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-09 16:09:22,645 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-09 16:09:22,645 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-09 16:09:22,744 INFO L238 CfgBuilder]: Building ICFG [2024-11-09 16:09:22,746 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-09 16:09:24,179 INFO L? ?]: Removed 524 outVars from TransFormulas that were not future-live. [2024-11-09 16:09:24,179 INFO L287 CfgBuilder]: Performing block encoding [2024-11-09 16:09:24,222 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-09 16:09:24,223 INFO L316 CfgBuilder]: Removed 13 assume(true) statements. [2024-11-09 16:09:24,223 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:09:24 BoogieIcfgContainer [2024-11-09 16:09:24,224 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-09 16:09:24,224 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-09 16:09:24,225 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-09 16:09:24,228 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-09 16:09:24,229 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:09:24,229 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 04:09:21" (1/3) ... [2024-11-09 16:09:24,230 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2c0f930b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:09:24, skipping insertion in model container [2024-11-09 16:09:24,230 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:09:24,230 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:09:22" (2/3) ... [2024-11-09 16:09:24,231 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2c0f930b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:09:24, skipping insertion in model container [2024-11-09 16:09:24,231 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:09:24,231 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:09:24" (3/3) ... [2024-11-09 16:09:24,232 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.09.cil.c [2024-11-09 16:09:24,311 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-09 16:09:24,311 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-09 16:09:24,311 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-09 16:09:24,311 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-09 16:09:24,311 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-09 16:09:24,312 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-09 16:09:24,312 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-09 16:09:24,312 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-09 16:09:24,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:24,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 983 [2024-11-09 16:09:24,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:24,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:24,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:24,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:24,391 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-09 16:09:24,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:24,411 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 983 [2024-11-09 16:09:24,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:24,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:24,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:24,419 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:24,438 INFO L745 eck$LassoCheckResult]: Stem: 138#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1013#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 813#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1008#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 733#L641true assume !(1 == ~m_i~0);~m_st~0 := 2; 786#L641-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 705#L646-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 495#L651-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 988#L656-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 333#L661-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 945#L666-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 869#L671-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 684#L676-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 382#L681-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 221#L686-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1102#L922true assume !(0 == ~M_E~0); 1041#L922-2true assume !(0 == ~T1_E~0); 1058#L927-1true assume !(0 == ~T2_E~0); 552#L932-1true assume !(0 == ~T3_E~0); 437#L937-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 494#L942-1true assume !(0 == ~T5_E~0); 736#L947-1true assume !(0 == ~T6_E~0); 556#L952-1true assume !(0 == ~T7_E~0); 627#L957-1true assume !(0 == ~T8_E~0); 982#L962-1true assume !(0 == ~T9_E~0); 420#L967-1true assume !(0 == ~E_1~0); 954#L972-1true assume !(0 == ~E_2~0); 715#L977-1true assume 0 == ~E_3~0;~E_3~0 := 1; 1050#L982-1true assume !(0 == ~E_4~0); 104#L987-1true assume !(0 == ~E_5~0); 107#L992-1true assume !(0 == ~E_6~0); 363#L997-1true assume !(0 == ~E_7~0); 900#L1002-1true assume !(0 == ~E_8~0); 354#L1007-1true assume !(0 == ~E_9~0); 6#L1012-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 891#L443true assume !(1 == ~m_pc~0); 571#L443-2true is_master_triggered_~__retres1~0#1 := 0; 562#L454true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 693#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 187#L1140true assume !(0 != activate_threads_~tmp~1#1); 55#L1140-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 914#L462true assume 1 == ~t1_pc~0; 459#L463true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 961#L473true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 579#L1148true assume !(0 != activate_threads_~tmp___0~0#1); 318#L1148-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 995#L481true assume !(1 == ~t2_pc~0); 790#L481-2true is_transmit2_triggered_~__retres1~2#1 := 0; 543#L492true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 255#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 234#L1156true assume !(0 != activate_threads_~tmp___1~0#1); 299#L1156-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1094#L500true assume 1 == ~t3_pc~0; 474#L501true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 754#L511true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 781#L1164true assume !(0 != activate_threads_~tmp___2~0#1); 7#L1164-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766#L519true assume 1 == ~t4_pc~0; 154#L520true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 298#L530true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 206#L1172true assume !(0 != activate_threads_~tmp___3~0#1); 515#L1172-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87#L538true assume !(1 == ~t5_pc~0); 845#L538-2true is_transmit5_triggered_~__retres1~5#1 := 0; 36#L549true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 697#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176#L1180true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 611#L1180-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1113#L557true assume 1 == ~t6_pc~0; 410#L558true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 824#L568true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 207#L1188true assume !(0 != activate_threads_~tmp___5~0#1); 948#L1188-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1065#L576true assume !(1 == ~t7_pc~0); 303#L576-2true is_transmit7_triggered_~__retres1~7#1 := 0; 409#L587true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1030#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1059#L1196true assume !(0 != activate_threads_~tmp___6~0#1); 670#L1196-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 257#L595true assume 1 == ~t8_pc~0; 1015#L596true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 700#L606true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 616#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 517#L1204true assume !(0 != activate_threads_~tmp___7~0#1); 952#L1204-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 151#L614true assume !(1 == ~t9_pc~0); 460#L614-2true is_transmit9_triggered_~__retres1~9#1 := 0; 99#L625true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 282#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 682#L1212true assume !(0 != activate_threads_~tmp___8~0#1); 236#L1212-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L1025true assume !(1 == ~M_E~0); 473#L1025-2true assume !(1 == ~T1_E~0); 603#L1030-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 761#L1035-1true assume !(1 == ~T3_E~0); 230#L1040-1true assume !(1 == ~T4_E~0); 740#L1045-1true assume !(1 == ~T5_E~0); 181#L1050-1true assume !(1 == ~T6_E~0); 292#L1055-1true assume !(1 == ~T7_E~0); 92#L1060-1true assume !(1 == ~T8_E~0); 123#L1065-1true assume !(1 == ~T9_E~0); 966#L1070-1true assume 1 == ~E_1~0;~E_1~0 := 2; 557#L1075-1true assume !(1 == ~E_2~0); 1098#L1080-1true assume !(1 == ~E_3~0); 549#L1085-1true assume !(1 == ~E_4~0); 858#L1090-1true assume !(1 == ~E_5~0); 980#L1095-1true assume !(1 == ~E_6~0); 586#L1100-1true assume !(1 == ~E_7~0); 591#L1105-1true assume !(1 == ~E_8~0); 79#L1110-1true assume 1 == ~E_9~0;~E_9~0 := 2; 262#L1115-1true assume { :end_inline_reset_delta_events } true; 202#L1396-2true [2024-11-09 16:09:24,442 INFO L747 eck$LassoCheckResult]: Loop: 202#L1396-2true assume !false; 967#L1397true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 946#L897-1true assume false; 621#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 387#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 349#L922-3true assume 0 == ~M_E~0;~M_E~0 := 1; 987#L922-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 172#L927-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 277#L932-3true assume !(0 == ~T3_E~0); 547#L937-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 75#L942-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 632#L947-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 278#L952-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 826#L957-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 850#L962-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 645#L967-3true assume 0 == ~E_1~0;~E_1~0 := 1; 875#L972-3true assume !(0 == ~E_2~0); 551#L977-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1101#L982-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1074#L987-3true assume 0 == ~E_5~0;~E_5~0 := 1; 243#L992-3true assume 0 == ~E_6~0;~E_6~0 := 1; 369#L997-3true assume 0 == ~E_7~0;~E_7~0 := 1; 241#L1002-3true assume 0 == ~E_8~0;~E_8~0 := 1; 507#L1007-3true assume 0 == ~E_9~0;~E_9~0 := 1; 93#L1012-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269#L443-30true assume !(1 == ~m_pc~0); 691#L443-32true is_master_triggered_~__retres1~0#1 := 0; 260#L454-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 265#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 964#L1140-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 721#L1140-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 339#L462-30true assume 1 == ~t1_pc~0; 225#L463-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 711#L473-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 435#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 757#L1148-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1079#L1148-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329#L481-30true assume !(1 == ~t2_pc~0); 726#L481-32true is_transmit2_triggered_~__retres1~2#1 := 0; 679#L492-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 140#L1156-30true assume !(0 != activate_threads_~tmp___1~0#1); 302#L1156-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567#L500-30true assume !(1 == ~t3_pc~0); 1080#L500-32true is_transmit3_triggered_~__retres1~3#1 := 0; 371#L511-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 414#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1040#L1164-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 290#L1164-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 651#L519-30true assume !(1 == ~t4_pc~0); 433#L519-32true is_transmit4_triggered_~__retres1~4#1 := 0; 415#L530-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 919#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422#L1172-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 533#L1172-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 943#L538-30true assume 1 == ~t5_pc~0; 98#L539-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 280#L549-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 522#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 674#L1180-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137#L1180-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143#L557-30true assume 1 == ~t6_pc~0; 2#L558-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 399#L568-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1056#L1188-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150#L1188-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 525#L576-30true assume 1 == ~t7_pc~0; 1044#L577-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 393#L587-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 578#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 855#L1196-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 231#L1196-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 211#L595-30true assume !(1 == ~t8_pc~0); 772#L595-32true is_transmit8_triggered_~__retres1~8#1 := 0; 178#L606-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1071#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 856#L1204-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1104#L1204-32true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 958#L614-30true assume !(1 == ~t9_pc~0); 788#L614-32true is_transmit9_triggered_~__retres1~9#1 := 0; 653#L625-10true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19#is_transmit9_triggered_returnLabel#11true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94#L1212-30true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 625#L1212-32true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L1025-3true assume 1 == ~M_E~0;~M_E~0 := 2; 321#L1025-5true assume !(1 == ~T1_E~0); 476#L1030-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 876#L1035-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1033#L1040-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1052#L1045-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 864#L1050-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 698#L1055-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 40#L1060-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 732#L1065-3true assume !(1 == ~T9_E~0); 723#L1070-3true assume 1 == ~E_1~0;~E_1~0 := 2; 536#L1075-3true assume 1 == ~E_2~0;~E_2~0 := 2; 877#L1080-3true assume 1 == ~E_3~0;~E_3~0 := 2; 959#L1085-3true assume 1 == ~E_4~0;~E_4~0 := 2; 708#L1090-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1019#L1095-3true assume 1 == ~E_6~0;~E_6~0 := 2; 738#L1100-3true assume 1 == ~E_7~0;~E_7~0 := 2; 932#L1105-3true assume !(1 == ~E_8~0); 116#L1110-3true assume 1 == ~E_9~0;~E_9~0 := 2; 793#L1115-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 769#L699-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 120#L751-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 222#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 720#L1415true assume !(0 == start_simulation_~tmp~3#1); 419#L1415-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 986#L699-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 423#L751-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1090#L1370true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1075#L1377true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 411#stop_simulation_returnLabel#1true start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 160#L1428true assume !(0 != start_simulation_~tmp___0~1#1); 202#L1396-2true [2024-11-09 16:09:24,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:24,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1400170149, now seen corresponding path program 1 times [2024-11-09 16:09:24,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:24,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56309826] [2024-11-09 16:09:24,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:24,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:24,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:24,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:24,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:24,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56309826] [2024-11-09 16:09:24,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56309826] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:24,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:24,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:24,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [251563289] [2024-11-09 16:09:24,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:24,744 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:24,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:24,745 INFO L85 PathProgramCache]: Analyzing trace with hash -541420616, now seen corresponding path program 1 times [2024-11-09 16:09:24,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:24,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717464006] [2024-11-09 16:09:24,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:24,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:24,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:24,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:24,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:24,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717464006] [2024-11-09 16:09:24,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717464006] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:24,813 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:24,813 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:24,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228337511] [2024-11-09 16:09:24,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:24,815 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:24,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:24,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:24,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:24,847 INFO L87 Difference]: Start difference. First operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:24,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:24,922 INFO L93 Difference]: Finished difference Result 1110 states and 1646 transitions. [2024-11-09 16:09:24,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1110 states and 1646 transitions. [2024-11-09 16:09:24,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:24,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1110 states to 1104 states and 1640 transitions. [2024-11-09 16:09:24,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-11-09 16:09:24,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-11-09 16:09:24,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1640 transitions. [2024-11-09 16:09:24,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:24,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2024-11-09 16:09:24,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1640 transitions. [2024-11-09 16:09:25,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-11-09 16:09:25,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4855072463768115) internal successors, (1640), 1103 states have internal predecessors, (1640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1640 transitions. [2024-11-09 16:09:25,017 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2024-11-09 16:09:25,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:25,023 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2024-11-09 16:09:25,026 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-09 16:09:25,026 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1640 transitions. [2024-11-09 16:09:25,031 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:25,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:25,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,038 INFO L745 eck$LassoCheckResult]: Stem: 2514#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3225#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3226#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3208#L646-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3030#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3031#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2839#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2840#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3294#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3200#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2899#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2670#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2671#L922 assume !(0 == ~M_E~0); 3331#L922-2 assume !(0 == ~T1_E~0); 3332#L927-1 assume !(0 == ~T2_E~0); 3094#L932-1 assume !(0 == ~T3_E~0); 2969#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2970#L942-1 assume !(0 == ~T5_E~0); 3029#L947-1 assume !(0 == ~T6_E~0); 3098#L952-1 assume !(0 == ~T7_E~0); 3099#L957-1 assume !(0 == ~T8_E~0); 3156#L962-1 assume !(0 == ~T9_E~0); 2948#L967-1 assume !(0 == ~E_1~0); 2949#L972-1 assume !(0 == ~E_2~0); 3212#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3213#L982-1 assume !(0 == ~E_4~0); 2447#L987-1 assume !(0 == ~E_5~0); 2448#L992-1 assume !(0 == ~E_6~0); 2454#L997-1 assume !(0 == ~E_7~0); 2875#L1002-1 assume !(0 == ~E_8~0); 2864#L1007-1 assume !(0 == ~E_9~0); 2241#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2242#L443 assume !(1 == ~m_pc~0); 3114#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3106#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3107#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2609#L1140 assume !(0 != activate_threads_~tmp~1#1); 2346#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2347#L462 assume 1 == ~t1_pc~0; 2995#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2961#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2283#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2818#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2819#L481 assume !(1 == ~t2_pc~0); 2603#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2602#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2729#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2693#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2694#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2786#L500 assume 1 == ~t3_pc~0; 3014#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3015#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2248#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2249#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2243#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2244#L519 assume 1 == ~t4_pc~0; 2546#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2547#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2349#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2643#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2410#L538 assume !(1 == ~t5_pc~0); 2411#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2308#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2309#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2589#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2590#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3141#L557 assume 1 == ~t6_pc~0; 2936#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2624#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2711#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2644#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2645#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3318#L576 assume !(1 == ~t7_pc~0); 2613#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2614#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2935#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3328#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3192#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2730#L595 assume 1 == ~t8_pc~0; 2731#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3205#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3146#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3053#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3054#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2539#L614 assume !(1 == ~t9_pc~0); 2540#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2436#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2437#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2762#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2696#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2697#L1025 assume !(1 == ~M_E~0); 2955#L1025-2 assume !(1 == ~T1_E~0); 3013#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3136#L1035-1 assume !(1 == ~T3_E~0); 2689#L1040-1 assume !(1 == ~T4_E~0); 2690#L1045-1 assume !(1 == ~T5_E~0); 2599#L1050-1 assume !(1 == ~T6_E~0); 2600#L1055-1 assume !(1 == ~T7_E~0); 2421#L1060-1 assume !(1 == ~T8_E~0); 2422#L1065-1 assume !(1 == ~T9_E~0); 2486#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3100#L1075-1 assume !(1 == ~E_2~0); 3101#L1080-1 assume !(1 == ~E_3~0); 3089#L1085-1 assume !(1 == ~E_4~0); 3090#L1090-1 assume !(1 == ~E_5~0); 3289#L1095-1 assume !(1 == ~E_6~0); 3123#L1100-1 assume !(1 == ~E_7~0); 3124#L1105-1 assume !(1 == ~E_8~0); 2392#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2393#L1115-1 assume { :end_inline_reset_delta_events } true; 2558#L1396-2 [2024-11-09 16:09:25,040 INFO L747 eck$LassoCheckResult]: Loop: 2558#L1396-2 assume !false; 2635#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3293#L897-1 assume !false; 3316#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3227#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2266#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2267#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2750#L766 assume !(0 != eval_~tmp~0#1); 3151#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2857#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2858#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2581#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2582#L932-3 assume !(0 == ~T3_E~0); 2755#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2384#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2385#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2756#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2757#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3278#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3173#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3174#L972-3 assume !(0 == ~E_2~0); 3092#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3093#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3333#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2709#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2710#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2704#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2705#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2423#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2424#L443-30 assume 1 == ~m_pc~0; 2457#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2458#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2736#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2741#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3216#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2846#L462-30 assume 1 == ~t1_pc~0; 2678#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2679#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2965#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2966#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3241#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2831#L481-30 assume 1 == ~t2_pc~0; 2549#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2550#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2639#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2518#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 2519#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2791#L500-30 assume 1 == ~t3_pc~0; 2554#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2555#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2884#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2940#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2775#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2776#L519-30 assume !(1 == ~t4_pc~0); 2964#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2941#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2942#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2952#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2953#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3072#L538-30 assume 1 == ~t5_pc~0; 2432#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2433#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2759#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3059#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2512#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2513#L557-30 assume 1 == ~t6_pc~0; 2231#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2233#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2352#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2353#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2537#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2538#L576-30 assume !(1 == ~t7_pc~0); 2306#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2307#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2914#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3121#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2688#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2652#L595-30 assume !(1 == ~t8_pc~0); 2653#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2591#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2592#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3287#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3288#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3319#L614-30 assume 1 == ~t9_pc~0; 2595#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2596#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2270#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2271#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2425#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3046#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2820#L1025-5 assume !(1 == ~T1_E~0); 2821#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3018#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3297#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3329#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3292#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3204#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2316#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2317#L1065-3 assume !(1 == ~T9_E~0); 3218#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3075#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3076#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3298#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3209#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3210#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3229#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3230#L1105-3 assume !(1 == ~E_8~0); 2471#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2472#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3245#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2327#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2672#L1415 assume !(0 == start_simulation_~tmp~3#1); 2945#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2946#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2380#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2282#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3334#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2937#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2557#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2558#L1396-2 [2024-11-09 16:09:25,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,041 INFO L85 PathProgramCache]: Analyzing trace with hash -1247434205, now seen corresponding path program 1 times [2024-11-09 16:09:25,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271478305] [2024-11-09 16:09:25,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271478305] [2024-11-09 16:09:25,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271478305] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,118 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,118 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1974514235] [2024-11-09 16:09:25,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,119 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:25,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,123 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 1 times [2024-11-09 16:09:25,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605343750] [2024-11-09 16:09:25,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [605343750] [2024-11-09 16:09:25,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [605343750] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243203653] [2024-11-09 16:09:25,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,247 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:25,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:25,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:25,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:25,248 INFO L87 Difference]: Start difference. First operand 1104 states and 1640 transitions. cyclomatic complexity: 537 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:25,267 INFO L93 Difference]: Finished difference Result 1104 states and 1639 transitions. [2024-11-09 16:09:25,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1639 transitions. [2024-11-09 16:09:25,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1639 transitions. [2024-11-09 16:09:25,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-11-09 16:09:25,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-11-09 16:09:25,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1639 transitions. [2024-11-09 16:09:25,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:25,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2024-11-09 16:09:25,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1639 transitions. [2024-11-09 16:09:25,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-11-09 16:09:25,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4846014492753623) internal successors, (1639), 1103 states have internal predecessors, (1639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1639 transitions. [2024-11-09 16:09:25,294 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2024-11-09 16:09:25,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:25,295 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2024-11-09 16:09:25,295 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-09 16:09:25,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1639 transitions. [2024-11-09 16:09:25,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:25,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:25,303 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,303 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,304 INFO L745 eck$LassoCheckResult]: Stem: 4729#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 4730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5488#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5489#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5440#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5441#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5423#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5245#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5246#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5054#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5055#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5509#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5415#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5114#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4885#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4886#L922 assume !(0 == ~M_E~0); 5546#L922-2 assume !(0 == ~T1_E~0); 5547#L927-1 assume !(0 == ~T2_E~0); 5309#L932-1 assume !(0 == ~T3_E~0); 5184#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5185#L942-1 assume !(0 == ~T5_E~0); 5244#L947-1 assume !(0 == ~T6_E~0); 5313#L952-1 assume !(0 == ~T7_E~0); 5314#L957-1 assume !(0 == ~T8_E~0); 5373#L962-1 assume !(0 == ~T9_E~0); 5163#L967-1 assume !(0 == ~E_1~0); 5164#L972-1 assume !(0 == ~E_2~0); 5427#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5428#L982-1 assume !(0 == ~E_4~0); 4662#L987-1 assume !(0 == ~E_5~0); 4663#L992-1 assume !(0 == ~E_6~0); 4669#L997-1 assume !(0 == ~E_7~0); 5090#L1002-1 assume !(0 == ~E_8~0); 5079#L1007-1 assume !(0 == ~E_9~0); 4456#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4457#L443 assume !(1 == ~m_pc~0); 5329#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5321#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5322#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4824#L1140 assume !(0 != activate_threads_~tmp~1#1); 4561#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4562#L462 assume 1 == ~t1_pc~0; 5210#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5176#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4498#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4499#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 5033#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5034#L481 assume !(1 == ~t2_pc~0); 4818#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4817#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4908#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4909#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5003#L500 assume 1 == ~t3_pc~0; 5229#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5230#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4463#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4464#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4458#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4459#L519 assume 1 == ~t4_pc~0; 4761#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4762#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4563#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4564#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4860#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4625#L538 assume !(1 == ~t5_pc~0); 4626#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4523#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4524#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4804#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4805#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5358#L557 assume 1 == ~t6_pc~0; 5151#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4839#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4926#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4861#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4862#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5533#L576 assume !(1 == ~t7_pc~0); 4828#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4829#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5150#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5543#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5407#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4945#L595 assume 1 == ~t8_pc~0; 4946#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5420#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5361#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5268#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5269#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4754#L614 assume !(1 == ~t9_pc~0); 4755#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4651#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4977#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4911#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4912#L1025 assume !(1 == ~M_E~0); 5170#L1025-2 assume !(1 == ~T1_E~0); 5228#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5351#L1035-1 assume !(1 == ~T3_E~0); 4904#L1040-1 assume !(1 == ~T4_E~0); 4905#L1045-1 assume !(1 == ~T5_E~0); 4814#L1050-1 assume !(1 == ~T6_E~0); 4815#L1055-1 assume !(1 == ~T7_E~0); 4636#L1060-1 assume !(1 == ~T8_E~0); 4637#L1065-1 assume !(1 == ~T9_E~0); 4701#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5315#L1075-1 assume !(1 == ~E_2~0); 5316#L1080-1 assume !(1 == ~E_3~0); 5304#L1085-1 assume !(1 == ~E_4~0); 5305#L1090-1 assume !(1 == ~E_5~0); 5504#L1095-1 assume !(1 == ~E_6~0); 5338#L1100-1 assume !(1 == ~E_7~0); 5339#L1105-1 assume !(1 == ~E_8~0); 4607#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 4608#L1115-1 assume { :end_inline_reset_delta_events } true; 4773#L1396-2 [2024-11-09 16:09:25,305 INFO L747 eck$LassoCheckResult]: Loop: 4773#L1396-2 assume !false; 4850#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5508#L897-1 assume !false; 5531#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5442#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4481#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4482#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4965#L766 assume !(0 != eval_~tmp~0#1); 5366#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5120#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5072#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5073#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4796#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4797#L932-3 assume !(0 == ~T3_E~0); 4970#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4599#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4600#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4971#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4972#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5493#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5388#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5389#L972-3 assume !(0 == ~E_2~0); 5307#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5308#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5548#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4924#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4925#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4922#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4923#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4638#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4639#L443-30 assume 1 == ~m_pc~0; 4672#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4673#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4951#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4956#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5431#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5061#L462-30 assume !(1 == ~t1_pc~0); 4897#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4896#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5180#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5181#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5456#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5046#L481-30 assume 1 == ~t2_pc~0; 4764#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4765#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4854#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4733#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 4734#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5006#L500-30 assume 1 == ~t3_pc~0; 4769#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4770#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5099#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5155#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4991#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4992#L519-30 assume 1 == ~t4_pc~0; 5344#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5156#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5157#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5167#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5168#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5287#L538-30 assume 1 == ~t5_pc~0; 4647#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4648#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4973#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5273#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4727#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4728#L557-30 assume 1 == ~t6_pc~0; 4446#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4448#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4567#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4568#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4752#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4753#L576-30 assume !(1 == ~t7_pc~0); 4516#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4517#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5129#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5335#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4903#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4867#L595-30 assume !(1 == ~t8_pc~0); 4868#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4806#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4807#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5502#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5503#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5534#L614-30 assume 1 == ~t9_pc~0; 4810#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4811#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4485#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4486#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4640#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5261#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5035#L1025-5 assume !(1 == ~T1_E~0); 5036#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5233#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5512#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5544#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5507#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5419#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4531#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4532#L1065-3 assume !(1 == ~T9_E~0); 5433#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5290#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5291#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5513#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5424#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5425#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5444#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5445#L1105-3 assume !(1 == ~E_8~0); 4686#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4687#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5461#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4542#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4887#L1415 assume !(0 == start_simulation_~tmp~3#1); 5160#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5161#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4595#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4496#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4497#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5549#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4772#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 4773#L1396-2 [2024-11-09 16:09:25,305 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,305 INFO L85 PathProgramCache]: Analyzing trace with hash -208849631, now seen corresponding path program 1 times [2024-11-09 16:09:25,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086153915] [2024-11-09 16:09:25,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,366 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086153915] [2024-11-09 16:09:25,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086153915] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1936917680] [2024-11-09 16:09:25,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,366 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:25,367 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,367 INFO L85 PathProgramCache]: Analyzing trace with hash 1344839060, now seen corresponding path program 1 times [2024-11-09 16:09:25,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222735375] [2024-11-09 16:09:25,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1222735375] [2024-11-09 16:09:25,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1222735375] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233438599] [2024-11-09 16:09:25,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,415 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:25,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:25,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:25,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:25,416 INFO L87 Difference]: Start difference. First operand 1104 states and 1639 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:25,433 INFO L93 Difference]: Finished difference Result 1104 states and 1638 transitions. [2024-11-09 16:09:25,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1638 transitions. [2024-11-09 16:09:25,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1638 transitions. [2024-11-09 16:09:25,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-11-09 16:09:25,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-11-09 16:09:25,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1638 transitions. [2024-11-09 16:09:25,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:25,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2024-11-09 16:09:25,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1638 transitions. [2024-11-09 16:09:25,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-11-09 16:09:25,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.483695652173913) internal successors, (1638), 1103 states have internal predecessors, (1638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1638 transitions. [2024-11-09 16:09:25,457 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2024-11-09 16:09:25,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:25,458 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2024-11-09 16:09:25,458 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-09 16:09:25,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1638 transitions. [2024-11-09 16:09:25,462 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:25,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:25,464 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,464 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,465 INFO L745 eck$LassoCheckResult]: Stem: 6946#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 6947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7655#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7656#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7638#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7460#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7461#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7269#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7270#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7725#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7630#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7329#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7100#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7101#L922 assume !(0 == ~M_E~0); 7761#L922-2 assume !(0 == ~T1_E~0); 7762#L927-1 assume !(0 == ~T2_E~0); 7524#L932-1 assume !(0 == ~T3_E~0); 7399#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7400#L942-1 assume !(0 == ~T5_E~0); 7459#L947-1 assume !(0 == ~T6_E~0); 7528#L952-1 assume !(0 == ~T7_E~0); 7529#L957-1 assume !(0 == ~T8_E~0); 7588#L962-1 assume !(0 == ~T9_E~0); 7378#L967-1 assume !(0 == ~E_1~0); 7379#L972-1 assume !(0 == ~E_2~0); 7642#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7643#L982-1 assume !(0 == ~E_4~0); 6877#L987-1 assume !(0 == ~E_5~0); 6878#L992-1 assume !(0 == ~E_6~0); 6884#L997-1 assume !(0 == ~E_7~0); 7307#L1002-1 assume !(0 == ~E_8~0); 7294#L1007-1 assume !(0 == ~E_9~0); 6671#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6672#L443 assume !(1 == ~m_pc~0); 7544#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7536#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7537#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7039#L1140 assume !(0 != activate_threads_~tmp~1#1); 6776#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6777#L462 assume 1 == ~t1_pc~0; 7425#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7392#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6714#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7248#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7249#L481 assume !(1 == ~t2_pc~0); 7033#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7032#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7123#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7124#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7218#L500 assume 1 == ~t3_pc~0; 7444#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7445#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6679#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6676#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6677#L519 assume 1 == ~t4_pc~0; 6976#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6977#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6778#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6779#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7075#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6840#L538 assume !(1 == ~t5_pc~0); 6841#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6738#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6739#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7019#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7020#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7573#L557 assume 1 == ~t6_pc~0; 7366#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7054#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7141#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7076#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7077#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7748#L576 assume !(1 == ~t7_pc~0); 7043#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7044#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7365#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7758#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7622#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7160#L595 assume 1 == ~t8_pc~0; 7161#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7635#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7576#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7483#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7484#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6969#L614 assume !(1 == ~t9_pc~0); 6970#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6866#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6867#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7192#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7126#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7127#L1025 assume !(1 == ~M_E~0); 7385#L1025-2 assume !(1 == ~T1_E~0); 7443#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7566#L1035-1 assume !(1 == ~T3_E~0); 7119#L1040-1 assume !(1 == ~T4_E~0); 7120#L1045-1 assume !(1 == ~T5_E~0); 7029#L1050-1 assume !(1 == ~T6_E~0); 7030#L1055-1 assume !(1 == ~T7_E~0); 6851#L1060-1 assume !(1 == ~T8_E~0); 6852#L1065-1 assume !(1 == ~T9_E~0); 6916#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7531#L1075-1 assume !(1 == ~E_2~0); 7532#L1080-1 assume !(1 == ~E_3~0); 7519#L1085-1 assume !(1 == ~E_4~0); 7520#L1090-1 assume !(1 == ~E_5~0); 7719#L1095-1 assume !(1 == ~E_6~0); 7553#L1100-1 assume !(1 == ~E_7~0); 7554#L1105-1 assume !(1 == ~E_8~0); 6822#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 6823#L1115-1 assume { :end_inline_reset_delta_events } true; 6988#L1396-2 [2024-11-09 16:09:25,465 INFO L747 eck$LassoCheckResult]: Loop: 6988#L1396-2 assume !false; 7065#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7723#L897-1 assume !false; 7746#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7657#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6696#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6697#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7180#L766 assume !(0 != eval_~tmp~0#1); 7581#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7335#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7289#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7290#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7011#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7012#L932-3 assume !(0 == ~T3_E~0); 7185#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6814#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6815#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7186#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7187#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7708#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7603#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L972-3 assume !(0 == ~E_2~0); 7522#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7523#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7763#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7139#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7140#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7137#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7138#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6853#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6854#L443-30 assume 1 == ~m_pc~0; 6887#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6888#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7166#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7171#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7647#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7276#L462-30 assume 1 == ~t1_pc~0; 7110#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7111#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7395#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7396#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7671#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7261#L481-30 assume 1 == ~t2_pc~0; 6979#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6980#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7069#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6948#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 6949#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7221#L500-30 assume 1 == ~t3_pc~0; 6984#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6985#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7314#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7370#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7205#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7206#L519-30 assume 1 == ~t4_pc~0; 7558#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7371#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7372#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7382#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7383#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7502#L538-30 assume !(1 == ~t5_pc~0); 6864#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 6863#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7188#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7488#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6942#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6943#L557-30 assume 1 == ~t6_pc~0; 6661#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6663#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6782#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6783#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6967#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6968#L576-30 assume 1 == ~t7_pc~0; 7492#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6735#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7344#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7550#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7118#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7082#L595-30 assume !(1 == ~t8_pc~0); 7083#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 7023#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7024#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7717#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7718#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7749#L614-30 assume 1 == ~t9_pc~0; 7026#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7027#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6700#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6701#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6855#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7476#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7250#L1025-5 assume !(1 == ~T1_E~0); 7251#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7448#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7727#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7759#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7722#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7634#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6746#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6747#L1065-3 assume !(1 == ~T9_E~0); 7648#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7505#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7506#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7728#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7639#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7640#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7659#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7660#L1105-3 assume !(1 == ~E_8~0); 6901#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6902#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7676#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6757#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6910#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 7102#L1415 assume !(0 == start_simulation_~tmp~3#1); 7376#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7377#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6810#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6712#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7764#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7367#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6987#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 6988#L1396-2 [2024-11-09 16:09:25,466 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,466 INFO L85 PathProgramCache]: Analyzing trace with hash 1764315747, now seen corresponding path program 1 times [2024-11-09 16:09:25,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684403651] [2024-11-09 16:09:25,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684403651] [2024-11-09 16:09:25,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684403651] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,505 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1200723154] [2024-11-09 16:09:25,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,505 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:25,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,505 INFO L85 PathProgramCache]: Analyzing trace with hash -321985611, now seen corresponding path program 1 times [2024-11-09 16:09:25,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606141256] [2024-11-09 16:09:25,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,551 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,551 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606141256] [2024-11-09 16:09:25,551 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [606141256] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [112704079] [2024-11-09 16:09:25,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,552 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:25,553 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:25,553 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:25,553 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:25,553 INFO L87 Difference]: Start difference. First operand 1104 states and 1638 transitions. cyclomatic complexity: 535 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:25,569 INFO L93 Difference]: Finished difference Result 1104 states and 1637 transitions. [2024-11-09 16:09:25,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1637 transitions. [2024-11-09 16:09:25,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1637 transitions. [2024-11-09 16:09:25,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-11-09 16:09:25,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-11-09 16:09:25,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1637 transitions. [2024-11-09 16:09:25,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:25,580 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2024-11-09 16:09:25,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1637 transitions. [2024-11-09 16:09:25,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-11-09 16:09:25,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4827898550724639) internal successors, (1637), 1103 states have internal predecessors, (1637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1637 transitions. [2024-11-09 16:09:25,596 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2024-11-09 16:09:25,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:25,598 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2024-11-09 16:09:25,598 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-09 16:09:25,598 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1637 transitions. [2024-11-09 16:09:25,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:25,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:25,605 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,607 INFO L745 eck$LassoCheckResult]: Stem: 9161#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 9162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9918#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9919#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9870#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 9871#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9853#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9675#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9676#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9484#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9485#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9940#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9845#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9544#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9315#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9316#L922 assume !(0 == ~M_E~0); 9976#L922-2 assume !(0 == ~T1_E~0); 9977#L927-1 assume !(0 == ~T2_E~0); 9739#L932-1 assume !(0 == ~T3_E~0); 9614#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9615#L942-1 assume !(0 == ~T5_E~0); 9674#L947-1 assume !(0 == ~T6_E~0); 9743#L952-1 assume !(0 == ~T7_E~0); 9744#L957-1 assume !(0 == ~T8_E~0); 9803#L962-1 assume !(0 == ~T9_E~0); 9593#L967-1 assume !(0 == ~E_1~0); 9594#L972-1 assume !(0 == ~E_2~0); 9857#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9858#L982-1 assume !(0 == ~E_4~0); 9092#L987-1 assume !(0 == ~E_5~0); 9093#L992-1 assume !(0 == ~E_6~0); 9099#L997-1 assume !(0 == ~E_7~0); 9522#L1002-1 assume !(0 == ~E_8~0); 9509#L1007-1 assume !(0 == ~E_9~0); 8886#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8887#L443 assume !(1 == ~m_pc~0); 9759#L443-2 is_master_triggered_~__retres1~0#1 := 0; 9751#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9752#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9254#L1140 assume !(0 != activate_threads_~tmp~1#1); 8991#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8992#L462 assume 1 == ~t1_pc~0; 9640#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9609#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8930#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8931#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 9463#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9464#L481 assume !(1 == ~t2_pc~0); 9248#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9247#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9338#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 9339#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9433#L500 assume 1 == ~t3_pc~0; 9659#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9660#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8893#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8894#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 8891#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8892#L519 assume 1 == ~t4_pc~0; 9194#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9195#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8993#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8994#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 9290#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9055#L538 assume !(1 == ~t5_pc~0); 9056#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8953#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8954#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9234#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9235#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9788#L557 assume 1 == ~t6_pc~0; 9581#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9269#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9356#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9291#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 9292#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9963#L576 assume !(1 == ~t7_pc~0); 9258#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9259#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9580#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9973#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 9837#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9377#L595 assume 1 == ~t8_pc~0; 9378#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9850#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9791#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9698#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 9699#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9184#L614 assume !(1 == ~t9_pc~0); 9185#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9081#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9082#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9407#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 9341#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9342#L1025 assume !(1 == ~M_E~0); 9600#L1025-2 assume !(1 == ~T1_E~0); 9658#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9781#L1035-1 assume !(1 == ~T3_E~0); 9334#L1040-1 assume !(1 == ~T4_E~0); 9335#L1045-1 assume !(1 == ~T5_E~0); 9244#L1050-1 assume !(1 == ~T6_E~0); 9245#L1055-1 assume !(1 == ~T7_E~0); 9066#L1060-1 assume !(1 == ~T8_E~0); 9067#L1065-1 assume !(1 == ~T9_E~0); 9131#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9746#L1075-1 assume !(1 == ~E_2~0); 9747#L1080-1 assume !(1 == ~E_3~0); 9734#L1085-1 assume !(1 == ~E_4~0); 9735#L1090-1 assume !(1 == ~E_5~0); 9934#L1095-1 assume !(1 == ~E_6~0); 9768#L1100-1 assume !(1 == ~E_7~0); 9769#L1105-1 assume !(1 == ~E_8~0); 9037#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 9038#L1115-1 assume { :end_inline_reset_delta_events } true; 9203#L1396-2 [2024-11-09 16:09:25,607 INFO L747 eck$LassoCheckResult]: Loop: 9203#L1396-2 assume !false; 9283#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9938#L897-1 assume !false; 9961#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9872#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8911#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8912#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9395#L766 assume !(0 != eval_~tmp~0#1); 9797#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9552#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9504#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9505#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9226#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9227#L932-3 assume !(0 == ~T3_E~0); 9400#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9029#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9030#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9401#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9402#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9923#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9818#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9819#L972-3 assume !(0 == ~E_2~0); 9737#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9738#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9978#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9354#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9355#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9352#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9353#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9068#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9069#L443-30 assume !(1 == ~m_pc~0); 9104#L443-32 is_master_triggered_~__retres1~0#1 := 0; 9103#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9381#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9386#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9861#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9491#L462-30 assume 1 == ~t1_pc~0; 9323#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9324#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9610#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9611#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9886#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9476#L481-30 assume 1 == ~t2_pc~0; 9191#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9192#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9284#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9163#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 9164#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9436#L500-30 assume !(1 == ~t3_pc~0); 9201#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 9200#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9529#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9585#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9420#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9421#L519-30 assume !(1 == ~t4_pc~0); 9607#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9586#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9587#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9597#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9598#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9717#L538-30 assume 1 == ~t5_pc~0; 9077#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9078#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9403#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9703#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9157#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9158#L557-30 assume 1 == ~t6_pc~0; 8876#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8878#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8997#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8998#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9183#L576-30 assume !(1 == ~t7_pc~0); 8949#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 8950#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9559#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9766#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9333#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9297#L595-30 assume !(1 == ~t8_pc~0); 9298#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 9238#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9239#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9932#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9933#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9964#L614-30 assume 1 == ~t9_pc~0; 9241#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9242#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8915#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8916#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9070#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9691#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9465#L1025-5 assume !(1 == ~T1_E~0); 9466#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9663#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9942#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9974#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9937#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9849#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8961#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8962#L1065-3 assume !(1 == ~T9_E~0); 9863#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9720#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9721#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9943#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9854#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9855#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9874#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9875#L1105-3 assume !(1 == ~E_8~0); 9116#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9117#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9891#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8972#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9125#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 9317#L1415 assume !(0 == start_simulation_~tmp~3#1); 9591#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9592#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9025#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8926#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8927#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9979#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9582#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9202#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 9203#L1396-2 [2024-11-09 16:09:25,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,608 INFO L85 PathProgramCache]: Analyzing trace with hash -388791071, now seen corresponding path program 1 times [2024-11-09 16:09:25,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174486440] [2024-11-09 16:09:25,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1174486440] [2024-11-09 16:09:25,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1174486440] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684963353] [2024-11-09 16:09:25,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,646 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:25,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,647 INFO L85 PathProgramCache]: Analyzing trace with hash -1993645742, now seen corresponding path program 1 times [2024-11-09 16:09:25,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756249102] [2024-11-09 16:09:25,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,714 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1756249102] [2024-11-09 16:09:25,714 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1756249102] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,714 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873767890] [2024-11-09 16:09:25,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,715 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:25,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:25,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:25,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:25,716 INFO L87 Difference]: Start difference. First operand 1104 states and 1637 transitions. cyclomatic complexity: 534 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:25,732 INFO L93 Difference]: Finished difference Result 1104 states and 1636 transitions. [2024-11-09 16:09:25,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1636 transitions. [2024-11-09 16:09:25,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,740 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1636 transitions. [2024-11-09 16:09:25,740 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-11-09 16:09:25,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-11-09 16:09:25,741 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1636 transitions. [2024-11-09 16:09:25,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:25,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2024-11-09 16:09:25,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1636 transitions. [2024-11-09 16:09:25,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-11-09 16:09:25,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4818840579710144) internal successors, (1636), 1103 states have internal predecessors, (1636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1636 transitions. [2024-11-09 16:09:25,755 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2024-11-09 16:09:25,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:25,756 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2024-11-09 16:09:25,756 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-09 16:09:25,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1636 transitions. [2024-11-09 16:09:25,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:25,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:25,762 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,763 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,763 INFO L745 eck$LassoCheckResult]: Stem: 11376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 11377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12133#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12134#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12085#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 12086#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12068#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11890#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11891#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11699#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11700#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12155#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12060#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11759#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11530#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11531#L922 assume !(0 == ~M_E~0); 12191#L922-2 assume !(0 == ~T1_E~0); 12192#L927-1 assume !(0 == ~T2_E~0); 11954#L932-1 assume !(0 == ~T3_E~0); 11829#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11830#L942-1 assume !(0 == ~T5_E~0); 11889#L947-1 assume !(0 == ~T6_E~0); 11958#L952-1 assume !(0 == ~T7_E~0); 11959#L957-1 assume !(0 == ~T8_E~0); 12019#L962-1 assume !(0 == ~T9_E~0); 11808#L967-1 assume !(0 == ~E_1~0); 11809#L972-1 assume !(0 == ~E_2~0); 12072#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 12073#L982-1 assume !(0 == ~E_4~0); 11309#L987-1 assume !(0 == ~E_5~0); 11310#L992-1 assume !(0 == ~E_6~0); 11314#L997-1 assume !(0 == ~E_7~0); 11737#L1002-1 assume !(0 == ~E_8~0); 11724#L1007-1 assume !(0 == ~E_9~0); 11101#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11102#L443 assume !(1 == ~m_pc~0); 11974#L443-2 is_master_triggered_~__retres1~0#1 := 0; 11966#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11967#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11469#L1140 assume !(0 != activate_threads_~tmp~1#1); 11206#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11207#L462 assume 1 == ~t1_pc~0; 11855#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11824#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11145#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11146#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 11678#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11679#L481 assume !(1 == ~t2_pc~0); 11463#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11462#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11589#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11553#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 11554#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11648#L500 assume 1 == ~t3_pc~0; 11874#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11875#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11108#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11109#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 11106#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11107#L519 assume 1 == ~t4_pc~0; 11409#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11410#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11209#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 11505#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11270#L538 assume !(1 == ~t5_pc~0); 11271#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11170#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11171#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11449#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11450#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12003#L557 assume 1 == ~t6_pc~0; 11796#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11484#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11571#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11506#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 11507#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12178#L576 assume !(1 == ~t7_pc~0); 11473#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11474#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12188#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 12052#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11592#L595 assume 1 == ~t8_pc~0; 11593#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12065#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12008#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11913#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 11914#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11399#L614 assume !(1 == ~t9_pc~0); 11400#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11296#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11297#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11622#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 11556#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11557#L1025 assume !(1 == ~M_E~0); 11815#L1025-2 assume !(1 == ~T1_E~0); 11873#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11997#L1035-1 assume !(1 == ~T3_E~0); 11549#L1040-1 assume !(1 == ~T4_E~0); 11550#L1045-1 assume !(1 == ~T5_E~0); 11459#L1050-1 assume !(1 == ~T6_E~0); 11460#L1055-1 assume !(1 == ~T7_E~0); 11281#L1060-1 assume !(1 == ~T8_E~0); 11282#L1065-1 assume !(1 == ~T9_E~0); 11346#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11961#L1075-1 assume !(1 == ~E_2~0); 11962#L1080-1 assume !(1 == ~E_3~0); 11949#L1085-1 assume !(1 == ~E_4~0); 11950#L1090-1 assume !(1 == ~E_5~0); 12149#L1095-1 assume !(1 == ~E_6~0); 11983#L1100-1 assume !(1 == ~E_7~0); 11984#L1105-1 assume !(1 == ~E_8~0); 11252#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11253#L1115-1 assume { :end_inline_reset_delta_events } true; 11418#L1396-2 [2024-11-09 16:09:25,764 INFO L747 eck$LassoCheckResult]: Loop: 11418#L1396-2 assume !false; 11498#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12153#L897-1 assume !false; 12176#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12087#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11126#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11127#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11610#L766 assume !(0 != eval_~tmp~0#1); 12012#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11767#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11719#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11720#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11441#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11442#L932-3 assume !(0 == ~T3_E~0); 11615#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11244#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11245#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11616#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11617#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12138#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12033#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12034#L972-3 assume !(0 == ~E_2~0); 11952#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11953#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12193#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11569#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11570#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11564#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11565#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11283#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11284#L443-30 assume 1 == ~m_pc~0; 11317#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11318#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11596#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11601#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12076#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11706#L462-30 assume 1 == ~t1_pc~0; 11538#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11539#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11825#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11826#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12101#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11691#L481-30 assume !(1 == ~t2_pc~0); 11408#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 11407#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11499#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11378#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 11379#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11651#L500-30 assume 1 == ~t3_pc~0; 11414#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11415#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11744#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11800#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11635#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11636#L519-30 assume 1 == ~t4_pc~0; 11988#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11801#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11802#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11812#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11813#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11932#L538-30 assume 1 == ~t5_pc~0; 11292#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11293#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11619#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11919#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11372#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11373#L557-30 assume 1 == ~t6_pc~0; 11091#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11093#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11212#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11213#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11397#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11398#L576-30 assume 1 == ~t7_pc~0; 11922#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11167#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11774#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11981#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11548#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11512#L595-30 assume !(1 == ~t8_pc~0); 11513#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 11453#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11454#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12147#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12148#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12179#L614-30 assume 1 == ~t9_pc~0; 11456#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11457#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11130#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11131#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11285#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11906#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11680#L1025-5 assume !(1 == ~T1_E~0); 11681#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11878#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12157#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12189#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12152#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12064#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11176#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11177#L1065-3 assume !(1 == ~T9_E~0); 12078#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11935#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11936#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12158#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12069#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12070#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12089#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12090#L1105-3 assume !(1 == ~E_8~0); 11331#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11332#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12106#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11187#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 11532#L1415 assume !(0 == start_simulation_~tmp~3#1); 11806#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11807#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11240#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11141#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 11142#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12194#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11797#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 11417#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 11418#L1396-2 [2024-11-09 16:09:25,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,765 INFO L85 PathProgramCache]: Analyzing trace with hash 234490531, now seen corresponding path program 1 times [2024-11-09 16:09:25,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217055686] [2024-11-09 16:09:25,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217055686] [2024-11-09 16:09:25,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217055686] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822916904] [2024-11-09 16:09:25,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,802 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:25,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,802 INFO L85 PathProgramCache]: Analyzing trace with hash -1124783627, now seen corresponding path program 1 times [2024-11-09 16:09:25,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425982759] [2024-11-09 16:09:25,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425982759] [2024-11-09 16:09:25,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425982759] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,847 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792681480] [2024-11-09 16:09:25,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,848 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:25,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:25,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:25,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:25,849 INFO L87 Difference]: Start difference. First operand 1104 states and 1636 transitions. cyclomatic complexity: 533 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:25,864 INFO L93 Difference]: Finished difference Result 1104 states and 1635 transitions. [2024-11-09 16:09:25,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1635 transitions. [2024-11-09 16:09:25,869 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1635 transitions. [2024-11-09 16:09:25,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-11-09 16:09:25,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-11-09 16:09:25,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1635 transitions. [2024-11-09 16:09:25,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:25,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2024-11-09 16:09:25,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1635 transitions. [2024-11-09 16:09:25,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-11-09 16:09:25,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4809782608695652) internal successors, (1635), 1103 states have internal predecessors, (1635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:25,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1635 transitions. [2024-11-09 16:09:25,888 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2024-11-09 16:09:25,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:25,890 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2024-11-09 16:09:25,890 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-09 16:09:25,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1635 transitions. [2024-11-09 16:09:25,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:25,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:25,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:25,896 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,896 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:25,896 INFO L745 eck$LassoCheckResult]: Stem: 13591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 13592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14348#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14349#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14300#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 14301#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14283#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14105#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14106#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13914#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13915#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14370#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14275#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13974#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13745#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13746#L922 assume !(0 == ~M_E~0); 14406#L922-2 assume !(0 == ~T1_E~0); 14407#L927-1 assume !(0 == ~T2_E~0); 14169#L932-1 assume !(0 == ~T3_E~0); 14044#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14045#L942-1 assume !(0 == ~T5_E~0); 14104#L947-1 assume !(0 == ~T6_E~0); 14173#L952-1 assume !(0 == ~T7_E~0); 14174#L957-1 assume !(0 == ~T8_E~0); 14234#L962-1 assume !(0 == ~T9_E~0); 14025#L967-1 assume !(0 == ~E_1~0); 14026#L972-1 assume !(0 == ~E_2~0); 14287#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 14288#L982-1 assume !(0 == ~E_4~0); 13524#L987-1 assume !(0 == ~E_5~0); 13525#L992-1 assume !(0 == ~E_6~0); 13529#L997-1 assume !(0 == ~E_7~0); 13952#L1002-1 assume !(0 == ~E_8~0); 13939#L1007-1 assume !(0 == ~E_9~0); 13316#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13317#L443 assume !(1 == ~m_pc~0); 14189#L443-2 is_master_triggered_~__retres1~0#1 := 0; 14181#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14182#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13684#L1140 assume !(0 != activate_threads_~tmp~1#1); 13421#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13422#L462 assume 1 == ~t1_pc~0; 14070#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14039#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13360#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13361#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 13893#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13894#L481 assume !(1 == ~t2_pc~0); 13678#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13677#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13804#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13768#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 13769#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13863#L500 assume 1 == ~t3_pc~0; 14089#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14090#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13323#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13324#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 13321#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13322#L519 assume 1 == ~t4_pc~0; 13624#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13625#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13424#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 13720#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13485#L538 assume !(1 == ~t5_pc~0); 13486#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13385#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13386#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13664#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13665#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14219#L557 assume 1 == ~t6_pc~0; 14011#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13699#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13721#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 13722#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14393#L576 assume !(1 == ~t7_pc~0); 13688#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13689#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14010#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14403#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 14267#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13805#L595 assume 1 == ~t8_pc~0; 13806#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14280#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14128#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 14129#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13614#L614 assume !(1 == ~t9_pc~0); 13615#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13510#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13511#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13837#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 13771#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13772#L1025 assume !(1 == ~M_E~0); 14030#L1025-2 assume !(1 == ~T1_E~0); 14088#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14211#L1035-1 assume !(1 == ~T3_E~0); 13763#L1040-1 assume !(1 == ~T4_E~0); 13764#L1045-1 assume !(1 == ~T5_E~0); 13674#L1050-1 assume !(1 == ~T6_E~0); 13675#L1055-1 assume !(1 == ~T7_E~0); 13496#L1060-1 assume !(1 == ~T8_E~0); 13497#L1065-1 assume !(1 == ~T9_E~0); 13561#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14175#L1075-1 assume !(1 == ~E_2~0); 14176#L1080-1 assume !(1 == ~E_3~0); 14164#L1085-1 assume !(1 == ~E_4~0); 14165#L1090-1 assume !(1 == ~E_5~0); 14364#L1095-1 assume !(1 == ~E_6~0); 14198#L1100-1 assume !(1 == ~E_7~0); 14199#L1105-1 assume !(1 == ~E_8~0); 13467#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 13468#L1115-1 assume { :end_inline_reset_delta_events } true; 13635#L1396-2 [2024-11-09 16:09:25,897 INFO L747 eck$LassoCheckResult]: Loop: 13635#L1396-2 assume !false; 13710#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14368#L897-1 assume !false; 14391#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14302#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13339#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13340#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13825#L766 assume !(0 != eval_~tmp~0#1); 14226#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13979#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13931#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13932#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13656#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13657#L932-3 assume !(0 == ~T3_E~0); 13830#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13459#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13460#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14353#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14248#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14249#L972-3 assume !(0 == ~E_2~0); 14167#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14168#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14408#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13784#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13785#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13779#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13780#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13498#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13499#L443-30 assume 1 == ~m_pc~0; 13532#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13533#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13811#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13816#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14291#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13921#L462-30 assume 1 == ~t1_pc~0; 13753#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13754#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14040#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14041#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14316#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13906#L481-30 assume 1 == ~t2_pc~0; 13621#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13622#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13714#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13593#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 13594#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13866#L500-30 assume 1 == ~t3_pc~0; 13629#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13630#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13959#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14015#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13850#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13851#L519-30 assume !(1 == ~t4_pc~0); 14037#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14016#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14017#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14027#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14028#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14147#L538-30 assume 1 == ~t5_pc~0; 13507#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13508#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13834#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14134#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13587#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13588#L557-30 assume 1 == ~t6_pc~0; 13306#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13308#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13427#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13428#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13612#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13613#L576-30 assume !(1 == ~t7_pc~0); 13381#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 13382#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13989#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14196#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13765#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13727#L595-30 assume !(1 == ~t8_pc~0); 13728#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 13668#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13669#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14362#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14363#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14394#L614-30 assume 1 == ~t9_pc~0; 13671#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13672#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13345#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13346#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13500#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14121#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13895#L1025-5 assume !(1 == ~T1_E~0); 13896#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14093#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14372#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14404#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14367#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14279#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13391#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13392#L1065-3 assume !(1 == ~T9_E~0); 14293#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14150#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14151#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14373#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14284#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14285#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14304#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14305#L1105-3 assume !(1 == ~E_8~0); 13546#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13547#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14321#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13402#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13555#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 13747#L1415 assume !(0 == start_simulation_~tmp~3#1); 14021#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14022#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13455#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13356#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 13357#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14409#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14012#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 13634#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 13635#L1396-2 [2024-11-09 16:09:25,898 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,898 INFO L85 PathProgramCache]: Analyzing trace with hash 116049057, now seen corresponding path program 1 times [2024-11-09 16:09:25,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157004557] [2024-11-09 16:09:25,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157004557] [2024-11-09 16:09:25,934 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157004557] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,934 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,934 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1895943858] [2024-11-09 16:09:25,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,935 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:25,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:25,935 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 2 times [2024-11-09 16:09:25,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:25,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981863932] [2024-11-09 16:09:25,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:25,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:25,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:25,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:25,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:25,985 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981863932] [2024-11-09 16:09:25,985 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981863932] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:25,985 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:25,985 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:25,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857864981] [2024-11-09 16:09:25,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:25,986 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:25,986 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:25,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:25,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:25,987 INFO L87 Difference]: Start difference. First operand 1104 states and 1635 transitions. cyclomatic complexity: 532 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:26,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:26,003 INFO L93 Difference]: Finished difference Result 1104 states and 1634 transitions. [2024-11-09 16:09:26,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1634 transitions. [2024-11-09 16:09:26,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:26,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1634 transitions. [2024-11-09 16:09:26,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-11-09 16:09:26,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-11-09 16:09:26,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1634 transitions. [2024-11-09 16:09:26,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:26,014 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2024-11-09 16:09:26,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1634 transitions. [2024-11-09 16:09:26,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-11-09 16:09:26,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.480072463768116) internal successors, (1634), 1103 states have internal predecessors, (1634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:26,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1634 transitions. [2024-11-09 16:09:26,029 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2024-11-09 16:09:26,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:26,030 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2024-11-09 16:09:26,030 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-09 16:09:26,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1634 transitions. [2024-11-09 16:09:26,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:26,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:26,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:26,035 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:26,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:26,036 INFO L745 eck$LassoCheckResult]: Stem: 15804#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 15805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 16563#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16515#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 16516#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16498#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16320#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16321#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16128#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16129#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16584#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16489#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16189#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15960#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15961#L922 assume !(0 == ~M_E~0); 16621#L922-2 assume !(0 == ~T1_E~0); 16622#L927-1 assume !(0 == ~T2_E~0); 16384#L932-1 assume !(0 == ~T3_E~0); 16259#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16260#L942-1 assume !(0 == ~T5_E~0); 16319#L947-1 assume !(0 == ~T6_E~0); 16388#L952-1 assume !(0 == ~T7_E~0); 16389#L957-1 assume !(0 == ~T8_E~0); 16446#L962-1 assume !(0 == ~T9_E~0); 16238#L967-1 assume !(0 == ~E_1~0); 16239#L972-1 assume !(0 == ~E_2~0); 16502#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16503#L982-1 assume !(0 == ~E_4~0); 15737#L987-1 assume !(0 == ~E_5~0); 15738#L992-1 assume !(0 == ~E_6~0); 15744#L997-1 assume !(0 == ~E_7~0); 16165#L1002-1 assume !(0 == ~E_8~0); 16154#L1007-1 assume !(0 == ~E_9~0); 15531#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15532#L443 assume !(1 == ~m_pc~0); 16404#L443-2 is_master_triggered_~__retres1~0#1 := 0; 16396#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16397#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15899#L1140 assume !(0 != activate_threads_~tmp~1#1); 15636#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15637#L462 assume 1 == ~t1_pc~0; 16285#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16251#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15573#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 16106#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16107#L481 assume !(1 == ~t2_pc~0); 15893#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15892#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16019#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15983#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 15984#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16076#L500 assume 1 == ~t3_pc~0; 16304#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16305#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15539#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 15533#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15534#L519 assume 1 == ~t4_pc~0; 15836#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15837#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15638#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15639#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 15933#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15700#L538 assume !(1 == ~t5_pc~0); 15701#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15598#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15599#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15879#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15880#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16431#L557 assume 1 == ~t6_pc~0; 16226#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15914#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16001#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15934#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 15935#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16608#L576 assume !(1 == ~t7_pc~0); 15903#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15904#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16618#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 16482#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16020#L595 assume 1 == ~t8_pc~0; 16021#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16495#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16436#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16343#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 16344#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15829#L614 assume !(1 == ~t9_pc~0); 15830#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15725#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15726#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16052#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 15986#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15987#L1025 assume !(1 == ~M_E~0); 16245#L1025-2 assume !(1 == ~T1_E~0); 16303#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16426#L1035-1 assume !(1 == ~T3_E~0); 15978#L1040-1 assume !(1 == ~T4_E~0); 15979#L1045-1 assume !(1 == ~T5_E~0); 15889#L1050-1 assume !(1 == ~T6_E~0); 15890#L1055-1 assume !(1 == ~T7_E~0); 15711#L1060-1 assume !(1 == ~T8_E~0); 15712#L1065-1 assume !(1 == ~T9_E~0); 15776#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16390#L1075-1 assume !(1 == ~E_2~0); 16391#L1080-1 assume !(1 == ~E_3~0); 16379#L1085-1 assume !(1 == ~E_4~0); 16380#L1090-1 assume !(1 == ~E_5~0); 16579#L1095-1 assume !(1 == ~E_6~0); 16413#L1100-1 assume !(1 == ~E_7~0); 16414#L1105-1 assume !(1 == ~E_8~0); 15682#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 15683#L1115-1 assume { :end_inline_reset_delta_events } true; 15850#L1396-2 [2024-11-09 16:09:26,036 INFO L747 eck$LassoCheckResult]: Loop: 15850#L1396-2 assume !false; 15925#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16583#L897-1 assume !false; 16606#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16517#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15554#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15555#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16040#L766 assume !(0 != eval_~tmp~0#1); 16441#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16146#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16147#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15871#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15872#L932-3 assume !(0 == ~T3_E~0); 16045#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15674#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15675#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16046#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16047#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16568#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16463#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16464#L972-3 assume !(0 == ~E_2~0); 16382#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16383#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16623#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15999#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16000#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15994#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15995#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15713#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15714#L443-30 assume 1 == ~m_pc~0; 15747#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15748#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16026#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16031#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16506#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16136#L462-30 assume 1 == ~t1_pc~0; 15968#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15969#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16255#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16256#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16531#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16121#L481-30 assume !(1 == ~t2_pc~0); 15841#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 15840#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15929#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15808#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 15809#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16081#L500-30 assume 1 == ~t3_pc~0; 15844#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15845#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16174#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16230#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16065#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16066#L519-30 assume 1 == ~t4_pc~0; 16418#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16231#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16232#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16242#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16243#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16362#L538-30 assume 1 == ~t5_pc~0; 15722#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15723#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16049#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16349#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15802#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15803#L557-30 assume 1 == ~t6_pc~0; 15521#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15523#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15642#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15643#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15827#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15828#L576-30 assume 1 == ~t7_pc~0; 16352#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15597#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16204#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16411#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15980#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15942#L595-30 assume !(1 == ~t8_pc~0); 15943#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 15883#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15884#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16577#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16578#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16609#L614-30 assume !(1 == ~t9_pc~0); 15888#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 15887#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15560#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15561#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15715#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16336#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16110#L1025-5 assume !(1 == ~T1_E~0); 16111#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16308#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16587#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16619#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16582#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16494#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15606#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15607#L1065-3 assume !(1 == ~T9_E~0); 16508#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16365#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16366#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16588#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16499#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16500#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16519#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16520#L1105-3 assume !(1 == ~E_8~0); 15761#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15762#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16536#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15617#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15770#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 15962#L1415 assume !(0 == start_simulation_~tmp~3#1); 16236#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16237#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15670#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 15572#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16624#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16227#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15849#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 15850#L1396-2 [2024-11-09 16:09:26,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:26,037 INFO L85 PathProgramCache]: Analyzing trace with hash -1273244957, now seen corresponding path program 1 times [2024-11-09 16:09:26,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:26,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452390297] [2024-11-09 16:09:26,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:26,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:26,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:26,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:26,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:26,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452390297] [2024-11-09 16:09:26,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1452390297] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:26,095 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:26,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:26,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005870835] [2024-11-09 16:09:26,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:26,096 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:26,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:26,096 INFO L85 PathProgramCache]: Analyzing trace with hash -601462956, now seen corresponding path program 1 times [2024-11-09 16:09:26,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:26,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189228853] [2024-11-09 16:09:26,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:26,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:26,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:26,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:26,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:26,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1189228853] [2024-11-09 16:09:26,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1189228853] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:26,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:26,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:26,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1188914749] [2024-11-09 16:09:26,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:26,146 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:26,146 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:26,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:26,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:26,147 INFO L87 Difference]: Start difference. First operand 1104 states and 1634 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:26,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:26,163 INFO L93 Difference]: Finished difference Result 1104 states and 1633 transitions. [2024-11-09 16:09:26,163 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1633 transitions. [2024-11-09 16:09:26,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:26,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1633 transitions. [2024-11-09 16:09:26,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-11-09 16:09:26,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-11-09 16:09:26,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1633 transitions. [2024-11-09 16:09:26,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:26,176 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2024-11-09 16:09:26,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1633 transitions. [2024-11-09 16:09:26,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-11-09 16:09:26,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4791666666666667) internal successors, (1633), 1103 states have internal predecessors, (1633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:26,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1633 transitions. [2024-11-09 16:09:26,192 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2024-11-09 16:09:26,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:26,193 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2024-11-09 16:09:26,194 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-09 16:09:26,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1633 transitions. [2024-11-09 16:09:26,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-11-09 16:09:26,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:26,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:26,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:26,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:26,200 INFO L745 eck$LassoCheckResult]: Stem: 18019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 18020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 18778#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18779#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18730#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 18731#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18713#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18535#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18536#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18343#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18344#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18799#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18704#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18404#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18175#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18176#L922 assume !(0 == ~M_E~0); 18836#L922-2 assume !(0 == ~T1_E~0); 18837#L927-1 assume !(0 == ~T2_E~0); 18599#L932-1 assume !(0 == ~T3_E~0); 18474#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18475#L942-1 assume !(0 == ~T5_E~0); 18534#L947-1 assume !(0 == ~T6_E~0); 18603#L952-1 assume !(0 == ~T7_E~0); 18604#L957-1 assume !(0 == ~T8_E~0); 18661#L962-1 assume !(0 == ~T9_E~0); 18453#L967-1 assume !(0 == ~E_1~0); 18454#L972-1 assume !(0 == ~E_2~0); 18717#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 18718#L982-1 assume !(0 == ~E_4~0); 17952#L987-1 assume !(0 == ~E_5~0); 17953#L992-1 assume !(0 == ~E_6~0); 17959#L997-1 assume !(0 == ~E_7~0); 18380#L1002-1 assume !(0 == ~E_8~0); 18369#L1007-1 assume !(0 == ~E_9~0); 17746#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17747#L443 assume !(1 == ~m_pc~0); 18619#L443-2 is_master_triggered_~__retres1~0#1 := 0; 18611#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18612#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18114#L1140 assume !(0 != activate_threads_~tmp~1#1); 17851#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17852#L462 assume 1 == ~t1_pc~0; 18500#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18466#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17789#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 18321#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18322#L481 assume !(1 == ~t2_pc~0); 18108#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18107#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18234#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18198#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 18199#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18291#L500 assume 1 == ~t3_pc~0; 18519#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18520#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17753#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17754#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 17748#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17749#L519 assume 1 == ~t4_pc~0; 18051#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18052#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17853#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17854#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 18148#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17915#L538 assume !(1 == ~t5_pc~0); 17916#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17813#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17814#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18094#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18095#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18646#L557 assume 1 == ~t6_pc~0; 18441#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18129#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18149#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 18150#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18823#L576 assume !(1 == ~t7_pc~0); 18118#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18119#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18440#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18833#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 18697#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18235#L595 assume 1 == ~t8_pc~0; 18236#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18710#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18651#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18558#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 18559#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18044#L614 assume !(1 == ~t9_pc~0); 18045#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 17940#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17941#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18267#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 18201#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18202#L1025 assume !(1 == ~M_E~0); 18460#L1025-2 assume !(1 == ~T1_E~0); 18518#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18641#L1035-1 assume !(1 == ~T3_E~0); 18193#L1040-1 assume !(1 == ~T4_E~0); 18194#L1045-1 assume !(1 == ~T5_E~0); 18104#L1050-1 assume !(1 == ~T6_E~0); 18105#L1055-1 assume !(1 == ~T7_E~0); 17926#L1060-1 assume !(1 == ~T8_E~0); 17927#L1065-1 assume !(1 == ~T9_E~0); 17991#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18605#L1075-1 assume !(1 == ~E_2~0); 18606#L1080-1 assume !(1 == ~E_3~0); 18594#L1085-1 assume !(1 == ~E_4~0); 18595#L1090-1 assume !(1 == ~E_5~0); 18794#L1095-1 assume !(1 == ~E_6~0); 18628#L1100-1 assume !(1 == ~E_7~0); 18629#L1105-1 assume !(1 == ~E_8~0); 17897#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 17898#L1115-1 assume { :end_inline_reset_delta_events } true; 18065#L1396-2 [2024-11-09 16:09:26,200 INFO L747 eck$LassoCheckResult]: Loop: 18065#L1396-2 assume !false; 18140#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18798#L897-1 assume !false; 18821#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18732#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17769#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17770#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18255#L766 assume !(0 != eval_~tmp~0#1); 18656#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18409#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18361#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18362#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18086#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18087#L932-3 assume !(0 == ~T3_E~0); 18260#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17889#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17890#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18261#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18262#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18783#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18678#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18679#L972-3 assume !(0 == ~E_2~0); 18597#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18598#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18838#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18214#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18215#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18209#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18210#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17928#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17929#L443-30 assume 1 == ~m_pc~0; 17962#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17963#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18241#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18246#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18721#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18351#L462-30 assume 1 == ~t1_pc~0; 18183#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18184#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18470#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18471#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18746#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18336#L481-30 assume 1 == ~t2_pc~0; 18054#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18055#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18144#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18023#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 18024#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18296#L500-30 assume 1 == ~t3_pc~0; 18059#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18060#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18389#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18445#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18280#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18281#L519-30 assume !(1 == ~t4_pc~0); 18469#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 18446#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18447#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18457#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18458#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18577#L538-30 assume 1 == ~t5_pc~0; 17937#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17938#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18264#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18564#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18017#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18018#L557-30 assume 1 == ~t6_pc~0; 17736#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17738#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17857#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17858#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18042#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18043#L576-30 assume !(1 == ~t7_pc~0); 17811#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 17812#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18419#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18626#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18195#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18157#L595-30 assume !(1 == ~t8_pc~0); 18158#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 18098#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18099#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18792#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18793#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18824#L614-30 assume 1 == ~t9_pc~0; 18101#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18102#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17775#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17776#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17930#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18551#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18325#L1025-5 assume !(1 == ~T1_E~0); 18326#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18523#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18802#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18834#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18797#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18709#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17821#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17822#L1065-3 assume !(1 == ~T9_E~0); 18723#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18580#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18581#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18803#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18714#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18715#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18734#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18735#L1105-3 assume !(1 == ~E_8~0); 17976#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17977#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18751#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17832#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17985#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 18177#L1415 assume !(0 == start_simulation_~tmp~3#1); 18451#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18452#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17885#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 17787#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18839#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18442#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 18064#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 18065#L1396-2 [2024-11-09 16:09:26,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:26,201 INFO L85 PathProgramCache]: Analyzing trace with hash 760149089, now seen corresponding path program 1 times [2024-11-09 16:09:26,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:26,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [835893341] [2024-11-09 16:09:26,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:26,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:26,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:26,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:26,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:26,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [835893341] [2024-11-09 16:09:26,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [835893341] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:26,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:26,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:26,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285358701] [2024-11-09 16:09:26,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:26,269 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:26,269 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:26,269 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 3 times [2024-11-09 16:09:26,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:26,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125256458] [2024-11-09 16:09:26,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:26,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:26,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:26,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:26,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:26,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125256458] [2024-11-09 16:09:26,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125256458] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:26,316 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:26,316 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:26,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526285948] [2024-11-09 16:09:26,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:26,317 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:26,317 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:26,317 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:26,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:26,317 INFO L87 Difference]: Start difference. First operand 1104 states and 1633 transitions. cyclomatic complexity: 530 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:26,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:26,424 INFO L93 Difference]: Finished difference Result 2100 states and 3099 transitions. [2024-11-09 16:09:26,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2100 states and 3099 transitions. [2024-11-09 16:09:26,432 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1958 [2024-11-09 16:09:26,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2100 states to 2100 states and 3099 transitions. [2024-11-09 16:09:26,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2100 [2024-11-09 16:09:26,440 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2100 [2024-11-09 16:09:26,440 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2100 states and 3099 transitions. [2024-11-09 16:09:26,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:26,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2024-11-09 16:09:26,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2100 states and 3099 transitions. [2024-11-09 16:09:26,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2100 to 2100. [2024-11-09 16:09:26,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2100 states, 2100 states have (on average 1.4757142857142858) internal successors, (3099), 2099 states have internal predecessors, (3099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:26,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2100 states to 2100 states and 3099 transitions. [2024-11-09 16:09:26,475 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2024-11-09 16:09:26,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:26,476 INFO L425 stractBuchiCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2024-11-09 16:09:26,476 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-09 16:09:26,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2100 states and 3099 transitions. [2024-11-09 16:09:26,512 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1958 [2024-11-09 16:09:26,512 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:26,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:26,514 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:26,514 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:26,514 INFO L745 eck$LassoCheckResult]: Stem: 21234#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 21235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22035#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22036#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21976#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 21977#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21954#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21757#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21758#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21561#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21562#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22065#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21944#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21621#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21390#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21391#L922 assume !(0 == ~M_E~0); 22129#L922-2 assume !(0 == ~T1_E~0); 22130#L927-1 assume !(0 == ~T2_E~0); 21821#L932-1 assume !(0 == ~T3_E~0); 21695#L937-1 assume !(0 == ~T4_E~0); 21696#L942-1 assume !(0 == ~T5_E~0); 21756#L947-1 assume !(0 == ~T6_E~0); 21825#L952-1 assume !(0 == ~T7_E~0); 21826#L957-1 assume !(0 == ~T8_E~0); 21890#L962-1 assume !(0 == ~T9_E~0); 21673#L967-1 assume !(0 == ~E_1~0); 21674#L972-1 assume !(0 == ~E_2~0); 21959#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 21960#L982-1 assume !(0 == ~E_4~0); 21166#L987-1 assume !(0 == ~E_5~0); 21167#L992-1 assume !(0 == ~E_6~0); 21173#L997-1 assume !(0 == ~E_7~0); 21597#L1002-1 assume !(0 == ~E_8~0); 21586#L1007-1 assume !(0 == ~E_9~0); 20960#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20961#L443 assume !(1 == ~m_pc~0); 21841#L443-2 is_master_triggered_~__retres1~0#1 := 0; 21833#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21834#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21329#L1140 assume !(0 != activate_threads_~tmp~1#1); 21065#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21066#L462 assume 1 == ~t1_pc~0; 21721#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21687#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21002#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21003#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 21540#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21541#L481 assume !(1 == ~t2_pc~0); 21323#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21322#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21451#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21414#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 21415#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21508#L500 assume 1 == ~t3_pc~0; 21741#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21742#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20967#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20968#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 20962#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20963#L519 assume 1 == ~t4_pc~0; 21266#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21267#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21067#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21068#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 21363#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21129#L538 assume !(1 == ~t5_pc~0); 21130#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21027#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21028#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21309#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21310#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21872#L557 assume 1 == ~t6_pc~0; 21659#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21344#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21432#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21364#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 21365#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22101#L576 assume !(1 == ~t7_pc~0); 21333#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21334#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21658#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22126#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 21934#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21452#L595 assume 1 == ~t8_pc~0; 21453#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21951#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21878#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21780#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 21781#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21259#L614 assume !(1 == ~t9_pc~0); 21260#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21155#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21156#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21484#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 21417#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21418#L1025 assume !(1 == ~M_E~0); 21681#L1025-2 assume !(1 == ~T1_E~0); 21740#L1030-1 assume !(1 == ~T2_E~0); 21866#L1035-1 assume !(1 == ~T3_E~0); 21409#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21410#L1045-1 assume !(1 == ~T5_E~0); 21319#L1050-1 assume !(1 == ~T6_E~0); 21320#L1055-1 assume !(1 == ~T7_E~0); 21140#L1060-1 assume !(1 == ~T8_E~0); 21141#L1065-1 assume !(1 == ~T9_E~0); 21206#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21827#L1075-1 assume !(1 == ~E_2~0); 21828#L1080-1 assume !(1 == ~E_3~0); 21816#L1085-1 assume !(1 == ~E_4~0); 21817#L1090-1 assume !(1 == ~E_5~0); 22060#L1095-1 assume !(1 == ~E_6~0); 21851#L1100-1 assume !(1 == ~E_7~0); 21852#L1105-1 assume !(1 == ~E_8~0); 21111#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 21112#L1115-1 assume { :end_inline_reset_delta_events } true; 21278#L1396-2 [2024-11-09 16:09:26,515 INFO L747 eck$LassoCheckResult]: Loop: 21278#L1396-2 assume !false; 21355#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22155#L897-1 assume !false; 22154#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22153#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22143#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22142#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22048#L766 assume !(0 != eval_~tmp~0#1); 22050#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22141#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21579#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21580#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22139#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22140#L932-3 assume !(0 == ~T3_E~0); 23023#L937-3 assume !(0 == ~T4_E~0); 23022#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23021#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23020#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23019#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23018#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23017#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23016#L972-3 assume !(0 == ~E_2~0); 23015#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22138#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22135#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21430#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21431#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21425#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21426#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21142#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21143#L443-30 assume 1 == ~m_pc~0; 21176#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21177#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21458#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21463#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21966#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21568#L462-30 assume 1 == ~t1_pc~0; 21400#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21401#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21691#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21692#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22770#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22768#L481-30 assume 1 == ~t2_pc~0; 22764#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22762#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22760#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22758#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 22756#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22754#L500-30 assume 1 == ~t3_pc~0; 22750#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22749#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22748#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22747#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22746#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22745#L519-30 assume 1 == ~t4_pc~0; 22743#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22742#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22741#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22740#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22739#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22738#L538-30 assume 1 == ~t5_pc~0; 22736#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22735#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22734#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22733#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22732#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22731#L557-30 assume !(1 == ~t6_pc~0); 22729#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 22728#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22727#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22726#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22725#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22724#L576-30 assume 1 == ~t7_pc~0; 22722#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22721#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22720#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22719#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22718#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22717#L595-30 assume !(1 == ~t8_pc~0); 22714#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 22713#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22711#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22058#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22059#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22106#L614-30 assume 1 == ~t9_pc~0; 21315#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21316#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20989#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20990#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21144#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21773#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21542#L1025-5 assume !(1 == ~T1_E~0); 21543#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21745#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22068#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22127#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22063#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21950#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21035#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21036#L1065-3 assume !(1 == ~T9_E~0); 21969#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21802#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21803#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22069#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21956#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21957#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21980#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21981#L1105-3 assume !(1 == ~E_8~0); 21191#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21192#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22000#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21046#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 21392#L1415 assume !(0 == start_simulation_~tmp~3#1); 22520#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22115#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21099#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21000#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 21001#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22136#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21660#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 21277#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 21278#L1396-2 [2024-11-09 16:09:26,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:26,515 INFO L85 PathProgramCache]: Analyzing trace with hash -1269658465, now seen corresponding path program 1 times [2024-11-09 16:09:26,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:26,519 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333304256] [2024-11-09 16:09:26,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:26,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:26,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:26,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:26,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:26,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333304256] [2024-11-09 16:09:26,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333304256] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:26,587 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:26,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:26,587 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880791116] [2024-11-09 16:09:26,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:26,588 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:26,589 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:26,589 INFO L85 PathProgramCache]: Analyzing trace with hash 187840947, now seen corresponding path program 1 times [2024-11-09 16:09:26,589 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:26,590 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [461959232] [2024-11-09 16:09:26,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:26,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:26,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:26,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:26,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:26,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [461959232] [2024-11-09 16:09:26,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [461959232] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:26,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:26,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:26,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [315537056] [2024-11-09 16:09:26,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:26,641 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:26,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:26,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:26,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:26,642 INFO L87 Difference]: Start difference. First operand 2100 states and 3099 transitions. cyclomatic complexity: 1001 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:26,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:26,775 INFO L93 Difference]: Finished difference Result 3938 states and 5806 transitions. [2024-11-09 16:09:26,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3938 states and 5806 transitions. [2024-11-09 16:09:26,791 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2024-11-09 16:09:26,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3938 states to 3938 states and 5806 transitions. [2024-11-09 16:09:26,807 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3938 [2024-11-09 16:09:26,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3938 [2024-11-09 16:09:26,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3938 states and 5806 transitions. [2024-11-09 16:09:26,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:26,815 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3938 states and 5806 transitions. [2024-11-09 16:09:26,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3938 states and 5806 transitions. [2024-11-09 16:09:26,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3938 to 3936. [2024-11-09 16:09:26,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3936 states, 3936 states have (on average 1.4745934959349594) internal successors, (5804), 3935 states have internal predecessors, (5804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:26,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3936 states to 3936 states and 5804 transitions. [2024-11-09 16:09:26,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3936 states and 5804 transitions. [2024-11-09 16:09:26,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:26,879 INFO L425 stractBuchiCegarLoop]: Abstraction has 3936 states and 5804 transitions. [2024-11-09 16:09:26,879 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-09 16:09:26,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3936 states and 5804 transitions. [2024-11-09 16:09:26,895 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2024-11-09 16:09:26,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:26,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:26,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:26,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:26,898 INFO L745 eck$LassoCheckResult]: Stem: 27284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 27285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 28099#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28100#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28044#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 28045#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28023#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27817#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27818#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27612#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27613#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28135#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28012#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27675#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27439#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27440#L922 assume !(0 == ~M_E~0); 28186#L922-2 assume !(0 == ~T1_E~0); 28187#L927-1 assume !(0 == ~T2_E~0); 27888#L932-1 assume !(0 == ~T3_E~0); 27750#L937-1 assume !(0 == ~T4_E~0); 27751#L942-1 assume !(0 == ~T5_E~0); 27816#L947-1 assume !(0 == ~T6_E~0); 27892#L952-1 assume !(0 == ~T7_E~0); 27893#L957-1 assume !(0 == ~T8_E~0); 27963#L962-1 assume !(0 == ~T9_E~0); 27726#L967-1 assume !(0 == ~E_1~0); 27727#L972-1 assume !(0 == ~E_2~0); 28028#L977-1 assume !(0 == ~E_3~0); 28029#L982-1 assume !(0 == ~E_4~0); 27214#L987-1 assume !(0 == ~E_5~0); 27215#L992-1 assume !(0 == ~E_6~0); 27221#L997-1 assume !(0 == ~E_7~0); 27652#L1002-1 assume !(0 == ~E_8~0); 27637#L1007-1 assume !(0 == ~E_9~0); 27008#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27009#L443 assume !(1 == ~m_pc~0); 27909#L443-2 is_master_triggered_~__retres1~0#1 := 0; 27900#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27901#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27377#L1140 assume !(0 != activate_threads_~tmp~1#1); 27113#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27114#L462 assume 1 == ~t1_pc~0; 27776#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27745#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27053#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 27591#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27592#L481 assume !(1 == ~t2_pc~0); 27371#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27370#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27462#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 27463#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27561#L500 assume 1 == ~t3_pc~0; 27797#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27798#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27016#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 27013#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27014#L519 assume 1 == ~t4_pc~0; 27317#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27318#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27115#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27116#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 27414#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27177#L538 assume !(1 == ~t5_pc~0); 27178#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 27075#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27076#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27357#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27358#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27944#L557 assume 1 == ~t6_pc~0; 27714#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27393#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27415#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 27416#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28162#L576 assume !(1 == ~t7_pc~0); 27381#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27382#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27713#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28182#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 28004#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27500#L595 assume 1 == ~t8_pc~0; 27501#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28019#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27947#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27841#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 27842#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27307#L614 assume !(1 == ~t9_pc~0); 27308#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27203#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27204#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27534#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 27465#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27466#L1025 assume !(1 == ~M_E~0); 27734#L1025-2 assume !(1 == ~T1_E~0); 27796#L1030-1 assume !(1 == ~T2_E~0); 27935#L1035-1 assume !(1 == ~T3_E~0); 28360#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28050#L1045-1 assume !(1 == ~T5_E~0); 27367#L1050-1 assume !(1 == ~T6_E~0); 27368#L1055-1 assume !(1 == ~T7_E~0); 27188#L1060-1 assume !(1 == ~T8_E~0); 27189#L1065-1 assume !(1 == ~T9_E~0); 27254#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28166#L1075-1 assume !(1 == ~E_2~0); 28350#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28284#L1085-1 assume !(1 == ~E_4~0); 28262#L1090-1 assume !(1 == ~E_5~0); 28260#L1095-1 assume !(1 == ~E_6~0); 28258#L1100-1 assume !(1 == ~E_7~0); 28256#L1105-1 assume !(1 == ~E_8~0); 28246#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 28237#L1115-1 assume { :end_inline_reset_delta_events } true; 28230#L1396-2 [2024-11-09 16:09:26,898 INFO L747 eck$LassoCheckResult]: Loop: 28230#L1396-2 assume !false; 28224#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28220#L897-1 assume !false; 28219#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28218#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28208#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28207#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28205#L766 assume !(0 != eval_~tmp~0#1); 28204#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28203#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28202#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28201#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28200#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27526#L932-3 assume !(0 == ~T3_E~0); 27527#L937-3 assume !(0 == ~T4_E~0); 27151#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27152#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27528#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27529#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28104#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27981#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27982#L972-3 assume !(0 == ~E_2~0); 27886#L977-3 assume !(0 == ~E_3~0); 27887#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28191#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27479#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27480#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27477#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27478#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27190#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27191#L443-30 assume 1 == ~m_pc~0; 30699#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30697#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30695#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30693#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30692#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27619#L462-30 assume 1 == ~t1_pc~0; 27447#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27448#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27746#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27747#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28062#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27604#L481-30 assume 1 == ~t2_pc~0; 27314#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27315#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27408#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27286#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 27287#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27564#L500-30 assume 1 == ~t3_pc~0; 27322#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27323#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27659#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27718#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27547#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27548#L519-30 assume 1 == ~t4_pc~0; 27927#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27719#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27720#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27731#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27732#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29313#L538-30 assume 1 == ~t5_pc~0; 29310#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29307#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29305#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29303#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29302#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29300#L557-30 assume !(1 == ~t6_pc~0); 29296#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 29294#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29291#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29289#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29163#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29161#L576-30 assume 1 == ~t7_pc~0; 29158#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29155#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29153#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29151#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29149#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29147#L595-30 assume !(1 == ~t8_pc~0); 29143#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 29053#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29050#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29048#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28966#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28963#L614-30 assume 1 == ~t9_pc~0; 28960#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28854#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28735#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28732#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28730#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28624#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28621#L1025-5 assume !(1 == ~T1_E~0); 28619#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27801#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28616#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28183#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28541#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28539#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28537#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28535#L1065-3 assume !(1 == ~T9_E~0); 28534#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28465#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28418#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28415#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28413#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28412#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28410#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28408#L1105-3 assume !(1 == ~E_8~0); 28406#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28361#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28310#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28299#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28297#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 28289#L1415 assume !(0 == start_simulation_~tmp~3#1); 28287#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28270#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28263#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 28259#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28257#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28247#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 28238#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 28230#L1396-2 [2024-11-09 16:09:26,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:26,899 INFO L85 PathProgramCache]: Analyzing trace with hash -1455005537, now seen corresponding path program 1 times [2024-11-09 16:09:26,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:26,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267746032] [2024-11-09 16:09:26,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:26,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:26,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:26,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:26,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:26,943 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267746032] [2024-11-09 16:09:26,943 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267746032] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:26,943 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:26,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:26,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727545663] [2024-11-09 16:09:26,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:26,943 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:26,944 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:26,944 INFO L85 PathProgramCache]: Analyzing trace with hash 2085337713, now seen corresponding path program 1 times [2024-11-09 16:09:26,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:26,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86415508] [2024-11-09 16:09:26,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:26,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:26,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:26,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:26,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:26,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86415508] [2024-11-09 16:09:26,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86415508] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:26,989 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:26,989 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:26,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [542417975] [2024-11-09 16:09:26,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:26,990 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:26,990 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:26,990 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:26,990 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:26,991 INFO L87 Difference]: Start difference. First operand 3936 states and 5804 transitions. cyclomatic complexity: 1872 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:27,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:27,115 INFO L93 Difference]: Finished difference Result 7377 states and 10808 transitions. [2024-11-09 16:09:27,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7377 states and 10808 transitions. [2024-11-09 16:09:27,145 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7206 [2024-11-09 16:09:27,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7377 states to 7377 states and 10808 transitions. [2024-11-09 16:09:27,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7377 [2024-11-09 16:09:27,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7377 [2024-11-09 16:09:27,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7377 states and 10808 transitions. [2024-11-09 16:09:27,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:27,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7377 states and 10808 transitions. [2024-11-09 16:09:27,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7377 states and 10808 transitions. [2024-11-09 16:09:27,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7377 to 7369. [2024-11-09 16:09:27,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7369 states, 7369 states have (on average 1.4655991314968109) internal successors, (10800), 7368 states have internal predecessors, (10800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:27,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7369 states to 7369 states and 10800 transitions. [2024-11-09 16:09:27,318 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7369 states and 10800 transitions. [2024-11-09 16:09:27,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:27,319 INFO L425 stractBuchiCegarLoop]: Abstraction has 7369 states and 10800 transitions. [2024-11-09 16:09:27,319 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-09 16:09:27,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7369 states and 10800 transitions. [2024-11-09 16:09:27,341 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7198 [2024-11-09 16:09:27,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:27,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:27,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:27,343 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:27,343 INFO L745 eck$LassoCheckResult]: Stem: 38605#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 38606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 39496#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39497#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39427#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 39428#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39399#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39168#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39169#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38946#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38947#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39543#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39387#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39017#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38763#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38764#L922 assume !(0 == ~M_E~0); 39619#L922-2 assume !(0 == ~T1_E~0); 39620#L927-1 assume !(0 == ~T2_E~0); 39249#L932-1 assume !(0 == ~T3_E~0); 39099#L937-1 assume !(0 == ~T4_E~0); 39100#L942-1 assume !(0 == ~T5_E~0); 39167#L947-1 assume !(0 == ~T6_E~0); 39253#L952-1 assume !(0 == ~T7_E~0); 39254#L957-1 assume !(0 == ~T8_E~0); 39329#L962-1 assume !(0 == ~T9_E~0); 39072#L967-1 assume !(0 == ~E_1~0); 39073#L972-1 assume !(0 == ~E_2~0); 39407#L977-1 assume !(0 == ~E_3~0); 39408#L982-1 assume !(0 == ~E_4~0); 38534#L987-1 assume !(0 == ~E_5~0); 38535#L992-1 assume !(0 == ~E_6~0); 38541#L997-1 assume !(0 == ~E_7~0); 38991#L1002-1 assume !(0 == ~E_8~0); 38978#L1007-1 assume !(0 == ~E_9~0); 38328#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38329#L443 assume !(1 == ~m_pc~0); 39272#L443-2 is_master_triggered_~__retres1~0#1 := 0; 39263#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39264#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38699#L1140 assume !(0 != activate_threads_~tmp~1#1); 38433#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38434#L462 assume !(1 == ~t1_pc~0); 39092#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39093#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38373#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 38920#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38921#L481 assume !(1 == ~t2_pc~0); 38693#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38692#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38824#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38787#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 38788#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38887#L500 assume 1 == ~t3_pc~0; 39148#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39149#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38335#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38336#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 38333#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38334#L519 assume 1 == ~t4_pc~0; 38638#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38639#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38435#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38436#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 38737#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38497#L538 assume !(1 == ~t5_pc~0); 38498#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 38395#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38679#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38680#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39312#L557 assume 1 == ~t6_pc~0; 39059#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38715#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38806#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38738#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 38739#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39575#L576 assume !(1 == ~t7_pc~0); 38703#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 38704#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39058#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39611#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 39373#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38827#L595 assume 1 == ~t8_pc~0; 38828#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39395#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39200#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 39201#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38628#L614 assume !(1 == ~t9_pc~0); 38629#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 38523#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38524#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38859#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 38790#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38791#L1025 assume !(1 == ~M_E~0); 39081#L1025-2 assume !(1 == ~T1_E~0); 39147#L1030-1 assume !(1 == ~T2_E~0); 39301#L1035-1 assume !(1 == ~T3_E~0); 39450#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40703#L1045-1 assume !(1 == ~T5_E~0); 40702#L1050-1 assume !(1 == ~T6_E~0); 40700#L1055-1 assume !(1 == ~T7_E~0); 38508#L1060-1 assume !(1 == ~T8_E~0); 38509#L1065-1 assume !(1 == ~T9_E~0); 38575#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40664#L1075-1 assume !(1 == ~E_2~0); 40661#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 40660#L1085-1 assume !(1 == ~E_4~0); 40659#L1090-1 assume !(1 == ~E_5~0); 40658#L1095-1 assume !(1 == ~E_6~0); 40633#L1100-1 assume !(1 == ~E_7~0); 40614#L1105-1 assume !(1 == ~E_8~0); 40601#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 40592#L1115-1 assume { :end_inline_reset_delta_events } true; 40585#L1396-2 [2024-11-09 16:09:27,343 INFO L747 eck$LassoCheckResult]: Loop: 40585#L1396-2 assume !false; 40579#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40575#L897-1 assume !false; 40574#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40573#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40563#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40560#L766 assume !(0 != eval_~tmp~0#1); 40559#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40558#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40557#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40556#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40553#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40554#L932-3 assume !(0 == ~T3_E~0); 42854#L937-3 assume !(0 == ~T4_E~0); 42852#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42850#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42848#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42846#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42845#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42844#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42843#L972-3 assume !(0 == ~E_2~0); 42842#L977-3 assume !(0 == ~E_3~0); 42841#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42840#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42839#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42838#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42837#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42836#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42835#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42834#L443-30 assume 1 == ~m_pc~0; 42832#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42831#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42830#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42829#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42828#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42827#L462-30 assume !(1 == ~t1_pc~0); 39499#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 39405#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39095#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39096#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39448#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38936#L481-30 assume !(1 == ~t2_pc~0); 38937#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 42821#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42820#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38607#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 38608#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39268#L500-30 assume 1 == ~t3_pc~0; 38643#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38644#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39000#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39063#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38872#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38873#L519-30 assume !(1 == ~t4_pc~0); 39091#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 39064#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39065#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39077#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39078#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39223#L538-30 assume 1 == ~t5_pc~0; 38519#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38520#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38856#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39206#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38601#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38602#L557-30 assume 1 == ~t6_pc~0; 38318#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38320#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38439#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38440#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38626#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38627#L576-30 assume !(1 == ~t7_pc~0); 38393#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 38394#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39037#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39280#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38782#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38744#L595-30 assume !(1 == ~t8_pc~0); 38745#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 38683#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38684#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39526#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39527#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39578#L614-30 assume !(1 == ~t9_pc~0); 38688#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 38687#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38357#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38358#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38512#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39192#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38922#L1025-5 assume !(1 == ~T1_E~0); 38923#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39152#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39547#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39612#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39535#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39394#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38403#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38404#L1065-3 assume !(1 == ~T9_E~0); 39417#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39226#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39227#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39548#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39579#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40845#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40843#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40811#L1105-3 assume !(1 == ~E_8~0); 40809#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40807#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40747#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40736#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40711#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 40689#L1415 assume !(0 == start_simulation_~tmp~3#1); 40663#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40640#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40619#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40617#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 40616#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40615#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40602#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 40593#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 40585#L1396-2 [2024-11-09 16:09:27,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:27,344 INFO L85 PathProgramCache]: Analyzing trace with hash 212114046, now seen corresponding path program 1 times [2024-11-09 16:09:27,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:27,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721082313] [2024-11-09 16:09:27,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:27,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:27,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:27,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:27,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:27,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1721082313] [2024-11-09 16:09:27,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1721082313] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:27,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:27,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:27,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949249200] [2024-11-09 16:09:27,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:27,397 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:27,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:27,398 INFO L85 PathProgramCache]: Analyzing trace with hash 352264749, now seen corresponding path program 1 times [2024-11-09 16:09:27,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:27,398 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729480892] [2024-11-09 16:09:27,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:27,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:27,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:27,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:27,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:27,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729480892] [2024-11-09 16:09:27,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729480892] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:27,433 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:27,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:27,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1628042485] [2024-11-09 16:09:27,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:27,433 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:27,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:27,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:27,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:27,434 INFO L87 Difference]: Start difference. First operand 7369 states and 10800 transitions. cyclomatic complexity: 3439 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:27,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:27,579 INFO L93 Difference]: Finished difference Result 13914 states and 20281 transitions. [2024-11-09 16:09:27,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13914 states and 20281 transitions. [2024-11-09 16:09:27,635 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13728 [2024-11-09 16:09:27,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13914 states to 13914 states and 20281 transitions. [2024-11-09 16:09:27,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13914 [2024-11-09 16:09:27,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13914 [2024-11-09 16:09:27,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13914 states and 20281 transitions. [2024-11-09 16:09:27,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:27,708 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13914 states and 20281 transitions. [2024-11-09 16:09:27,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13914 states and 20281 transitions. [2024-11-09 16:09:27,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13914 to 13898. [2024-11-09 16:09:27,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13898 states, 13898 states have (on average 1.458123471003022) internal successors, (20265), 13897 states have internal predecessors, (20265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:27,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13898 states to 13898 states and 20265 transitions. [2024-11-09 16:09:27,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13898 states and 20265 transitions. [2024-11-09 16:09:27,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:27,903 INFO L425 stractBuchiCegarLoop]: Abstraction has 13898 states and 20265 transitions. [2024-11-09 16:09:27,903 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-09 16:09:27,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13898 states and 20265 transitions. [2024-11-09 16:09:27,973 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13712 [2024-11-09 16:09:27,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:27,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:27,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:27,975 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:27,975 INFO L745 eck$LassoCheckResult]: Stem: 59892#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 59893#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 60775#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60776#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60708#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 60709#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60686#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60448#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60449#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60229#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60230#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60820#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60675#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60298#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60050#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60051#L922 assume !(0 == ~M_E~0); 60895#L922-2 assume !(0 == ~T1_E~0); 60896#L927-1 assume !(0 == ~T2_E~0); 60528#L932-1 assume !(0 == ~T3_E~0); 60375#L937-1 assume !(0 == ~T4_E~0); 60376#L942-1 assume !(0 == ~T5_E~0); 60447#L947-1 assume !(0 == ~T6_E~0); 60532#L952-1 assume !(0 == ~T7_E~0); 60533#L957-1 assume !(0 == ~T8_E~0); 60610#L962-1 assume !(0 == ~T9_E~0); 60352#L967-1 assume !(0 == ~E_1~0); 60353#L972-1 assume !(0 == ~E_2~0); 60692#L977-1 assume !(0 == ~E_3~0); 60693#L982-1 assume !(0 == ~E_4~0); 59824#L987-1 assume !(0 == ~E_5~0); 59825#L992-1 assume !(0 == ~E_6~0); 59831#L997-1 assume !(0 == ~E_7~0); 60271#L1002-1 assume !(0 == ~E_8~0); 60260#L1007-1 assume !(0 == ~E_9~0); 59618#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59619#L443 assume !(1 == ~m_pc~0); 60551#L443-2 is_master_triggered_~__retres1~0#1 := 0; 60541#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60542#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 59988#L1140 assume !(0 != activate_threads_~tmp~1#1); 59723#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59724#L462 assume !(1 == ~t1_pc~0); 60366#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60367#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59660#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59661#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 60205#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60206#L481 assume !(1 == ~t2_pc~0); 59982#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59981#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 60076#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 60077#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60174#L500 assume !(1 == ~t3_pc~0); 60763#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60726#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59625#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59626#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 59620#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59621#L519 assume 1 == ~t4_pc~0; 59924#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59925#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59726#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 60023#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59787#L538 assume !(1 == ~t5_pc~0); 59788#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59685#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59968#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59969#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60591#L557 assume 1 == ~t6_pc~0; 60340#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60004#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60094#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60024#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 60025#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60860#L576 assume !(1 == ~t7_pc~0); 59992#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59993#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60339#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60889#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 60663#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60115#L595 assume 1 == ~t8_pc~0; 60116#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60683#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60597#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60480#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 60481#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59917#L614 assume !(1 == ~t9_pc~0); 59918#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 59812#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59813#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60150#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 60079#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60080#L1025 assume !(1 == ~M_E~0); 60361#L1025-2 assume !(1 == ~T1_E~0); 60425#L1030-1 assume !(1 == ~T2_E~0); 60585#L1035-1 assume !(1 == ~T3_E~0); 60733#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69430#L1045-1 assume !(1 == ~T5_E~0); 69424#L1050-1 assume !(1 == ~T6_E~0); 69418#L1055-1 assume !(1 == ~T7_E~0); 69414#L1060-1 assume !(1 == ~T8_E~0); 69411#L1065-1 assume !(1 == ~T9_E~0); 69408#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 69404#L1075-1 assume !(1 == ~E_2~0); 69400#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 69401#L1085-1 assume !(1 == ~E_4~0); 70260#L1090-1 assume !(1 == ~E_5~0); 70258#L1095-1 assume !(1 == ~E_6~0); 70257#L1100-1 assume !(1 == ~E_7~0); 70246#L1105-1 assume !(1 == ~E_8~0); 70244#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 70236#L1115-1 assume { :end_inline_reset_delta_events } true; 70225#L1396-2 [2024-11-09 16:09:27,976 INFO L747 eck$LassoCheckResult]: Loop: 70225#L1396-2 assume !false; 70214#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70204#L897-1 assume !false; 70199#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70026#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70010#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70004#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69997#L766 assume !(0 != eval_~tmp~0#1); 69998#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71917#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 71915#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 71913#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 71910#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60141#L932-3 assume !(0 == ~T3_E~0); 60142#L937-3 assume !(0 == ~T4_E~0); 59761#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59762#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60143#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60144#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60785#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60633#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60634#L972-3 assume !(0 == ~E_2~0); 60526#L977-3 assume !(0 == ~E_3~0); 60527#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71956#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71955#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 71954#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60087#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 60088#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 71767#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60134#L443-30 assume 1 == ~m_pc~0; 59834#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59835#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60121#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60126#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60695#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60239#L462-30 assume !(1 == ~t1_pc~0); 60240#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 60691#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60371#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60372#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60730#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60222#L481-30 assume 1 == ~t2_pc~0; 59927#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59928#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60019#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59896#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 59897#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60179#L500-30 assume !(1 == ~t3_pc~0); 60548#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 60281#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60282#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60344#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60163#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60164#L519-30 assume !(1 == ~t4_pc~0); 60370#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 60345#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60346#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60357#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60358#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60504#L538-30 assume 1 == ~t5_pc~0; 59809#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59810#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60147#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60487#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59890#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59891#L557-30 assume 1 == ~t6_pc~0; 59608#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59610#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59729#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59730#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59915#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59916#L576-30 assume !(1 == ~t7_pc~0); 59683#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 59684#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60314#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60559#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60072#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60032#L595-30 assume !(1 == ~t8_pc~0); 60033#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 59970#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59971#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60806#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60807#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60863#L614-30 assume 1 == ~t9_pc~0; 59975#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59976#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59647#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59648#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59802#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60470#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60209#L1025-5 assume !(1 == ~T1_E~0); 60210#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60427#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60823#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60890#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70935#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70930#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70924#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70919#L1065-3 assume !(1 == ~T9_E~0); 70911#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70904#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70897#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69463#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70885#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70879#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70871#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70866#L1105-3 assume !(1 == ~E_8~0); 70861#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70856#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70462#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70451#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70449#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 70445#L1415 assume !(0 == start_simulation_~tmp~3#1); 70360#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70253#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70245#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70243#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 70242#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70241#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70239#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 70237#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 70225#L1396-2 [2024-11-09 16:09:27,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:27,977 INFO L85 PathProgramCache]: Analyzing trace with hash 2031839965, now seen corresponding path program 1 times [2024-11-09 16:09:27,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:27,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945417810] [2024-11-09 16:09:27,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:27,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:27,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:28,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:28,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:28,014 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945417810] [2024-11-09 16:09:28,014 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945417810] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:28,014 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:28,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:28,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574500968] [2024-11-09 16:09:28,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:28,015 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:28,015 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:28,015 INFO L85 PathProgramCache]: Analyzing trace with hash 479135758, now seen corresponding path program 1 times [2024-11-09 16:09:28,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:28,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031175454] [2024-11-09 16:09:28,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:28,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:28,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:28,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:28,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:28,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031175454] [2024-11-09 16:09:28,069 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031175454] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:28,069 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:28,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:28,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267857258] [2024-11-09 16:09:28,069 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:28,070 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:28,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:28,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:28,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:28,072 INFO L87 Difference]: Start difference. First operand 13898 states and 20265 transitions. cyclomatic complexity: 6383 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:28,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:28,235 INFO L93 Difference]: Finished difference Result 26345 states and 38242 transitions. [2024-11-09 16:09:28,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26345 states and 38242 transitions. [2024-11-09 16:09:28,416 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26104 [2024-11-09 16:09:28,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26345 states to 26345 states and 38242 transitions. [2024-11-09 16:09:28,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26345 [2024-11-09 16:09:28,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26345 [2024-11-09 16:09:28,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26345 states and 38242 transitions. [2024-11-09 16:09:28,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:28,576 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26345 states and 38242 transitions. [2024-11-09 16:09:28,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26345 states and 38242 transitions. [2024-11-09 16:09:29,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26345 to 26313. [2024-11-09 16:09:29,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26313 states, 26313 states have (on average 1.4521339261961768) internal successors, (38210), 26312 states have internal predecessors, (38210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:29,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26313 states to 26313 states and 38210 transitions. [2024-11-09 16:09:29,109 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26313 states and 38210 transitions. [2024-11-09 16:09:29,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:29,112 INFO L425 stractBuchiCegarLoop]: Abstraction has 26313 states and 38210 transitions. [2024-11-09 16:09:29,112 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-09 16:09:29,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26313 states and 38210 transitions. [2024-11-09 16:09:29,183 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26072 [2024-11-09 16:09:29,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:29,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:29,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:29,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:29,185 INFO L745 eck$LassoCheckResult]: Stem: 100144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 100145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 101018#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101019#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100956#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 100957#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100928#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100700#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100701#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100483#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100484#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 101058#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 100917#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 100552#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 100301#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100302#L922 assume !(0 == ~M_E~0); 101151#L922-2 assume !(0 == ~T1_E~0); 101152#L927-1 assume !(0 == ~T2_E~0); 100772#L932-1 assume !(0 == ~T3_E~0); 100634#L937-1 assume !(0 == ~T4_E~0); 100635#L942-1 assume !(0 == ~T5_E~0); 100699#L947-1 assume !(0 == ~T6_E~0); 100776#L952-1 assume !(0 == ~T7_E~0); 100777#L957-1 assume !(0 == ~T8_E~0); 100855#L962-1 assume !(0 == ~T9_E~0); 100609#L967-1 assume !(0 == ~E_1~0); 100610#L972-1 assume !(0 == ~E_2~0); 100936#L977-1 assume !(0 == ~E_3~0); 100937#L982-1 assume !(0 == ~E_4~0); 100075#L987-1 assume !(0 == ~E_5~0); 100076#L992-1 assume !(0 == ~E_6~0); 100082#L997-1 assume !(0 == ~E_7~0); 100525#L1002-1 assume !(0 == ~E_8~0); 100512#L1007-1 assume !(0 == ~E_9~0); 99868#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99869#L443 assume !(1 == ~m_pc~0); 100796#L443-2 is_master_triggered_~__retres1~0#1 := 0; 100785#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100786#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100238#L1140 assume !(0 != activate_threads_~tmp~1#1); 99973#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99974#L462 assume !(1 == ~t1_pc~0); 100625#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100626#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99910#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 99911#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 100460#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100461#L481 assume !(1 == ~t2_pc~0); 100232#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100231#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100365#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100326#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 100327#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100430#L500 assume !(1 == ~t3_pc~0); 101007#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100975#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99875#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 99876#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 99870#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99871#L519 assume !(1 == ~t4_pc~0); 100688#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100429#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 99976#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 100274#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100038#L538 assume !(1 == ~t5_pc~0); 100039#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 99935#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99936#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100218#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100219#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100839#L557 assume 1 == ~t6_pc~0; 100594#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 100254#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100275#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 100276#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101100#L576 assume !(1 == ~t7_pc~0); 100242#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 100243#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100593#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101139#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 100906#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100366#L595 assume 1 == ~t8_pc~0; 100367#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100923#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100844#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100724#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 100725#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100169#L614 assume !(1 == ~t9_pc~0); 100170#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 100063#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100064#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100401#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 100329#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100330#L1025 assume !(1 == ~M_E~0); 100618#L1025-2 assume !(1 == ~T1_E~0); 100679#L1030-1 assume !(1 == ~T2_E~0); 100828#L1035-1 assume !(1 == ~T3_E~0); 100320#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100321#L1045-1 assume !(1 == ~T5_E~0); 106392#L1050-1 assume !(1 == ~T6_E~0); 100419#L1055-1 assume !(1 == ~T7_E~0); 100420#L1060-1 assume !(1 == ~T8_E~0); 100115#L1065-1 assume !(1 == ~T9_E~0); 100116#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 100778#L1075-1 assume !(1 == ~E_2~0); 100779#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 106334#L1085-1 assume !(1 == ~E_4~0); 106328#L1090-1 assume !(1 == ~E_5~0); 105933#L1095-1 assume !(1 == ~E_6~0); 105931#L1100-1 assume !(1 == ~E_7~0); 105841#L1105-1 assume !(1 == ~E_8~0); 105822#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 105811#L1115-1 assume { :end_inline_reset_delta_events } true; 105801#L1396-2 [2024-11-09 16:09:29,185 INFO L747 eck$LassoCheckResult]: Loop: 105801#L1396-2 assume !false; 105793#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105787#L897-1 assume !false; 105784#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 105780#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 105766#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 105763#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105759#L766 assume !(0 != eval_~tmp~0#1); 105760#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106789#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106787#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 106785#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 106783#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 106781#L932-3 assume !(0 == ~T3_E~0); 106779#L937-3 assume !(0 == ~T4_E~0); 106777#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106776#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 106773#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 106771#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 106769#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 106767#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 106765#L972-3 assume !(0 == ~E_2~0); 106763#L977-3 assume !(0 == ~E_3~0); 106761#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106759#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106757#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 106755#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 106753#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 106751#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 106748#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106746#L443-30 assume 1 == ~m_pc~0; 106743#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 106741#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106739#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106737#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 106735#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106733#L462-30 assume !(1 == ~t1_pc~0); 106731#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 106729#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106727#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 106725#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 106723#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106721#L481-30 assume 1 == ~t2_pc~0; 106715#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 106713#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106711#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106709#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 106707#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106704#L500-30 assume !(1 == ~t3_pc~0); 106702#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 106685#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106679#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 106672#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 106664#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106658#L519-30 assume !(1 == ~t4_pc~0); 106652#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 106645#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106637#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 106629#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106622#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106611#L538-30 assume 1 == ~t5_pc~0; 106603#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106580#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106577#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 106575#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 106573#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106571#L557-30 assume !(1 == ~t6_pc~0); 106567#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 106565#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 106563#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 106561#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 106559#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 106557#L576-30 assume !(1 == ~t7_pc~0); 106555#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 106552#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 106550#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 106548#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 106546#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 106543#L595-30 assume 1 == ~t8_pc~0; 106541#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 106538#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 106536#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 106534#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 106533#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106521#L614-30 assume !(1 == ~t9_pc~0); 106401#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 106398#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106396#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106386#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 106375#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106367#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 106357#L1025-5 assume !(1 == ~T1_E~0); 106348#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106092#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106085#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106081#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 106079#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 106077#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 106074#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 106070#L1065-3 assume !(1 == ~T9_E~0); 106068#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 106066#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 106064#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 106060#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106058#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 106056#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 106054#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 106050#L1105-3 assume !(1 == ~E_8~0); 106048#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 106046#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 106043#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 106026#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 106020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 106013#L1415 assume !(0 == start_simulation_~tmp~3#1); 106010#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 105858#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 105849#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 105847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 105845#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 105843#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105823#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 105812#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 105801#L1396-2 [2024-11-09 16:09:29,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:29,186 INFO L85 PathProgramCache]: Analyzing trace with hash 2039590524, now seen corresponding path program 1 times [2024-11-09 16:09:29,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:29,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780314364] [2024-11-09 16:09:29,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:29,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:29,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:29,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:29,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:29,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780314364] [2024-11-09 16:09:29,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780314364] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:29,242 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:29,242 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:29,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833395092] [2024-11-09 16:09:29,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:29,244 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:29,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:29,244 INFO L85 PathProgramCache]: Analyzing trace with hash -2009657619, now seen corresponding path program 1 times [2024-11-09 16:09:29,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:29,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683628269] [2024-11-09 16:09:29,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:29,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:29,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:29,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:29,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:29,280 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683628269] [2024-11-09 16:09:29,280 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683628269] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:29,280 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:29,280 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:29,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940101025] [2024-11-09 16:09:29,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:29,281 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:29,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:29,282 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:29,282 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:29,282 INFO L87 Difference]: Start difference. First operand 26313 states and 38210 transitions. cyclomatic complexity: 11929 Second operand has 5 states, 5 states have (on average 23.0) internal successors, (115), 5 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:29,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:29,684 INFO L93 Difference]: Finished difference Result 27180 states and 39077 transitions. [2024-11-09 16:09:29,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27180 states and 39077 transitions. [2024-11-09 16:09:29,781 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26936 [2024-11-09 16:09:29,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27180 states to 27180 states and 39077 transitions. [2024-11-09 16:09:29,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27180 [2024-11-09 16:09:29,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27180 [2024-11-09 16:09:29,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27180 states and 39077 transitions. [2024-11-09 16:09:30,012 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:30,013 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27180 states and 39077 transitions. [2024-11-09 16:09:30,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27180 states and 39077 transitions. [2024-11-09 16:09:30,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27180 to 27180. [2024-11-09 16:09:30,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27180 states, 27180 states have (on average 1.4377115526122148) internal successors, (39077), 27179 states have internal predecessors, (39077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:30,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27180 states to 27180 states and 39077 transitions. [2024-11-09 16:09:30,546 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27180 states and 39077 transitions. [2024-11-09 16:09:30,546 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:30,547 INFO L425 stractBuchiCegarLoop]: Abstraction has 27180 states and 39077 transitions. [2024-11-09 16:09:30,547 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-09 16:09:30,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27180 states and 39077 transitions. [2024-11-09 16:09:30,668 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26936 [2024-11-09 16:09:30,669 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:30,669 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:30,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:30,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:30,671 INFO L745 eck$LassoCheckResult]: Stem: 153647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 153648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 154484#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 154485#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 154430#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 154431#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154410#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154197#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154198#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 153990#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 153991#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154521#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 154398#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154056#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 153806#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 153807#L922 assume !(0 == ~M_E~0); 154585#L922-2 assume !(0 == ~T1_E~0); 154586#L927-1 assume !(0 == ~T2_E~0); 154270#L932-1 assume !(0 == ~T3_E~0); 154131#L937-1 assume !(0 == ~T4_E~0); 154132#L942-1 assume !(0 == ~T5_E~0); 154196#L947-1 assume !(0 == ~T6_E~0); 154274#L952-1 assume !(0 == ~T7_E~0); 154275#L957-1 assume !(0 == ~T8_E~0); 154349#L962-1 assume !(0 == ~T9_E~0); 154109#L967-1 assume !(0 == ~E_1~0); 154110#L972-1 assume !(0 == ~E_2~0); 154416#L977-1 assume !(0 == ~E_3~0); 154417#L982-1 assume !(0 == ~E_4~0); 153577#L987-1 assume !(0 == ~E_5~0); 153578#L992-1 assume !(0 == ~E_6~0); 153584#L997-1 assume !(0 == ~E_7~0); 154031#L1002-1 assume !(0 == ~E_8~0); 154018#L1007-1 assume !(0 == ~E_9~0); 153370#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153371#L443 assume !(1 == ~m_pc~0); 154294#L443-2 is_master_triggered_~__retres1~0#1 := 0; 154283#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154284#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 153740#L1140 assume !(0 != activate_threads_~tmp~1#1); 153476#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153477#L462 assume !(1 == ~t1_pc~0); 154125#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154126#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153414#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 153415#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 153967#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153968#L481 assume !(1 == ~t2_pc~0); 153734#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 153733#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153868#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 153829#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 153830#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153935#L500 assume !(1 == ~t3_pc~0); 154474#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154448#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153377#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153378#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 153375#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153376#L519 assume !(1 == ~t4_pc~0); 154186#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153932#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153478#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 153479#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 153779#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153540#L538 assume !(1 == ~t5_pc~0); 153541#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 153437#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153438#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 153720#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 153721#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154333#L557 assume 1 == ~t6_pc~0; 154094#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 153756#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 153848#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153780#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 153781#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154560#L576 assume !(1 == ~t7_pc~0); 153744#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 153745#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154093#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154581#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 154388#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 153871#L595 assume 1 == ~t8_pc~0; 153872#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 154405#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 154338#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154222#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 154223#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153670#L614 assume !(1 == ~t9_pc~0); 153671#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 153566#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 153567#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 153906#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 153832#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153833#L1025 assume !(1 == ~M_E~0); 154115#L1025-2 assume !(1 == ~T1_E~0); 154178#L1030-1 assume !(1 == ~T2_E~0); 154323#L1035-1 assume !(1 == ~T3_E~0); 157965#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 157966#L1045-1 assume !(1 == ~T5_E~0); 158210#L1050-1 assume !(1 == ~T6_E~0); 157962#L1055-1 assume !(1 == ~T7_E~0); 157960#L1060-1 assume !(1 == ~T8_E~0); 157958#L1065-1 assume !(1 == ~T9_E~0); 157957#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 157956#L1075-1 assume !(1 == ~E_2~0); 157873#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 157833#L1085-1 assume !(1 == ~E_4~0); 157831#L1090-1 assume !(1 == ~E_5~0); 157829#L1095-1 assume !(1 == ~E_6~0); 157789#L1100-1 assume !(1 == ~E_7~0); 157787#L1105-1 assume !(1 == ~E_8~0); 157786#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 157758#L1115-1 assume { :end_inline_reset_delta_events } true; 157730#L1396-2 [2024-11-09 16:09:30,671 INFO L747 eck$LassoCheckResult]: Loop: 157730#L1396-2 assume !false; 157718#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 157710#L897-1 assume !false; 157661#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 157624#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 157594#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 157561#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 157557#L766 assume !(0 != eval_~tmp~0#1); 157558#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159790#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 159788#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 159786#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 159645#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 159643#L932-3 assume !(0 == ~T3_E~0); 159641#L937-3 assume !(0 == ~T4_E~0); 159638#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 159636#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 159634#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 159632#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 159630#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 159628#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 159465#L972-3 assume !(0 == ~E_2~0); 159230#L977-3 assume !(0 == ~E_3~0); 159219#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159217#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 159215#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 159213#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 159211#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 159209#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 159207#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159205#L443-30 assume 1 == ~m_pc~0; 159202#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 159200#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159198#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159196#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159194#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159192#L462-30 assume !(1 == ~t1_pc~0); 159190#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 159188#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159186#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159184#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 159182#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159180#L481-30 assume !(1 == ~t2_pc~0); 159178#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 159175#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159173#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 159171#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 159169#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159167#L500-30 assume !(1 == ~t3_pc~0); 159165#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 159162#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159160#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159158#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 159156#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159154#L519-30 assume !(1 == ~t4_pc~0); 159152#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 159150#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159148#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 159146#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 158949#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158331#L538-30 assume !(1 == ~t5_pc~0); 158327#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 158325#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158323#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 158320#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 158317#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158315#L557-30 assume !(1 == ~t6_pc~0); 158310#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 158308#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158306#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 158304#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 158301#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 158299#L576-30 assume 1 == ~t7_pc~0; 158296#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 158294#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 158292#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 158290#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 158289#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 158286#L595-30 assume !(1 == ~t8_pc~0); 158283#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 158281#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 158279#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 158277#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 158275#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 158272#L614-30 assume !(1 == ~t9_pc~0); 158270#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 158267#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 158265#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 158263#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 158261#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158259#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 158257#L1025-5 assume !(1 == ~T1_E~0); 158255#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 158249#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 158247#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 158243#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 158241#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 158239#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 158237#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 158235#L1065-3 assume !(1 == ~T9_E~0); 158233#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 158232#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 158231#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 158227#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 158226#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 158225#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 158224#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 158223#L1105-3 assume !(1 == ~E_8~0); 158222#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 158220#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 157987#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 157976#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 157974#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 157970#L1415 assume !(0 == start_simulation_~tmp~3#1); 157967#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 157881#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 157834#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 157832#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 157830#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 157790#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 157788#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 157759#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 157730#L1396-2 [2024-11-09 16:09:30,674 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:30,674 INFO L85 PathProgramCache]: Analyzing trace with hash -327104070, now seen corresponding path program 1 times [2024-11-09 16:09:30,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:30,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63409637] [2024-11-09 16:09:30,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:30,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:30,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:30,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:30,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:30,739 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63409637] [2024-11-09 16:09:30,739 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63409637] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:30,739 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:30,739 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:30,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672455567] [2024-11-09 16:09:30,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:30,740 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:30,740 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:30,740 INFO L85 PathProgramCache]: Analyzing trace with hash 1715959657, now seen corresponding path program 1 times [2024-11-09 16:09:30,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:30,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685246152] [2024-11-09 16:09:30,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:30,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:30,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:30,786 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:30,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:30,786 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685246152] [2024-11-09 16:09:30,787 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685246152] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:30,787 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:30,787 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:30,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528016331] [2024-11-09 16:09:30,787 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:30,787 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:30,788 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:30,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:30,788 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:30,788 INFO L87 Difference]: Start difference. First operand 27180 states and 39077 transitions. cyclomatic complexity: 11929 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:31,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:31,086 INFO L93 Difference]: Finished difference Result 51555 states and 73842 transitions. [2024-11-09 16:09:31,086 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51555 states and 73842 transitions. [2024-11-09 16:09:31,415 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 51168 [2024-11-09 16:09:31,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51555 states to 51555 states and 73842 transitions. [2024-11-09 16:09:31,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51555 [2024-11-09 16:09:31,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51555 [2024-11-09 16:09:31,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51555 states and 73842 transitions. [2024-11-09 16:09:31,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:31,752 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51555 states and 73842 transitions. [2024-11-09 16:09:31,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51555 states and 73842 transitions. [2024-11-09 16:09:32,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51555 to 51491. [2024-11-09 16:09:32,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51491 states, 51491 states have (on average 1.4328329222582588) internal successors, (73778), 51490 states have internal predecessors, (73778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:32,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51491 states to 51491 states and 73778 transitions. [2024-11-09 16:09:32,583 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51491 states and 73778 transitions. [2024-11-09 16:09:32,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:32,596 INFO L425 stractBuchiCegarLoop]: Abstraction has 51491 states and 73778 transitions. [2024-11-09 16:09:32,596 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-09 16:09:32,596 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51491 states and 73778 transitions. [2024-11-09 16:09:32,730 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 51104 [2024-11-09 16:09:32,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:32,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:32,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:32,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:32,732 INFO L745 eck$LassoCheckResult]: Stem: 232384#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 232385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 233246#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 233247#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 233181#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 233182#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 233155#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 232935#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 232936#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 232720#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 232721#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 233276#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 233142#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 232791#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 232545#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 232546#L922 assume !(0 == ~M_E~0); 233343#L922-2 assume !(0 == ~T1_E~0); 233344#L927-1 assume !(0 == ~T2_E~0); 233009#L932-1 assume !(0 == ~T3_E~0); 232867#L937-1 assume !(0 == ~T4_E~0); 232868#L942-1 assume !(0 == ~T5_E~0); 232934#L947-1 assume !(0 == ~T6_E~0); 233013#L952-1 assume !(0 == ~T7_E~0); 233014#L957-1 assume !(0 == ~T8_E~0); 233084#L962-1 assume !(0 == ~T9_E~0); 232841#L967-1 assume !(0 == ~E_1~0); 232842#L972-1 assume !(0 == ~E_2~0); 233161#L977-1 assume !(0 == ~E_3~0); 233162#L982-1 assume !(0 == ~E_4~0); 232318#L987-1 assume !(0 == ~E_5~0); 232319#L992-1 assume !(0 == ~E_6~0); 232325#L997-1 assume !(0 == ~E_7~0); 232762#L1002-1 assume !(0 == ~E_8~0); 232748#L1007-1 assume !(0 == ~E_9~0); 232112#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 232113#L443 assume !(1 == ~m_pc~0); 233031#L443-2 is_master_triggered_~__retres1~0#1 := 0; 233021#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233022#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 232481#L1140 assume !(0 != activate_threads_~tmp~1#1); 232218#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232219#L462 assume !(1 == ~t1_pc~0); 232858#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 232859#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 232154#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 232155#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 232698#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232699#L481 assume !(1 == ~t2_pc~0); 232475#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 232474#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 232609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 232568#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 232569#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 232668#L500 assume !(1 == ~t3_pc~0); 233234#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 233199#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 232119#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 232120#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 232114#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232115#L519 assume !(1 == ~t4_pc~0); 232923#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 232667#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 232220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 232221#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 232517#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 232282#L538 assume !(1 == ~t5_pc~0); 232283#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 232179#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 232180#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 232460#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 232461#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 233065#L557 assume !(1 == ~t6_pc~0); 232496#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 232497#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232588#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 232518#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 232519#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 233318#L576 assume !(1 == ~t7_pc~0); 232485#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 232486#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 232828#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 233340#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 233132#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 232610#L595 assume 1 == ~t8_pc~0; 232611#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 233151#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 233070#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 232961#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 232962#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 232412#L614 assume !(1 == ~t9_pc~0); 232413#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 232307#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 232308#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 232644#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 232572#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232573#L1025 assume !(1 == ~M_E~0); 232849#L1025-2 assume !(1 == ~T1_E~0); 232915#L1030-1 assume !(1 == ~T2_E~0); 233057#L1035-1 assume !(1 == ~T3_E~0); 238817#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 238815#L1045-1 assume !(1 == ~T5_E~0); 238814#L1050-1 assume !(1 == ~T6_E~0); 238813#L1055-1 assume !(1 == ~T7_E~0); 238811#L1060-1 assume !(1 == ~T8_E~0); 238809#L1065-1 assume !(1 == ~T9_E~0); 238807#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 238805#L1075-1 assume !(1 == ~E_2~0); 238802#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 238801#L1085-1 assume !(1 == ~E_4~0); 238797#L1090-1 assume !(1 == ~E_5~0); 238796#L1095-1 assume !(1 == ~E_6~0); 238795#L1100-1 assume !(1 == ~E_7~0); 238794#L1105-1 assume !(1 == ~E_8~0); 238793#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 238768#L1115-1 assume { :end_inline_reset_delta_events } true; 238765#L1396-2 [2024-11-09 16:09:32,733 INFO L747 eck$LassoCheckResult]: Loop: 238765#L1396-2 assume !false; 238763#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 238758#L897-1 assume !false; 238756#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 238753#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 238741#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 238739#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 238736#L766 assume !(0 != eval_~tmp~0#1); 238737#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 249582#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 249580#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 249577#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 249575#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 249573#L932-3 assume !(0 == ~T3_E~0); 249571#L937-3 assume !(0 == ~T4_E~0); 249569#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 249567#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 249565#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 249563#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 249533#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 249526#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 249519#L972-3 assume !(0 == ~E_2~0); 249511#L977-3 assume !(0 == ~E_3~0); 249503#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 249496#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 249487#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 249480#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 249472#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 249466#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 249460#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 249453#L443-30 assume !(1 == ~m_pc~0); 249446#L443-32 is_master_triggered_~__retres1~0#1 := 0; 249442#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 249439#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 249438#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 249437#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 249436#L462-30 assume !(1 == ~t1_pc~0); 249434#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 249432#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 249430#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 249428#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 249426#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 249424#L481-30 assume !(1 == ~t2_pc~0); 249411#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 249406#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 249403#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 249362#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 249359#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 249357#L500-30 assume !(1 == ~t3_pc~0); 249355#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 249353#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 249351#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 249349#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 249347#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 249345#L519-30 assume !(1 == ~t4_pc~0); 249343#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 249341#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 249326#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 249320#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 249312#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 249305#L538-30 assume !(1 == ~t5_pc~0); 249299#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 249290#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 249282#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 249275#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 249268#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 249262#L557-30 assume !(1 == ~t6_pc~0); 249256#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 249250#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 249244#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 249238#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 249231#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 249225#L576-30 assume !(1 == ~t7_pc~0); 249219#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 249210#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 249204#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 249199#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 249193#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 249187#L595-30 assume 1 == ~t8_pc~0; 249181#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 249174#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 249168#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 249163#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 249158#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 249153#L614-30 assume !(1 == ~t9_pc~0); 248274#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 248267#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 248262#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 248257#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 248253#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 248248#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 248242#L1025-5 assume !(1 == ~T1_E~0); 248235#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 244230#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 248222#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 248214#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 248210#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 248204#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 248197#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 248191#L1065-3 assume !(1 == ~T9_E~0); 248186#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 248181#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 248176#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 248169#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 248162#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 248158#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 248153#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 248150#L1105-3 assume !(1 == ~E_8~0); 248144#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 248138#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 247708#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 247697#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 247695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 247616#L1415 assume !(0 == start_simulation_~tmp~3#1); 247614#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 238788#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 238779#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 238777#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 238775#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 238773#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 238771#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 238769#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 238765#L1396-2 [2024-11-09 16:09:32,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:32,733 INFO L85 PathProgramCache]: Analyzing trace with hash -1602206759, now seen corresponding path program 1 times [2024-11-09 16:09:32,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:32,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486304708] [2024-11-09 16:09:32,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:32,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:32,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:32,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:32,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:32,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [486304708] [2024-11-09 16:09:32,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [486304708] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:32,777 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:32,777 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:32,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1357224590] [2024-11-09 16:09:32,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:32,778 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:32,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:32,778 INFO L85 PathProgramCache]: Analyzing trace with hash -365804472, now seen corresponding path program 1 times [2024-11-09 16:09:32,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:32,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715460844] [2024-11-09 16:09:32,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:32,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:32,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:32,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:32,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:32,815 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715460844] [2024-11-09 16:09:32,815 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715460844] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:32,815 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:32,815 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:32,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259748378] [2024-11-09 16:09:32,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:32,816 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:32,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:32,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:32,816 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:32,817 INFO L87 Difference]: Start difference. First operand 51491 states and 73778 transitions. cyclomatic complexity: 22351 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:33,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:33,217 INFO L93 Difference]: Finished difference Result 97602 states and 139391 transitions. [2024-11-09 16:09:33,218 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97602 states and 139391 transitions. [2024-11-09 16:09:33,940 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 96864 [2024-11-09 16:09:34,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97602 states to 97602 states and 139391 transitions. [2024-11-09 16:09:34,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97602 [2024-11-09 16:09:34,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97602 [2024-11-09 16:09:34,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97602 states and 139391 transitions. [2024-11-09 16:09:34,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:34,307 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97602 states and 139391 transitions. [2024-11-09 16:09:34,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97602 states and 139391 transitions. [2024-11-09 16:09:35,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97602 to 97474. [2024-11-09 16:09:35,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97474 states, 97474 states have (on average 1.4287194533926997) internal successors, (139263), 97473 states have internal predecessors, (139263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:35,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97474 states to 97474 states and 139263 transitions. [2024-11-09 16:09:35,532 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97474 states and 139263 transitions. [2024-11-09 16:09:35,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:35,534 INFO L425 stractBuchiCegarLoop]: Abstraction has 97474 states and 139263 transitions. [2024-11-09 16:09:35,534 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-09 16:09:35,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97474 states and 139263 transitions. [2024-11-09 16:09:36,227 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 96736 [2024-11-09 16:09:36,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:36,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:36,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:36,229 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:36,229 INFO L745 eck$LassoCheckResult]: Stem: 381484#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 381485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 382364#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 382365#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 382299#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 382300#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 382274#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 382053#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 382054#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 381827#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 381828#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 382410#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 382261#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 381903#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 381642#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 381643#L922 assume !(0 == ~M_E~0); 382495#L922-2 assume !(0 == ~T1_E~0); 382496#L927-1 assume !(0 == ~T2_E~0); 382127#L932-1 assume !(0 == ~T3_E~0); 381988#L937-1 assume !(0 == ~T4_E~0); 381989#L942-1 assume !(0 == ~T5_E~0); 382052#L947-1 assume !(0 == ~T6_E~0); 382132#L952-1 assume !(0 == ~T7_E~0); 382133#L957-1 assume !(0 == ~T8_E~0); 382208#L962-1 assume !(0 == ~T9_E~0); 381961#L967-1 assume !(0 == ~E_1~0); 381962#L972-1 assume !(0 == ~E_2~0); 382284#L977-1 assume !(0 == ~E_3~0); 382285#L982-1 assume !(0 == ~E_4~0); 381418#L987-1 assume !(0 == ~E_5~0); 381419#L992-1 assume !(0 == ~E_6~0); 381425#L997-1 assume !(0 == ~E_7~0); 381874#L1002-1 assume !(0 == ~E_8~0); 381861#L1007-1 assume !(0 == ~E_9~0); 381212#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 381213#L443 assume !(1 == ~m_pc~0); 382150#L443-2 is_master_triggered_~__retres1~0#1 := 0; 382140#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 382141#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 381578#L1140 assume !(0 != activate_threads_~tmp~1#1); 381318#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 381319#L462 assume !(1 == ~t1_pc~0); 381977#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 381978#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 381254#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 381255#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 381801#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 381802#L481 assume !(1 == ~t2_pc~0); 381572#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 381571#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 381708#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 381668#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 381669#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 381771#L500 assume !(1 == ~t3_pc~0); 382353#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 382319#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 381219#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 381220#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 381214#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 381215#L519 assume !(1 == ~t4_pc~0); 382044#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 381770#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 381320#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 381321#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 381614#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 381382#L538 assume !(1 == ~t5_pc~0); 381383#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 381279#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 381280#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 381557#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 381558#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 382190#L557 assume !(1 == ~t6_pc~0); 381593#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 381594#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 381687#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 381615#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 381616#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 382457#L576 assume !(1 == ~t7_pc~0); 381582#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 381583#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 381946#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 382487#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 382253#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 381709#L595 assume !(1 == ~t8_pc~0); 381710#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 382269#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 382196#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 382080#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 382081#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 381509#L614 assume !(1 == ~t9_pc~0); 381510#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 381407#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 381408#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 381746#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 381671#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 381672#L1025 assume !(1 == ~M_E~0); 381971#L1025-2 assume !(1 == ~T1_E~0); 382035#L1030-1 assume !(1 == ~T2_E~0); 382182#L1035-1 assume !(1 == ~T3_E~0); 381662#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 381663#L1045-1 assume !(1 == ~T5_E~0); 388342#L1050-1 assume !(1 == ~T6_E~0); 388340#L1055-1 assume !(1 == ~T7_E~0); 388338#L1060-1 assume !(1 == ~T8_E~0); 388336#L1065-1 assume !(1 == ~T9_E~0); 388334#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 388332#L1075-1 assume !(1 == ~E_2~0); 388329#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 388330#L1085-1 assume !(1 == ~E_4~0); 388366#L1090-1 assume !(1 == ~E_5~0); 388365#L1095-1 assume !(1 == ~E_6~0); 388362#L1100-1 assume !(1 == ~E_7~0); 388361#L1105-1 assume !(1 == ~E_8~0); 388359#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 388354#L1115-1 assume { :end_inline_reset_delta_events } true; 388350#L1396-2 [2024-11-09 16:09:36,230 INFO L747 eck$LassoCheckResult]: Loop: 388350#L1396-2 assume !false; 388349#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 388345#L897-1 assume !false; 388344#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 387359#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 387348#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 387346#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 387342#L766 assume !(0 != eval_~tmp~0#1); 387343#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 393857#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 393855#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 393853#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 393851#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 393849#L932-3 assume !(0 == ~T3_E~0); 393847#L937-3 assume !(0 == ~T4_E~0); 393845#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 393843#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 393841#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 393839#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 393837#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 393835#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 393833#L972-3 assume !(0 == ~E_2~0); 393831#L977-3 assume !(0 == ~E_3~0); 393829#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 393827#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 393825#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 393823#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 393821#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 393819#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 393817#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 393814#L443-30 assume !(1 == ~m_pc~0); 393812#L443-32 is_master_triggered_~__retres1~0#1 := 0; 393809#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393807#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 393805#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 393803#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 393801#L462-30 assume !(1 == ~t1_pc~0); 393799#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 393797#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 393795#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 393793#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 393791#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 393790#L481-30 assume 1 == ~t2_pc~0; 393788#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 393785#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 393783#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393781#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 393779#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 393777#L500-30 assume !(1 == ~t3_pc~0); 393775#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 393773#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 393771#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 393769#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 393757#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 393754#L519-30 assume !(1 == ~t4_pc~0); 393751#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 393747#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 393744#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 393741#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 393737#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 393734#L538-30 assume 1 == ~t5_pc~0; 393730#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 393725#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 393720#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393715#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 393711#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 393708#L557-30 assume !(1 == ~t6_pc~0); 393704#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 393699#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 393695#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 393691#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 393686#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 393682#L576-30 assume !(1 == ~t7_pc~0); 393678#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 393672#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 393668#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 393664#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 393660#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 393656#L595-30 assume !(1 == ~t8_pc~0); 393652#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 393647#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 393643#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 393639#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 393635#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 393631#L614-30 assume 1 == ~t9_pc~0; 393626#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 393621#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 393617#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 393613#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 393608#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 393603#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 393598#L1025-5 assume !(1 == ~T1_E~0); 393593#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 392767#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 393586#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 393581#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 393578#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 393575#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 393571#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 393567#L1065-3 assume !(1 == ~T9_E~0); 393563#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 393558#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 393555#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 392743#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 393550#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 393547#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 393543#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 393538#L1105-3 assume !(1 == ~E_8~0); 393535#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 393533#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 393459#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 393447#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 393444#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 393440#L1415 assume !(0 == start_simulation_~tmp~3#1); 393438#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 393427#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 393418#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 393415#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 390332#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 390329#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 390325#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 388355#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 388350#L1396-2 [2024-11-09 16:09:36,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:36,230 INFO L85 PathProgramCache]: Analyzing trace with hash -683232136, now seen corresponding path program 1 times [2024-11-09 16:09:36,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:36,231 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807465079] [2024-11-09 16:09:36,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:36,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:36,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:36,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:36,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:36,278 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807465079] [2024-11-09 16:09:36,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807465079] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:36,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:36,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:36,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934984684] [2024-11-09 16:09:36,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:36,278 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:36,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:36,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1139643444, now seen corresponding path program 1 times [2024-11-09 16:09:36,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:36,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379691743] [2024-11-09 16:09:36,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:36,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:36,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:36,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:36,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:36,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1379691743] [2024-11-09 16:09:36,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1379691743] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:36,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:36,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:36,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437119445] [2024-11-09 16:09:36,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:36,312 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:36,312 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:36,312 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:36,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:36,313 INFO L87 Difference]: Start difference. First operand 97474 states and 139263 transitions. cyclomatic complexity: 41917 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:36,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:36,442 INFO L93 Difference]: Finished difference Result 48786 states and 69423 transitions. [2024-11-09 16:09:36,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48786 states and 69423 transitions. [2024-11-09 16:09:36,596 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 48368 [2024-11-09 16:09:36,724 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48786 states to 48786 states and 69423 transitions. [2024-11-09 16:09:36,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48786 [2024-11-09 16:09:36,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48786 [2024-11-09 16:09:36,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48786 states and 69423 transitions. [2024-11-09 16:09:37,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:37,056 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48786 states and 69423 transitions. [2024-11-09 16:09:37,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48786 states and 69423 transitions. [2024-11-09 16:09:37,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48786 to 25611. [2024-11-09 16:09:37,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.4194681972589902) internal successors, (36354), 25610 states have internal predecessors, (36354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:37,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 36354 transitions. [2024-11-09 16:09:37,389 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 36354 transitions. [2024-11-09 16:09:37,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:37,389 INFO L425 stractBuchiCegarLoop]: Abstraction has 25611 states and 36354 transitions. [2024-11-09 16:09:37,389 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-09 16:09:37,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 36354 transitions. [2024-11-09 16:09:37,452 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2024-11-09 16:09:37,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:37,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:37,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:37,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:37,454 INFO L745 eck$LassoCheckResult]: Stem: 527754#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 527755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 528603#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 528604#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 528543#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 528544#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 528516#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 528301#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 528302#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 528092#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 528093#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 528638#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 528499#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 528159#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 527910#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 527911#L922 assume !(0 == ~M_E~0); 528706#L922-2 assume !(0 == ~T1_E~0); 528707#L927-1 assume !(0 == ~T2_E~0); 528373#L932-1 assume !(0 == ~T3_E~0); 528234#L937-1 assume !(0 == ~T4_E~0); 528235#L942-1 assume !(0 == ~T5_E~0); 528300#L947-1 assume !(0 == ~T6_E~0); 528378#L952-1 assume !(0 == ~T7_E~0); 528379#L957-1 assume !(0 == ~T8_E~0); 528441#L962-1 assume !(0 == ~T9_E~0); 528208#L967-1 assume !(0 == ~E_1~0); 528209#L972-1 assume !(0 == ~E_2~0); 528525#L977-1 assume !(0 == ~E_3~0); 528526#L982-1 assume !(0 == ~E_4~0); 527689#L987-1 assume !(0 == ~E_5~0); 527690#L992-1 assume !(0 == ~E_6~0); 527696#L997-1 assume !(0 == ~E_7~0); 528133#L1002-1 assume !(0 == ~E_8~0); 528120#L1007-1 assume !(0 == ~E_9~0); 527482#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 527483#L443 assume !(1 == ~m_pc~0); 528393#L443-2 is_master_triggered_~__retres1~0#1 := 0; 528385#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 528386#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 527850#L1140 assume !(0 != activate_threads_~tmp~1#1); 527588#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 527589#L462 assume !(1 == ~t1_pc~0); 528223#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 528224#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527524#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 527525#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 528070#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 528071#L481 assume !(1 == ~t2_pc~0); 527844#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 527843#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 527972#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 527934#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 527935#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 528037#L500 assume !(1 == ~t3_pc~0); 528594#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 528564#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 527489#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 527490#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 527484#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527485#L519 assume !(1 == ~t4_pc~0); 528289#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 528036#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 527590#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 527591#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 527884#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 527652#L538 assume !(1 == ~t5_pc~0); 527653#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 527549#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 527550#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 527829#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 527830#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 528426#L557 assume !(1 == ~t6_pc~0); 527864#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 527865#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 527953#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 527885#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 527886#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 528673#L576 assume !(1 == ~t7_pc~0); 527854#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 527855#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 528195#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 528698#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 528491#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 527976#L595 assume !(1 == ~t8_pc~0); 527977#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 528510#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 528431#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 528330#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 528331#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 527779#L614 assume !(1 == ~t9_pc~0); 527780#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 527677#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 527678#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 528012#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 527937#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 527938#L1025 assume !(1 == ~M_E~0); 528217#L1025-2 assume !(1 == ~T1_E~0); 528281#L1030-1 assume !(1 == ~T2_E~0); 528418#L1035-1 assume !(1 == ~T3_E~0); 527929#L1040-1 assume !(1 == ~T4_E~0); 527930#L1045-1 assume !(1 == ~T5_E~0); 527840#L1050-1 assume !(1 == ~T6_E~0); 527841#L1055-1 assume !(1 == ~T7_E~0); 527663#L1060-1 assume !(1 == ~T8_E~0); 527664#L1065-1 assume !(1 == ~T9_E~0); 527727#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 528380#L1075-1 assume !(1 == ~E_2~0); 528381#L1080-1 assume !(1 == ~E_3~0); 528368#L1085-1 assume !(1 == ~E_4~0); 528369#L1090-1 assume !(1 == ~E_5~0); 528627#L1095-1 assume !(1 == ~E_6~0); 528402#L1100-1 assume !(1 == ~E_7~0); 528403#L1105-1 assume !(1 == ~E_8~0); 527634#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 527635#L1115-1 assume { :end_inline_reset_delta_events } true; 527985#L1396-2 [2024-11-09 16:09:37,455 INFO L747 eck$LassoCheckResult]: Loop: 527985#L1396-2 assume !false; 536795#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 536791#L897-1 assume !false; 536789#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 536785#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 536774#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 536772#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 536769#L766 assume !(0 != eval_~tmp~0#1); 536770#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 537139#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 537137#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 537135#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 537133#L927-3 assume !(0 == ~T2_E~0); 537131#L932-3 assume !(0 == ~T3_E~0); 537129#L937-3 assume !(0 == ~T4_E~0); 537127#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 537122#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 537120#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 537118#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 537117#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 537106#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 537104#L972-3 assume !(0 == ~E_2~0); 537102#L977-3 assume !(0 == ~E_3~0); 537099#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 537095#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 537091#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 537087#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 537083#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 537080#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 537077#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 537076#L443-30 assume 1 == ~m_pc~0; 537074#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 537073#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 537072#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 537071#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 537070#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 537069#L462-30 assume !(1 == ~t1_pc~0); 537068#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 537067#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 537066#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 537065#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 537064#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 537063#L481-30 assume 1 == ~t2_pc~0; 537060#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 537058#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 537056#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 537055#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 537052#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 537051#L500-30 assume !(1 == ~t3_pc~0); 537050#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 537049#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 537048#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 537047#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 537046#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 537045#L519-30 assume !(1 == ~t4_pc~0); 537044#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 537043#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 537042#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 537041#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 537040#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 537038#L538-30 assume !(1 == ~t5_pc~0); 537035#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 537034#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 537032#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 537030#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 537027#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 537026#L557-30 assume !(1 == ~t6_pc~0); 537023#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 537022#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 537021#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 537020#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 537019#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 537018#L576-30 assume 1 == ~t7_pc~0; 537016#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 537015#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 537014#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 537013#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 537012#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 537011#L595-30 assume !(1 == ~t8_pc~0); 537010#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 537009#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 537008#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 537007#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 537006#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 537005#L614-30 assume 1 == ~t9_pc~0; 537003#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 537002#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 537001#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 537000#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 536998#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 536995#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 536993#L1025-5 assume !(1 == ~T1_E~0); 536991#L1030-3 assume !(1 == ~T2_E~0); 536989#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 536987#L1040-3 assume !(1 == ~T4_E~0); 536985#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 536983#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 536981#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 536979#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 536977#L1065-3 assume !(1 == ~T9_E~0); 536975#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 536973#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 536970#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 536968#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 536966#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 536964#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 536962#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 536960#L1105-3 assume !(1 == ~E_8~0); 536958#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 536956#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 536953#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 536942#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 536940#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 536831#L1415 assume !(0 == start_simulation_~tmp~3#1); 536828#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 536816#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 536808#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 536806#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 536804#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 536802#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 536800#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 536798#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 527985#L1396-2 [2024-11-09 16:09:37,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:37,455 INFO L85 PathProgramCache]: Analyzing trace with hash 1781320180, now seen corresponding path program 1 times [2024-11-09 16:09:37,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:37,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425524973] [2024-11-09 16:09:37,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:37,456 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:37,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:37,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:37,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:37,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425524973] [2024-11-09 16:09:37,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425524973] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:37,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:37,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:37,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [228496785] [2024-11-09 16:09:37,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:37,501 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:37,502 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:37,502 INFO L85 PathProgramCache]: Analyzing trace with hash 1852486821, now seen corresponding path program 1 times [2024-11-09 16:09:37,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:37,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181207650] [2024-11-09 16:09:37,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:37,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:37,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:37,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:37,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:37,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [181207650] [2024-11-09 16:09:37,535 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [181207650] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:37,535 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:37,535 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:37,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387860392] [2024-11-09 16:09:37,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:37,536 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:37,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:37,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:37,536 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:37,536 INFO L87 Difference]: Start difference. First operand 25611 states and 36354 transitions. cyclomatic complexity: 10775 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:37,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:37,739 INFO L93 Difference]: Finished difference Result 52812 states and 74750 transitions. [2024-11-09 16:09:37,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52812 states and 74750 transitions. [2024-11-09 16:09:38,169 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 52240 [2024-11-09 16:09:38,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52812 states to 52812 states and 74750 transitions. [2024-11-09 16:09:38,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52812 [2024-11-09 16:09:38,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52812 [2024-11-09 16:09:38,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52812 states and 74750 transitions. [2024-11-09 16:09:38,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:38,389 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52812 states and 74750 transitions. [2024-11-09 16:09:38,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52812 states and 74750 transitions. [2024-11-09 16:09:38,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52812 to 28595. [2024-11-09 16:09:38,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.4160867284490295) internal successors, (40493), 28594 states have internal predecessors, (40493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:38,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 40493 transitions. [2024-11-09 16:09:38,828 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 40493 transitions. [2024-11-09 16:09:38,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:38,829 INFO L425 stractBuchiCegarLoop]: Abstraction has 28595 states and 40493 transitions. [2024-11-09 16:09:38,829 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-09 16:09:38,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 40493 transitions. [2024-11-09 16:09:38,912 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2024-11-09 16:09:38,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:38,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:38,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:38,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:38,915 INFO L745 eck$LassoCheckResult]: Stem: 606190#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 606191#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 607017#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 607018#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 606959#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 606960#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 606939#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 606737#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 606738#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 606521#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 606522#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 607046#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 606926#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 606595#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 606346#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 606347#L922 assume !(0 == ~M_E~0); 607101#L922-2 assume !(0 == ~T1_E~0); 607102#L927-1 assume !(0 == ~T2_E~0); 606804#L932-1 assume !(0 == ~T3_E~0); 606672#L937-1 assume !(0 == ~T4_E~0); 606673#L942-1 assume !(0 == ~T5_E~0); 606736#L947-1 assume !(0 == ~T6_E~0); 606808#L952-1 assume !(0 == ~T7_E~0); 606809#L957-1 assume !(0 == ~T8_E~0); 606876#L962-1 assume !(0 == ~T9_E~0); 606645#L967-1 assume 0 == ~E_1~0;~E_1~0 := 1; 606646#L972-1 assume !(0 == ~E_2~0); 606944#L977-1 assume !(0 == ~E_3~0); 606945#L982-1 assume !(0 == ~E_4~0); 606122#L987-1 assume !(0 == ~E_5~0); 606123#L992-1 assume !(0 == ~E_6~0); 606567#L997-1 assume !(0 == ~E_7~0); 606568#L1002-1 assume !(0 == ~E_8~0); 606552#L1007-1 assume !(0 == ~E_9~0); 606553#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607059#L443 assume !(1 == ~m_pc~0); 607060#L443-2 is_master_triggered_~__retres1~0#1 := 0; 606815#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 606816#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 606284#L1140 assume !(0 != activate_threads_~tmp~1#1); 606021#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 606022#L462 assume !(1 == ~t1_pc~0); 606663#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 606664#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 605957#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 605958#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 606500#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 606501#L481 assume !(1 == ~t2_pc~0); 606278#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 606277#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607171#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 607170#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 606468#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 606469#L500 assume !(1 == ~t3_pc~0); 607169#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 607168#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 605922#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 605923#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 605917#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 605918#L519 assume !(1 == ~t4_pc~0); 606726#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 606727#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 607163#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 607162#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 607161#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607160#L538 assume !(1 == ~t5_pc~0); 606499#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 607159#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 607156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 607153#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 606858#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 606859#L557 assume !(1 == ~t6_pc~0); 607151#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 607150#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 607149#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 607148#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 607147#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 607107#L576 assume !(1 == ~t7_pc~0); 606288#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 606289#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 606633#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 607098#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 607142#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 607141#L595 assume !(1 == ~t8_pc~0); 607140#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 607139#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 607138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 607137#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 607136#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 607135#L614 assume !(1 == ~t9_pc~0); 607133#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 607132#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 606443#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 606444#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 606371#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 606372#L1025 assume !(1 == ~M_E~0); 606655#L1025-2 assume !(1 == ~T1_E~0); 606719#L1030-1 assume !(1 == ~T2_E~0); 606851#L1035-1 assume !(1 == ~T3_E~0); 606363#L1040-1 assume !(1 == ~T4_E~0); 606364#L1045-1 assume !(1 == ~T5_E~0); 606274#L1050-1 assume !(1 == ~T6_E~0); 606275#L1055-1 assume !(1 == ~T7_E~0); 607122#L1060-1 assume !(1 == ~T8_E~0); 607121#L1065-1 assume !(1 == ~T9_E~0); 607120#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 606810#L1075-1 assume !(1 == ~E_2~0); 606811#L1080-1 assume !(1 == ~E_3~0); 606799#L1085-1 assume !(1 == ~E_4~0); 606800#L1090-1 assume !(1 == ~E_5~0); 607037#L1095-1 assume !(1 == ~E_6~0); 606837#L1100-1 assume !(1 == ~E_7~0); 606838#L1105-1 assume !(1 == ~E_8~0); 606067#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 606068#L1115-1 assume { :end_inline_reset_delta_events } true; 606418#L1396-2 [2024-11-09 16:09:38,915 INFO L747 eck$LassoCheckResult]: Loop: 606418#L1396-2 assume !false; 613919#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 613914#L897-1 assume !false; 613912#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 613909#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 613898#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 613896#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 613893#L766 assume !(0 != eval_~tmp~0#1); 613894#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 614247#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 614245#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 614244#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 614240#L927-3 assume !(0 == ~T2_E~0); 614238#L932-3 assume !(0 == ~T3_E~0); 614236#L937-3 assume !(0 == ~T4_E~0); 614234#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 614231#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 614229#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 614227#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 614224#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 614222#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 614221#L972-3 assume !(0 == ~E_2~0); 614220#L977-3 assume !(0 == ~E_3~0); 614219#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 614218#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 614217#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 614216#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 614215#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 614214#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 614213#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 614212#L443-30 assume !(1 == ~m_pc~0); 614211#L443-32 is_master_triggered_~__retres1~0#1 := 0; 614209#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 614208#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 614207#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 614206#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 614205#L462-30 assume !(1 == ~t1_pc~0); 614204#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 614203#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 614202#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 614201#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 614200#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 614199#L481-30 assume 1 == ~t2_pc~0; 614197#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 614196#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 614195#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 614194#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 614193#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 614192#L500-30 assume !(1 == ~t3_pc~0); 614191#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 614190#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 614189#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 614188#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 614187#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 614186#L519-30 assume !(1 == ~t4_pc~0); 614185#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 614184#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 614183#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 614182#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 614181#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 614180#L538-30 assume !(1 == ~t5_pc~0); 614179#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 614177#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 614175#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 614173#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 614171#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 614170#L557-30 assume !(1 == ~t6_pc~0); 614169#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 614168#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 614167#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 614166#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614165#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 614164#L576-30 assume !(1 == ~t7_pc~0); 614163#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 614161#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 614160#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 614159#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 614158#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 614157#L595-30 assume !(1 == ~t8_pc~0); 614156#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 614155#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 614154#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 614153#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 614152#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 614151#L614-30 assume 1 == ~t9_pc~0; 614149#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 614148#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 614147#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 614146#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 614145#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 614144#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 614143#L1025-5 assume !(1 == ~T1_E~0); 614142#L1030-3 assume !(1 == ~T2_E~0); 614141#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 614140#L1040-3 assume !(1 == ~T4_E~0); 614139#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 614138#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 614137#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 614136#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 614135#L1065-3 assume !(1 == ~T9_E~0); 614133#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 614132#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 614131#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 614130#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 614129#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 614128#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 614126#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 614123#L1105-3 assume !(1 == ~E_8~0); 614121#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 614119#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 614116#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 614105#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 614103#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 613958#L1415 assume !(0 == start_simulation_~tmp~3#1); 613956#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 613940#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 613930#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 613929#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 613928#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 613927#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 613925#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 613922#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 606418#L1396-2 [2024-11-09 16:09:38,916 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:38,916 INFO L85 PathProgramCache]: Analyzing trace with hash -95743050, now seen corresponding path program 1 times [2024-11-09 16:09:38,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:38,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036055382] [2024-11-09 16:09:38,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:38,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:38,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:38,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:38,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:38,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2036055382] [2024-11-09 16:09:38,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2036055382] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:38,969 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:38,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:38,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1438679759] [2024-11-09 16:09:38,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:38,969 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:38,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:38,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1504379997, now seen corresponding path program 1 times [2024-11-09 16:09:38,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:38,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389380758] [2024-11-09 16:09:38,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:38,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:38,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:39,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:39,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:39,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389380758] [2024-11-09 16:09:39,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389380758] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:39,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:39,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:39,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563304984] [2024-11-09 16:09:39,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:39,009 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:39,009 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:39,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:39,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:39,010 INFO L87 Difference]: Start difference. First operand 28595 states and 40493 transitions. cyclomatic complexity: 11930 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:39,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:39,221 INFO L93 Difference]: Finished difference Result 48811 states and 68992 transitions. [2024-11-09 16:09:39,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48811 states and 68992 transitions. [2024-11-09 16:09:39,582 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 48336 [2024-11-09 16:09:39,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48811 states to 48811 states and 68992 transitions. [2024-11-09 16:09:39,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48811 [2024-11-09 16:09:39,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48811 [2024-11-09 16:09:39,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48811 states and 68992 transitions. [2024-11-09 16:09:39,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:39,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48811 states and 68992 transitions. [2024-11-09 16:09:39,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48811 states and 68992 transitions. [2024-11-09 16:09:39,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48811 to 25611. [2024-11-09 16:09:40,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.4106438639647028) internal successors, (36128), 25610 states have internal predecessors, (36128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:40,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 36128 transitions. [2024-11-09 16:09:40,051 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 36128 transitions. [2024-11-09 16:09:40,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:40,052 INFO L425 stractBuchiCegarLoop]: Abstraction has 25611 states and 36128 transitions. [2024-11-09 16:09:40,052 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-09 16:09:40,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 36128 transitions. [2024-11-09 16:09:40,110 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2024-11-09 16:09:40,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:40,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:40,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:40,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:40,111 INFO L745 eck$LassoCheckResult]: Stem: 683607#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 683608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 684436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 684437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 684376#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 684377#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 684353#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 684141#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 684142#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 683935#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 683936#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 684477#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 684343#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 684002#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 683759#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 683760#L922 assume !(0 == ~M_E~0); 684533#L922-2 assume !(0 == ~T1_E~0); 684534#L927-1 assume !(0 == ~T2_E~0); 684213#L932-1 assume !(0 == ~T3_E~0); 684080#L937-1 assume !(0 == ~T4_E~0); 684081#L942-1 assume !(0 == ~T5_E~0); 684140#L947-1 assume !(0 == ~T6_E~0); 684219#L952-1 assume !(0 == ~T7_E~0); 684220#L957-1 assume !(0 == ~T8_E~0); 684287#L962-1 assume !(0 == ~T9_E~0); 684059#L967-1 assume !(0 == ~E_1~0); 684060#L972-1 assume !(0 == ~E_2~0); 684358#L977-1 assume !(0 == ~E_3~0); 684359#L982-1 assume !(0 == ~E_4~0); 683541#L987-1 assume !(0 == ~E_5~0); 683542#L992-1 assume !(0 == ~E_6~0); 683546#L997-1 assume !(0 == ~E_7~0); 683978#L1002-1 assume !(0 == ~E_8~0); 683965#L1007-1 assume !(0 == ~E_9~0); 683331#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 683332#L443 assume !(1 == ~m_pc~0); 684235#L443-2 is_master_triggered_~__retres1~0#1 := 0; 684227#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 684228#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 683698#L1140 assume !(0 != activate_threads_~tmp~1#1); 683438#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 683439#L462 assume !(1 == ~t1_pc~0); 684071#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 684072#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 683373#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 683374#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 683914#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 683915#L481 assume !(1 == ~t2_pc~0); 683692#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 683691#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 683820#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 683782#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 683783#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 683884#L500 assume !(1 == ~t3_pc~0); 684427#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 684393#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 683338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 683339#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 683336#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 683337#L519 assume !(1 == ~t4_pc~0); 684132#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 683881#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 683440#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 683441#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 683734#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 683502#L538 assume !(1 == ~t5_pc~0); 683503#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 683400#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 683401#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 683677#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 683678#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 684271#L557 assume !(1 == ~t6_pc~0); 683712#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 683713#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 683801#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 683735#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 683736#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 684507#L576 assume !(1 == ~t7_pc~0); 683702#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 683703#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 684042#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 684529#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 684332#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 683825#L595 assume !(1 == ~t8_pc~0); 683826#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 684349#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 684275#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 684164#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 684165#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683629#L614 assume !(1 == ~t9_pc~0); 683630#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 683528#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 683529#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 683858#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 683785#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 683786#L1025 assume !(1 == ~M_E~0); 684064#L1025-2 assume !(1 == ~T1_E~0); 684125#L1030-1 assume !(1 == ~T2_E~0); 684261#L1035-1 assume !(1 == ~T3_E~0); 683778#L1040-1 assume !(1 == ~T4_E~0); 683779#L1045-1 assume !(1 == ~T5_E~0); 683688#L1050-1 assume !(1 == ~T6_E~0); 683689#L1055-1 assume !(1 == ~T7_E~0); 683513#L1060-1 assume !(1 == ~T8_E~0); 683514#L1065-1 assume !(1 == ~T9_E~0); 683578#L1070-1 assume !(1 == ~E_1~0); 684222#L1075-1 assume !(1 == ~E_2~0); 684223#L1080-1 assume !(1 == ~E_3~0); 684208#L1085-1 assume !(1 == ~E_4~0); 684209#L1090-1 assume !(1 == ~E_5~0); 684467#L1095-1 assume !(1 == ~E_6~0); 684244#L1100-1 assume !(1 == ~E_7~0); 684245#L1105-1 assume !(1 == ~E_8~0); 683484#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 683485#L1115-1 assume { :end_inline_reset_delta_events } true; 683832#L1396-2 [2024-11-09 16:09:40,111 INFO L747 eck$LassoCheckResult]: Loop: 683832#L1396-2 assume !false; 694726#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 694671#L897-1 assume !false; 694668#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 694543#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 694533#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 694532#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 694526#L766 assume !(0 != eval_~tmp~0#1); 694527#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 695481#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 695479#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 695477#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 695475#L927-3 assume !(0 == ~T2_E~0); 695473#L932-3 assume !(0 == ~T3_E~0); 695471#L937-3 assume !(0 == ~T4_E~0); 695469#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 695467#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 695465#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 695437#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 695432#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 695427#L967-3 assume !(0 == ~E_1~0); 695418#L972-3 assume !(0 == ~E_2~0); 695415#L977-3 assume !(0 == ~E_3~0); 695413#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 695411#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 695409#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 695407#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 695405#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 695403#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 695401#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 695399#L443-30 assume 1 == ~m_pc~0; 695396#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 695394#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 695392#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 695379#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 695374#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 695368#L462-30 assume !(1 == ~t1_pc~0); 695363#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 695359#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 695355#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 695351#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 695346#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 695338#L481-30 assume 1 == ~t2_pc~0; 695332#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 695327#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 695323#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 695319#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 695315#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 695309#L500-30 assume !(1 == ~t3_pc~0); 695305#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 695300#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 695295#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 695290#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 695284#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 695278#L519-30 assume !(1 == ~t4_pc~0); 695273#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 695268#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 695263#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 695258#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 695253#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 695247#L538-30 assume !(1 == ~t5_pc~0); 695242#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 695236#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 695230#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 695224#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 695218#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 695212#L557-30 assume !(1 == ~t6_pc~0); 695206#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 695200#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 695194#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 695189#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 695184#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 695177#L576-30 assume 1 == ~t7_pc~0; 695170#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 695164#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 695158#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 695153#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 695149#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 695143#L595-30 assume !(1 == ~t8_pc~0); 695137#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 695131#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 695125#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 695119#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 695111#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 695108#L614-30 assume !(1 == ~t9_pc~0); 695106#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 695103#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 695101#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 695099#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 695097#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 695087#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 695080#L1025-5 assume !(1 == ~T1_E~0); 695074#L1030-3 assume !(1 == ~T2_E~0); 694851#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 694850#L1040-3 assume !(1 == ~T4_E~0); 694849#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 694848#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 694847#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 694845#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 694843#L1065-3 assume !(1 == ~T9_E~0); 694841#L1070-3 assume !(1 == ~E_1~0); 694838#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 694836#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 694834#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 694832#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 694830#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 694829#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 694828#L1105-3 assume !(1 == ~E_8~0); 694827#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 694826#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 694823#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 694811#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 694809#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 694800#L1415 assume !(0 == start_simulation_~tmp~3#1); 694797#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 694748#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 694739#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 694737#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 694735#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 694733#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 694731#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 694729#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 683832#L1396-2 [2024-11-09 16:09:40,115 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:40,115 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293170, now seen corresponding path program 1 times [2024-11-09 16:09:40,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:40,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158887517] [2024-11-09 16:09:40,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:40,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:40,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:40,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:40,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:40,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158887517] [2024-11-09 16:09:40,163 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158887517] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:40,163 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:40,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:40,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698409281] [2024-11-09 16:09:40,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:40,163 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:40,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:40,163 INFO L85 PathProgramCache]: Analyzing trace with hash 727953536, now seen corresponding path program 1 times [2024-11-09 16:09:40,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:40,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378294710] [2024-11-09 16:09:40,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:40,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:40,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:40,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:40,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:40,191 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [378294710] [2024-11-09 16:09:40,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [378294710] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:40,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:40,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:40,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [629045231] [2024-11-09 16:09:40,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:40,192 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:40,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:40,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:40,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:40,193 INFO L87 Difference]: Start difference. First operand 25611 states and 36128 transitions. cyclomatic complexity: 10549 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:40,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:40,393 INFO L93 Difference]: Finished difference Result 53052 states and 74347 transitions. [2024-11-09 16:09:40,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53052 states and 74347 transitions. [2024-11-09 16:09:40,798 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 52512 [2024-11-09 16:09:40,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53052 states to 53052 states and 74347 transitions. [2024-11-09 16:09:40,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53052 [2024-11-09 16:09:40,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53052 [2024-11-09 16:09:40,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53052 states and 74347 transitions. [2024-11-09 16:09:40,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:40,977 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53052 states and 74347 transitions. [2024-11-09 16:09:41,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53052 states and 74347 transitions. [2024-11-09 16:09:41,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53052 to 28595. [2024-11-09 16:09:41,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.4031124322433992) internal successors, (40122), 28594 states have internal predecessors, (40122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:41,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 40122 transitions. [2024-11-09 16:09:41,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 40122 transitions. [2024-11-09 16:09:41,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:41,308 INFO L425 stractBuchiCegarLoop]: Abstraction has 28595 states and 40122 transitions. [2024-11-09 16:09:41,308 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-09 16:09:41,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 40122 transitions. [2024-11-09 16:09:41,375 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2024-11-09 16:09:41,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:41,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:41,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:41,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:41,376 INFO L745 eck$LassoCheckResult]: Stem: 762275#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 762276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 763092#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 763093#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 763038#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 763039#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 763015#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 762808#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 762809#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 762605#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 762606#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 763122#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 763003#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 762674#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 762430#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 762431#L922 assume !(0 == ~M_E~0); 763176#L922-2 assume !(0 == ~T1_E~0); 763177#L927-1 assume !(0 == ~T2_E~0); 762879#L932-1 assume !(0 == ~T3_E~0); 762748#L937-1 assume !(0 == ~T4_E~0); 762749#L942-1 assume !(0 == ~T5_E~0); 762807#L947-1 assume !(0 == ~T6_E~0); 762884#L952-1 assume !(0 == ~T7_E~0); 762885#L957-1 assume !(0 == ~T8_E~0); 762954#L962-1 assume !(0 == ~T9_E~0); 762723#L967-1 assume !(0 == ~E_1~0); 762724#L972-1 assume !(0 == ~E_2~0); 763024#L977-1 assume !(0 == ~E_3~0); 763025#L982-1 assume !(0 == ~E_4~0); 762210#L987-1 assume !(0 == ~E_5~0); 762211#L992-1 assume !(0 == ~E_6~0); 762217#L997-1 assume !(0 == ~E_7~0); 762649#L1002-1 assume !(0 == ~E_8~0); 762636#L1007-1 assume 0 == ~E_9~0;~E_9~0 := 1; 762004#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 762005#L443 assume !(1 == ~m_pc~0); 763132#L443-2 is_master_triggered_~__retres1~0#1 := 0; 762892#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 762893#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 763268#L1140 assume !(0 != activate_threads_~tmp~1#1); 763267#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 763143#L462 assume !(1 == ~t1_pc~0); 762738#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 762739#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 762045#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 762046#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 762583#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 762584#L481 assume !(1 == ~t2_pc~0); 762361#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 762360#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 763260#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 763259#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 762552#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 762553#L500 assume !(1 == ~t3_pc~0); 763258#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 763257#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 762011#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 762012#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 762006#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 762007#L519 assume !(1 == ~t4_pc~0); 762799#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 762551#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 762111#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 762112#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 762403#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 762173#L538 assume !(1 == ~t5_pc~0); 762174#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 762070#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 762071#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 762347#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 762348#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 762938#L557 assume !(1 == ~t6_pc~0); 763236#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 763235#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 763234#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 763233#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 763232#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 763181#L576 assume !(1 == ~t7_pc~0); 762372#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 762373#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 762710#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 763171#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 763227#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 763226#L595 assume !(1 == ~t8_pc~0); 763225#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 763224#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 763223#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 763222#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 763221#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 763220#L614 assume !(1 == ~t9_pc~0); 763218#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 763217#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 763216#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 763215#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 763214#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 763213#L1025 assume !(1 == ~M_E~0); 763212#L1025-2 assume !(1 == ~T1_E~0); 763211#L1030-1 assume !(1 == ~T2_E~0); 763210#L1035-1 assume !(1 == ~T3_E~0); 763209#L1040-1 assume !(1 == ~T4_E~0); 763208#L1045-1 assume !(1 == ~T5_E~0); 763207#L1050-1 assume !(1 == ~T6_E~0); 763206#L1055-1 assume !(1 == ~T7_E~0); 763205#L1060-1 assume !(1 == ~T8_E~0); 763204#L1065-1 assume !(1 == ~T9_E~0); 763203#L1070-1 assume !(1 == ~E_1~0); 763202#L1075-1 assume !(1 == ~E_2~0); 763201#L1080-1 assume !(1 == ~E_3~0); 763200#L1085-1 assume !(1 == ~E_4~0); 763199#L1090-1 assume !(1 == ~E_5~0); 763198#L1095-1 assume !(1 == ~E_6~0); 763197#L1100-1 assume !(1 == ~E_7~0); 763196#L1105-1 assume !(1 == ~E_8~0); 763195#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 762156#L1115-1 assume { :end_inline_reset_delta_events } true; 762502#L1396-2 [2024-11-09 16:09:41,377 INFO L747 eck$LassoCheckResult]: Loop: 762502#L1396-2 assume !false; 766461#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 766456#L897-1 assume !false; 766454#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 766450#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 766439#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 766437#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 766434#L766 assume !(0 != eval_~tmp~0#1); 766435#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 772945#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 772943#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 772941#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 772939#L927-3 assume !(0 == ~T2_E~0); 772936#L932-3 assume !(0 == ~T3_E~0); 772934#L937-3 assume !(0 == ~T4_E~0); 772932#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 772930#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 772928#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 772926#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 772923#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 772921#L967-3 assume !(0 == ~E_1~0); 772903#L972-3 assume !(0 == ~E_2~0); 772896#L977-3 assume !(0 == ~E_3~0); 772890#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 772882#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 772874#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 772865#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 772855#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 772853#L1007-3 assume !(0 == ~E_9~0); 772854#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 773316#L443-30 assume !(1 == ~m_pc~0); 773315#L443-32 is_master_triggered_~__retres1~0#1 := 0; 773313#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 773312#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 773310#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 773309#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 773308#L462-30 assume !(1 == ~t1_pc~0); 773307#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 773306#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 773305#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 773304#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 773302#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 773299#L481-30 assume !(1 == ~t2_pc~0); 773297#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 773294#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 773292#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 773290#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 773288#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 773286#L500-30 assume !(1 == ~t3_pc~0); 773284#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 773282#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 773280#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 773278#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 773276#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 773273#L519-30 assume !(1 == ~t4_pc~0); 773271#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 773269#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 773267#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 773265#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 773263#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 773261#L538-30 assume 1 == ~t5_pc~0; 773259#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 773260#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 773311#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 773250#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 773248#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 773246#L557-30 assume !(1 == ~t6_pc~0); 773244#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 773242#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 773240#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 773238#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 773237#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 773233#L576-30 assume !(1 == ~t7_pc~0); 773231#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 773228#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 773226#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 773022#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 773019#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 773017#L595-30 assume !(1 == ~t8_pc~0); 773015#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 773013#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 773011#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 773008#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 772997#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 772989#L614-30 assume !(1 == ~t9_pc~0); 772788#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 772979#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 772977#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 772976#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 772975#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 772974#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 772972#L1025-5 assume !(1 == ~T1_E~0); 772969#L1030-3 assume !(1 == ~T2_E~0); 772967#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 772965#L1040-3 assume !(1 == ~T4_E~0); 772963#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 772961#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 772959#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 772957#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 772955#L1065-3 assume !(1 == ~T9_E~0); 772953#L1070-3 assume !(1 == ~E_1~0); 772905#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 772898#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 772892#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 772884#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 772877#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 772869#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 772859#L1105-3 assume !(1 == ~E_8~0); 772764#L1110-3 assume !(1 == ~E_9~0); 772762#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 772551#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 772534#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 772527#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 772517#L1415 assume !(0 == start_simulation_~tmp~3#1); 768851#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 766484#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 766476#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 766474#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 766472#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 766470#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 766468#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 766466#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 762502#L1396-2 [2024-11-09 16:09:41,377 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:41,377 INFO L85 PathProgramCache]: Analyzing trace with hash -178464780, now seen corresponding path program 1 times [2024-11-09 16:09:41,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:41,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482926127] [2024-11-09 16:09:41,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:41,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:41,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:41,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:41,415 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:41,415 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482926127] [2024-11-09 16:09:41,415 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482926127] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:41,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:41,416 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:41,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1536746889] [2024-11-09 16:09:41,416 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:41,416 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:41,416 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:41,416 INFO L85 PathProgramCache]: Analyzing trace with hash 2094402044, now seen corresponding path program 1 times [2024-11-09 16:09:41,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:41,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37390311] [2024-11-09 16:09:41,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:41,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:41,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:41,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:41,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:41,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37390311] [2024-11-09 16:09:41,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37390311] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:41,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:41,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:41,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213723253] [2024-11-09 16:09:41,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:41,445 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:41,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:41,445 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:41,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:41,446 INFO L87 Difference]: Start difference. First operand 28595 states and 40122 transitions. cyclomatic complexity: 11559 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:41,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:41,586 INFO L93 Difference]: Finished difference Result 37875 states and 53025 transitions. [2024-11-09 16:09:41,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37875 states and 53025 transitions. [2024-11-09 16:09:41,708 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 37536 [2024-11-09 16:09:41,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37875 states to 37875 states and 53025 transitions. [2024-11-09 16:09:41,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37875 [2024-11-09 16:09:42,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37875 [2024-11-09 16:09:42,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37875 states and 53025 transitions. [2024-11-09 16:09:42,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:42,124 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37875 states and 53025 transitions. [2024-11-09 16:09:42,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37875 states and 53025 transitions. [2024-11-09 16:09:42,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37875 to 25611. [2024-11-09 16:09:42,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.3967826324626138) internal successors, (35773), 25610 states have internal predecessors, (35773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:42,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 35773 transitions. [2024-11-09 16:09:42,362 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 35773 transitions. [2024-11-09 16:09:42,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:42,362 INFO L425 stractBuchiCegarLoop]: Abstraction has 25611 states and 35773 transitions. [2024-11-09 16:09:42,362 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-09 16:09:42,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 35773 transitions. [2024-11-09 16:09:42,423 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2024-11-09 16:09:42,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:42,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:42,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:42,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:42,425 INFO L745 eck$LassoCheckResult]: Stem: 828757#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 828758#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 829589#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 829590#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 829530#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 829531#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 829508#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 829301#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 829302#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 829092#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 829093#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 829619#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 829498#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 829163#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 828919#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 828920#L922 assume !(0 == ~M_E~0); 829676#L922-2 assume !(0 == ~T1_E~0); 829677#L927-1 assume !(0 == ~T2_E~0); 829372#L932-1 assume !(0 == ~T3_E~0); 829237#L937-1 assume !(0 == ~T4_E~0); 829238#L942-1 assume !(0 == ~T5_E~0); 829300#L947-1 assume !(0 == ~T6_E~0); 829376#L952-1 assume !(0 == ~T7_E~0); 829377#L957-1 assume !(0 == ~T8_E~0); 829449#L962-1 assume !(0 == ~T9_E~0); 829214#L967-1 assume !(0 == ~E_1~0); 829215#L972-1 assume !(0 == ~E_2~0); 829514#L977-1 assume !(0 == ~E_3~0); 829515#L982-1 assume !(0 == ~E_4~0); 828689#L987-1 assume !(0 == ~E_5~0); 828690#L992-1 assume !(0 == ~E_6~0); 828696#L997-1 assume !(0 == ~E_7~0); 829135#L1002-1 assume !(0 == ~E_8~0); 829123#L1007-1 assume !(0 == ~E_9~0); 828484#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 828485#L443 assume !(1 == ~m_pc~0); 829394#L443-2 is_master_triggered_~__retres1~0#1 := 0; 829384#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 829385#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 828853#L1140 assume !(0 != activate_threads_~tmp~1#1); 828589#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 828590#L462 assume !(1 == ~t1_pc~0); 829227#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 829228#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 828525#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 828526#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 829070#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 829071#L481 assume !(1 == ~t2_pc~0); 828847#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 828846#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 828980#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 828941#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 828942#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 829038#L500 assume !(1 == ~t3_pc~0); 829576#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 829548#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 828491#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 828492#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 828486#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 828487#L519 assume !(1 == ~t4_pc~0); 829290#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 829037#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 828591#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 828592#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 828890#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 828653#L538 assume !(1 == ~t5_pc~0); 828654#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 828550#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 828551#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 828833#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 828834#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 829431#L557 assume !(1 == ~t6_pc~0); 828868#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 828869#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 828960#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 828891#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 828892#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 829657#L576 assume !(1 == ~t7_pc~0); 828857#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 828858#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 829201#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 829672#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 829490#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 828981#L595 assume !(1 == ~t8_pc~0); 828982#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 829505#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 829436#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 829328#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 829329#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 828784#L614 assume !(1 == ~t9_pc~0); 828785#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 828678#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 828679#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 829013#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 828944#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 828945#L1025 assume !(1 == ~M_E~0); 829221#L1025-2 assume !(1 == ~T1_E~0); 829283#L1030-1 assume !(1 == ~T2_E~0); 829423#L1035-1 assume !(1 == ~T3_E~0); 828936#L1040-1 assume !(1 == ~T4_E~0); 828937#L1045-1 assume !(1 == ~T5_E~0); 828843#L1050-1 assume !(1 == ~T6_E~0); 828844#L1055-1 assume !(1 == ~T7_E~0); 828664#L1060-1 assume !(1 == ~T8_E~0); 828665#L1065-1 assume !(1 == ~T9_E~0); 828728#L1070-1 assume !(1 == ~E_1~0); 829378#L1075-1 assume !(1 == ~E_2~0); 829379#L1080-1 assume !(1 == ~E_3~0); 829367#L1085-1 assume !(1 == ~E_4~0); 829368#L1090-1 assume !(1 == ~E_5~0); 829609#L1095-1 assume !(1 == ~E_6~0); 829404#L1100-1 assume !(1 == ~E_7~0); 829405#L1105-1 assume !(1 == ~E_8~0); 828635#L1110-1 assume !(1 == ~E_9~0); 828636#L1115-1 assume { :end_inline_reset_delta_events } true; 828989#L1396-2 [2024-11-09 16:09:42,425 INFO L747 eck$LassoCheckResult]: Loop: 828989#L1396-2 assume !false; 831163#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 831155#L897-1 assume !false; 831151#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 831125#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 831107#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 831101#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 831092#L766 assume !(0 != eval_~tmp~0#1); 831093#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 831666#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 831665#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 831664#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 831663#L927-3 assume !(0 == ~T2_E~0); 831662#L932-3 assume !(0 == ~T3_E~0); 831661#L937-3 assume !(0 == ~T4_E~0); 831660#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 831659#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 831658#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 831657#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 831656#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 831655#L967-3 assume !(0 == ~E_1~0); 831654#L972-3 assume !(0 == ~E_2~0); 831653#L977-3 assume !(0 == ~E_3~0); 831652#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 831651#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 831650#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 831649#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 831648#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 831647#L1007-3 assume !(0 == ~E_9~0); 831646#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 831645#L443-30 assume !(1 == ~m_pc~0); 831644#L443-32 is_master_triggered_~__retres1~0#1 := 0; 831642#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 831641#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 831640#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 831639#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 831638#L462-30 assume !(1 == ~t1_pc~0); 831637#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 831636#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 831635#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 831633#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 831630#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 831628#L481-30 assume 1 == ~t2_pc~0; 831625#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 831623#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 831621#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 831619#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 831617#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 831615#L500-30 assume !(1 == ~t3_pc~0); 831613#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 831611#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 831609#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 831607#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 831604#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 831602#L519-30 assume !(1 == ~t4_pc~0); 831600#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 831598#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 831596#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 831594#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 831592#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 831590#L538-30 assume !(1 == ~t5_pc~0); 831588#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 831585#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 831582#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 831579#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 831576#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 831574#L557-30 assume !(1 == ~t6_pc~0); 831572#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 831570#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 831568#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 831565#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 831560#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 831556#L576-30 assume 1 == ~t7_pc~0; 831550#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 831544#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 831540#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 831536#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 831532#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 831528#L595-30 assume !(1 == ~t8_pc~0); 831524#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 831520#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 831516#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 831512#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 831506#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 831502#L614-30 assume !(1 == ~t9_pc~0); 831497#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 831492#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 831488#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 831484#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 831480#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 831476#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 831472#L1025-5 assume !(1 == ~T1_E~0); 831468#L1030-3 assume !(1 == ~T2_E~0); 831463#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 831457#L1040-3 assume !(1 == ~T4_E~0); 831451#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 831446#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 831441#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 831436#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 831432#L1065-3 assume !(1 == ~T9_E~0); 831428#L1070-3 assume !(1 == ~E_1~0); 831422#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 831417#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 831413#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 831407#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 831402#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 831397#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 831390#L1105-3 assume !(1 == ~E_8~0); 831385#L1110-3 assume !(1 == ~E_9~0); 831381#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 831254#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 831240#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 831233#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 831227#L1415 assume !(0 == start_simulation_~tmp~3#1); 831224#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 831214#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 831202#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 831197#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 831192#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 831187#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 831181#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 831175#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 828989#L1396-2 [2024-11-09 16:09:42,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:42,426 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 1 times [2024-11-09 16:09:42,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:42,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080274239] [2024-11-09 16:09:42,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:42,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:42,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:42,434 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:42,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:42,476 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:42,476 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:42,476 INFO L85 PathProgramCache]: Analyzing trace with hash 766298907, now seen corresponding path program 1 times [2024-11-09 16:09:42,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:42,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607243122] [2024-11-09 16:09:42,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:42,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:42,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:42,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:42,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:42,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607243122] [2024-11-09 16:09:42,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607243122] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:42,504 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:42,504 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:42,504 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675917808] [2024-11-09 16:09:42,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:42,505 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:42,505 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:42,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:42,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:42,505 INFO L87 Difference]: Start difference. First operand 25611 states and 35773 transitions. cyclomatic complexity: 10194 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:42,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:42,581 INFO L93 Difference]: Finished difference Result 28595 states and 39957 transitions. [2024-11-09 16:09:42,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28595 states and 39957 transitions. [2024-11-09 16:09:42,683 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2024-11-09 16:09:42,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28595 states to 28595 states and 39957 transitions. [2024-11-09 16:09:42,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28595 [2024-11-09 16:09:42,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28595 [2024-11-09 16:09:42,771 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28595 states and 39957 transitions. [2024-11-09 16:09:42,788 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:42,788 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28595 states and 39957 transitions. [2024-11-09 16:09:42,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28595 states and 39957 transitions. [2024-11-09 16:09:42,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28595 to 28595. [2024-11-09 16:09:42,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.3973421926910299) internal successors, (39957), 28594 states have internal predecessors, (39957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:43,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 39957 transitions. [2024-11-09 16:09:43,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 39957 transitions. [2024-11-09 16:09:43,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:43,355 INFO L425 stractBuchiCegarLoop]: Abstraction has 28595 states and 39957 transitions. [2024-11-09 16:09:43,355 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-09 16:09:43,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 39957 transitions. [2024-11-09 16:09:43,423 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2024-11-09 16:09:43,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:43,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:43,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:43,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:43,425 INFO L745 eck$LassoCheckResult]: Stem: 882969#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 882970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 883819#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 883820#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 883753#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 883754#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 883732#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 883511#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 883512#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 883303#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 883304#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 883847#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 883715#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 883371#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 883126#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 883127#L922 assume !(0 == ~M_E~0); 883911#L922-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 883912#L927-1 assume !(0 == ~T2_E~0); 883588#L932-1 assume !(0 == ~T3_E~0); 883589#L937-1 assume !(0 == ~T4_E~0); 883509#L942-1 assume !(0 == ~T5_E~0); 883510#L947-1 assume !(0 == ~T6_E~0); 883594#L952-1 assume !(0 == ~T7_E~0); 883595#L957-1 assume !(0 == ~T8_E~0); 883892#L962-1 assume !(0 == ~T9_E~0); 883893#L967-1 assume !(0 == ~E_1~0); 883884#L972-1 assume !(0 == ~E_2~0); 883885#L977-1 assume !(0 == ~E_3~0); 883916#L982-1 assume !(0 == ~E_4~0); 883917#L987-1 assume !(0 == ~E_5~0); 882909#L992-1 assume !(0 == ~E_6~0); 882910#L997-1 assume !(0 == ~E_7~0); 883863#L1002-1 assume !(0 == ~E_8~0); 883864#L1007-1 assume !(0 == ~E_9~0); 882696#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 882697#L443 assume !(1 == ~m_pc~0); 883610#L443-2 is_master_triggered_~__retres1~0#1 := 0; 883611#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 883720#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 883721#L1140 assume !(0 != activate_threads_~tmp~1#1); 882801#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 882802#L462 assume !(1 == ~t1_pc~0); 883989#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 883988#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 882737#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 882738#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 883280#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 883281#L481 assume !(1 == ~t2_pc~0); 883055#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 883054#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 883984#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 883983#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 883250#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 883251#L500 assume !(1 == ~t3_pc~0); 883982#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 883981#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 882703#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 882704#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 882698#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 882699#L519 assume !(1 == ~t4_pc~0); 883499#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 883500#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 883976#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 883975#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 883974#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 883972#L538 assume !(1 == ~t5_pc~0); 883969#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 883967#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 883965#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 883963#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 883962#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 883936#L557 assume !(1 == ~t6_pc~0); 883077#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 883078#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 883168#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 883099#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 883100#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 883883#L576 assume !(1 == ~t7_pc~0); 883955#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 883954#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 883953#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 883921#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 883708#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 883189#L595 assume !(1 == ~t8_pc~0); 883190#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 883728#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 883655#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 883540#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 883541#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 882993#L614 assume !(1 == ~t9_pc~0); 882994#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 882890#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 882891#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 883224#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 883152#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 883153#L1025 assume !(1 == ~M_E~0); 883433#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 883492#L1030-1 assume !(1 == ~T2_E~0); 883639#L1035-1 assume !(1 == ~T3_E~0); 883144#L1040-1 assume !(1 == ~T4_E~0); 883145#L1045-1 assume !(1 == ~T5_E~0); 883051#L1050-1 assume !(1 == ~T6_E~0); 883052#L1055-1 assume !(1 == ~T7_E~0); 882876#L1060-1 assume !(1 == ~T8_E~0); 882877#L1065-1 assume !(1 == ~T9_E~0); 882942#L1070-1 assume !(1 == ~E_1~0); 883596#L1075-1 assume !(1 == ~E_2~0); 883597#L1080-1 assume !(1 == ~E_3~0); 883583#L1085-1 assume !(1 == ~E_4~0); 883584#L1090-1 assume !(1 == ~E_5~0); 883840#L1095-1 assume !(1 == ~E_6~0); 883622#L1100-1 assume !(1 == ~E_7~0); 883623#L1105-1 assume !(1 == ~E_8~0); 882847#L1110-1 assume !(1 == ~E_9~0); 882848#L1115-1 assume { :end_inline_reset_delta_events } true; 883198#L1396-2 [2024-11-09 16:09:43,426 INFO L747 eck$LassoCheckResult]: Loop: 883198#L1396-2 assume !false; 886433#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 886428#L897-1 assume !false; 886426#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 886422#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 886404#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 886397#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 886387#L766 assume !(0 != eval_~tmp~0#1); 886388#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 886683#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 886682#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 886680#L922-5 assume !(0 == ~T1_E~0); 886681#L927-3 assume !(0 == ~T2_E~0); 886843#L932-3 assume !(0 == ~T3_E~0); 886841#L937-3 assume !(0 == ~T4_E~0); 886839#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 886837#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 886835#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 886833#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 886831#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 886829#L967-3 assume !(0 == ~E_1~0); 886827#L972-3 assume !(0 == ~E_2~0); 886825#L977-3 assume !(0 == ~E_3~0); 886822#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 886820#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 886818#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 886816#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 886814#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 886812#L1007-3 assume !(0 == ~E_9~0); 886810#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 886808#L443-30 assume 1 == ~m_pc~0; 886805#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 886803#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 886801#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 886799#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 886797#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 886795#L462-30 assume !(1 == ~t1_pc~0); 886793#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 886791#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 886789#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 886785#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 886783#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 886781#L481-30 assume !(1 == ~t2_pc~0); 886779#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 886775#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 886773#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 886771#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 886769#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 886767#L500-30 assume !(1 == ~t3_pc~0); 886765#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 886763#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 886761#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 886759#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 886756#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 886754#L519-30 assume !(1 == ~t4_pc~0); 886752#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 886750#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 886748#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 886746#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 886744#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 886742#L538-30 assume 1 == ~t5_pc~0; 886740#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 886741#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 886850#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 886730#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 886728#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 886726#L557-30 assume !(1 == ~t6_pc~0); 886724#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 886722#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 886720#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 886719#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 886715#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 886713#L576-30 assume !(1 == ~t7_pc~0); 886711#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 886709#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 886706#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 886702#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 886698#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 886697#L595-30 assume !(1 == ~t8_pc~0); 886696#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 886695#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 886694#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 886693#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 886692#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 886691#L614-30 assume !(1 == ~t9_pc~0); 886689#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 886688#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 886687#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 886686#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 886685#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 886684#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 886519#L1025-5 assume !(1 == ~T1_E~0); 886517#L1030-3 assume !(1 == ~T2_E~0); 886515#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 886513#L1040-3 assume !(1 == ~T4_E~0); 886511#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 886509#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 886507#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 886505#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 886503#L1065-3 assume !(1 == ~T9_E~0); 886501#L1070-3 assume !(1 == ~E_1~0); 886499#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 886497#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 886495#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 886493#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 886491#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 886489#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 886487#L1105-3 assume !(1 == ~E_8~0); 886485#L1110-3 assume !(1 == ~E_9~0); 886483#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 886480#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 886469#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 886467#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 886463#L1415 assume !(0 == start_simulation_~tmp~3#1); 886462#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 886454#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 886446#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 886444#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 886442#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 886440#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 886438#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 886436#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 883198#L1396-2 [2024-11-09 16:09:43,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:43,426 INFO L85 PathProgramCache]: Analyzing trace with hash 2046196076, now seen corresponding path program 1 times [2024-11-09 16:09:43,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:43,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433985284] [2024-11-09 16:09:43,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:43,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:43,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:43,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:43,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:43,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433985284] [2024-11-09 16:09:43,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433985284] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:43,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:43,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:09:43,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102390470] [2024-11-09 16:09:43,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:43,466 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:43,466 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:43,466 INFO L85 PathProgramCache]: Analyzing trace with hash 2073568863, now seen corresponding path program 1 times [2024-11-09 16:09:43,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:43,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809527365] [2024-11-09 16:09:43,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:43,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:43,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:43,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:43,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:43,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809527365] [2024-11-09 16:09:43,506 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1809527365] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:43,506 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:43,506 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:43,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [628970427] [2024-11-09 16:09:43,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:43,506 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:43,506 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:43,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:43,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:43,507 INFO L87 Difference]: Start difference. First operand 28595 states and 39957 transitions. cyclomatic complexity: 11394 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:43,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:43,595 INFO L93 Difference]: Finished difference Result 25611 states and 35675 transitions. [2024-11-09 16:09:43,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25611 states and 35675 transitions. [2024-11-09 16:09:43,704 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2024-11-09 16:09:43,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25611 states to 25611 states and 35675 transitions. [2024-11-09 16:09:43,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25611 [2024-11-09 16:09:43,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25611 [2024-11-09 16:09:43,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25611 states and 35675 transitions. [2024-11-09 16:09:43,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:43,810 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25611 states and 35675 transitions. [2024-11-09 16:09:43,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25611 states and 35675 transitions. [2024-11-09 16:09:44,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25611 to 25611. [2024-11-09 16:09:44,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.3929561516535864) internal successors, (35675), 25610 states have internal predecessors, (35675), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:44,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 35675 transitions. [2024-11-09 16:09:44,090 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 35675 transitions. [2024-11-09 16:09:44,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:44,090 INFO L425 stractBuchiCegarLoop]: Abstraction has 25611 states and 35675 transitions. [2024-11-09 16:09:44,091 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-09 16:09:44,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 35675 transitions. [2024-11-09 16:09:44,164 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2024-11-09 16:09:44,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:44,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:44,166 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:44,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:44,166 INFO L745 eck$LassoCheckResult]: Stem: 937183#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 937184#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 938007#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 938008#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 937944#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 937945#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 937922#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 937720#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 937721#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 937512#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 937513#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 938040#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 937910#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 937580#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 937338#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 937339#L922 assume !(0 == ~M_E~0); 938094#L922-2 assume !(0 == ~T1_E~0); 938095#L927-1 assume !(0 == ~T2_E~0); 937787#L932-1 assume !(0 == ~T3_E~0); 937656#L937-1 assume !(0 == ~T4_E~0); 937657#L942-1 assume !(0 == ~T5_E~0); 937719#L947-1 assume !(0 == ~T6_E~0); 937791#L952-1 assume !(0 == ~T7_E~0); 937792#L957-1 assume !(0 == ~T8_E~0); 937857#L962-1 assume !(0 == ~T9_E~0); 937633#L967-1 assume !(0 == ~E_1~0); 937634#L972-1 assume !(0 == ~E_2~0); 937928#L977-1 assume !(0 == ~E_3~0); 937929#L982-1 assume !(0 == ~E_4~0); 937114#L987-1 assume !(0 == ~E_5~0); 937115#L992-1 assume !(0 == ~E_6~0); 937121#L997-1 assume !(0 == ~E_7~0); 937555#L1002-1 assume !(0 == ~E_8~0); 937542#L1007-1 assume !(0 == ~E_9~0); 936909#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 936910#L443 assume !(1 == ~m_pc~0); 937809#L443-2 is_master_triggered_~__retres1~0#1 := 0; 937799#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 937800#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 937274#L1140 assume !(0 != activate_threads_~tmp~1#1); 937014#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 937015#L462 assume !(1 == ~t1_pc~0); 937649#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 937650#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 936952#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 936953#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 937491#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 937492#L481 assume !(1 == ~t2_pc~0); 937268#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 937267#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 937400#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 937360#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 937361#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 937460#L500 assume !(1 == ~t3_pc~0); 937996#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 937963#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 936916#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 936917#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 936914#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 936915#L519 assume !(1 == ~t4_pc~0); 937708#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 937457#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 937016#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 937017#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 937312#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 937078#L538 assume !(1 == ~t5_pc~0); 937079#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 936977#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 936978#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 937254#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 937255#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 937841#L557 assume !(1 == ~t6_pc~0); 937289#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 937290#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 937379#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 937313#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 937314#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 938071#L576 assume !(1 == ~t7_pc~0); 937278#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 937279#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 937618#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 938089#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 937901#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 937403#L595 assume !(1 == ~t8_pc~0); 937404#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 937917#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 937845#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 937742#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 937743#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 937206#L614 assume !(1 == ~t9_pc~0); 937207#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 937104#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 937105#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 937435#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 937363#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 937364#L1025 assume !(1 == ~M_E~0); 937639#L1025-2 assume !(1 == ~T1_E~0); 937700#L1030-1 assume !(1 == ~T2_E~0); 937833#L1035-1 assume !(1 == ~T3_E~0); 937356#L1040-1 assume !(1 == ~T4_E~0); 937357#L1045-1 assume !(1 == ~T5_E~0); 937264#L1050-1 assume !(1 == ~T6_E~0); 937265#L1055-1 assume !(1 == ~T7_E~0); 937089#L1060-1 assume !(1 == ~T8_E~0); 937090#L1065-1 assume !(1 == ~T9_E~0); 937153#L1070-1 assume !(1 == ~E_1~0); 937794#L1075-1 assume !(1 == ~E_2~0); 937795#L1080-1 assume !(1 == ~E_3~0); 937782#L1085-1 assume !(1 == ~E_4~0); 937783#L1090-1 assume !(1 == ~E_5~0); 938031#L1095-1 assume !(1 == ~E_6~0); 937818#L1100-1 assume !(1 == ~E_7~0); 937819#L1105-1 assume !(1 == ~E_8~0); 937060#L1110-1 assume !(1 == ~E_9~0); 937061#L1115-1 assume { :end_inline_reset_delta_events } true; 937409#L1396-2 [2024-11-09 16:09:44,166 INFO L747 eck$LassoCheckResult]: Loop: 937409#L1396-2 assume !false; 941838#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 941832#L897-1 assume !false; 941830#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 941827#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 941816#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 941814#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 941811#L766 assume !(0 != eval_~tmp~0#1); 941812#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 942145#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 942143#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 942141#L922-5 assume !(0 == ~T1_E~0); 942139#L927-3 assume !(0 == ~T2_E~0); 942137#L932-3 assume !(0 == ~T3_E~0); 942135#L937-3 assume !(0 == ~T4_E~0); 942133#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 942131#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 942129#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 942127#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 942125#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 942122#L967-3 assume !(0 == ~E_1~0); 942120#L972-3 assume !(0 == ~E_2~0); 942118#L977-3 assume !(0 == ~E_3~0); 942116#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 942114#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 942112#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 942111#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 942107#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 942105#L1007-3 assume !(0 == ~E_9~0); 942103#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 942102#L443-30 assume 1 == ~m_pc~0; 942100#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 942097#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 942094#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 942090#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 942089#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 942088#L462-30 assume !(1 == ~t1_pc~0); 942087#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 942086#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 942085#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 942084#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 942083#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 942082#L481-30 assume 1 == ~t2_pc~0; 942080#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 942079#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 942078#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 942077#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 942076#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 942075#L500-30 assume !(1 == ~t3_pc~0); 942074#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 942073#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 942072#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 942070#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 942069#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 942068#L519-30 assume !(1 == ~t4_pc~0); 942067#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 942066#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 942065#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 942063#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 942062#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 942061#L538-30 assume !(1 == ~t5_pc~0); 942058#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 942057#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 942055#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 942052#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 942049#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 942047#L557-30 assume !(1 == ~t6_pc~0); 942045#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 942043#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 942041#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 942039#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 942037#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 942035#L576-30 assume 1 == ~t7_pc~0; 942032#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 942030#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 942028#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 942025#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 942023#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 942021#L595-30 assume !(1 == ~t8_pc~0); 942019#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 942017#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 942015#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 942013#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 942011#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 942009#L614-30 assume !(1 == ~t9_pc~0); 942006#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 942004#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 942002#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 942000#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 941998#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 941996#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 941994#L1025-5 assume !(1 == ~T1_E~0); 941992#L1030-3 assume !(1 == ~T2_E~0); 941991#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 941987#L1040-3 assume !(1 == ~T4_E~0); 941985#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 941983#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 941981#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 941978#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 941976#L1065-3 assume !(1 == ~T9_E~0); 941974#L1070-3 assume !(1 == ~E_1~0); 941972#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 941970#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 941968#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 941966#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 941964#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 941962#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 941959#L1105-3 assume !(1 == ~E_8~0); 941957#L1110-3 assume !(1 == ~E_9~0); 941955#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 941952#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 941941#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 941939#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 941880#L1415 assume !(0 == start_simulation_~tmp~3#1); 941878#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 941860#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 941852#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 941850#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 941847#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 941845#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 941843#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 941841#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 937409#L1396-2 [2024-11-09 16:09:44,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:44,167 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 2 times [2024-11-09 16:09:44,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:44,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662286975] [2024-11-09 16:09:44,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:44,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:44,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:44,178 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:44,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:44,208 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:44,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:44,209 INFO L85 PathProgramCache]: Analyzing trace with hash 745465726, now seen corresponding path program 1 times [2024-11-09 16:09:44,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:44,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873420531] [2024-11-09 16:09:44,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:44,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:44,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:44,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:44,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:44,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873420531] [2024-11-09 16:09:44,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873420531] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:44,245 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:44,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:44,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [250705650] [2024-11-09 16:09:44,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:44,245 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:44,245 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:44,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:44,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:44,246 INFO L87 Difference]: Start difference. First operand 25611 states and 35675 transitions. cyclomatic complexity: 10096 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:44,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:44,343 INFO L93 Difference]: Finished difference Result 28595 states and 39826 transitions. [2024-11-09 16:09:44,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28595 states and 39826 transitions. [2024-11-09 16:09:44,471 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2024-11-09 16:09:44,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28595 states to 28595 states and 39826 transitions. [2024-11-09 16:09:44,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28595 [2024-11-09 16:09:44,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28595 [2024-11-09 16:09:44,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28595 states and 39826 transitions. [2024-11-09 16:09:44,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:44,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28595 states and 39826 transitions. [2024-11-09 16:09:44,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28595 states and 39826 transitions. [2024-11-09 16:09:45,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28595 to 28595. [2024-11-09 16:09:45,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.3927609721979366) internal successors, (39826), 28594 states have internal predecessors, (39826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:45,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 39826 transitions. [2024-11-09 16:09:45,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 39826 transitions. [2024-11-09 16:09:45,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:45,116 INFO L425 stractBuchiCegarLoop]: Abstraction has 28595 states and 39826 transitions. [2024-11-09 16:09:45,116 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-09 16:09:45,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 39826 transitions. [2024-11-09 16:09:45,182 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2024-11-09 16:09:45,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:45,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:45,183 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:45,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:45,186 INFO L745 eck$LassoCheckResult]: Stem: 991392#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 991393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 992256#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 992257#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 992187#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 992188#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 992162#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 991948#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 991949#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 991730#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 991731#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 992289#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 992148#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 991799#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 991553#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 991554#L922 assume !(0 == ~M_E~0); 992350#L922-2 assume !(0 == ~T1_E~0); 992351#L927-1 assume !(0 == ~T2_E~0); 992020#L932-1 assume !(0 == ~T3_E~0); 991878#L937-1 assume !(0 == ~T4_E~0); 991879#L942-1 assume !(0 == ~T5_E~0); 991947#L947-1 assume !(0 == ~T6_E~0); 992024#L952-1 assume !(0 == ~T7_E~0); 992025#L957-1 assume !(0 == ~T8_E~0); 992098#L962-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 991852#L967-1 assume !(0 == ~E_1~0); 991853#L972-1 assume !(0 == ~E_2~0); 992169#L977-1 assume !(0 == ~E_3~0); 992170#L982-1 assume !(0 == ~E_4~0); 991326#L987-1 assume !(0 == ~E_5~0); 991327#L992-1 assume !(0 == ~E_6~0); 991333#L997-1 assume !(0 == ~E_7~0); 991771#L1002-1 assume !(0 == ~E_8~0); 991758#L1007-1 assume !(0 == ~E_9~0); 991121#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 991122#L443 assume !(1 == ~m_pc~0); 992041#L443-2 is_master_triggered_~__retres1~0#1 := 0; 992032#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 992033#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 992434#L1140 assume !(0 != activate_threads_~tmp~1#1); 992433#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 992432#L462 assume !(1 == ~t1_pc~0); 992431#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 992430#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 992429#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 992050#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 992051#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 992428#L481 assume !(1 == ~t2_pc~0); 992426#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 992010#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991612#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 991575#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 991576#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 992366#L500 assume !(1 == ~t3_pc~0); 992244#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 992204#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 992205#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 992421#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 992420#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 992419#L519 assume !(1 == ~t4_pc~0); 992418#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 991675#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 991228#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 991229#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 991526#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 991290#L538 assume !(1 == ~t5_pc~0); 991291#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 991187#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 991188#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 991467#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 991468#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 992079#L557 assume !(1 == ~t6_pc~0); 992402#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 992401#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 992400#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 992399#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 992398#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 992359#L576 assume !(1 == ~t7_pc~0); 991491#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 991492#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 991837#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 992345#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 992393#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 992392#L595 assume !(1 == ~t8_pc~0); 992391#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 992390#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 992389#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 992388#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 992387#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 992385#L614 assume !(1 == ~t9_pc~0); 992384#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 991316#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 991317#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 991651#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 991578#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 991579#L1025 assume !(1 == ~M_E~0); 991860#L1025-2 assume !(1 == ~T1_E~0); 991928#L1030-1 assume !(1 == ~T2_E~0); 992069#L1035-1 assume !(1 == ~T3_E~0); 991571#L1040-1 assume !(1 == ~T4_E~0); 991572#L1045-1 assume !(1 == ~T5_E~0); 991477#L1050-1 assume !(1 == ~T6_E~0); 991478#L1055-1 assume !(1 == ~T7_E~0); 991301#L1060-1 assume !(1 == ~T8_E~0); 991302#L1065-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 991365#L1070-1 assume !(1 == ~E_1~0); 992026#L1075-1 assume !(1 == ~E_2~0); 992027#L1080-1 assume !(1 == ~E_3~0); 992015#L1085-1 assume !(1 == ~E_4~0); 992016#L1090-1 assume !(1 == ~E_5~0); 992279#L1095-1 assume !(1 == ~E_6~0); 992053#L1100-1 assume !(1 == ~E_7~0); 992054#L1105-1 assume !(1 == ~E_8~0); 991272#L1110-1 assume !(1 == ~E_9~0); 991273#L1115-1 assume { :end_inline_reset_delta_events } true; 991624#L1396-2 [2024-11-09 16:09:45,186 INFO L747 eck$LassoCheckResult]: Loop: 991624#L1396-2 assume !false; 995133#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 995128#L897-1 assume !false; 995126#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 995123#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 995112#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 995110#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 995107#L766 assume !(0 != eval_~tmp~0#1); 995108#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 997558#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 997556#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 997554#L922-5 assume !(0 == ~T1_E~0); 997552#L927-3 assume !(0 == ~T2_E~0); 997550#L932-3 assume !(0 == ~T3_E~0); 997548#L937-3 assume !(0 == ~T4_E~0); 997546#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 997544#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 997543#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 997542#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 997540#L962-3 assume !(0 == ~T9_E~0); 997541#L967-3 assume !(0 == ~E_1~0); 997693#L972-3 assume !(0 == ~E_2~0); 997691#L977-3 assume !(0 == ~E_3~0); 997689#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 997688#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 997687#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 997686#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 997685#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 997683#L1007-3 assume !(0 == ~E_9~0); 997681#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 997679#L443-30 assume !(1 == ~m_pc~0); 997677#L443-32 is_master_triggered_~__retres1~0#1 := 0; 997674#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 997672#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 997670#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 997668#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 997666#L462-30 assume !(1 == ~t1_pc~0); 997664#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 997661#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 997659#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 997658#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 997657#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 997656#L481-30 assume !(1 == ~t2_pc~0); 997655#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 997653#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 997652#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 997650#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 997649#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 997648#L500-30 assume !(1 == ~t3_pc~0); 997647#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 997646#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 997644#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 997642#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 997640#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 997638#L519-30 assume !(1 == ~t4_pc~0); 997636#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 997634#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 997632#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 997630#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 997628#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 997626#L538-30 assume 1 == ~t5_pc~0; 997624#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 997625#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 997651#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 997614#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 997612#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 997610#L557-30 assume !(1 == ~t6_pc~0); 997608#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 997606#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 997604#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 997602#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 997600#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 997598#L576-30 assume !(1 == ~t7_pc~0); 997595#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 997592#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 997590#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 997588#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 997586#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 997584#L595-30 assume !(1 == ~t8_pc~0); 997582#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 997580#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 997578#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 997576#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 997574#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 997572#L614-30 assume !(1 == ~t9_pc~0); 997569#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 997567#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 997565#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 997563#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 997561#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 997560#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 997559#L1025-5 assume !(1 == ~T1_E~0); 997557#L1030-3 assume !(1 == ~T2_E~0); 997555#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 997553#L1040-3 assume !(1 == ~T4_E~0); 997551#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 997549#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 997547#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 997545#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 997378#L1065-3 assume !(1 == ~T9_E~0); 997376#L1070-3 assume !(1 == ~E_1~0); 997374#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 997372#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 997370#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 997368#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 997366#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 997364#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 997362#L1105-3 assume !(1 == ~E_8~0); 997360#L1110-3 assume !(1 == ~E_9~0); 997358#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 997355#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 997339#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 997331#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 997322#L1415 assume !(0 == start_simulation_~tmp~3#1); 997313#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 995155#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 995146#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 995144#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 995142#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 995140#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 995138#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 995136#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 991624#L1396-2 [2024-11-09 16:09:45,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:45,186 INFO L85 PathProgramCache]: Analyzing trace with hash -1667156628, now seen corresponding path program 1 times [2024-11-09 16:09:45,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:45,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831763927] [2024-11-09 16:09:45,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:45,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:45,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:45,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:45,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:45,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831763927] [2024-11-09 16:09:45,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831763927] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:45,225 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:45,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:45,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277367132] [2024-11-09 16:09:45,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:45,225 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:45,225 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:45,226 INFO L85 PathProgramCache]: Analyzing trace with hash -1586354944, now seen corresponding path program 1 times [2024-11-09 16:09:45,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:45,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600076225] [2024-11-09 16:09:45,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:45,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:45,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:45,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:45,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:45,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600076225] [2024-11-09 16:09:45,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600076225] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:45,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:45,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:45,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810864190] [2024-11-09 16:09:45,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:45,251 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:45,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:45,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:45,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:45,252 INFO L87 Difference]: Start difference. First operand 28595 states and 39826 transitions. cyclomatic complexity: 11263 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:45,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:45,395 INFO L93 Difference]: Finished difference Result 51109 states and 71131 transitions. [2024-11-09 16:09:45,395 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51109 states and 71131 transitions. [2024-11-09 16:09:45,568 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 50688 [2024-11-09 16:09:45,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51109 states to 51109 states and 71131 transitions. [2024-11-09 16:09:45,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51109 [2024-11-09 16:09:45,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51109 [2024-11-09 16:09:45,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51109 states and 71131 transitions. [2024-11-09 16:09:45,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:45,740 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51109 states and 71131 transitions. [2024-11-09 16:09:45,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51109 states and 71131 transitions. [2024-11-09 16:09:46,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51109 to 25611. [2024-11-09 16:09:46,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.39166764280973) internal successors, (35642), 25610 states have internal predecessors, (35642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:46,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 35642 transitions. [2024-11-09 16:09:46,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 35642 transitions. [2024-11-09 16:09:46,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:46,062 INFO L425 stractBuchiCegarLoop]: Abstraction has 25611 states and 35642 transitions. [2024-11-09 16:09:46,062 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-09 16:09:46,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 35642 transitions. [2024-11-09 16:09:46,243 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2024-11-09 16:09:46,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:46,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:46,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:46,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:46,245 INFO L745 eck$LassoCheckResult]: Stem: 1071110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1071111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1071948#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1071949#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1071886#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1071887#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1071862#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1071651#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1071652#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1071443#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1071444#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1071980#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1071853#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1071508#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1071266#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1071267#L922 assume !(0 == ~M_E~0); 1072034#L922-2 assume !(0 == ~T1_E~0); 1072035#L927-1 assume !(0 == ~T2_E~0); 1071719#L932-1 assume !(0 == ~T3_E~0); 1071584#L937-1 assume !(0 == ~T4_E~0); 1071585#L942-1 assume !(0 == ~T5_E~0); 1071650#L947-1 assume !(0 == ~T6_E~0); 1071723#L952-1 assume !(0 == ~T7_E~0); 1071724#L957-1 assume !(0 == ~T8_E~0); 1071791#L962-1 assume !(0 == ~T9_E~0); 1071558#L967-1 assume !(0 == ~E_1~0); 1071559#L972-1 assume !(0 == ~E_2~0); 1071869#L977-1 assume !(0 == ~E_3~0); 1071870#L982-1 assume !(0 == ~E_4~0); 1071041#L987-1 assume !(0 == ~E_5~0); 1071042#L992-1 assume !(0 == ~E_6~0); 1071048#L997-1 assume !(0 == ~E_7~0); 1071486#L1002-1 assume !(0 == ~E_8~0); 1071473#L1007-1 assume !(0 == ~E_9~0); 1070835#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1070836#L443 assume !(1 == ~m_pc~0); 1071740#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1071731#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1071732#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1071203#L1140 assume !(0 != activate_threads_~tmp~1#1); 1070940#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1070941#L462 assume !(1 == ~t1_pc~0); 1071575#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1071576#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1070878#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1070879#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1071421#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1071422#L481 assume !(1 == ~t2_pc~0); 1071197#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1071196#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1071328#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1071289#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1071290#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1071389#L500 assume !(1 == ~t3_pc~0); 1071937#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1071903#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1070842#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1070843#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1070840#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1070841#L519 assume !(1 == ~t4_pc~0); 1071639#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1071386#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1070942#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1070943#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1071240#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1071004#L538 assume !(1 == ~t5_pc~0); 1071005#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1070901#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1070902#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1071183#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1071184#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1071776#L557 assume !(1 == ~t6_pc~0); 1071218#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1071219#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1071308#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1071241#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1071242#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1072010#L576 assume !(1 == ~t7_pc~0); 1071207#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1071208#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1071546#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1072030#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1071840#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1071329#L595 assume !(1 == ~t8_pc~0); 1071330#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1071859#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1071779#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1071676#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1071677#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1071135#L614 assume !(1 == ~t9_pc~0); 1071136#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1071030#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1071031#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1071363#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1071292#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1071293#L1025 assume !(1 == ~M_E~0); 1071566#L1025-2 assume !(1 == ~T1_E~0); 1071631#L1030-1 assume !(1 == ~T2_E~0); 1071767#L1035-1 assume !(1 == ~T3_E~0); 1071285#L1040-1 assume !(1 == ~T4_E~0); 1071286#L1045-1 assume !(1 == ~T5_E~0); 1071193#L1050-1 assume !(1 == ~T6_E~0); 1071194#L1055-1 assume !(1 == ~T7_E~0); 1071015#L1060-1 assume !(1 == ~T8_E~0); 1071016#L1065-1 assume !(1 == ~T9_E~0); 1071080#L1070-1 assume !(1 == ~E_1~0); 1071726#L1075-1 assume !(1 == ~E_2~0); 1071727#L1080-1 assume !(1 == ~E_3~0); 1071714#L1085-1 assume !(1 == ~E_4~0); 1071715#L1090-1 assume !(1 == ~E_5~0); 1071971#L1095-1 assume !(1 == ~E_6~0); 1071750#L1100-1 assume !(1 == ~E_7~0); 1071751#L1105-1 assume !(1 == ~E_8~0); 1070986#L1110-1 assume !(1 == ~E_9~0); 1070987#L1115-1 assume { :end_inline_reset_delta_events } true; 1071337#L1396-2 [2024-11-09 16:09:46,245 INFO L747 eck$LassoCheckResult]: Loop: 1071337#L1396-2 assume !false; 1075774#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1075768#L897-1 assume !false; 1075766#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1075763#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1075752#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1075750#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1075747#L766 assume !(0 != eval_~tmp~0#1); 1075748#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1076081#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1076079#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1076077#L922-5 assume !(0 == ~T1_E~0); 1076075#L927-3 assume !(0 == ~T2_E~0); 1076073#L932-3 assume !(0 == ~T3_E~0); 1076071#L937-3 assume !(0 == ~T4_E~0); 1076069#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1076067#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1076065#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1076063#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1076061#L962-3 assume !(0 == ~T9_E~0); 1076058#L967-3 assume !(0 == ~E_1~0); 1076056#L972-3 assume !(0 == ~E_2~0); 1076054#L977-3 assume !(0 == ~E_3~0); 1076052#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1076050#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1076048#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1076047#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1076043#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1076041#L1007-3 assume !(0 == ~E_9~0); 1076039#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1076038#L443-30 assume 1 == ~m_pc~0; 1076036#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1076033#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1076030#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1076026#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1076025#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1076024#L462-30 assume !(1 == ~t1_pc~0); 1076023#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1076022#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1076021#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1076020#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1076019#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1076018#L481-30 assume 1 == ~t2_pc~0; 1076016#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1076015#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1076014#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1076013#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1076012#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1076011#L500-30 assume !(1 == ~t3_pc~0); 1076010#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1076009#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1076008#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1076006#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1076005#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1076004#L519-30 assume !(1 == ~t4_pc~0); 1076003#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1076002#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1076001#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1075999#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1075998#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1075997#L538-30 assume !(1 == ~t5_pc~0); 1075994#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1075993#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1075991#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1075988#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1075985#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1075983#L557-30 assume !(1 == ~t6_pc~0); 1075981#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1075979#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1075977#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1075975#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1075973#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1075971#L576-30 assume 1 == ~t7_pc~0; 1075968#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1075966#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1075964#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1075961#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1075959#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1075957#L595-30 assume !(1 == ~t8_pc~0); 1075955#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1075953#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1075951#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1075949#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1075947#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1075945#L614-30 assume !(1 == ~t9_pc~0); 1075942#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1075940#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1075938#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1075936#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1075934#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1075932#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1075930#L1025-5 assume !(1 == ~T1_E~0); 1075928#L1030-3 assume !(1 == ~T2_E~0); 1075927#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1075923#L1040-3 assume !(1 == ~T4_E~0); 1075921#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1075919#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1075917#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1075914#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1075912#L1065-3 assume !(1 == ~T9_E~0); 1075910#L1070-3 assume !(1 == ~E_1~0); 1075908#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1075906#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1075904#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1075902#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1075900#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1075898#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1075895#L1105-3 assume !(1 == ~E_8~0); 1075893#L1110-3 assume !(1 == ~E_9~0); 1075891#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1075888#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1075877#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1075875#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1075816#L1415 assume !(0 == start_simulation_~tmp~3#1); 1075814#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1075796#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1075788#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1075786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1075783#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1075781#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1075779#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1075777#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1071337#L1396-2 [2024-11-09 16:09:46,246 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:46,246 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 3 times [2024-11-09 16:09:46,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:46,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057956762] [2024-11-09 16:09:46,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:46,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:46,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:46,254 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:46,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:46,283 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:46,284 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:46,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1287928320, now seen corresponding path program 1 times [2024-11-09 16:09:46,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:46,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1843061061] [2024-11-09 16:09:46,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:46,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:46,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:46,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:46,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:46,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1843061061] [2024-11-09 16:09:46,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1843061061] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:46,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:46,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:46,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [470604677] [2024-11-09 16:09:46,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:46,312 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:46,312 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:46,312 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:46,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:46,312 INFO L87 Difference]: Start difference. First operand 25611 states and 35642 transitions. cyclomatic complexity: 10063 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:46,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:46,448 INFO L93 Difference]: Finished difference Result 37851 states and 52550 transitions. [2024-11-09 16:09:46,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37851 states and 52550 transitions. [2024-11-09 16:09:46,578 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37440 [2024-11-09 16:09:46,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37851 states to 37851 states and 52550 transitions. [2024-11-09 16:09:46,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37851 [2024-11-09 16:09:46,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37851 [2024-11-09 16:09:46,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37851 states and 52550 transitions. [2024-11-09 16:09:46,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:46,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37851 states and 52550 transitions. [2024-11-09 16:09:46,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37851 states and 52550 transitions. [2024-11-09 16:09:46,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37851 to 37835. [2024-11-09 16:09:47,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37835 states, 37835 states have (on average 1.3885027091317563) internal successors, (52534), 37834 states have internal predecessors, (52534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:47,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37835 states to 37835 states and 52534 transitions. [2024-11-09 16:09:47,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37835 states and 52534 transitions. [2024-11-09 16:09:47,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:47,057 INFO L425 stractBuchiCegarLoop]: Abstraction has 37835 states and 52534 transitions. [2024-11-09 16:09:47,058 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-09 16:09:47,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37835 states and 52534 transitions. [2024-11-09 16:09:47,146 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37424 [2024-11-09 16:09:47,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:47,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:47,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:47,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:47,147 INFO L745 eck$LassoCheckResult]: Stem: 1134576#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1134577#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1135424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1135425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1135361#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1135362#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1135342#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1135126#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1135127#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1134909#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1134910#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1135456#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1135331#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1134981#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1134731#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1134732#L922 assume !(0 == ~M_E~0); 1135518#L922-2 assume !(0 == ~T1_E~0); 1135519#L927-1 assume !(0 == ~T2_E~0); 1135196#L932-1 assume !(0 == ~T3_E~0); 1135057#L937-1 assume !(0 == ~T4_E~0); 1135058#L942-1 assume !(0 == ~T5_E~0); 1135125#L947-1 assume !(0 == ~T6_E~0); 1135202#L952-1 assume !(0 == ~T7_E~0); 1135203#L957-1 assume !(0 == ~T8_E~0); 1135275#L962-1 assume !(0 == ~T9_E~0); 1135034#L967-1 assume !(0 == ~E_1~0); 1135035#L972-1 assume !(0 == ~E_2~0); 1135347#L977-1 assume !(0 == ~E_3~0); 1135348#L982-1 assume !(0 == ~E_4~0); 1134509#L987-1 assume !(0 == ~E_5~0); 1134510#L992-1 assume !(0 == ~E_6~0); 1134514#L997-1 assume !(0 == ~E_7~0); 1134956#L1002-1 assume 0 == ~E_8~0;~E_8~0 := 1; 1135470#L1007-1 assume !(0 == ~E_9~0); 1134303#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1134304#L443 assume !(1 == ~m_pc~0); 1135218#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1135219#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1135608#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1135607#L1140 assume !(0 != activate_threads_~tmp~1#1); 1134408#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1134409#L462 assume !(1 == ~t1_pc~0); 1135606#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1135605#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1135604#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1135228#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1135229#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1135603#L481 assume !(1 == ~t2_pc~0); 1135601#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1135186#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134790#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1134753#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1134754#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1135532#L500 assume !(1 == ~t3_pc~0); 1135414#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1135379#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1135380#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1135596#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1135595#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1135594#L519 assume !(1 == ~t4_pc~0); 1135593#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1134853#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1134410#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1134411#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1134705#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1134471#L538 assume !(1 == ~t5_pc~0); 1134472#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1134371#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1134372#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1134648#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1134649#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1135260#L557 assume !(1 == ~t6_pc~0); 1135577#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1135576#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1135575#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1135574#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1135573#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1135524#L576 assume !(1 == ~t7_pc~0); 1134673#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1134674#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1135019#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1135514#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1135568#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1135567#L595 assume !(1 == ~t8_pc~0); 1135566#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1135565#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1135564#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1135563#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1135562#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1135560#L614 assume !(1 == ~t9_pc~0); 1135559#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1135558#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1134828#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1134829#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1134756#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1134757#L1025 assume !(1 == ~M_E~0); 1135040#L1025-2 assume !(1 == ~T1_E~0); 1135107#L1030-1 assume !(1 == ~T2_E~0); 1135251#L1035-1 assume !(1 == ~T3_E~0); 1134749#L1040-1 assume !(1 == ~T4_E~0); 1134750#L1045-1 assume !(1 == ~T5_E~0); 1134658#L1050-1 assume !(1 == ~T6_E~0); 1134659#L1055-1 assume !(1 == ~T7_E~0); 1134482#L1060-1 assume !(1 == ~T8_E~0); 1134483#L1065-1 assume !(1 == ~T9_E~0); 1134546#L1070-1 assume !(1 == ~E_1~0); 1135205#L1075-1 assume !(1 == ~E_2~0); 1135206#L1080-1 assume !(1 == ~E_3~0); 1135191#L1085-1 assume !(1 == ~E_4~0); 1135192#L1090-1 assume !(1 == ~E_5~0); 1135447#L1095-1 assume !(1 == ~E_6~0); 1135233#L1100-1 assume !(1 == ~E_7~0); 1135234#L1105-1 assume 1 == ~E_8~0;~E_8~0 := 2; 1134454#L1110-1 assume !(1 == ~E_9~0); 1134455#L1115-1 assume { :end_inline_reset_delta_events } true; 1134802#L1396-2 [2024-11-09 16:09:47,148 INFO L747 eck$LassoCheckResult]: Loop: 1134802#L1396-2 assume !false; 1142498#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1142493#L897-1 assume !false; 1142489#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1142486#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1142476#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1142473#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1142471#L766 assume !(0 != eval_~tmp~0#1); 1142472#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1143879#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1143878#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1143877#L922-5 assume !(0 == ~T1_E~0); 1143876#L927-3 assume !(0 == ~T2_E~0); 1143875#L932-3 assume !(0 == ~T3_E~0); 1143874#L937-3 assume !(0 == ~T4_E~0); 1143873#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1143872#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1143870#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1143869#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1143868#L962-3 assume !(0 == ~T9_E~0); 1143866#L967-3 assume !(0 == ~E_1~0); 1143865#L972-3 assume !(0 == ~E_2~0); 1143864#L977-3 assume !(0 == ~E_3~0); 1143863#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1143862#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1143861#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1143860#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1143859#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1143857#L1007-3 assume !(0 == ~E_9~0); 1143855#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1143853#L443-30 assume 1 == ~m_pc~0; 1143849#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1143847#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1143845#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1143843#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1143841#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1143839#L462-30 assume !(1 == ~t1_pc~0); 1143837#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1143835#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1143833#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1143831#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1143829#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1143827#L481-30 assume !(1 == ~t2_pc~0); 1143824#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1143821#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1143819#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1143817#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1143815#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1143813#L500-30 assume !(1 == ~t3_pc~0); 1143811#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1143809#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1143807#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1143805#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1143803#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1143801#L519-30 assume !(1 == ~t4_pc~0); 1143799#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1143797#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1143795#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1143793#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1143791#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1143787#L538-30 assume !(1 == ~t5_pc~0); 1143783#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1143781#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1143779#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1143776#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1143773#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1143771#L557-30 assume !(1 == ~t6_pc~0); 1143769#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1143767#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1143765#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1143763#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1143761#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1143759#L576-30 assume 1 == ~t7_pc~0; 1143755#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1143753#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1143751#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1143749#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143747#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1143745#L595-30 assume !(1 == ~t8_pc~0); 1143743#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1143741#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1143739#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1143737#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1143735#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1143732#L614-30 assume !(1 == ~t9_pc~0); 1143729#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1143727#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1143725#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1143723#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1143721#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1143719#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1143717#L1025-5 assume !(1 == ~T1_E~0); 1143715#L1030-3 assume !(1 == ~T2_E~0); 1143713#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1143711#L1040-3 assume !(1 == ~T4_E~0); 1143709#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1143707#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1143705#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1143703#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1143701#L1065-3 assume !(1 == ~T9_E~0); 1143699#L1070-3 assume !(1 == ~E_1~0); 1143697#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1143695#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1143693#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1143691#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1143689#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1143687#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1143686#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1143684#L1110-3 assume !(1 == ~E_9~0); 1143683#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1143682#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1143672#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1143671#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1142532#L1415 assume !(0 == start_simulation_~tmp~3#1); 1142530#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1142520#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1142512#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1142510#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1142508#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1142505#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1142503#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1142501#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1134802#L1396-2 [2024-11-09 16:09:47,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:47,148 INFO L85 PathProgramCache]: Analyzing trace with hash 63435116, now seen corresponding path program 1 times [2024-11-09 16:09:47,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:47,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174966212] [2024-11-09 16:09:47,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:47,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:47,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:47,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:47,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:47,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [174966212] [2024-11-09 16:09:47,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [174966212] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:47,187 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:47,187 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:47,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121143935] [2024-11-09 16:09:47,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:47,188 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:09:47,188 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:47,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1008863261, now seen corresponding path program 1 times [2024-11-09 16:09:47,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:47,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967948850] [2024-11-09 16:09:47,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:47,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:47,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:47,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:47,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:47,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967948850] [2024-11-09 16:09:47,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967948850] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:47,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:47,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:47,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557974391] [2024-11-09 16:09:47,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:47,226 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:47,227 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:47,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:09:47,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:09:47,227 INFO L87 Difference]: Start difference. First operand 37835 states and 52534 transitions. cyclomatic complexity: 14731 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:47,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:47,643 INFO L93 Difference]: Finished difference Result 70205 states and 97555 transitions. [2024-11-09 16:09:47,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70205 states and 97555 transitions. [2024-11-09 16:09:47,877 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 67408 [2024-11-09 16:09:48,014 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70205 states to 70205 states and 97555 transitions. [2024-11-09 16:09:48,014 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70205 [2024-11-09 16:09:48,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70205 [2024-11-09 16:09:48,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70205 states and 97555 transitions. [2024-11-09 16:09:48,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:48,086 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70205 states and 97555 transitions. [2024-11-09 16:09:48,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70205 states and 97555 transitions. [2024-11-09 16:09:48,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70205 to 36307. [2024-11-09 16:09:48,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36307 states, 36307 states have (on average 1.3874184041644861) internal successors, (50373), 36306 states have internal predecessors, (50373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:48,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36307 states to 36307 states and 50373 transitions. [2024-11-09 16:09:48,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36307 states and 50373 transitions. [2024-11-09 16:09:48,561 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:09:48,562 INFO L425 stractBuchiCegarLoop]: Abstraction has 36307 states and 50373 transitions. [2024-11-09 16:09:48,562 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-09 16:09:48,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36307 states and 50373 transitions. [2024-11-09 16:09:48,647 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35984 [2024-11-09 16:09:48,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:48,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:48,648 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:48,648 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:48,648 INFO L745 eck$LassoCheckResult]: Stem: 1242630#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1242631#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1243465#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1243466#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1243401#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1243402#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1243380#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1243177#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1243178#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1242967#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1242968#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1243498#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1243369#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1243033#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1242786#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1242787#L922 assume !(0 == ~M_E~0); 1243568#L922-2 assume !(0 == ~T1_E~0); 1243569#L927-1 assume !(0 == ~T2_E~0); 1243247#L932-1 assume !(0 == ~T3_E~0); 1243109#L937-1 assume !(0 == ~T4_E~0); 1243110#L942-1 assume !(0 == ~T5_E~0); 1243176#L947-1 assume !(0 == ~T6_E~0); 1243251#L952-1 assume !(0 == ~T7_E~0); 1243252#L957-1 assume !(0 == ~T8_E~0); 1243319#L962-1 assume !(0 == ~T9_E~0); 1243088#L967-1 assume !(0 == ~E_1~0); 1243089#L972-1 assume !(0 == ~E_2~0); 1243387#L977-1 assume !(0 == ~E_3~0); 1243388#L982-1 assume !(0 == ~E_4~0); 1242562#L987-1 assume !(0 == ~E_5~0); 1242563#L992-1 assume !(0 == ~E_6~0); 1242567#L997-1 assume !(0 == ~E_7~0); 1243010#L1002-1 assume !(0 == ~E_8~0); 1242996#L1007-1 assume !(0 == ~E_9~0); 1242355#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1242356#L443 assume !(1 == ~m_pc~0); 1243268#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1243259#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1243260#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1242723#L1140 assume !(0 != activate_threads_~tmp~1#1); 1242461#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1242462#L462 assume !(1 == ~t1_pc~0); 1243103#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1243104#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1242398#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1242399#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1242946#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1242947#L481 assume !(1 == ~t2_pc~0); 1242717#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1242716#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1242850#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1242809#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1242810#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1242915#L500 assume !(1 == ~t3_pc~0); 1243454#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1243420#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1242362#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1242363#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1242360#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1242361#L519 assume !(1 == ~t4_pc~0); 1243163#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1242912#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1242463#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1242464#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1242763#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1242524#L538 assume !(1 == ~t5_pc~0); 1242525#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1242423#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1242424#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1242703#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1242704#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1243302#L557 assume !(1 == ~t6_pc~0); 1242737#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1242738#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1242828#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1242761#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1242762#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1243537#L576 assume !(1 == ~t7_pc~0); 1242727#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1242728#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1243072#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1243562#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1243360#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1242854#L595 assume !(1 == ~t8_pc~0); 1242855#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1243377#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1243306#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1243204#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1243205#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1242653#L614 assume !(1 == ~t9_pc~0); 1242654#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1242550#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1242551#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1242887#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1242813#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1242814#L1025 assume !(1 == ~M_E~0); 1243093#L1025-2 assume !(1 == ~T1_E~0); 1243156#L1030-1 assume !(1 == ~T2_E~0); 1243293#L1035-1 assume !(1 == ~T3_E~0); 1242805#L1040-1 assume !(1 == ~T4_E~0); 1242806#L1045-1 assume !(1 == ~T5_E~0); 1242713#L1050-1 assume !(1 == ~T6_E~0); 1242714#L1055-1 assume !(1 == ~T7_E~0); 1242535#L1060-1 assume !(1 == ~T8_E~0); 1242536#L1065-1 assume !(1 == ~T9_E~0); 1242599#L1070-1 assume !(1 == ~E_1~0); 1243254#L1075-1 assume !(1 == ~E_2~0); 1243255#L1080-1 assume !(1 == ~E_3~0); 1243242#L1085-1 assume !(1 == ~E_4~0); 1243243#L1090-1 assume !(1 == ~E_5~0); 1243490#L1095-1 assume !(1 == ~E_6~0); 1243278#L1100-1 assume !(1 == ~E_7~0); 1243279#L1105-1 assume !(1 == ~E_8~0); 1242507#L1110-1 assume !(1 == ~E_9~0); 1242508#L1115-1 assume { :end_inline_reset_delta_events } true; 1242860#L1396-2 [2024-11-09 16:09:48,649 INFO L747 eck$LassoCheckResult]: Loop: 1242860#L1396-2 assume !false; 1251019#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1251014#L897-1 assume !false; 1251012#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1251007#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1250957#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1250949#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1250938#L766 assume !(0 != eval_~tmp~0#1); 1250939#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1253084#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1253082#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1253080#L922-5 assume !(0 == ~T1_E~0); 1253077#L927-3 assume !(0 == ~T2_E~0); 1253075#L932-3 assume !(0 == ~T3_E~0); 1253073#L937-3 assume !(0 == ~T4_E~0); 1253041#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1253038#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1253036#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1253034#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1253032#L962-3 assume !(0 == ~T9_E~0); 1253030#L967-3 assume !(0 == ~E_1~0); 1253028#L972-3 assume !(0 == ~E_2~0); 1253026#L977-3 assume !(0 == ~E_3~0); 1253024#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1253022#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1253020#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1253018#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1253016#L1002-3 assume !(0 == ~E_8~0); 1253014#L1007-3 assume !(0 == ~E_9~0); 1253012#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1253010#L443-30 assume !(1 == ~m_pc~0); 1253006#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1253003#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1253001#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1252999#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1252997#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1252995#L462-30 assume !(1 == ~t1_pc~0); 1252993#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1252991#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1252989#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1252987#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1252985#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1252983#L481-30 assume !(1 == ~t2_pc~0); 1252981#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1252976#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1252975#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1252974#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1252973#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1252972#L500-30 assume !(1 == ~t3_pc~0); 1252971#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1252969#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1252966#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1252964#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1252962#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1252960#L519-30 assume !(1 == ~t4_pc~0); 1252958#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1252956#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1252914#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1252440#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1251262#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1251260#L538-30 assume 1 == ~t5_pc~0; 1251258#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1251259#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1251507#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1251247#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1251243#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1251242#L557-30 assume !(1 == ~t6_pc~0); 1251241#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1251240#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1251239#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1251238#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1251237#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1251236#L576-30 assume !(1 == ~t7_pc~0); 1251235#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1251233#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1251232#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1251231#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1251230#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1251229#L595-30 assume !(1 == ~t8_pc~0); 1251228#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1251227#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1251226#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1251225#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1251224#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1251223#L614-30 assume !(1 == ~t9_pc~0); 1251220#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1251217#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1251215#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1251213#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1251211#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1251209#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1251207#L1025-5 assume !(1 == ~T1_E~0); 1251205#L1030-3 assume !(1 == ~T2_E~0); 1251203#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1251201#L1040-3 assume !(1 == ~T4_E~0); 1251199#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1251197#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1251195#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1251192#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1251190#L1065-3 assume !(1 == ~T9_E~0); 1251188#L1070-3 assume !(1 == ~E_1~0); 1251186#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1251184#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1251182#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1251180#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1251178#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1251176#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1251174#L1105-3 assume !(1 == ~E_8~0); 1251172#L1110-3 assume !(1 == ~E_9~0); 1251170#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1251167#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1251156#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1251154#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1251053#L1415 assume !(0 == start_simulation_~tmp~3#1); 1251051#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1251041#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1251033#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1251030#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1251028#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1251026#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1251024#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1251022#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1242860#L1396-2 [2024-11-09 16:09:48,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:48,649 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 4 times [2024-11-09 16:09:48,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:48,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775901436] [2024-11-09 16:09:48,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:48,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:48,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:48,657 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:48,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:48,678 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:48,678 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:48,678 INFO L85 PathProgramCache]: Analyzing trace with hash -234969726, now seen corresponding path program 1 times [2024-11-09 16:09:48,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:48,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646445193] [2024-11-09 16:09:48,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:48,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:48,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:48,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:48,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:48,714 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646445193] [2024-11-09 16:09:48,714 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646445193] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:48,714 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:48,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:48,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588263611] [2024-11-09 16:09:48,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:48,715 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:48,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:48,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:48,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:48,715 INFO L87 Difference]: Start difference. First operand 36307 states and 50373 transitions. cyclomatic complexity: 14098 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:49,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:49,035 INFO L93 Difference]: Finished difference Result 36579 states and 50645 transitions. [2024-11-09 16:09:49,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36579 states and 50645 transitions. [2024-11-09 16:09:49,180 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36256 [2024-11-09 16:09:49,274 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36579 states to 36579 states and 50645 transitions. [2024-11-09 16:09:49,274 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36579 [2024-11-09 16:09:49,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36579 [2024-11-09 16:09:49,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36579 states and 50645 transitions. [2024-11-09 16:09:49,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:49,322 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36579 states and 50645 transitions. [2024-11-09 16:09:49,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36579 states and 50645 transitions. [2024-11-09 16:09:49,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36579 to 36451. [2024-11-09 16:09:49,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36451 states, 36451 states have (on average 1.3858879043098955) internal successors, (50517), 36450 states have internal predecessors, (50517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:49,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36451 states to 36451 states and 50517 transitions. [2024-11-09 16:09:49,727 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36451 states and 50517 transitions. [2024-11-09 16:09:49,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:49,728 INFO L425 stractBuchiCegarLoop]: Abstraction has 36451 states and 50517 transitions. [2024-11-09 16:09:49,728 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-09 16:09:49,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36451 states and 50517 transitions. [2024-11-09 16:09:49,833 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36128 [2024-11-09 16:09:49,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:49,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:49,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:49,834 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:49,834 INFO L745 eck$LassoCheckResult]: Stem: 1315521#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1315522#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1316371#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1316372#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1316307#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1316308#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1316283#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1316070#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1316071#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1315855#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1315856#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1316413#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1316274#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1315923#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1315678#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1315679#L922 assume !(0 == ~M_E~0); 1316484#L922-2 assume !(0 == ~T1_E~0); 1316485#L927-1 assume !(0 == ~T2_E~0); 1316145#L932-1 assume !(0 == ~T3_E~0); 1316005#L937-1 assume !(0 == ~T4_E~0); 1316006#L942-1 assume !(0 == ~T5_E~0); 1316069#L947-1 assume !(0 == ~T6_E~0); 1316150#L952-1 assume !(0 == ~T7_E~0); 1316151#L957-1 assume !(0 == ~T8_E~0); 1316220#L962-1 assume !(0 == ~T9_E~0); 1315980#L967-1 assume !(0 == ~E_1~0); 1315981#L972-1 assume !(0 == ~E_2~0); 1316289#L977-1 assume !(0 == ~E_3~0); 1316290#L982-1 assume !(0 == ~E_4~0); 1315454#L987-1 assume !(0 == ~E_5~0); 1315455#L992-1 assume !(0 == ~E_6~0); 1315461#L997-1 assume !(0 == ~E_7~0); 1315899#L1002-1 assume !(0 == ~E_8~0); 1315885#L1007-1 assume !(0 == ~E_9~0); 1315249#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1315250#L443 assume !(1 == ~m_pc~0); 1316168#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1316160#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1316161#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1315614#L1140 assume !(0 != activate_threads_~tmp~1#1); 1315354#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1315355#L462 assume !(1 == ~t1_pc~0); 1315998#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1315999#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1315292#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1315293#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1315834#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1315835#L481 assume !(1 == ~t2_pc~0); 1315608#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1315607#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1315738#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1315700#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1315701#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1315803#L500 assume !(1 == ~t3_pc~0); 1316362#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1316327#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1315256#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1315257#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1315251#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1315252#L519 assume !(1 == ~t4_pc~0); 1316059#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1315800#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1315356#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1315357#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1315652#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1315417#L538 assume !(1 == ~t5_pc~0); 1315418#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1315315#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1315316#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1315595#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1315596#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1316205#L557 assume !(1 == ~t6_pc~0); 1315628#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1315629#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1315718#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1315650#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1315651#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1316454#L576 assume !(1 == ~t7_pc~0); 1315618#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1315619#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1315966#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1316479#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1316265#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1315741#L595 assume !(1 == ~t8_pc~0); 1315742#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1316280#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1316209#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1316095#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1316096#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1315545#L614 assume !(1 == ~t9_pc~0); 1315546#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1315443#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1315444#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1315777#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1315703#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1315704#L1025 assume !(1 == ~M_E~0); 1315989#L1025-2 assume !(1 == ~T1_E~0); 1316052#L1030-1 assume !(1 == ~T2_E~0); 1316194#L1035-1 assume !(1 == ~T3_E~0); 1315696#L1040-1 assume !(1 == ~T4_E~0); 1315697#L1045-1 assume !(1 == ~T5_E~0); 1315604#L1050-1 assume !(1 == ~T6_E~0); 1315605#L1055-1 assume !(1 == ~T7_E~0); 1315428#L1060-1 assume !(1 == ~T8_E~0); 1315429#L1065-1 assume !(1 == ~T9_E~0); 1315494#L1070-1 assume !(1 == ~E_1~0); 1316152#L1075-1 assume !(1 == ~E_2~0); 1316153#L1080-1 assume !(1 == ~E_3~0); 1316140#L1085-1 assume !(1 == ~E_4~0); 1316141#L1090-1 assume !(1 == ~E_5~0); 1316401#L1095-1 assume !(1 == ~E_6~0); 1316178#L1100-1 assume !(1 == ~E_7~0); 1316179#L1105-1 assume !(1 == ~E_8~0); 1315400#L1110-1 assume !(1 == ~E_9~0); 1315401#L1115-1 assume { :end_inline_reset_delta_events } true; 1315750#L1396-2 [2024-11-09 16:09:49,835 INFO L747 eck$LassoCheckResult]: Loop: 1315750#L1396-2 assume !false; 1329878#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1329875#L897-1 assume !false; 1329874#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1329873#L699 assume !(0 == ~m_st~0); 1329865#L703 assume !(0 == ~t1_st~0); 1329866#L707 assume !(0 == ~t2_st~0); 1329870#L711 assume !(0 == ~t3_st~0); 1329863#L715 assume !(0 == ~t4_st~0); 1329864#L719 assume !(0 == ~t5_st~0); 1329869#L723 assume !(0 == ~t6_st~0); 1329872#L727 assume !(0 == ~t7_st~0); 1329867#L731 assume !(0 == ~t8_st~0); 1329868#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1329871#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1326626#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1326627#L766 assume !(0 != eval_~tmp~0#1); 1331564#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1331563#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1331562#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1331561#L922-5 assume !(0 == ~T1_E~0); 1331560#L927-3 assume !(0 == ~T2_E~0); 1331559#L932-3 assume !(0 == ~T3_E~0); 1331558#L937-3 assume !(0 == ~T4_E~0); 1331557#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1331556#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1331555#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1331554#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1331553#L962-3 assume !(0 == ~T9_E~0); 1331552#L967-3 assume !(0 == ~E_1~0); 1331551#L972-3 assume !(0 == ~E_2~0); 1331550#L977-3 assume !(0 == ~E_3~0); 1331549#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1331548#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1331547#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1331546#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1331545#L1002-3 assume !(0 == ~E_8~0); 1331544#L1007-3 assume !(0 == ~E_9~0); 1331543#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1331542#L443-30 assume 1 == ~m_pc~0; 1331540#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1331539#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1331538#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1331537#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1331536#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1331535#L462-30 assume !(1 == ~t1_pc~0); 1331534#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1331533#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1331532#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1331531#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1331530#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1331529#L481-30 assume 1 == ~t2_pc~0; 1331527#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1331526#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1331525#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1331524#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1331523#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1331522#L500-30 assume !(1 == ~t3_pc~0); 1331521#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1331520#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1331519#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1331518#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1331517#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1331516#L519-30 assume !(1 == ~t4_pc~0); 1331515#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1331514#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1331513#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1331512#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1331511#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1331510#L538-30 assume 1 == ~t5_pc~0; 1331508#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1331506#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1331504#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1331502#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1331501#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1331500#L557-30 assume !(1 == ~t6_pc~0); 1331499#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1331498#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1331497#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1331496#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1331495#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1331494#L576-30 assume 1 == ~t7_pc~0; 1331492#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1331491#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1331490#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1331489#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1331488#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1331487#L595-30 assume !(1 == ~t8_pc~0); 1331486#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1331485#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1331484#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1331483#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1331482#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1331481#L614-30 assume !(1 == ~t9_pc~0); 1331479#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1331478#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1331477#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1331476#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1331475#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1331474#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1331473#L1025-5 assume !(1 == ~T1_E~0); 1331472#L1030-3 assume !(1 == ~T2_E~0); 1331471#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1331470#L1040-3 assume !(1 == ~T4_E~0); 1331469#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1331468#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1331467#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1331466#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1331465#L1065-3 assume !(1 == ~T9_E~0); 1331464#L1070-3 assume !(1 == ~E_1~0); 1331463#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1331462#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1331461#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1331460#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1331459#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1331458#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1331457#L1105-3 assume !(1 == ~E_8~0); 1331456#L1110-3 assume !(1 == ~E_9~0); 1331455#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1331454#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1330950#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1330482#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1330475#L1415 assume !(0 == start_simulation_~tmp~3#1); 1330469#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1330238#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1329946#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1329888#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1329887#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1329886#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1329884#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1329882#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1315750#L1396-2 [2024-11-09 16:09:49,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:49,835 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 5 times [2024-11-09 16:09:49,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:49,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045765783] [2024-11-09 16:09:49,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:49,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:49,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:49,845 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:49,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:49,871 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:49,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:49,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1818868306, now seen corresponding path program 1 times [2024-11-09 16:09:49,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:49,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610105911] [2024-11-09 16:09:49,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:49,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:49,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:49,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:49,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:49,926 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610105911] [2024-11-09 16:09:49,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610105911] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:49,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:49,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:49,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689573140] [2024-11-09 16:09:49,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:49,927 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:49,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:49,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:49,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:49,928 INFO L87 Difference]: Start difference. First operand 36451 states and 50517 transitions. cyclomatic complexity: 14098 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:50,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:50,228 INFO L93 Difference]: Finished difference Result 37606 states and 51672 transitions. [2024-11-09 16:09:50,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37606 states and 51672 transitions. [2024-11-09 16:09:50,378 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37280 [2024-11-09 16:09:50,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37606 states to 37606 states and 51672 transitions. [2024-11-09 16:09:50,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37606 [2024-11-09 16:09:50,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37606 [2024-11-09 16:09:50,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37606 states and 51672 transitions. [2024-11-09 16:09:50,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:50,524 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37606 states and 51672 transitions. [2024-11-09 16:09:50,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37606 states and 51672 transitions. [2024-11-09 16:09:50,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37606 to 37606. [2024-11-09 16:09:51,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37606 states, 37606 states have (on average 1.374036058075839) internal successors, (51672), 37605 states have internal predecessors, (51672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:51,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37606 states to 37606 states and 51672 transitions. [2024-11-09 16:09:51,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37606 states and 51672 transitions. [2024-11-09 16:09:51,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:51,069 INFO L425 stractBuchiCegarLoop]: Abstraction has 37606 states and 51672 transitions. [2024-11-09 16:09:51,069 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-09 16:09:51,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37606 states and 51672 transitions. [2024-11-09 16:09:51,157 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37280 [2024-11-09 16:09:51,157 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:51,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:51,158 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:51,158 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:51,158 INFO L745 eck$LassoCheckResult]: Stem: 1389587#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1389588#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1390465#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1390466#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1390400#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1390401#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1390371#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1390148#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1390149#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1389925#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1389926#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1390501#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1390359#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1389998#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1389748#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1389749#L922 assume !(0 == ~M_E~0); 1390569#L922-2 assume !(0 == ~T1_E~0); 1390570#L927-1 assume !(0 == ~T2_E~0); 1390224#L932-1 assume !(0 == ~T3_E~0); 1390073#L937-1 assume !(0 == ~T4_E~0); 1390074#L942-1 assume !(0 == ~T5_E~0); 1390147#L947-1 assume !(0 == ~T6_E~0); 1390229#L952-1 assume !(0 == ~T7_E~0); 1390230#L957-1 assume !(0 == ~T8_E~0); 1390301#L962-1 assume !(0 == ~T9_E~0); 1390053#L967-1 assume !(0 == ~E_1~0); 1390054#L972-1 assume !(0 == ~E_2~0); 1390383#L977-1 assume !(0 == ~E_3~0); 1390384#L982-1 assume !(0 == ~E_4~0); 1389521#L987-1 assume !(0 == ~E_5~0); 1389522#L992-1 assume !(0 == ~E_6~0); 1389526#L997-1 assume !(0 == ~E_7~0); 1389973#L1002-1 assume !(0 == ~E_8~0); 1389957#L1007-1 assume !(0 == ~E_9~0); 1389314#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1389315#L443 assume !(1 == ~m_pc~0); 1390247#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1390238#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1390239#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1389683#L1140 assume !(0 != activate_threads_~tmp~1#1); 1389419#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1389420#L462 assume !(1 == ~t1_pc~0); 1390067#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1390068#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1389357#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1389358#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1389903#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1389904#L481 assume !(1 == ~t2_pc~0); 1389675#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1390442#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1390597#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1390595#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1389772#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1389873#L500 assume !(1 == ~t3_pc~0); 1390454#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1390417#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1389321#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1389322#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1389319#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1389320#L519 assume !(1 == ~t4_pc~0); 1390132#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1389870#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1389421#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1389422#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1389720#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1389483#L538 assume !(1 == ~t5_pc~0); 1389484#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1389382#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1389383#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1389661#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1389662#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1390287#L557 assume !(1 == ~t6_pc~0); 1389697#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1389698#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1389789#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1389721#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1389722#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1390538#L576 assume !(1 == ~t7_pc~0); 1389687#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1389688#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1390038#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1390566#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1390346#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1389811#L595 assume !(1 == ~t8_pc~0); 1389812#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1390367#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1390291#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1390173#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1390174#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1389612#L614 assume !(1 == ~t9_pc~0); 1389613#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1389509#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1389510#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1389846#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1389774#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1389775#L1025 assume !(1 == ~M_E~0); 1390059#L1025-2 assume !(1 == ~T1_E~0); 1390123#L1030-1 assume !(1 == ~T2_E~0); 1390277#L1035-1 assume !(1 == ~T3_E~0); 1389766#L1040-1 assume !(1 == ~T4_E~0); 1389767#L1045-1 assume !(1 == ~T5_E~0); 1389671#L1050-1 assume !(1 == ~T6_E~0); 1389672#L1055-1 assume !(1 == ~T7_E~0); 1389494#L1060-1 assume !(1 == ~T8_E~0); 1389495#L1065-1 assume !(1 == ~T9_E~0); 1389558#L1070-1 assume !(1 == ~E_1~0); 1390232#L1075-1 assume !(1 == ~E_2~0); 1390233#L1080-1 assume !(1 == ~E_3~0); 1390218#L1085-1 assume !(1 == ~E_4~0); 1390219#L1090-1 assume !(1 == ~E_5~0); 1390493#L1095-1 assume !(1 == ~E_6~0); 1390259#L1100-1 assume !(1 == ~E_7~0); 1390260#L1105-1 assume !(1 == ~E_8~0); 1389465#L1110-1 assume !(1 == ~E_9~0); 1389466#L1115-1 assume { :end_inline_reset_delta_events } true; 1389820#L1396-2 [2024-11-09 16:09:51,158 INFO L747 eck$LassoCheckResult]: Loop: 1389820#L1396-2 assume !false; 1404332#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1404323#L897-1 assume !false; 1404319#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1404251#L699 assume !(0 == ~m_st~0); 1404243#L703 assume !(0 == ~t1_st~0); 1404244#L707 assume !(0 == ~t2_st~0); 1404248#L711 assume !(0 == ~t3_st~0); 1404241#L715 assume !(0 == ~t4_st~0); 1404242#L719 assume !(0 == ~t5_st~0); 1404247#L723 assume !(0 == ~t6_st~0); 1404250#L727 assume !(0 == ~t7_st~0); 1404245#L731 assume !(0 == ~t8_st~0); 1404246#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1404249#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1404075#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1404076#L766 assume !(0 != eval_~tmp~0#1); 1405429#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1405424#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1405418#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1405413#L922-5 assume !(0 == ~T1_E~0); 1405408#L927-3 assume !(0 == ~T2_E~0); 1405404#L932-3 assume !(0 == ~T3_E~0); 1405400#L937-3 assume !(0 == ~T4_E~0); 1405395#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1405391#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1405387#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1405383#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1405379#L962-3 assume !(0 == ~T9_E~0); 1405375#L967-3 assume !(0 == ~E_1~0); 1405369#L972-3 assume !(0 == ~E_2~0); 1405364#L977-3 assume !(0 == ~E_3~0); 1405359#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1405354#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1405349#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1405345#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1405339#L1002-3 assume !(0 == ~E_8~0); 1405333#L1007-3 assume !(0 == ~E_9~0); 1405328#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1405323#L443-30 assume !(1 == ~m_pc~0); 1405317#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1405310#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1405304#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1405297#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1405291#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1405285#L462-30 assume !(1 == ~t1_pc~0); 1405279#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1405274#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1405268#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1405261#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1405253#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1405246#L481-30 assume 1 == ~t2_pc~0; 1405239#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1405232#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1405225#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1405218#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1405212#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1405207#L500-30 assume !(1 == ~t3_pc~0); 1405201#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1405196#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1405190#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1405183#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1405176#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1405169#L519-30 assume !(1 == ~t4_pc~0); 1405163#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1405156#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1405150#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1405145#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1405139#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1405134#L538-30 assume !(1 == ~t5_pc~0); 1405127#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1405118#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1405108#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1405100#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1405092#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1405086#L557-30 assume !(1 == ~t6_pc~0); 1405080#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1405074#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1405067#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1405061#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1405054#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1405031#L576-30 assume !(1 == ~t7_pc~0); 1405027#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1405024#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1405022#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1405020#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1405017#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1405015#L595-30 assume !(1 == ~t8_pc~0); 1405013#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1405011#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1405009#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1405007#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1405005#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1405003#L614-30 assume !(1 == ~t9_pc~0); 1405001#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1405000#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1404998#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1404996#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1404988#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1404845#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1404804#L1025-5 assume !(1 == ~T1_E~0); 1404795#L1030-3 assume !(1 == ~T2_E~0); 1404779#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1404768#L1040-3 assume !(1 == ~T4_E~0); 1404760#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1404752#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1404739#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1404697#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1404694#L1065-3 assume !(1 == ~T9_E~0); 1404692#L1070-3 assume !(1 == ~E_1~0); 1404690#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1404688#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1404686#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1404684#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1404682#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1404680#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1404678#L1105-3 assume !(1 == ~E_8~0); 1404675#L1110-3 assume !(1 == ~E_9~0); 1404673#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1404558#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1404547#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1404545#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1404541#L1415 assume !(0 == start_simulation_~tmp~3#1); 1404540#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1404536#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1404528#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1404401#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1404375#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1404356#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1404347#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1404346#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1389820#L1396-2 [2024-11-09 16:09:51,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:51,159 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 6 times [2024-11-09 16:09:51,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:51,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263684199] [2024-11-09 16:09:51,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:51,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:51,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:51,171 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:51,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:51,195 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:51,195 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:51,196 INFO L85 PathProgramCache]: Analyzing trace with hash -844943221, now seen corresponding path program 1 times [2024-11-09 16:09:51,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:51,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730663741] [2024-11-09 16:09:51,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:51,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:51,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:51,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:51,255 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:51,255 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [730663741] [2024-11-09 16:09:51,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [730663741] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:51,255 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:51,255 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:51,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088866364] [2024-11-09 16:09:51,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:51,256 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:51,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:51,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:51,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:51,256 INFO L87 Difference]: Start difference. First operand 37606 states and 51672 transitions. cyclomatic complexity: 14098 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:51,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:51,503 INFO L93 Difference]: Finished difference Result 38761 states and 52827 transitions. [2024-11-09 16:09:51,503 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38761 states and 52827 transitions. [2024-11-09 16:09:51,641 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38432 [2024-11-09 16:09:51,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38761 states to 38761 states and 52827 transitions. [2024-11-09 16:09:51,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38761 [2024-11-09 16:09:51,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38761 [2024-11-09 16:09:51,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38761 states and 52827 transitions. [2024-11-09 16:09:51,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:51,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38761 states and 52827 transitions. [2024-11-09 16:09:51,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38761 states and 52827 transitions. [2024-11-09 16:09:52,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38761 to 38761. [2024-11-09 16:09:52,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38761 states, 38761 states have (on average 1.3628905342999407) internal successors, (52827), 38760 states have internal predecessors, (52827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:52,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38761 states to 38761 states and 52827 transitions. [2024-11-09 16:09:52,514 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38761 states and 52827 transitions. [2024-11-09 16:09:52,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:52,514 INFO L425 stractBuchiCegarLoop]: Abstraction has 38761 states and 52827 transitions. [2024-11-09 16:09:52,515 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-09 16:09:52,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38761 states and 52827 transitions. [2024-11-09 16:09:52,600 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38432 [2024-11-09 16:09:52,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:52,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:52,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:52,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:52,602 INFO L745 eck$LassoCheckResult]: Stem: 1465963#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1465964#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1466832#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1466833#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1466766#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1466767#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1466737#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1466514#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1466515#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1466301#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1466302#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1466865#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1466725#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1466372#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1466119#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1466120#L922 assume !(0 == ~M_E~0); 1466937#L922-2 assume !(0 == ~T1_E~0); 1466938#L927-1 assume !(0 == ~T2_E~0); 1466591#L932-1 assume !(0 == ~T3_E~0); 1466450#L937-1 assume !(0 == ~T4_E~0); 1466451#L942-1 assume !(0 == ~T5_E~0); 1466513#L947-1 assume !(0 == ~T6_E~0); 1466596#L952-1 assume !(0 == ~T7_E~0); 1466597#L957-1 assume !(0 == ~T8_E~0); 1466669#L962-1 assume !(0 == ~T9_E~0); 1466428#L967-1 assume !(0 == ~E_1~0); 1466429#L972-1 assume !(0 == ~E_2~0); 1466745#L977-1 assume !(0 == ~E_3~0); 1466746#L982-1 assume !(0 == ~E_4~0); 1465897#L987-1 assume !(0 == ~E_5~0); 1465898#L992-1 assume !(0 == ~E_6~0); 1465902#L997-1 assume !(0 == ~E_7~0); 1466348#L1002-1 assume !(0 == ~E_8~0); 1466333#L1007-1 assume !(0 == ~E_9~0); 1465689#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1465690#L443 assume !(1 == ~m_pc~0); 1466614#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1466604#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1466605#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1466055#L1140 assume !(0 != activate_threads_~tmp~1#1); 1465794#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1465795#L462 assume !(1 == ~t1_pc~0); 1466443#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1466444#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1465732#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1465733#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1466279#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1466280#L481 assume !(1 == ~t2_pc~0); 1466049#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1466811#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1466962#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1466960#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1466143#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1466248#L500 assume !(1 == ~t3_pc~0); 1466823#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1466786#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1465696#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1465697#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1465694#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1465695#L519 assume !(1 == ~t4_pc~0); 1466503#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1466245#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1465796#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1465797#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1466096#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1465858#L538 assume !(1 == ~t5_pc~0); 1465859#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1465757#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1465758#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1466035#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1466036#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1466652#L557 assume !(1 == ~t6_pc~0); 1466069#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1466070#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1466161#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1466094#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1466095#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1466911#L576 assume !(1 == ~t7_pc~0); 1466059#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1466060#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1466412#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1466932#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1466715#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1466184#L595 assume !(1 == ~t8_pc~0); 1466185#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1466733#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1466657#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1466542#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1466543#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1465985#L614 assume !(1 == ~t9_pc~0); 1465986#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1465884#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1465885#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1466221#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1466145#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1466146#L1025 assume !(1 == ~M_E~0); 1466434#L1025-2 assume !(1 == ~T1_E~0); 1466496#L1030-1 assume !(1 == ~T2_E~0); 1466642#L1035-1 assume !(1 == ~T3_E~0); 1466138#L1040-1 assume !(1 == ~T4_E~0); 1466139#L1045-1 assume !(1 == ~T5_E~0); 1466045#L1050-1 assume !(1 == ~T6_E~0); 1466046#L1055-1 assume !(1 == ~T7_E~0); 1465869#L1060-1 assume !(1 == ~T8_E~0); 1465870#L1065-1 assume !(1 == ~T9_E~0); 1465934#L1070-1 assume !(1 == ~E_1~0); 1466599#L1075-1 assume !(1 == ~E_2~0); 1466600#L1080-1 assume !(1 == ~E_3~0); 1466585#L1085-1 assume !(1 == ~E_4~0); 1466586#L1090-1 assume !(1 == ~E_5~0); 1466855#L1095-1 assume !(1 == ~E_6~0); 1466627#L1100-1 assume !(1 == ~E_7~0); 1466628#L1105-1 assume !(1 == ~E_8~0); 1465840#L1110-1 assume !(1 == ~E_9~0); 1465841#L1115-1 assume { :end_inline_reset_delta_events } true; 1466193#L1396-2 [2024-11-09 16:09:52,602 INFO L747 eck$LassoCheckResult]: Loop: 1466193#L1396-2 assume !false; 1470136#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1470130#L897-1 assume !false; 1470127#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1470113#L699 assume !(0 == ~m_st~0); 1470105#L703 assume !(0 == ~t1_st~0); 1470106#L707 assume !(0 == ~t2_st~0); 1470110#L711 assume !(0 == ~t3_st~0); 1470103#L715 assume !(0 == ~t4_st~0); 1470104#L719 assume !(0 == ~t5_st~0); 1470109#L723 assume !(0 == ~t6_st~0); 1470112#L727 assume !(0 == ~t7_st~0); 1470107#L731 assume !(0 == ~t8_st~0); 1470108#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1470111#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1472089#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1472087#L766 assume !(0 != eval_~tmp~0#1); 1472085#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1472081#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1472079#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1472077#L922-5 assume !(0 == ~T1_E~0); 1472075#L927-3 assume !(0 == ~T2_E~0); 1472072#L932-3 assume !(0 == ~T3_E~0); 1472070#L937-3 assume !(0 == ~T4_E~0); 1472068#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1472066#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1472064#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1472062#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1472060#L962-3 assume !(0 == ~T9_E~0); 1472058#L967-3 assume !(0 == ~E_1~0); 1472056#L972-3 assume !(0 == ~E_2~0); 1472053#L977-3 assume !(0 == ~E_3~0); 1471990#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1471979#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1471965#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1471953#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1471947#L1002-3 assume !(0 == ~E_8~0); 1471945#L1007-3 assume !(0 == ~E_9~0); 1471943#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1471324#L443-30 assume 1 == ~m_pc~0; 1471322#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1471323#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1471726#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1471312#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1471310#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1471308#L462-30 assume !(1 == ~t1_pc~0); 1471306#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1471304#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1471303#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1471302#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1471299#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1471297#L481-30 assume 1 == ~t2_pc~0; 1471295#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1471296#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1471042#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1470890#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1470880#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1470870#L500-30 assume !(1 == ~t3_pc~0); 1470860#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1470852#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1470843#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1470835#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1470830#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1470823#L519-30 assume !(1 == ~t4_pc~0); 1470762#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1470755#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1470748#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1470636#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1470632#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1470630#L538-30 assume !(1 == ~t5_pc~0); 1470628#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1470637#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1470593#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1470582#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1470572#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1470564#L557-30 assume !(1 == ~t6_pc~0); 1470558#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1470553#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1470550#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1470549#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1470535#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1470532#L576-30 assume !(1 == ~t7_pc~0); 1470530#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1470527#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1470525#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1470523#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1470521#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1470518#L595-30 assume !(1 == ~t8_pc~0); 1470514#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1470510#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1470506#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1470502#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1470499#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1470496#L614-30 assume !(1 == ~t9_pc~0); 1470492#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1470489#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1470485#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1470481#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1470477#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1470473#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1470469#L1025-5 assume !(1 == ~T1_E~0); 1470465#L1030-3 assume !(1 == ~T2_E~0); 1470460#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1470456#L1040-3 assume !(1 == ~T4_E~0); 1470453#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1470450#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1470447#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1470444#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1470440#L1065-3 assume !(1 == ~T9_E~0); 1470437#L1070-3 assume !(1 == ~E_1~0); 1470434#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1470431#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1470428#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1470425#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1470422#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1470418#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1470414#L1105-3 assume !(1 == ~E_8~0); 1470410#L1110-3 assume !(1 == ~E_9~0); 1470405#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1470246#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1470230#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1470225#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1470219#L1415 assume !(0 == start_simulation_~tmp~3#1); 1470214#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1470205#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1470192#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1470185#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1470181#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1470174#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1470161#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1470151#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1466193#L1396-2 [2024-11-09 16:09:52,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:52,602 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 7 times [2024-11-09 16:09:52,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:52,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1630250666] [2024-11-09 16:09:52,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:52,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:52,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:52,611 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:52,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:52,633 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:52,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:52,638 INFO L85 PathProgramCache]: Analyzing trace with hash 781586540, now seen corresponding path program 1 times [2024-11-09 16:09:52,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:52,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592360944] [2024-11-09 16:09:52,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:52,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:52,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:52,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:52,688 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:52,689 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592360944] [2024-11-09 16:09:52,689 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592360944] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:52,689 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:52,689 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:52,689 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191527795] [2024-11-09 16:09:52,689 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:52,689 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:52,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:52,690 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:52,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:52,690 INFO L87 Difference]: Start difference. First operand 38761 states and 52827 transitions. cyclomatic complexity: 14098 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:52,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:52,901 INFO L93 Difference]: Finished difference Result 38833 states and 52538 transitions. [2024-11-09 16:09:52,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38833 states and 52538 transitions. [2024-11-09 16:09:53,026 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38504 [2024-11-09 16:09:53,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38833 states to 38833 states and 52538 transitions. [2024-11-09 16:09:53,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38833 [2024-11-09 16:09:53,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38833 [2024-11-09 16:09:53,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38833 states and 52538 transitions. [2024-11-09 16:09:53,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:53,158 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38833 states and 52538 transitions. [2024-11-09 16:09:53,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38833 states and 52538 transitions. [2024-11-09 16:09:53,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38833 to 38833. [2024-11-09 16:09:53,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38833 states, 38833 states have (on average 1.3529214843045863) internal successors, (52538), 38832 states have internal predecessors, (52538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:53,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38833 states to 38833 states and 52538 transitions. [2024-11-09 16:09:53,478 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38833 states and 52538 transitions. [2024-11-09 16:09:53,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:53,478 INFO L425 stractBuchiCegarLoop]: Abstraction has 38833 states and 52538 transitions. [2024-11-09 16:09:53,478 INFO L332 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-09 16:09:53,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38833 states and 52538 transitions. [2024-11-09 16:09:53,570 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38504 [2024-11-09 16:09:53,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:53,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:53,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:53,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:53,571 INFO L745 eck$LassoCheckResult]: Stem: 1543565#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1543566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1544431#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1544432#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1544367#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1544368#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1544338#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1544107#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1544108#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1543901#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1543902#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1544466#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1544323#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1543966#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1543719#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1543720#L922 assume !(0 == ~M_E~0); 1544523#L922-2 assume !(0 == ~T1_E~0); 1544524#L927-1 assume !(0 == ~T2_E~0); 1544184#L932-1 assume !(0 == ~T3_E~0); 1544043#L937-1 assume !(0 == ~T4_E~0); 1544044#L942-1 assume !(0 == ~T5_E~0); 1544106#L947-1 assume !(0 == ~T6_E~0); 1544189#L952-1 assume !(0 == ~T7_E~0); 1544190#L957-1 assume !(0 == ~T8_E~0); 1544266#L962-1 assume !(0 == ~T9_E~0); 1544022#L967-1 assume !(0 == ~E_1~0); 1544023#L972-1 assume !(0 == ~E_2~0); 1544350#L977-1 assume !(0 == ~E_3~0); 1544351#L982-1 assume !(0 == ~E_4~0); 1543499#L987-1 assume !(0 == ~E_5~0); 1543500#L992-1 assume !(0 == ~E_6~0); 1543504#L997-1 assume !(0 == ~E_7~0); 1543943#L1002-1 assume !(0 == ~E_8~0); 1543928#L1007-1 assume !(0 == ~E_9~0); 1543291#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1543292#L443 assume !(1 == ~m_pc~0); 1544208#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1544198#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1544199#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1543656#L1140 assume !(0 != activate_threads_~tmp~1#1); 1543396#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1543397#L462 assume !(1 == ~t1_pc~0); 1544037#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1544038#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1543334#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1543335#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1543879#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1543880#L481 assume !(1 == ~t2_pc~0); 1543649#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1544409#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1544556#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1544554#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1543742#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1543850#L500 assume !(1 == ~t3_pc~0); 1544421#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1544387#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1543298#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1543299#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1543296#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1543297#L519 assume !(1 == ~t4_pc~0); 1544097#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1543847#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1543398#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1543399#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1543696#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1543460#L538 assume !(1 == ~t5_pc~0); 1543461#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1543359#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1543360#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1543635#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1543636#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1544248#L557 assume !(1 == ~t6_pc~0); 1543670#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1543671#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1543760#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1543694#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1543695#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1544498#L576 assume !(1 == ~t7_pc~0); 1543660#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1543661#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1544006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1544520#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1544312#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1543784#L595 assume !(1 == ~t8_pc~0); 1543785#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1544335#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1544253#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1544136#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1544137#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1543587#L614 assume !(1 == ~t9_pc~0); 1543588#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1543486#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1543487#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1543823#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1543744#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1543745#L1025 assume !(1 == ~M_E~0); 1544028#L1025-2 assume !(1 == ~T1_E~0); 1544089#L1030-1 assume !(1 == ~T2_E~0); 1544239#L1035-1 assume !(1 == ~T3_E~0); 1543737#L1040-1 assume !(1 == ~T4_E~0); 1543738#L1045-1 assume !(1 == ~T5_E~0); 1543645#L1050-1 assume !(1 == ~T6_E~0); 1543646#L1055-1 assume !(1 == ~T7_E~0); 1543471#L1060-1 assume !(1 == ~T8_E~0); 1543472#L1065-1 assume !(1 == ~T9_E~0); 1543536#L1070-1 assume !(1 == ~E_1~0); 1544193#L1075-1 assume !(1 == ~E_2~0); 1544194#L1080-1 assume !(1 == ~E_3~0); 1544178#L1085-1 assume !(1 == ~E_4~0); 1544179#L1090-1 assume !(1 == ~E_5~0); 1544457#L1095-1 assume !(1 == ~E_6~0); 1544219#L1100-1 assume !(1 == ~E_7~0); 1544220#L1105-1 assume !(1 == ~E_8~0); 1543442#L1110-1 assume !(1 == ~E_9~0); 1543443#L1115-1 assume { :end_inline_reset_delta_events } true; 1543792#L1396-2 [2024-11-09 16:09:53,572 INFO L747 eck$LassoCheckResult]: Loop: 1543792#L1396-2 assume !false; 1546441#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1546437#L897-1 assume !false; 1546436#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1546435#L699 assume !(0 == ~m_st~0); 1546428#L703 assume !(0 == ~t1_st~0); 1546429#L707 assume !(0 == ~t2_st~0); 1546433#L711 assume !(0 == ~t3_st~0); 1546425#L715 assume !(0 == ~t4_st~0); 1546427#L719 assume !(0 == ~t5_st~0); 1546432#L723 assume !(0 == ~t6_st~0); 1546434#L727 assume !(0 == ~t7_st~0); 1546430#L731 assume !(0 == ~t8_st~0); 1546431#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1546423#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1546366#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1546367#L766 assume !(0 != eval_~tmp~0#1); 1546991#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1546989#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1546987#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1546985#L922-5 assume !(0 == ~T1_E~0); 1546983#L927-3 assume !(0 == ~T2_E~0); 1546981#L932-3 assume !(0 == ~T3_E~0); 1546977#L937-3 assume !(0 == ~T4_E~0); 1546975#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1546973#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1546971#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1546968#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1546966#L962-3 assume !(0 == ~T9_E~0); 1546964#L967-3 assume !(0 == ~E_1~0); 1546962#L972-3 assume !(0 == ~E_2~0); 1546960#L977-3 assume !(0 == ~E_3~0); 1546958#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1546956#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1546954#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1546952#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1546951#L1002-3 assume !(0 == ~E_8~0); 1546948#L1007-3 assume !(0 == ~E_9~0); 1546946#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1546944#L443-30 assume 1 == ~m_pc~0; 1546942#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1546943#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1547017#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1546933#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1546931#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1546929#L462-30 assume !(1 == ~t1_pc~0); 1546927#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1546925#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1546922#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1546920#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 1546918#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1546916#L481-30 assume 1 == ~t2_pc~0; 1546914#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1546915#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1547035#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1546909#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1546906#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1546904#L500-30 assume !(1 == ~t3_pc~0); 1546902#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1546899#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1546897#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1546895#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1546893#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1546891#L519-30 assume !(1 == ~t4_pc~0); 1546889#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1546887#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1546885#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1546883#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1546881#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1546879#L538-30 assume 1 == ~t5_pc~0; 1546877#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1546878#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1547031#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1546867#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1546865#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1546863#L557-30 assume !(1 == ~t6_pc~0); 1546862#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1546861#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1546860#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1546859#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1546855#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1546853#L576-30 assume !(1 == ~t7_pc~0); 1546851#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1546848#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1546798#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1546790#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1546768#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1546759#L595-30 assume !(1 == ~t8_pc~0); 1546749#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1546738#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1546728#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1546718#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1546709#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1546694#L614-30 assume !(1 == ~t9_pc~0); 1546691#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1546689#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1546687#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1546685#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1546683#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1546681#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1546677#L1025-5 assume !(1 == ~T1_E~0); 1546645#L1030-3 assume !(1 == ~T2_E~0); 1546640#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1546636#L1040-3 assume !(1 == ~T4_E~0); 1546631#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1546627#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1546623#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1546619#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1546615#L1065-3 assume !(1 == ~T9_E~0); 1546611#L1070-3 assume !(1 == ~E_1~0); 1546606#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1546602#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1546598#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1546594#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1546590#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1546585#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1546580#L1105-3 assume !(1 == ~E_8~0); 1546575#L1110-3 assume !(1 == ~E_9~0); 1546570#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1546528#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1546515#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1546510#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1546504#L1415 assume !(0 == start_simulation_~tmp~3#1); 1546501#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1546492#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1546481#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1546478#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1546472#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1546466#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1546459#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1546452#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1543792#L1396-2 [2024-11-09 16:09:53,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:53,572 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 8 times [2024-11-09 16:09:53,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:53,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [847871856] [2024-11-09 16:09:53,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:53,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:53,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:53,580 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:53,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:53,602 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:53,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:53,603 INFO L85 PathProgramCache]: Analyzing trace with hash 94889485, now seen corresponding path program 1 times [2024-11-09 16:09:53,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:53,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588779433] [2024-11-09 16:09:53,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:53,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:53,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:53,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:53,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:53,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588779433] [2024-11-09 16:09:53,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588779433] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:53,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:53,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:53,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1156226922] [2024-11-09 16:09:53,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:53,912 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:53,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:53,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:53,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:53,913 INFO L87 Difference]: Start difference. First operand 38833 states and 52538 transitions. cyclomatic complexity: 13737 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:54,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:54,157 INFO L93 Difference]: Finished difference Result 39445 states and 52969 transitions. [2024-11-09 16:09:54,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39445 states and 52969 transitions. [2024-11-09 16:09:54,283 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 39116 [2024-11-09 16:09:54,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39445 states to 39445 states and 52969 transitions. [2024-11-09 16:09:54,365 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39445 [2024-11-09 16:09:54,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39445 [2024-11-09 16:09:54,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39445 states and 52969 transitions. [2024-11-09 16:09:54,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:54,415 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39445 states and 52969 transitions. [2024-11-09 16:09:54,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39445 states and 52969 transitions. [2024-11-09 16:09:54,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39445 to 39445. [2024-11-09 16:09:54,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39445 states, 39445 states have (on average 1.3428571428571427) internal successors, (52969), 39444 states have internal predecessors, (52969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:54,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39445 states to 39445 states and 52969 transitions. [2024-11-09 16:09:54,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39445 states and 52969 transitions. [2024-11-09 16:09:54,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:54,760 INFO L425 stractBuchiCegarLoop]: Abstraction has 39445 states and 52969 transitions. [2024-11-09 16:09:54,760 INFO L332 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-11-09 16:09:54,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39445 states and 52969 transitions. [2024-11-09 16:09:54,852 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 39116 [2024-11-09 16:09:54,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:54,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:54,853 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:54,853 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:54,853 INFO L745 eck$LassoCheckResult]: Stem: 1621851#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1621852#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1622700#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1622701#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1622635#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1622636#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1622611#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1622395#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1622396#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1622181#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1622182#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1622732#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1622596#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1622251#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1622006#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1622007#L922 assume !(0 == ~M_E~0); 1622794#L922-2 assume !(0 == ~T1_E~0); 1622795#L927-1 assume !(0 == ~T2_E~0); 1622466#L932-1 assume !(0 == ~T3_E~0); 1622329#L937-1 assume !(0 == ~T4_E~0); 1622330#L942-1 assume !(0 == ~T5_E~0); 1622394#L947-1 assume !(0 == ~T6_E~0); 1622470#L952-1 assume !(0 == ~T7_E~0); 1622471#L957-1 assume !(0 == ~T8_E~0); 1622541#L962-1 assume !(0 == ~T9_E~0); 1622305#L967-1 assume !(0 == ~E_1~0); 1622306#L972-1 assume !(0 == ~E_2~0); 1622616#L977-1 assume !(0 == ~E_3~0); 1622617#L982-1 assume !(0 == ~E_4~0); 1621783#L987-1 assume !(0 == ~E_5~0); 1621784#L992-1 assume !(0 == ~E_6~0); 1621790#L997-1 assume !(0 == ~E_7~0); 1622226#L1002-1 assume !(0 == ~E_8~0); 1622211#L1007-1 assume !(0 == ~E_9~0); 1621577#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1621578#L443 assume !(1 == ~m_pc~0); 1622489#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1622479#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1622480#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1621943#L1140 assume !(0 != activate_threads_~tmp~1#1); 1621682#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1621683#L462 assume !(1 == ~t1_pc~0); 1622319#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1622320#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1621618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1621619#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1622160#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1622161#L481 assume !(1 == ~t2_pc~0); 1621937#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1622676#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1622809#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1622808#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1622029#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1622130#L500 assume !(1 == ~t3_pc~0); 1622689#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1622653#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1621584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1621585#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1621579#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1621580#L519 assume !(1 == ~t4_pc~0); 1622382#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1622129#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1621684#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1621685#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1621979#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1621746#L538 assume !(1 == ~t5_pc~0); 1621747#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1621643#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1621644#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1621923#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1621924#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1622524#L557 assume !(1 == ~t6_pc~0); 1621958#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1621959#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1622047#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1621980#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1621981#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1622772#L576 assume !(1 == ~t7_pc~0); 1621947#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1621948#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1622292#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1622790#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1622587#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1622070#L595 assume !(1 == ~t8_pc~0); 1622071#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1622607#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1622529#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1622420#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1622421#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1621875#L614 assume !(1 == ~t9_pc~0); 1621876#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1621771#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1621772#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1622105#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1622031#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1622032#L1025 assume !(1 == ~M_E~0); 1622314#L1025-2 assume !(1 == ~T1_E~0); 1622375#L1030-1 assume !(1 == ~T2_E~0); 1622517#L1035-1 assume !(1 == ~T3_E~0); 1622023#L1040-1 assume !(1 == ~T4_E~0); 1622024#L1045-1 assume !(1 == ~T5_E~0); 1621933#L1050-1 assume !(1 == ~T6_E~0); 1621934#L1055-1 assume !(1 == ~T7_E~0); 1621757#L1060-1 assume !(1 == ~T8_E~0); 1621758#L1065-1 assume !(1 == ~T9_E~0); 1621823#L1070-1 assume !(1 == ~E_1~0); 1622472#L1075-1 assume !(1 == ~E_2~0); 1622473#L1080-1 assume !(1 == ~E_3~0); 1622460#L1085-1 assume !(1 == ~E_4~0); 1622461#L1090-1 assume !(1 == ~E_5~0); 1622724#L1095-1 assume !(1 == ~E_6~0); 1622500#L1100-1 assume !(1 == ~E_7~0); 1622501#L1105-1 assume !(1 == ~E_8~0); 1621728#L1110-1 assume !(1 == ~E_9~0); 1621729#L1115-1 assume { :end_inline_reset_delta_events } true; 1622079#L1396-2 [2024-11-09 16:09:54,853 INFO L747 eck$LassoCheckResult]: Loop: 1622079#L1396-2 assume !false; 1628994#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1628988#L897-1 assume !false; 1628986#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1628872#L699 assume !(0 == ~m_st~0); 1628864#L703 assume !(0 == ~t1_st~0); 1628865#L707 assume !(0 == ~t2_st~0); 1628869#L711 assume !(0 == ~t3_st~0); 1628862#L715 assume !(0 == ~t4_st~0); 1628863#L719 assume !(0 == ~t5_st~0); 1628868#L723 assume !(0 == ~t6_st~0); 1628871#L727 assume !(0 == ~t7_st~0); 1628866#L731 assume !(0 == ~t8_st~0); 1628867#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1628870#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1626069#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1626070#L766 assume !(0 != eval_~tmp~0#1); 1629498#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1629491#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1629485#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1629476#L922-5 assume !(0 == ~T1_E~0); 1629468#L927-3 assume !(0 == ~T2_E~0); 1629460#L932-3 assume !(0 == ~T3_E~0); 1629452#L937-3 assume !(0 == ~T4_E~0); 1629443#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1629437#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1629432#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1629425#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1629418#L962-3 assume !(0 == ~T9_E~0); 1629412#L967-3 assume !(0 == ~E_1~0); 1629411#L972-3 assume !(0 == ~E_2~0); 1629410#L977-3 assume !(0 == ~E_3~0); 1629408#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1629407#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1629406#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1629404#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1629402#L1002-3 assume !(0 == ~E_8~0); 1629401#L1007-3 assume !(0 == ~E_9~0); 1629400#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1629399#L443-30 assume !(1 == ~m_pc~0); 1629395#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1629394#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1629393#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1629391#L1140-30 assume !(0 != activate_threads_~tmp~1#1); 1629389#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1629388#L462-30 assume !(1 == ~t1_pc~0); 1629387#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1629383#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1629381#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1629379#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 1629377#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1629374#L481-30 assume 1 == ~t2_pc~0; 1629371#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1629369#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1629367#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1629365#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1629362#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1629360#L500-30 assume !(1 == ~t3_pc~0); 1629358#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1629357#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1629353#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1629351#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 1629349#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1629347#L519-30 assume !(1 == ~t4_pc~0); 1629344#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1629342#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1629340#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1629338#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1629336#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1629334#L538-30 assume 1 == ~t5_pc~0; 1629331#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1629329#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1629327#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1629299#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1629297#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1629295#L557-30 assume !(1 == ~t6_pc~0); 1629293#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1629291#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1629289#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1629287#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1629285#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1629283#L576-30 assume 1 == ~t7_pc~0; 1629280#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1629278#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1629276#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1629274#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1629272#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1629270#L595-30 assume !(1 == ~t8_pc~0); 1629268#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1629266#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1629264#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1629262#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1629260#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1629259#L614-30 assume !(1 == ~t9_pc~0); 1629254#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1629252#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1629250#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1629249#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1629246#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1629245#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1629244#L1025-5 assume !(1 == ~T1_E~0); 1629241#L1030-3 assume !(1 == ~T2_E~0); 1629238#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1629235#L1040-3 assume !(1 == ~T4_E~0); 1629232#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1629230#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1629228#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1629222#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1629217#L1065-3 assume !(1 == ~T9_E~0); 1629212#L1070-3 assume !(1 == ~E_1~0); 1629206#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1629201#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1629196#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1629191#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1629186#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1629181#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1629175#L1105-3 assume !(1 == ~E_8~0); 1629169#L1110-3 assume !(1 == ~E_9~0); 1629164#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1629115#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1629101#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1629093#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1629086#L1415 assume !(0 == start_simulation_~tmp~3#1); 1629081#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1629061#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1629046#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1629039#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1629031#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1629025#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1629018#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1629009#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1622079#L1396-2 [2024-11-09 16:09:54,854 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:54,854 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 9 times [2024-11-09 16:09:54,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:54,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [110816705] [2024-11-09 16:09:54,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:54,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:54,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:54,862 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:54,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:54,882 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:54,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:54,883 INFO L85 PathProgramCache]: Analyzing trace with hash 1112460873, now seen corresponding path program 1 times [2024-11-09 16:09:54,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:54,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [922745665] [2024-11-09 16:09:54,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:54,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:54,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:54,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:54,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:54,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [922745665] [2024-11-09 16:09:54,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [922745665] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:54,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:54,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:09:54,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84933628] [2024-11-09 16:09:54,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:54,908 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:54,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:54,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:09:54,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:09:54,908 INFO L87 Difference]: Start difference. First operand 39445 states and 52969 transitions. cyclomatic complexity: 13556 Second operand has 3 states, 3 states have (on average 43.666666666666664) internal successors, (131), 3 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:55,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:55,080 INFO L93 Difference]: Finished difference Result 75401 states and 100229 transitions. [2024-11-09 16:09:55,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75401 states and 100229 transitions. [2024-11-09 16:09:55,585 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 74872 [2024-11-09 16:09:55,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75401 states to 75401 states and 100229 transitions. [2024-11-09 16:09:55,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75401 [2024-11-09 16:09:55,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75401 [2024-11-09 16:09:55,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75401 states and 100229 transitions. [2024-11-09 16:09:55,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:55,870 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75401 states and 100229 transitions. [2024-11-09 16:09:55,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75401 states and 100229 transitions. [2024-11-09 16:09:56,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75401 to 71865. [2024-11-09 16:09:56,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71865 states, 71865 states have (on average 1.332122730118973) internal successors, (95733), 71864 states have internal predecessors, (95733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:56,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71865 states to 71865 states and 95733 transitions. [2024-11-09 16:09:56,680 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71865 states and 95733 transitions. [2024-11-09 16:09:56,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:09:56,681 INFO L425 stractBuchiCegarLoop]: Abstraction has 71865 states and 95733 transitions. [2024-11-09 16:09:56,681 INFO L332 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2024-11-09 16:09:56,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71865 states and 95733 transitions. [2024-11-09 16:09:57,104 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71336 [2024-11-09 16:09:57,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:57,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:57,105 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:57,105 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:57,106 INFO L745 eck$LassoCheckResult]: Stem: 1736704#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1736705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1737578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1737579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1737513#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1737514#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1737488#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1737261#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1737262#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1737047#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1737048#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1737612#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1737472#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1737112#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1736864#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1736865#L922 assume !(0 == ~M_E~0); 1737692#L922-2 assume !(0 == ~T1_E~0); 1737693#L927-1 assume !(0 == ~T2_E~0); 1737335#L932-1 assume !(0 == ~T3_E~0); 1737191#L937-1 assume !(0 == ~T4_E~0); 1737192#L942-1 assume !(0 == ~T5_E~0); 1737260#L947-1 assume !(0 == ~T6_E~0); 1737339#L952-1 assume !(0 == ~T7_E~0); 1737340#L957-1 assume !(0 == ~T8_E~0); 1737415#L962-1 assume !(0 == ~T9_E~0); 1737169#L967-1 assume !(0 == ~E_1~0); 1737170#L972-1 assume !(0 == ~E_2~0); 1737494#L977-1 assume !(0 == ~E_3~0); 1737495#L982-1 assume !(0 == ~E_4~0); 1736636#L987-1 assume !(0 == ~E_5~0); 1736637#L992-1 assume !(0 == ~E_6~0); 1736641#L997-1 assume !(0 == ~E_7~0); 1737088#L1002-1 assume !(0 == ~E_8~0); 1737075#L1007-1 assume !(0 == ~E_9~0); 1736429#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1736430#L443 assume !(1 == ~m_pc~0); 1737358#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1737349#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1737350#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1736799#L1140 assume !(0 != activate_threads_~tmp~1#1); 1736534#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1736535#L462 assume !(1 == ~t1_pc~0); 1737185#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1737186#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1736472#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1736473#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1737024#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1737025#L481 assume !(1 == ~t2_pc~0); 1736792#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1737555#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1737720#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1737718#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1736888#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1736994#L500 assume !(1 == ~t3_pc~0); 1737568#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1737533#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1736436#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1736437#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1736434#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1736435#L519 assume !(1 == ~t4_pc~0); 1737246#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1736991#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1736536#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1736537#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1736839#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1736598#L538 assume !(1 == ~t5_pc~0); 1736599#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1736497#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1736498#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1736778#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1736779#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1737398#L557 assume !(1 == ~t6_pc~0); 1736814#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1736815#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1736906#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1736837#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1736838#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1737663#L576 assume !(1 == ~t7_pc~0); 1736803#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1736804#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1737152#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1737685#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1737463#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1736929#L595 assume !(1 == ~t8_pc~0); 1736930#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1737483#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1737403#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1737289#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1737290#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1736727#L614 assume !(1 == ~t9_pc~0); 1736728#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1736624#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1736625#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1736966#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1736890#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1736891#L1025 assume !(1 == ~M_E~0); 1737176#L1025-2 assume !(1 == ~T1_E~0); 1737238#L1030-1 assume !(1 == ~T2_E~0); 1737390#L1035-1 assume !(1 == ~T3_E~0); 1736883#L1040-1 assume !(1 == ~T4_E~0); 1736884#L1045-1 assume !(1 == ~T5_E~0); 1736788#L1050-1 assume !(1 == ~T6_E~0); 1736789#L1055-1 assume !(1 == ~T7_E~0); 1736609#L1060-1 assume !(1 == ~T8_E~0); 1736610#L1065-1 assume !(1 == ~T9_E~0); 1736674#L1070-1 assume !(1 == ~E_1~0); 1737342#L1075-1 assume !(1 == ~E_2~0); 1737343#L1080-1 assume !(1 == ~E_3~0); 1737329#L1085-1 assume !(1 == ~E_4~0); 1737330#L1090-1 assume !(1 == ~E_5~0); 1737601#L1095-1 assume !(1 == ~E_6~0); 1737371#L1100-1 assume !(1 == ~E_7~0); 1737372#L1105-1 assume !(1 == ~E_8~0); 1736580#L1110-1 assume !(1 == ~E_9~0); 1736581#L1115-1 assume { :end_inline_reset_delta_events } true; 1736938#L1396-2 [2024-11-09 16:09:57,106 INFO L747 eck$LassoCheckResult]: Loop: 1736938#L1396-2 assume !false; 1750039#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1750034#L897-1 assume !false; 1750032#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1750029#L699 assume !(0 == ~m_st~0); 1750030#L703 assume !(0 == ~t1_st~0); 1752907#L707 assume !(0 == ~t2_st~0); 1752906#L711 assume !(0 == ~t3_st~0); 1752905#L715 assume !(0 == ~t4_st~0); 1752903#L719 assume !(0 == ~t5_st~0); 1752902#L723 assume !(0 == ~t6_st~0); 1752901#L727 assume !(0 == ~t7_st~0); 1752900#L731 assume !(0 == ~t8_st~0); 1752898#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1752896#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1752893#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1752891#L766 assume !(0 != eval_~tmp~0#1); 1752889#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1752888#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1752887#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1752886#L922-5 assume !(0 == ~T1_E~0); 1752882#L927-3 assume !(0 == ~T2_E~0); 1752880#L932-3 assume !(0 == ~T3_E~0); 1752878#L937-3 assume !(0 == ~T4_E~0); 1752876#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1752875#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1752874#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1752872#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1752867#L962-3 assume !(0 == ~T9_E~0); 1752865#L967-3 assume !(0 == ~E_1~0); 1752862#L972-3 assume !(0 == ~E_2~0); 1752860#L977-3 assume !(0 == ~E_3~0); 1752858#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1752856#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1752854#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1752852#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1752848#L1002-3 assume !(0 == ~E_8~0); 1752846#L1007-3 assume !(0 == ~E_9~0); 1752844#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1752842#L443-30 assume 1 == ~m_pc~0; 1752838#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1752836#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1752834#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1752832#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1752815#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1752805#L462-30 assume !(1 == ~t1_pc~0); 1752799#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1752792#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1752785#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1752776#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 1752769#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1752763#L481-30 assume !(1 == ~t2_pc~0); 1752755#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1752747#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1752737#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1752727#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1752718#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1752708#L500-30 assume !(1 == ~t3_pc~0); 1752699#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1752691#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1752683#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1752674#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 1752666#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1752658#L519-30 assume !(1 == ~t4_pc~0); 1752650#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1752643#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1752635#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1752621#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1752615#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1752386#L538-30 assume !(1 == ~t5_pc~0); 1752382#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1752378#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1752376#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1752374#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1752371#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1752370#L557-30 assume !(1 == ~t6_pc~0); 1752367#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1752365#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1752363#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1752361#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1752359#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1752357#L576-30 assume 1 == ~t7_pc~0; 1752354#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1752350#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1752348#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1752346#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1752344#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1752341#L595-30 assume !(1 == ~t8_pc~0); 1752338#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1752336#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1752334#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1752332#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1752330#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1752155#L614-30 assume !(1 == ~t9_pc~0); 1752152#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1752150#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1752148#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1752146#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1752144#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1752142#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1752140#L1025-5 assume !(1 == ~T1_E~0); 1752137#L1030-3 assume !(1 == ~T2_E~0); 1752135#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1752133#L1040-3 assume !(1 == ~T4_E~0); 1752131#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1752129#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1752125#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1752121#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1752116#L1065-3 assume !(1 == ~T9_E~0); 1752112#L1070-3 assume !(1 == ~E_1~0); 1752110#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1752108#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1752106#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1752098#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1752088#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1752080#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1751871#L1105-3 assume !(1 == ~E_8~0); 1751761#L1110-3 assume !(1 == ~E_9~0); 1751751#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1751741#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1751732#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1751723#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1751712#L1415 assume !(0 == start_simulation_~tmp~3#1); 1751704#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1751693#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1751684#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1751677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1751669#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1751663#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1751658#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1751652#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1736938#L1396-2 [2024-11-09 16:09:57,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:57,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 10 times [2024-11-09 16:09:57,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:57,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400390990] [2024-11-09 16:09:57,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:57,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:57,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:57,113 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:57,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:57,142 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:57,143 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:57,143 INFO L85 PathProgramCache]: Analyzing trace with hash 631763046, now seen corresponding path program 1 times [2024-11-09 16:09:57,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:57,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484368908] [2024-11-09 16:09:57,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:57,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:57,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:57,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:57,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:57,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484368908] [2024-11-09 16:09:57,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1484368908] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:57,224 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:57,224 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:57,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948580569] [2024-11-09 16:09:57,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:57,224 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:57,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:57,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:57,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:57,225 INFO L87 Difference]: Start difference. First operand 71865 states and 95733 transitions. cyclomatic complexity: 23900 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:57,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:57,532 INFO L93 Difference]: Finished difference Result 73017 states and 96548 transitions. [2024-11-09 16:09:57,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73017 states and 96548 transitions. [2024-11-09 16:09:57,797 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72488 [2024-11-09 16:09:57,963 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73017 states to 73017 states and 96548 transitions. [2024-11-09 16:09:57,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73017 [2024-11-09 16:09:58,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73017 [2024-11-09 16:09:58,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73017 states and 96548 transitions. [2024-11-09 16:09:58,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:09:58,048 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73017 states and 96548 transitions. [2024-11-09 16:09:58,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73017 states and 96548 transitions. [2024-11-09 16:09:58,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73017 to 73017. [2024-11-09 16:09:58,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73017 states, 73017 states have (on average 1.3222674171768218) internal successors, (96548), 73016 states have internal predecessors, (96548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:59,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73017 states to 73017 states and 96548 transitions. [2024-11-09 16:09:59,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73017 states and 96548 transitions. [2024-11-09 16:09:59,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:09:59,045 INFO L425 stractBuchiCegarLoop]: Abstraction has 73017 states and 96548 transitions. [2024-11-09 16:09:59,045 INFO L332 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2024-11-09 16:09:59,045 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73017 states and 96548 transitions. [2024-11-09 16:09:59,219 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72488 [2024-11-09 16:09:59,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:09:59,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:09:59,221 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:59,221 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:09:59,221 INFO L745 eck$LassoCheckResult]: Stem: 1881595#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1881596#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1882483#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1882484#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1882412#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1882413#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1882385#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1882150#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1882151#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1881937#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1881938#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1882520#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1882370#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1882003#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1881752#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1881753#L922 assume !(0 == ~M_E~0); 1882606#L922-2 assume !(0 == ~T1_E~0); 1882607#L927-1 assume !(0 == ~T2_E~0); 1882226#L932-1 assume !(0 == ~T3_E~0); 1882081#L937-1 assume !(0 == ~T4_E~0); 1882082#L942-1 assume !(0 == ~T5_E~0); 1882149#L947-1 assume !(0 == ~T6_E~0); 1882232#L952-1 assume !(0 == ~T7_E~0); 1882233#L957-1 assume !(0 == ~T8_E~0); 1882315#L962-1 assume !(0 == ~T9_E~0); 1882058#L967-1 assume !(0 == ~E_1~0); 1882059#L972-1 assume !(0 == ~E_2~0); 1882394#L977-1 assume !(0 == ~E_3~0); 1882395#L982-1 assume !(0 == ~E_4~0); 1881528#L987-1 assume !(0 == ~E_5~0); 1881529#L992-1 assume !(0 == ~E_6~0); 1881533#L997-1 assume !(0 == ~E_7~0); 1881980#L1002-1 assume !(0 == ~E_8~0); 1881966#L1007-1 assume !(0 == ~E_9~0); 1881319#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1881320#L443 assume !(1 == ~m_pc~0); 1882251#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1882240#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1882241#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1881687#L1140 assume !(0 != activate_threads_~tmp~1#1); 1881424#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1881425#L462 assume !(1 == ~t1_pc~0); 1882075#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1882076#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1881362#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1881363#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1881914#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1881915#L481 assume !(1 == ~t2_pc~0); 1881680#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1882458#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1882631#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1882629#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1881775#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1881883#L500 assume !(1 == ~t3_pc~0); 1882471#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1882430#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1881326#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1881327#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1881324#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1881325#L519 assume !(1 == ~t4_pc~0); 1882139#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1881880#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1881426#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1881427#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1881727#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1881489#L538 assume !(1 == ~t5_pc~0); 1881490#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1881387#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1881388#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1881666#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1881667#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1882298#L557 assume !(1 == ~t6_pc~0); 1881701#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1881702#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1881793#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1881725#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1881726#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1882566#L576 assume !(1 == ~t7_pc~0); 1881691#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1881692#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1882043#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1882600#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1882361#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1881814#L595 assume !(1 == ~t8_pc~0); 1881815#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1882380#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1882303#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1882177#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1882178#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1881617#L614 assume !(1 == ~t9_pc~0); 1881618#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1881515#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1881516#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1881855#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1881777#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1881778#L1025 assume !(1 == ~M_E~0); 1882063#L1025-2 assume !(1 == ~T1_E~0); 1882132#L1030-1 assume !(1 == ~T2_E~0); 1882286#L1035-1 assume !(1 == ~T3_E~0); 1881770#L1040-1 assume !(1 == ~T4_E~0); 1881771#L1045-1 assume !(1 == ~T5_E~0); 1881676#L1050-1 assume !(1 == ~T6_E~0); 1881677#L1055-1 assume !(1 == ~T7_E~0); 1881500#L1060-1 assume !(1 == ~T8_E~0); 1881501#L1065-1 assume !(1 == ~T9_E~0); 1881566#L1070-1 assume !(1 == ~E_1~0); 1882235#L1075-1 assume !(1 == ~E_2~0); 1882236#L1080-1 assume !(1 == ~E_3~0); 1882220#L1085-1 assume !(1 == ~E_4~0); 1882221#L1090-1 assume !(1 == ~E_5~0); 1882509#L1095-1 assume !(1 == ~E_6~0); 1882265#L1100-1 assume !(1 == ~E_7~0); 1882266#L1105-1 assume !(1 == ~E_8~0); 1881471#L1110-1 assume !(1 == ~E_9~0); 1881472#L1115-1 assume { :end_inline_reset_delta_events } true; 1881824#L1396-2 [2024-11-09 16:09:59,221 INFO L747 eck$LassoCheckResult]: Loop: 1881824#L1396-2 assume !false; 1899104#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1899099#L897-1 assume !false; 1899097#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1899094#L699 assume !(0 == ~m_st~0); 1899095#L703 assume !(0 == ~t1_st~0); 1899657#L707 assume !(0 == ~t2_st~0); 1899655#L711 assume !(0 == ~t3_st~0); 1899653#L715 assume !(0 == ~t4_st~0); 1899650#L719 assume !(0 == ~t5_st~0); 1899648#L723 assume !(0 == ~t6_st~0); 1899646#L727 assume !(0 == ~t7_st~0); 1899644#L731 assume !(0 == ~t8_st~0); 1899641#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1899639#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1899637#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1899636#L766 assume !(0 != eval_~tmp~0#1); 1899634#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1899632#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1899631#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1899628#L922-5 assume !(0 == ~T1_E~0); 1899624#L927-3 assume !(0 == ~T2_E~0); 1899620#L932-3 assume !(0 == ~T3_E~0); 1899616#L937-3 assume !(0 == ~T4_E~0); 1899613#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1899610#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1899608#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1899605#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1899603#L962-3 assume !(0 == ~T9_E~0); 1899601#L967-3 assume !(0 == ~E_1~0); 1899598#L972-3 assume !(0 == ~E_2~0); 1899596#L977-3 assume !(0 == ~E_3~0); 1899594#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1899593#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1899592#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1899590#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1899588#L1002-3 assume !(0 == ~E_8~0); 1899587#L1007-3 assume !(0 == ~E_9~0); 1899586#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1899584#L443-30 assume 1 == ~m_pc~0; 1899580#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1899578#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1899576#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1899570#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1899568#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1899566#L462-30 assume !(1 == ~t1_pc~0); 1899564#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1899562#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1899560#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1899558#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 1899556#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1899554#L481-30 assume 1 == ~t2_pc~0; 1899550#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1899548#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1899546#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1899543#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1899540#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1899538#L500-30 assume !(1 == ~t3_pc~0); 1899536#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1899534#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1899532#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1899530#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 1899528#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1899526#L519-30 assume !(1 == ~t4_pc~0); 1899524#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1899522#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1899520#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1899518#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 1899516#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1899512#L538-30 assume !(1 == ~t5_pc~0); 1899508#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1899506#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1899504#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1899501#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1899498#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1899496#L557-30 assume !(1 == ~t6_pc~0); 1899494#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1899492#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1899490#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1899488#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1899486#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1899484#L576-30 assume 1 == ~t7_pc~0; 1899480#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1899478#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1899476#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1899474#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1899472#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1899470#L595-30 assume !(1 == ~t8_pc~0); 1899468#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1899466#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1899464#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1899462#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1899460#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1899457#L614-30 assume !(1 == ~t9_pc~0); 1899454#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1899452#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1899450#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1899448#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1899446#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1899445#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1899441#L1025-5 assume !(1 == ~T1_E~0); 1899439#L1030-3 assume !(1 == ~T2_E~0); 1899437#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1899436#L1040-3 assume !(1 == ~T4_E~0); 1899433#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1899429#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1899425#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1899424#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1899423#L1065-3 assume !(1 == ~T9_E~0); 1899422#L1070-3 assume !(1 == ~E_1~0); 1899420#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1899419#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1899418#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1899417#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1899415#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1899411#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1899409#L1105-3 assume !(1 == ~E_8~0); 1899407#L1110-3 assume !(1 == ~E_9~0); 1899405#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1899402#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1899400#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1899398#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1899125#L1415 assume !(0 == start_simulation_~tmp~3#1); 1899123#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1899120#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1899118#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1899116#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1899114#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1899112#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1899110#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1899108#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1881824#L1396-2 [2024-11-09 16:09:59,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:59,222 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 11 times [2024-11-09 16:09:59,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:59,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184239982] [2024-11-09 16:09:59,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:59,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:59,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:59,230 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:09:59,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:09:59,254 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:09:59,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:09:59,258 INFO L85 PathProgramCache]: Analyzing trace with hash 1637779143, now seen corresponding path program 1 times [2024-11-09 16:09:59,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:09:59,258 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139291764] [2024-11-09 16:09:59,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:09:59,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:09:59,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:09:59,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:09:59,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:09:59,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139291764] [2024-11-09 16:09:59,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139291764] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:09:59,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:09:59,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:09:59,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692059818] [2024-11-09 16:09:59,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:09:59,307 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:09:59,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:09:59,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:09:59,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:09:59,308 INFO L87 Difference]: Start difference. First operand 73017 states and 96548 transitions. cyclomatic complexity: 23563 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:09:59,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:09:59,599 INFO L93 Difference]: Finished difference Result 74169 states and 97363 transitions. [2024-11-09 16:09:59,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74169 states and 97363 transitions. [2024-11-09 16:09:59,891 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73640 [2024-11-09 16:10:00,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74169 states to 74169 states and 97363 transitions. [2024-11-09 16:10:00,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74169 [2024-11-09 16:10:00,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74169 [2024-11-09 16:10:00,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74169 states and 97363 transitions. [2024-11-09 16:10:00,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:10:00,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74169 states and 97363 transitions. [2024-11-09 16:10:00,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74169 states and 97363 transitions. [2024-11-09 16:10:01,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74169 to 74169. [2024-11-09 16:10:01,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74169 states, 74169 states have (on average 1.312718251560625) internal successors, (97363), 74168 states have internal predecessors, (97363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:01,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74169 states to 74169 states and 97363 transitions. [2024-11-09 16:10:01,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74169 states and 97363 transitions. [2024-11-09 16:10:01,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:10:01,213 INFO L425 stractBuchiCegarLoop]: Abstraction has 74169 states and 97363 transitions. [2024-11-09 16:10:01,213 INFO L332 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2024-11-09 16:10:01,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74169 states and 97363 transitions. [2024-11-09 16:10:01,390 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73640 [2024-11-09 16:10:01,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:10:01,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:10:01,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:10:01,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:10:01,393 INFO L745 eck$LassoCheckResult]: Stem: 2028789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2028790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2029658#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2029659#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2029590#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2029591#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2029566#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2029336#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2029337#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2029125#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2029126#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2029694#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2029551#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2029192#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2028948#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2028949#L922 assume !(0 == ~M_E~0); 2029769#L922-2 assume !(0 == ~T1_E~0); 2029770#L927-1 assume !(0 == ~T2_E~0); 2029414#L932-1 assume !(0 == ~T3_E~0); 2029268#L937-1 assume !(0 == ~T4_E~0); 2029269#L942-1 assume !(0 == ~T5_E~0); 2029335#L947-1 assume !(0 == ~T6_E~0); 2029419#L952-1 assume !(0 == ~T7_E~0); 2029420#L957-1 assume !(0 == ~T8_E~0); 2029493#L962-1 assume !(0 == ~T9_E~0); 2029246#L967-1 assume !(0 == ~E_1~0); 2029247#L972-1 assume !(0 == ~E_2~0); 2029573#L977-1 assume !(0 == ~E_3~0); 2029574#L982-1 assume !(0 == ~E_4~0); 2028721#L987-1 assume !(0 == ~E_5~0); 2028722#L992-1 assume !(0 == ~E_6~0); 2028726#L997-1 assume !(0 == ~E_7~0); 2029167#L1002-1 assume !(0 == ~E_8~0); 2029154#L1007-1 assume !(0 == ~E_9~0); 2028513#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2028514#L443 assume !(1 == ~m_pc~0); 2029437#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2029427#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2029428#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2028882#L1140 assume !(0 != activate_threads_~tmp~1#1); 2028618#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2028619#L462 assume !(1 == ~t1_pc~0); 2029262#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2029263#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2028556#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2028557#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2029103#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2029104#L481 assume !(1 == ~t2_pc~0); 2028876#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2029636#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2029790#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2029788#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2028971#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2029073#L500 assume !(1 == ~t3_pc~0); 2029648#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2029606#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2028520#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2028521#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2028518#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2028519#L519 assume !(1 == ~t4_pc~0); 2029324#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2029070#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2028620#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2028621#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2028923#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2028682#L538 assume !(1 == ~t5_pc~0); 2028683#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2028581#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2028582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2028862#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2028863#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2029476#L557 assume !(1 == ~t6_pc~0); 2028897#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2028898#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2028989#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2028921#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2028922#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2029737#L576 assume !(1 == ~t7_pc~0); 2028886#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2028887#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2029230#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2029763#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2029542#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2029013#L595 assume !(1 == ~t8_pc~0); 2029014#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2029561#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2029480#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2029363#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2029364#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2028812#L614 assume !(1 == ~t9_pc~0); 2028813#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2028708#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2028709#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2029046#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2028973#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2028974#L1025 assume !(1 == ~M_E~0); 2029251#L1025-2 assume !(1 == ~T1_E~0); 2029317#L1030-1 assume !(1 == ~T2_E~0); 2029466#L1035-1 assume !(1 == ~T3_E~0); 2028966#L1040-1 assume !(1 == ~T4_E~0); 2028967#L1045-1 assume !(1 == ~T5_E~0); 2028872#L1050-1 assume !(1 == ~T6_E~0); 2028873#L1055-1 assume !(1 == ~T7_E~0); 2028693#L1060-1 assume !(1 == ~T8_E~0); 2028694#L1065-1 assume !(1 == ~T9_E~0); 2028759#L1070-1 assume !(1 == ~E_1~0); 2029422#L1075-1 assume !(1 == ~E_2~0); 2029423#L1080-1 assume !(1 == ~E_3~0); 2029408#L1085-1 assume !(1 == ~E_4~0); 2029409#L1090-1 assume !(1 == ~E_5~0); 2029684#L1095-1 assume !(1 == ~E_6~0); 2029447#L1100-1 assume !(1 == ~E_7~0); 2029448#L1105-1 assume !(1 == ~E_8~0); 2028664#L1110-1 assume !(1 == ~E_9~0); 2028665#L1115-1 assume { :end_inline_reset_delta_events } true; 2029021#L1396-2 [2024-11-09 16:10:01,393 INFO L747 eck$LassoCheckResult]: Loop: 2029021#L1396-2 assume !false; 2046235#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2046230#L897-1 assume !false; 2046228#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2046225#L699 assume !(0 == ~m_st~0); 2046226#L703 assume !(0 == ~t1_st~0); 2063336#L707 assume !(0 == ~t2_st~0); 2063325#L711 assume !(0 == ~t3_st~0); 2063320#L715 assume !(0 == ~t4_st~0); 2063316#L719 assume !(0 == ~t5_st~0); 2063312#L723 assume !(0 == ~t6_st~0); 2063306#L727 assume !(0 == ~t7_st~0); 2063301#L731 assume !(0 == ~t8_st~0); 2063295#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2063288#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2063282#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2063278#L766 assume !(0 != eval_~tmp~0#1); 2063273#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2063268#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2063263#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2063257#L922-5 assume !(0 == ~T1_E~0); 2063251#L927-3 assume !(0 == ~T2_E~0); 2063245#L932-3 assume !(0 == ~T3_E~0); 2063240#L937-3 assume !(0 == ~T4_E~0); 2063235#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2063230#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2063225#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2063219#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2063214#L962-3 assume !(0 == ~T9_E~0); 2063113#L967-3 assume !(0 == ~E_1~0); 2063110#L972-3 assume !(0 == ~E_2~0); 2063108#L977-3 assume !(0 == ~E_3~0); 2063104#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2063102#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2063100#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2063098#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2063095#L1002-3 assume !(0 == ~E_8~0); 2063093#L1007-3 assume !(0 == ~E_9~0); 2063091#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2063089#L443-30 assume 1 == ~m_pc~0; 2063086#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2063084#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2063082#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2063080#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2063079#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2063078#L462-30 assume !(1 == ~t1_pc~0); 2063013#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2063007#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2063002#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2062996#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2062991#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2062985#L481-30 assume 1 == ~t2_pc~0; 2062979#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2062973#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2062967#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2062961#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2062955#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2062950#L500-30 assume !(1 == ~t3_pc~0); 2062782#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2062778#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2062776#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2062774#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2062772#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2062770#L519-30 assume !(1 == ~t4_pc~0); 2062768#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2062766#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2062764#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2062762#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2062759#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2062757#L538-30 assume 1 == ~t5_pc~0; 2062755#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2062756#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2062797#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2062746#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2062744#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2062742#L557-30 assume !(1 == ~t6_pc~0); 2062740#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2062738#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2062736#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2062734#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2062732#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2062729#L576-30 assume !(1 == ~t7_pc~0); 2062727#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2062724#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2062723#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2062722#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2062720#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2062718#L595-30 assume !(1 == ~t8_pc~0); 2062565#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2062558#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2061923#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2061914#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2061912#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2061910#L614-30 assume !(1 == ~t9_pc~0); 2061907#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2061905#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2061903#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2061901#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2061899#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2061895#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2061893#L1025-5 assume !(1 == ~T1_E~0); 2061891#L1030-3 assume !(1 == ~T2_E~0); 2061889#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2061888#L1040-3 assume !(1 == ~T4_E~0); 2061886#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2061884#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2061882#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2057487#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2057486#L1065-3 assume !(1 == ~T9_E~0); 2057485#L1070-3 assume !(1 == ~E_1~0); 2057484#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2057482#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2046289#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2046286#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2046284#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2046280#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2046278#L1105-3 assume !(1 == ~E_8~0); 2046276#L1110-3 assume !(1 == ~E_9~0); 2046274#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2046270#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2046268#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2046266#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2046258#L1415 assume !(0 == start_simulation_~tmp~3#1); 2046256#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2046251#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2046249#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2046247#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2046245#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2046242#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2046240#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2046238#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2029021#L1396-2 [2024-11-09 16:10:01,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:01,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 12 times [2024-11-09 16:10:01,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:01,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510500901] [2024-11-09 16:10:01,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:01,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:01,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:01,403 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:10:01,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:01,421 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:10:01,422 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:01,422 INFO L85 PathProgramCache]: Analyzing trace with hash -807672889, now seen corresponding path program 1 times [2024-11-09 16:10:01,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:01,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448141458] [2024-11-09 16:10:01,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:01,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:01,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:10:01,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:10:01,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:10:01,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448141458] [2024-11-09 16:10:01,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1448141458] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:10:01,482 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:10:01,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:10:01,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1656264868] [2024-11-09 16:10:01,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:10:01,482 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:10:01,482 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:10:01,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:10:01,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:10:01,483 INFO L87 Difference]: Start difference. First operand 74169 states and 97363 transitions. cyclomatic complexity: 23226 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:01,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:10:01,796 INFO L93 Difference]: Finished difference Result 76332 states and 99526 transitions. [2024-11-09 16:10:01,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76332 states and 99526 transitions. [2024-11-09 16:10:02,594 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75800 [2024-11-09 16:10:02,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76332 states to 76332 states and 99526 transitions. [2024-11-09 16:10:02,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76332 [2024-11-09 16:10:02,804 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76332 [2024-11-09 16:10:02,804 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76332 states and 99526 transitions. [2024-11-09 16:10:02,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:10:02,839 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76332 states and 99526 transitions. [2024-11-09 16:10:02,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76332 states and 99526 transitions. [2024-11-09 16:10:03,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76332 to 76332. [2024-11-09 16:10:03,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76332 states, 76332 states have (on average 1.303856835927265) internal successors, (99526), 76331 states have internal predecessors, (99526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:03,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76332 states to 76332 states and 99526 transitions. [2024-11-09 16:10:03,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76332 states and 99526 transitions. [2024-11-09 16:10:03,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:10:03,616 INFO L425 stractBuchiCegarLoop]: Abstraction has 76332 states and 99526 transitions. [2024-11-09 16:10:03,616 INFO L332 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2024-11-09 16:10:03,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76332 states and 99526 transitions. [2024-11-09 16:10:03,800 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75800 [2024-11-09 16:10:03,800 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:10:03,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:10:03,801 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:10:03,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:10:03,801 INFO L745 eck$LassoCheckResult]: Stem: 2179295#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2179296#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2180208#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2180209#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2180135#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2180136#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2180107#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2179869#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2179870#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2179640#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2179641#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2180255#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2180088#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2179710#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2179457#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2179458#L922 assume !(0 == ~M_E~0); 2180334#L922-2 assume !(0 == ~T1_E~0); 2180335#L927-1 assume !(0 == ~T2_E~0); 2179946#L932-1 assume !(0 == ~T3_E~0); 2179792#L937-1 assume !(0 == ~T4_E~0); 2179793#L942-1 assume !(0 == ~T5_E~0); 2179868#L947-1 assume !(0 == ~T6_E~0); 2179951#L952-1 assume !(0 == ~T7_E~0); 2179952#L957-1 assume !(0 == ~T8_E~0); 2180027#L962-1 assume !(0 == ~T9_E~0); 2179763#L967-1 assume !(0 == ~E_1~0); 2179764#L972-1 assume !(0 == ~E_2~0); 2180117#L977-1 assume !(0 == ~E_3~0); 2180118#L982-1 assume !(0 == ~E_4~0); 2179229#L987-1 assume !(0 == ~E_5~0); 2179230#L992-1 assume !(0 == ~E_6~0); 2179236#L997-1 assume !(0 == ~E_7~0); 2179683#L1002-1 assume !(0 == ~E_8~0); 2179669#L1007-1 assume !(0 == ~E_9~0); 2179022#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2179023#L443 assume !(1 == ~m_pc~0); 2179969#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2179960#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2179961#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2179391#L1140 assume !(0 != activate_threads_~tmp~1#1); 2179128#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2179129#L462 assume !(1 == ~t1_pc~0); 2179781#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2179782#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2179063#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2179064#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2179617#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2179618#L481 assume !(1 == ~t2_pc~0); 2179385#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2180181#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2180362#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2180361#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2179480#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2179585#L500 assume !(1 == ~t3_pc~0); 2180193#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2180153#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2179029#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2179030#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2179024#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2179025#L519 assume !(1 == ~t4_pc~0); 2179854#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2179584#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2179130#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2179131#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2179431#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2179192#L538 assume !(1 == ~t5_pc~0); 2179193#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2179088#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2179089#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2179372#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2179373#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2180009#L557 assume !(1 == ~t6_pc~0); 2179406#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2179407#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2179499#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2179429#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2179430#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2180302#L576 assume !(1 == ~t7_pc~0); 2179395#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2179591#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2180365#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2180339#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2180080#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2179520#L595 assume !(1 == ~t8_pc~0); 2179521#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2180101#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2180016#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2179896#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2179897#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2179322#L614 assume !(1 == ~t9_pc~0); 2179323#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2179217#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2179218#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2179557#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2179483#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2179484#L1025 assume !(1 == ~M_E~0); 2179772#L1025-2 assume !(1 == ~T1_E~0); 2179842#L1030-1 assume !(1 == ~T2_E~0); 2180000#L1035-1 assume !(1 == ~T3_E~0); 2179474#L1040-1 assume !(1 == ~T4_E~0); 2179475#L1045-1 assume !(1 == ~T5_E~0); 2179381#L1050-1 assume !(1 == ~T6_E~0); 2179382#L1055-1 assume !(1 == ~T7_E~0); 2179203#L1060-1 assume !(1 == ~T8_E~0); 2179204#L1065-1 assume !(1 == ~T9_E~0); 2179268#L1070-1 assume !(1 == ~E_1~0); 2179953#L1075-1 assume !(1 == ~E_2~0); 2179954#L1080-1 assume !(1 == ~E_3~0); 2179939#L1085-1 assume !(1 == ~E_4~0); 2179940#L1090-1 assume !(1 == ~E_5~0); 2180244#L1095-1 assume !(1 == ~E_6~0); 2179981#L1100-1 assume !(1 == ~E_7~0); 2179982#L1105-1 assume !(1 == ~E_8~0); 2179174#L1110-1 assume !(1 == ~E_9~0); 2179175#L1115-1 assume { :end_inline_reset_delta_events } true; 2179530#L1396-2 [2024-11-09 16:10:03,802 INFO L747 eck$LassoCheckResult]: Loop: 2179530#L1396-2 assume !false; 2186404#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2186399#L897-1 assume !false; 2186397#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2186394#L699 assume !(0 == ~m_st~0); 2186395#L703 assume !(0 == ~t1_st~0); 2187420#L707 assume !(0 == ~t2_st~0); 2187418#L711 assume !(0 == ~t3_st~0); 2187416#L715 assume !(0 == ~t4_st~0); 2187413#L719 assume !(0 == ~t5_st~0); 2187411#L723 assume !(0 == ~t6_st~0); 2187409#L727 assume !(0 == ~t7_st~0); 2187407#L731 assume !(0 == ~t8_st~0); 2187404#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2187402#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2187401#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2187397#L766 assume !(0 != eval_~tmp~0#1); 2187395#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2187393#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2187392#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2187389#L922-5 assume !(0 == ~T1_E~0); 2187388#L927-3 assume !(0 == ~T2_E~0); 2187387#L932-3 assume !(0 == ~T3_E~0); 2187385#L937-3 assume !(0 == ~T4_E~0); 2187383#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2187379#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2187375#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2187371#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2187367#L962-3 assume !(0 == ~T9_E~0); 2187364#L967-3 assume !(0 == ~E_1~0); 2187361#L972-3 assume !(0 == ~E_2~0); 2187359#L977-3 assume !(0 == ~E_3~0); 2187356#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2187354#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2187352#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2187349#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2187347#L1002-3 assume !(0 == ~E_8~0); 2187345#L1007-3 assume !(0 == ~E_9~0); 2187344#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2187343#L443-30 assume 1 == ~m_pc~0; 2187340#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2187338#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2187336#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2187332#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2187330#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2187328#L462-30 assume !(1 == ~t1_pc~0); 2187323#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2187321#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2187319#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2187317#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2187315#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2187313#L481-30 assume !(1 == ~t2_pc~0); 2187311#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2187546#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2187544#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2187301#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 2187299#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2187297#L500-30 assume !(1 == ~t3_pc~0); 2187294#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2187292#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2187290#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2187288#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2187286#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2187284#L519-30 assume !(1 == ~t4_pc~0); 2187282#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2187280#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2187278#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2187276#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2187274#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2187272#L538-30 assume !(1 == ~t5_pc~0); 2187268#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2187266#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2187262#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2187260#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 2187257#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2187255#L557-30 assume !(1 == ~t6_pc~0); 2187252#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2187250#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2187246#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2187244#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2187242#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2187240#L576-30 assume !(1 == ~t7_pc~0); 2187235#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2187233#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2187231#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2187228#L1196-30 assume !(0 != activate_threads_~tmp___6~0#1); 2187225#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2187223#L595-30 assume !(1 == ~t8_pc~0); 2187220#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2187218#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2187216#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2187214#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2187212#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2187210#L614-30 assume !(1 == ~t9_pc~0); 2187207#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2187205#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2187202#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2187200#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2187198#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2187196#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2187194#L1025-5 assume !(1 == ~T1_E~0); 2187192#L1030-3 assume !(1 == ~T2_E~0); 2187191#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2187190#L1040-3 assume !(1 == ~T4_E~0); 2187189#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2187188#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2187186#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2187184#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2187183#L1065-3 assume !(1 == ~T9_E~0); 2187182#L1070-3 assume !(1 == ~E_1~0); 2187180#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2187179#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2187178#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2187176#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2187175#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2187174#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2187172#L1105-3 assume !(1 == ~E_8~0); 2187171#L1110-3 assume !(1 == ~E_9~0); 2187170#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2187167#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2187166#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2187165#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2186984#L1415 assume !(0 == start_simulation_~tmp~3#1); 2186982#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2186979#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2186977#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2186975#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2186973#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2186971#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2186968#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2186966#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2179530#L1396-2 [2024-11-09 16:10:03,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:03,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 13 times [2024-11-09 16:10:03,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:03,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267075183] [2024-11-09 16:10:03,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:03,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:04,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:04,103 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:10:04,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:04,125 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:10:04,125 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:04,126 INFO L85 PathProgramCache]: Analyzing trace with hash -1981321473, now seen corresponding path program 1 times [2024-11-09 16:10:04,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:04,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113398349] [2024-11-09 16:10:04,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:04,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:04,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:10:04,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:10:04,184 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:10:04,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113398349] [2024-11-09 16:10:04,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113398349] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:10:04,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:10:04,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:10:04,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115388590] [2024-11-09 16:10:04,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:10:04,184 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:10:04,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:10:04,185 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:10:04,185 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:10:04,185 INFO L87 Difference]: Start difference. First operand 76332 states and 99526 transitions. cyclomatic complexity: 23226 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:04,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:10:04,501 INFO L93 Difference]: Finished difference Result 77052 states and 99765 transitions. [2024-11-09 16:10:04,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77052 states and 99765 transitions. [2024-11-09 16:10:04,772 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76520 [2024-11-09 16:10:04,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77052 states to 77052 states and 99765 transitions. [2024-11-09 16:10:04,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77052 [2024-11-09 16:10:05,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77052 [2024-11-09 16:10:05,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77052 states and 99765 transitions. [2024-11-09 16:10:05,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:10:05,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77052 states and 99765 transitions. [2024-11-09 16:10:05,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77052 states and 99765 transitions. [2024-11-09 16:10:06,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77052 to 77052. [2024-11-09 16:10:06,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77052 states, 77052 states have (on average 1.2947749571717801) internal successors, (99765), 77051 states have internal predecessors, (99765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:06,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77052 states to 77052 states and 99765 transitions. [2024-11-09 16:10:06,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77052 states and 99765 transitions. [2024-11-09 16:10:06,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:10:06,206 INFO L425 stractBuchiCegarLoop]: Abstraction has 77052 states and 99765 transitions. [2024-11-09 16:10:06,206 INFO L332 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2024-11-09 16:10:06,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77052 states and 99765 transitions. [2024-11-09 16:10:06,378 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76520 [2024-11-09 16:10:06,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:10:06,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:10:06,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:10:06,379 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:10:06,379 INFO L745 eck$LassoCheckResult]: Stem: 2332687#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2332688#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2333591#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2333592#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2333513#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2333514#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2333489#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2333257#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2333258#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2333024#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2333025#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2333635#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2333474#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2333097#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2332844#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2332845#L922 assume !(0 == ~M_E~0); 2333712#L922-2 assume !(0 == ~T1_E~0); 2333713#L927-1 assume !(0 == ~T2_E~0); 2333339#L932-1 assume !(0 == ~T3_E~0); 2333179#L937-1 assume !(0 == ~T4_E~0); 2333180#L942-1 assume !(0 == ~T5_E~0); 2333256#L947-1 assume !(0 == ~T6_E~0); 2333344#L952-1 assume !(0 == ~T7_E~0); 2333345#L957-1 assume !(0 == ~T8_E~0); 2333420#L962-1 assume !(0 == ~T9_E~0); 2333156#L967-1 assume !(0 == ~E_1~0); 2333157#L972-1 assume !(0 == ~E_2~0); 2333497#L977-1 assume !(0 == ~E_3~0); 2333498#L982-1 assume !(0 == ~E_4~0); 2332619#L987-1 assume !(0 == ~E_5~0); 2332620#L992-1 assume !(0 == ~E_6~0); 2332626#L997-1 assume !(0 == ~E_7~0); 2333068#L1002-1 assume !(0 == ~E_8~0); 2333053#L1007-1 assume !(0 == ~E_9~0); 2332414#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2332415#L443 assume !(1 == ~m_pc~0); 2333365#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2333354#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2333355#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2332780#L1140 assume !(0 != activate_threads_~tmp~1#1); 2332519#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2332520#L462 assume !(1 == ~t1_pc~0); 2333170#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2333171#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2332455#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2332456#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2333001#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2333002#L481 assume !(1 == ~t2_pc~0); 2332774#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2333564#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2333747#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2333746#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2332868#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2332970#L500 assume !(1 == ~t3_pc~0); 2333577#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2333533#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2332421#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2332422#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2332416#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2332417#L519 assume !(1 == ~t4_pc~0); 2333240#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2332969#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2332521#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2332522#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2332815#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2332583#L538 assume !(1 == ~t5_pc~0); 2332584#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2332480#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2332481#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2332760#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2332761#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2333404#L557 assume !(1 == ~t6_pc~0); 2332794#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2332795#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2332887#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2332816#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2332817#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2333678#L576 assume !(1 == ~t7_pc~0); 2332784#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2332976#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2333750#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2333721#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2333467#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2332908#L595 assume !(1 == ~t8_pc~0); 2332909#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2333483#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2333408#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2333287#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2333288#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2332712#L614 assume !(1 == ~t9_pc~0); 2332713#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2332608#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2332609#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2332942#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2332870#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2332871#L1025 assume !(1 == ~M_E~0); 2333163#L1025-2 assume !(1 == ~T1_E~0); 2333232#L1030-1 assume !(1 == ~T2_E~0); 2333397#L1035-1 assume !(1 == ~T3_E~0); 2332861#L1040-1 assume !(1 == ~T4_E~0); 2332862#L1045-1 assume !(1 == ~T5_E~0); 2332770#L1050-1 assume !(1 == ~T6_E~0); 2332771#L1055-1 assume !(1 == ~T7_E~0); 2332594#L1060-1 assume !(1 == ~T8_E~0); 2332595#L1065-1 assume !(1 == ~T9_E~0); 2332659#L1070-1 assume !(1 == ~E_1~0); 2333346#L1075-1 assume !(1 == ~E_2~0); 2333347#L1080-1 assume !(1 == ~E_3~0); 2333333#L1085-1 assume !(1 == ~E_4~0); 2333334#L1090-1 assume !(1 == ~E_5~0); 2333624#L1095-1 assume !(1 == ~E_6~0); 2333377#L1100-1 assume !(1 == ~E_7~0); 2333378#L1105-1 assume !(1 == ~E_8~0); 2332566#L1110-1 assume !(1 == ~E_9~0); 2332567#L1115-1 assume { :end_inline_reset_delta_events } true; 2332917#L1396-2 [2024-11-09 16:10:06,380 INFO L747 eck$LassoCheckResult]: Loop: 2332917#L1396-2 assume !false; 2343211#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2343206#L897-1 assume !false; 2343204#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2343201#L699 assume !(0 == ~m_st~0); 2343202#L703 assume !(0 == ~t1_st~0); 2343615#L707 assume !(0 == ~t2_st~0); 2343613#L711 assume !(0 == ~t3_st~0); 2343611#L715 assume !(0 == ~t4_st~0); 2343609#L719 assume !(0 == ~t5_st~0); 2343607#L723 assume !(0 == ~t6_st~0); 2343604#L727 assume !(0 == ~t7_st~0); 2343602#L731 assume !(0 == ~t8_st~0); 2343599#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2343596#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2343594#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2343592#L766 assume !(0 != eval_~tmp~0#1); 2343590#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2343588#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2343586#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2343584#L922-5 assume !(0 == ~T1_E~0); 2343582#L927-3 assume !(0 == ~T2_E~0); 2343580#L932-3 assume !(0 == ~T3_E~0); 2343578#L937-3 assume !(0 == ~T4_E~0); 2343576#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2343574#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2343572#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2343570#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2343566#L962-3 assume !(0 == ~T9_E~0); 2343564#L967-3 assume !(0 == ~E_1~0); 2343562#L972-3 assume !(0 == ~E_2~0); 2343560#L977-3 assume !(0 == ~E_3~0); 2343557#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2343555#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2343553#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2343551#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2343549#L1002-3 assume !(0 == ~E_8~0); 2343547#L1007-3 assume !(0 == ~E_9~0); 2343545#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2343543#L443-30 assume 1 == ~m_pc~0; 2343538#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2343536#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2343534#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2343531#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2343528#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2343526#L462-30 assume !(1 == ~t1_pc~0); 2343524#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2343522#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2343520#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2343518#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2343516#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2343514#L481-30 assume !(1 == ~t2_pc~0); 2343511#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2343968#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2343966#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2343503#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 2343501#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2343499#L500-30 assume !(1 == ~t3_pc~0); 2343497#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2343495#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2343493#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2343491#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2343489#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2343487#L519-30 assume !(1 == ~t4_pc~0); 2343485#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2343483#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2343481#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2343479#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2343477#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2343475#L538-30 assume 1 == ~t5_pc~0; 2343473#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2343474#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2343981#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2343464#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2343462#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2343460#L557-30 assume !(1 == ~t6_pc~0); 2343458#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2343456#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2343454#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2343453#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2343452#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2343451#L576-30 assume 1 == ~t7_pc~0; 2343450#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2343448#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2343446#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2343443#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2343442#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2343441#L595-30 assume !(1 == ~t8_pc~0); 2343440#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2343439#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2343430#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2343428#L1204-30 assume !(0 != activate_threads_~tmp___7~0#1); 2343426#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2343423#L614-30 assume !(1 == ~t9_pc~0); 2343420#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2343418#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2343415#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2343413#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2343411#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2343410#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2343409#L1025-5 assume !(1 == ~T1_E~0); 2343407#L1030-3 assume !(1 == ~T2_E~0); 2343405#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2343404#L1040-3 assume !(1 == ~T4_E~0); 2343403#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2343401#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2343398#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2343396#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2343394#L1065-3 assume !(1 == ~T9_E~0); 2343389#L1070-3 assume !(1 == ~E_1~0); 2343387#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2343385#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2343383#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2343381#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2343379#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2343377#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2343375#L1105-3 assume !(1 == ~E_8~0); 2343371#L1110-3 assume !(1 == ~E_9~0); 2343369#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2343366#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2343364#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2343361#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2343234#L1415 assume !(0 == start_simulation_~tmp~3#1); 2343232#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2343229#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2343225#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2343223#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2343221#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2343219#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2343216#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2343214#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2332917#L1396-2 [2024-11-09 16:10:06,380 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:06,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 14 times [2024-11-09 16:10:06,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:06,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503212422] [2024-11-09 16:10:06,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:06,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:06,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:06,387 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:10:06,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:06,402 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:10:06,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:06,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1509552125, now seen corresponding path program 1 times [2024-11-09 16:10:06,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:06,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775695182] [2024-11-09 16:10:06,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:06,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:06,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:10:06,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:10:06,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:10:06,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775695182] [2024-11-09 16:10:06,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775695182] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:10:06,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:10:06,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:10:06,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576597109] [2024-11-09 16:10:06,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:10:06,457 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:10:06,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:10:06,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:10:06,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:10:06,457 INFO L87 Difference]: Start difference. First operand 77052 states and 99765 transitions. cyclomatic complexity: 22745 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:06,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:10:06,745 INFO L93 Difference]: Finished difference Result 77244 states and 99268 transitions. [2024-11-09 16:10:06,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77244 states and 99268 transitions. [2024-11-09 16:10:07,036 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76712 [2024-11-09 16:10:07,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77244 states to 77244 states and 99268 transitions. [2024-11-09 16:10:07,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77244 [2024-11-09 16:10:07,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77244 [2024-11-09 16:10:07,274 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77244 states and 99268 transitions. [2024-11-09 16:10:07,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:10:07,318 INFO L218 hiAutomatonCegarLoop]: Abstraction has 77244 states and 99268 transitions. [2024-11-09 16:10:07,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77244 states and 99268 transitions. [2024-11-09 16:10:08,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77244 to 77244. [2024-11-09 16:10:08,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77244 states, 77244 states have (on average 1.2851224690590854) internal successors, (99268), 77243 states have internal predecessors, (99268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:08,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77244 states to 77244 states and 99268 transitions. [2024-11-09 16:10:08,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77244 states and 99268 transitions. [2024-11-09 16:10:08,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:10:08,526 INFO L425 stractBuchiCegarLoop]: Abstraction has 77244 states and 99268 transitions. [2024-11-09 16:10:08,526 INFO L332 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2024-11-09 16:10:08,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77244 states and 99268 transitions. [2024-11-09 16:10:08,716 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76712 [2024-11-09 16:10:08,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:10:08,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:10:08,717 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:10:08,717 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:10:08,717 INFO L745 eck$LassoCheckResult]: Stem: 2486993#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2486994#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2487955#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2487956#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2487871#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2487872#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2487844#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2487584#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2487585#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2487346#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2487347#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2488005#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2487826#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2487424#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2487159#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2487160#L922 assume !(0 == ~M_E~0); 2488101#L922-2 assume !(0 == ~T1_E~0); 2488102#L927-1 assume !(0 == ~T2_E~0); 2487666#L932-1 assume !(0 == ~T3_E~0); 2487507#L937-1 assume !(0 == ~T4_E~0); 2487508#L942-1 assume !(0 == ~T5_E~0); 2487583#L947-1 assume !(0 == ~T6_E~0); 2487671#L952-1 assume !(0 == ~T7_E~0); 2487672#L957-1 assume !(0 == ~T8_E~0); 2487754#L962-1 assume !(0 == ~T9_E~0); 2487480#L967-1 assume !(0 == ~E_1~0); 2487481#L972-1 assume !(0 == ~E_2~0); 2487851#L977-1 assume !(0 == ~E_3~0); 2487852#L982-1 assume !(0 == ~E_4~0); 2486924#L987-1 assume !(0 == ~E_5~0); 2486925#L992-1 assume !(0 == ~E_6~0); 2486931#L997-1 assume !(0 == ~E_7~0); 2487395#L1002-1 assume !(0 == ~E_8~0); 2487380#L1007-1 assume !(0 == ~E_9~0); 2486718#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2486719#L443 assume !(1 == ~m_pc~0); 2487690#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2487679#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2487680#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2487091#L1140 assume !(0 != activate_threads_~tmp~1#1); 2486823#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2486824#L462 assume !(1 == ~t1_pc~0); 2487495#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2487496#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2486759#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2486760#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2487320#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2487321#L481 assume !(1 == ~t2_pc~0); 2487085#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2487923#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2488137#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2488136#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2487183#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2487288#L500 assume !(1 == ~t3_pc~0); 2487940#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2487894#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2486725#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2486726#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2486720#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2486721#L519 assume !(1 == ~t4_pc~0); 2487570#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2487287#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2486825#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2486826#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2487129#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2486887#L538 assume !(1 == ~t5_pc~0); 2486888#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2486784#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2486785#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2487071#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2487072#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2487735#L557 assume !(1 == ~t6_pc~0); 2487106#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2487107#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2487202#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2487130#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2487131#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2488063#L576 assume !(1 == ~t7_pc~0); 2487095#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2487294#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2488140#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2488109#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2487816#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2487224#L595 assume !(1 == ~t8_pc~0); 2487225#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2487839#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2487741#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2487612#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2487613#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2487020#L614 assume !(1 == ~t9_pc~0); 2487021#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2486913#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2486914#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2487262#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2487185#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2487186#L1025 assume !(1 == ~M_E~0); 2487488#L1025-2 assume !(1 == ~T1_E~0); 2487560#L1030-1 assume !(1 == ~T2_E~0); 2487725#L1035-1 assume !(1 == ~T3_E~0); 2487177#L1040-1 assume !(1 == ~T4_E~0); 2487178#L1045-1 assume !(1 == ~T5_E~0); 2487081#L1050-1 assume !(1 == ~T6_E~0); 2487082#L1055-1 assume !(1 == ~T7_E~0); 2486898#L1060-1 assume !(1 == ~T8_E~0); 2486899#L1065-1 assume !(1 == ~T9_E~0); 2486963#L1070-1 assume !(1 == ~E_1~0); 2487673#L1075-1 assume !(1 == ~E_2~0); 2487674#L1080-1 assume !(1 == ~E_3~0); 2487660#L1085-1 assume !(1 == ~E_4~0); 2487661#L1090-1 assume !(1 == ~E_5~0); 2487993#L1095-1 assume !(1 == ~E_6~0); 2487707#L1100-1 assume !(1 == ~E_7~0); 2487708#L1105-1 assume !(1 == ~E_8~0); 2486869#L1110-1 assume !(1 == ~E_9~0); 2486870#L1115-1 assume { :end_inline_reset_delta_events } true; 2487234#L1396-2 [2024-11-09 16:10:08,717 INFO L747 eck$LassoCheckResult]: Loop: 2487234#L1396-2 assume !false; 2498757#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2498752#L897-1 assume !false; 2498750#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2498747#L699 assume !(0 == ~m_st~0); 2498748#L703 assume !(0 == ~t1_st~0); 2512368#L707 assume !(0 == ~t2_st~0); 2512364#L711 assume !(0 == ~t3_st~0); 2512359#L715 assume !(0 == ~t4_st~0); 2512354#L719 assume !(0 == ~t5_st~0); 2512350#L723 assume !(0 == ~t6_st~0); 2512343#L727 assume !(0 == ~t7_st~0); 2512339#L731 assume !(0 == ~t8_st~0); 2512335#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2512331#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2512326#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2512320#L766 assume !(0 != eval_~tmp~0#1); 2512318#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2512310#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2512306#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2512092#L922-5 assume !(0 == ~T1_E~0); 2512091#L927-3 assume !(0 == ~T2_E~0); 2512090#L932-3 assume !(0 == ~T3_E~0); 2512089#L937-3 assume !(0 == ~T4_E~0); 2510084#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2510083#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2510082#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2510080#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2510079#L962-3 assume !(0 == ~T9_E~0); 2510078#L967-3 assume !(0 == ~E_1~0); 2510076#L972-3 assume !(0 == ~E_2~0); 2510074#L977-3 assume !(0 == ~E_3~0); 2506696#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2506691#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2506688#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2506686#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2506683#L1002-3 assume !(0 == ~E_8~0); 2506679#L1007-3 assume !(0 == ~E_9~0); 2499008#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2498999#L443-30 assume 1 == ~m_pc~0; 2498996#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2498994#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2498991#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2498988#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2498986#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2498983#L462-30 assume !(1 == ~t1_pc~0); 2498981#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2498979#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2498978#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2498977#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2498975#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2498974#L481-30 assume 1 == ~t2_pc~0; 2498972#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2498970#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2498968#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2498967#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2498965#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2498964#L500-30 assume !(1 == ~t3_pc~0); 2498960#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2498958#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2498956#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2498954#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2498949#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2498947#L519-30 assume !(1 == ~t4_pc~0); 2498945#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2498943#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2498941#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2498939#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2498937#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2498935#L538-30 assume 1 == ~t5_pc~0; 2498933#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2498934#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2505456#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2498922#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2498919#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2498917#L557-30 assume !(1 == ~t6_pc~0); 2498915#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2498913#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2498911#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2498909#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2498907#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2498905#L576-30 assume 1 == ~t7_pc~0; 2498903#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2498904#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2504219#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2498894#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2498892#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2498890#L595-30 assume !(1 == ~t8_pc~0); 2498889#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2498885#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2498883#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2498881#L1204-30 assume !(0 != activate_threads_~tmp___7~0#1); 2498879#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2498876#L614-30 assume !(1 == ~t9_pc~0); 2498873#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2498871#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2498869#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2498867#L1212-30 assume !(0 != activate_threads_~tmp___8~0#1); 2498865#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2498863#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2498861#L1025-5 assume !(1 == ~T1_E~0); 2498857#L1030-3 assume !(1 == ~T2_E~0); 2498855#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2498853#L1040-3 assume !(1 == ~T4_E~0); 2498851#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2498848#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2498846#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2498844#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2498842#L1065-3 assume !(1 == ~T9_E~0); 2498840#L1070-3 assume !(1 == ~E_1~0); 2498838#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2498836#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2498834#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2498831#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2498829#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2498827#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2498825#L1105-3 assume !(1 == ~E_8~0); 2498823#L1110-3 assume !(1 == ~E_9~0); 2498821#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2498818#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2498816#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2498814#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2498781#L1415 assume !(0 == start_simulation_~tmp~3#1); 2498779#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2498775#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2498773#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2498769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2498767#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2498765#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2498763#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2498760#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2487234#L1396-2 [2024-11-09 16:10:08,718 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:08,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 15 times [2024-11-09 16:10:08,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:08,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625537775] [2024-11-09 16:10:08,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:08,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:08,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:08,725 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:10:08,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:08,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:10:08,740 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:08,740 INFO L85 PathProgramCache]: Analyzing trace with hash 1601840868, now seen corresponding path program 1 times [2024-11-09 16:10:08,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:08,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544812288] [2024-11-09 16:10:08,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:08,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:08,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:08,752 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:10:08,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:10:08,765 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:10:08,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:08,766 INFO L85 PathProgramCache]: Analyzing trace with hash -927375339, now seen corresponding path program 1 times [2024-11-09 16:10:08,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:10:08,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466926775] [2024-11-09 16:10:08,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:10:08,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:10:08,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:10:08,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:10:08,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:10:08,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466926775] [2024-11-09 16:10:08,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466926775] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:10:08,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:10:08,798 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:10:08,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [518217285] [2024-11-09 16:10:08,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:10:10,712 INFO L204 LassoAnalysis]: Preferences: [2024-11-09 16:10:10,713 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-09 16:10:10,713 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-09 16:10:10,713 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-09 16:10:10,713 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-09 16:10:10,713 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:10,713 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-09 16:10:10,713 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-09 16:10:10,713 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.09.cil.c_Iteration39_Loop [2024-11-09 16:10:10,713 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-09 16:10:10,713 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-09 16:10:10,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,748 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,754 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,759 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,763 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,764 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,769 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,798 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,802 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,805 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,816 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,819 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,829 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,830 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,838 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,842 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,852 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,860 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,863 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,864 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,867 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,871 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,888 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,893 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,901 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,905 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,907 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,908 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,914 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,916 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,917 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,919 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,920 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,923 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,927 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,929 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,932 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,937 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,941 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,960 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,963 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,967 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:10,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,478 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-09 16:10:11,478 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-09 16:10:11,480 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,480 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,482 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,483 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-09 16:10:11,485 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,486 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,500 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,500 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,511 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-09 16:10:11,512 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,512 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,514 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,515 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-09 16:10:11,516 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,516 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,528 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,529 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,544 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-09 16:10:11,546 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,547 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,550 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,554 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-09 16:10:11,555 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,555 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,577 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,577 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,587 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-09 16:10:11,588 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,588 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,590 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,591 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-09 16:10:11,592 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,592 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,610 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,610 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_pc~0=4} Honda state: {~t4_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,620 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-09 16:10:11,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,621 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,622 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,623 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-09 16:10:11,624 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,624 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,635 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,635 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,645 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-09 16:10:11,646 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,646 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,647 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,648 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-09 16:10:11,651 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,651 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,662 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,662 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,673 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:11,673 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,673 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,674 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,675 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-09 16:10:11,676 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,676 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,687 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,687 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,698 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:11,698 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,698 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,699 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,700 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-09 16:10:11,701 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,701 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,718 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,719 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,729 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-09 16:10:11,730 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,730 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,731 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,732 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-09 16:10:11,732 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,732 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,743 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,743 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,754 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:11,754 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,754 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,755 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,756 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-09 16:10:11,757 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,757 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,768 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,768 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,779 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:11,779 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,780 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,781 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,782 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-09 16:10:11,782 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,782 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,795 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,796 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=1} Honda state: {~t7_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,806 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:11,807 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,807 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,808 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,809 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-09 16:10:11,809 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,809 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,820 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,820 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit7_triggered_~__retres1~7#1=0} Honda state: {ULTIMATE.start_is_transmit7_triggered_~__retres1~7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,830 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:11,831 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,831 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,832 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,833 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-09 16:10:11,834 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,834 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,844 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,845 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_9~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_9~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,855 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-09 16:10:11,855 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,855 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,857 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,858 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-09 16:10:11,858 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,858 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,876 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-09 16:10:11,876 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t9_st~0=4} Honda state: {~t9_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-09 16:10:11,886 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:11,887 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,887 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,888 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,889 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-09 16:10:11,890 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-09 16:10:11,890 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,911 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:11,912 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,912 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:11,913 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:11,913 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-09 16:10:11,914 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-09 16:10:11,914 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-09 16:10:11,931 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-09 16:10:11,944 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-09 16:10:11,944 INFO L204 LassoAnalysis]: Preferences: [2024-11-09 16:10:11,944 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-09 16:10:11,944 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-09 16:10:11,944 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-09 16:10:11,944 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-09 16:10:11,944 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:11,944 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-09 16:10:11,945 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-09 16:10:11,945 INFO L132 ssoRankerPreferences]: Filename of dumped script: transmitter.09.cil.c_Iteration39_Loop [2024-11-09 16:10:11,945 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-09 16:10:11,945 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-09 16:10:11,949 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,963 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,965 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,966 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,967 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,971 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,984 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:11,998 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,011 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,013 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,019 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,021 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,022 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,027 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,029 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,033 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,037 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,039 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,041 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,045 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,047 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,049 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,051 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,053 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,055 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,056 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,060 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,061 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,063 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,065 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,073 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,076 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,082 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,084 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,088 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,092 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,094 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,100 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,104 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,105 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,107 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,109 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,113 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,118 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,132 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,136 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,137 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,142 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,144 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,147 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,149 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,150 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,152 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,157 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,158 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,166 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,168 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,169 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,170 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,179 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,181 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,184 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,185 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,187 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,190 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,192 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,193 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,195 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,197 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,199 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,201 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,203 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,206 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,207 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,210 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,212 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,213 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,215 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,219 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,221 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,234 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,236 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-09 16:10:12,762 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-09 16:10:12,766 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-09 16:10:12,767 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,767 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,769 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,770 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-09 16:10:12,776 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:12,786 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:12,786 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:12,787 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:12,787 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:12,787 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:12,789 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:12,789 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:12,792 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:12,802 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-09 16:10:12,803 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,803 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,804 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,806 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-09 16:10:12,806 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:12,816 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:12,817 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:12,817 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:12,817 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:12,817 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:12,817 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:12,818 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:12,819 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:12,830 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-09 16:10:12,830 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,831 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,833 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,835 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-09 16:10:12,837 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:12,847 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:12,848 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:12,848 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:12,848 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:10:12,848 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:12,849 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:10:12,849 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:12,850 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:12,860 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:12,861 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,861 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,863 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,864 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-09 16:10:12,864 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:12,874 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:12,874 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:12,875 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:12,875 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:10:12,875 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:12,875 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:10:12,875 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:12,877 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:12,888 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-09 16:10:12,889 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,889 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,893 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,894 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-09 16:10:12,895 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:12,905 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:12,905 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:12,905 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:12,905 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:12,905 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:12,905 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:12,905 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:12,907 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:12,916 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:12,917 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,917 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,918 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,918 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-09 16:10:12,919 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:12,928 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:12,928 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:12,929 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:12,929 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:12,929 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:12,929 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:12,929 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:12,930 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:12,940 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-09 16:10:12,940 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,941 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,941 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,942 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-09 16:10:12,943 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:12,952 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:12,952 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:12,952 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:12,952 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:12,952 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:12,953 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:12,953 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:12,954 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:12,964 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:12,964 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,964 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,965 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,966 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-09 16:10:12,966 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:12,976 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:12,976 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:12,976 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:12,976 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:12,976 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:12,976 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:12,976 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:12,978 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:12,987 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-09 16:10:12,988 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:12,988 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:12,989 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:12,989 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-09 16:10:12,991 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:13,000 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:13,000 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:13,000 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:13,000 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:13,000 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:13,000 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:13,001 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:13,002 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:13,012 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:13,012 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:13,013 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:13,013 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:13,014 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-09 16:10:13,015 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:13,024 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:13,024 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:13,024 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:13,024 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:10:13,024 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:13,025 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:10:13,025 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:13,026 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:13,036 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:13,036 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:13,036 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:13,037 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:13,038 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-09 16:10:13,039 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:13,048 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:13,048 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:13,048 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:13,049 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:13,049 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:13,049 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:13,049 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:13,050 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:13,060 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2024-11-09 16:10:13,060 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:13,060 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:13,061 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:13,062 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-09 16:10:13,062 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:13,072 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:13,072 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:13,072 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:13,072 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:13,072 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:13,073 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:13,073 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:13,074 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:13,083 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2024-11-09 16:10:13,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:13,084 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:13,085 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:13,086 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-09 16:10:13,087 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:13,096 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:13,096 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:13,096 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:13,096 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:13,096 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:13,097 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:13,097 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:13,098 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:13,107 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2024-11-09 16:10:13,108 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:13,108 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:13,109 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:13,110 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-09 16:10:13,110 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:13,119 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:13,119 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:13,120 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:13,120 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-09 16:10:13,120 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:13,120 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-09 16:10:13,120 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:13,122 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-09 16:10:13,134 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2024-11-09 16:10:13,135 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:13,135 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:13,136 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:13,136 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-09 16:10:13,137 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-09 16:10:13,146 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-09 16:10:13,147 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-09 16:10:13,147 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-09 16:10:13,147 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-09 16:10:13,147 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-09 16:10:13,148 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-09 16:10:13,148 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-09 16:10:13,150 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-09 16:10:13,153 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-09 16:10:13,153 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-09 16:10:13,154 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:10:13,154 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:10:13,156 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:10:13,159 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-09 16:10:13,159 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-09 16:10:13,159 INFO L474 LassoAnalysis]: Proved termination. [2024-11-09 16:10:13,160 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-09 16:10:13,160 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -2*~E_3~0 + 3 Supporting invariants [] [2024-11-09 16:10:13,171 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-09 16:10:13,173 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-09 16:10:13,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:10:13,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:10:13,271 INFO L255 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-09 16:10:13,274 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-09 16:10:13,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:10:13,459 INFO L255 TraceCheckSpWp]: Trace formula consists of 275 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-09 16:10:13,462 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-09 16:10:13,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:10:13,704 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-09 16:10:13,705 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 77244 states and 99268 transitions. cyclomatic complexity: 22056 Second operand has 4 states, 4 states have (on average 61.5) internal successors, (246), 4 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:14,363 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-09 16:10:14,687 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 77244 states and 99268 transitions. cyclomatic complexity: 22056. Second operand has 4 states, 4 states have (on average 61.5) internal successors, (246), 4 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 215310 states and 278071 transitions. Complement of second has 5 states. [2024-11-09 16:10:14,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-09 16:10:14,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 61.5) internal successors, (246), 4 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:10:14,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1446 transitions. [2024-11-09 16:10:14,695 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1446 transitions. Stem has 115 letters. Loop has 131 letters. [2024-11-09 16:10:14,698 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:10:14,698 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1446 transitions. Stem has 246 letters. Loop has 131 letters. [2024-11-09 16:10:14,699 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:10:14,699 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1446 transitions. Stem has 115 letters. Loop has 262 letters. [2024-11-09 16:10:14,701 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-09 16:10:14,701 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215310 states and 278071 transitions. [2024-11-09 16:10:15,569 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 145056