./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:51:56,317 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:51:56,387 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:51:56,393 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:51:56,394 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:51:56,395 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:51:56,422 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:51:56,423 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:51:56,423 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:51:56,423 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:51:56,424 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:51:56,425 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:51:56,426 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:51:56,426 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:51:56,426 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:51:56,427 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:51:56,427 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:51:56,427 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:51:56,427 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:51:56,428 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:51:56,428 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:51:56,433 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:51:56,433 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:51:56,433 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:51:56,433 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:51:56,434 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:51:56,434 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:51:56,434 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:51:56,434 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:51:56,435 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:51:56,435 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:51:56,435 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:51:56,435 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:51:56,435 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:51:56,435 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:51:56,436 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:51:56,436 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:51:56,436 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:51:56,436 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:51:56,437 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:51:56,437 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2024-11-17 08:51:56,748 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:51:56,774 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:51:56,776 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:51:56,777 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:51:56,780 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:51:56,782 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2024-11-17 08:51:58,173 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:51:58,373 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:51:58,374 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2024-11-17 08:51:58,388 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/09f43b805/5b1ce0673e834a53b54a15bdb3d75209/FLAG437966936 [2024-11-17 08:51:58,400 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/09f43b805/5b1ce0673e834a53b54a15bdb3d75209 [2024-11-17 08:51:58,403 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:51:58,404 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:51:58,405 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:51:58,406 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:51:58,411 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:51:58,411 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,412 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5591fd03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58, skipping insertion in model container [2024-11-17 08:51:58,412 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,447 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:51:58,727 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:51:58,742 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:51:58,798 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:51:58,821 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:51:58,822 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58 WrapperNode [2024-11-17 08:51:58,822 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:51:58,824 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:51:58,824 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:51:58,825 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:51:58,831 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,843 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,890 INFO L138 Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1066 [2024-11-17 08:51:58,891 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:51:58,891 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:51:58,891 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:51:58,892 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:51:58,906 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,906 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,913 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,933 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:51:58,933 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,937 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,953 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,955 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,960 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,968 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,974 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:51:58,975 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:51:58,975 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:51:58,975 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:51:58,976 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (1/1) ... [2024-11-17 08:51:58,982 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:51:58,993 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:51:59,008 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:51:59,009 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:51:59,083 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:51:59,083 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:51:59,083 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:51:59,083 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:51:59,186 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:51:59,189 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:00,045 INFO L? ?]: Removed 194 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:00,045 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:00,080 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:00,080 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:00,081 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:00 BoogieIcfgContainer [2024-11-17 08:52:00,081 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:00,082 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:00,082 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:00,086 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:00,088 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:00,088 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:51:58" (1/3) ... [2024-11-17 08:52:00,089 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1fc8db41 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:00, skipping insertion in model container [2024-11-17 08:52:00,089 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:00,089 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:51:58" (2/3) ... [2024-11-17 08:52:00,090 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1fc8db41 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:00, skipping insertion in model container [2024-11-17 08:52:00,090 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:00,090 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:00" (3/3) ... [2024-11-17 08:52:00,091 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2024-11-17 08:52:00,163 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:00,164 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:00,164 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:00,164 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:00,164 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:00,164 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:00,164 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:00,164 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:00,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 462 states, 461 states have (on average 1.4967462039045554) internal successors, (690), 461 states have internal predecessors, (690), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:00,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 390 [2024-11-17 08:52:00,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:00,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:00,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:00,218 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:00,218 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:00,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 462 states, 461 states have (on average 1.4967462039045554) internal successors, (690), 461 states have internal predecessors, (690), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:00,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 390 [2024-11-17 08:52:00,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:00,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:00,233 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:00,233 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:00,241 INFO L745 eck$LassoCheckResult]: Stem: 454#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 32#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 229#L766true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 248#L346-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 13#L358true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 115#L363true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 441#L368true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 104#L373true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 332#L379true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 269#L514-1true assume !(0 == ~M_E~0); 359#L519-1true assume !(0 == ~T1_E~0); 43#L524-1true assume !(0 == ~T2_E~0); 111#L529-1true assume !(0 == ~T3_E~0); 361#L534-1true assume !(0 == ~T4_E~0); 286#L539-1true assume !(0 == ~E_M~0); 328#L544-1true assume !(0 == ~E_1~0); 329#L549-1true assume !(0 == ~E_2~0); 368#L554-1true assume !(0 == ~E_3~0); 41#L559-1true assume !(0 == ~E_4~0); 18#L565-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 374#L250-7true assume 1 == ~m_pc~0; 380#L251-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 158#L253-7true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30#L262-7true assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 243#L637-7true assume !(0 != activate_threads_~tmp~1#1); 393#L643-7true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 287#L269-7true assume 1 == ~t1_pc~0; 20#L270-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 233#L272-7true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8#L281-7true assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 372#L645-7true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 120#L651-7true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 177#L288-7true assume 1 == ~t2_pc~0; 434#L289-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 439#L291-7true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97#L300-7true assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 444#L653-7true assume !(0 != activate_threads_~tmp___1~0#1); 51#L659-7true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 437#L307-7true assume 1 == ~t3_pc~0; 315#L308-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 319#L310-7true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 234#L319-7true assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 188#L661-7true assume !(0 != activate_threads_~tmp___2~0#1); 209#L667-7true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 406#L326-7true assume 1 == ~t4_pc~0; 436#L327-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 278#L329-7true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131#L338-7true assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 113#L669-7true assume !(0 != activate_threads_~tmp___3~0#1); 6#L675-7true assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76#L572-1true assume !(1 == ~M_E~0); 48#L577-1true assume !(1 == ~T1_E~0); 263#L582-1true assume !(1 == ~T2_E~0); 271#L587-1true assume !(1 == ~T3_E~0); 404#L592-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 14#L597-1true assume !(1 == ~E_M~0); 440#L602-1true assume !(1 == ~E_1~0); 151#L607-1true assume !(1 == ~E_2~0); 443#L612-1true assume !(1 == ~E_3~0); 110#L617-1true assume !(1 == ~E_4~0); 296#L623-1true assume true;assume { :end_inline_reset_delta_events } true; 244#L803true [2024-11-17 08:52:00,243 INFO L747 eck$LassoCheckResult]: Loop: 244#L803true assume true; 56#L803-1true assume !false; 137#start_simulation_while_6_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21#L423true assume !true; 218#L431true assume true; 379#L507true assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47#L346true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75#L514true assume 0 == ~M_E~0;~M_E~0 := 1; 183#L519true assume 0 == ~T1_E~0;~T1_E~0 := 1; 383#L524true assume 0 == ~T2_E~0;~T2_E~0 := 1; 321#L529true assume 0 == ~T3_E~0;~T3_E~0 := 1; 317#L534true assume !(0 == ~T4_E~0); 282#L539true assume 0 == ~E_M~0;~E_M~0 := 1; 337#L544true assume 0 == ~E_1~0;~E_1~0 := 1; 50#L549true assume 0 == ~E_2~0;~E_2~0 := 1; 225#L554true assume 0 == ~E_3~0;~E_3~0 := 1; 149#L559true assume 0 == ~E_4~0;~E_4~0 := 1; 377#L565true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 324#L250-1true assume !(1 == ~m_pc~0); 428#L260-1true is_master_triggered_~__retres1~0#1 := 0; 247#L253-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 255#L262-1true assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 66#L637-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 322#L643-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327#L269-1true assume 1 == ~t1_pc~0; 16#L270-1true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 364#L272-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 323#L281-1true assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102#L645-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 415#L651-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163#L288-1true assume 1 == ~t2_pc~0; 2#L289-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 157#L291-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 277#L300-1true assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 402#L653-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 250#L659-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 384#L307-1true assume !(1 == ~t3_pc~0); 122#L317-1true is_transmit3_triggered_~__retres1~3#1 := 0; 422#L310-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 334#L319-1true assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 302#L661-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 198#L667-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 249#L326-1true assume 1 == ~t4_pc~0; 201#L327-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 284#L329-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91#L338-1true assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39#L669-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 185#L675-1true assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336#L572true assume 1 == ~M_E~0;~M_E~0 := 2; 162#L577true assume 1 == ~T1_E~0;~T1_E~0 := 2; 460#L582true assume 1 == ~T2_E~0;~T2_E~0 := 2; 355#L587true assume 1 == ~T3_E~0;~T3_E~0 := 2; 241#L592true assume 1 == ~T4_E~0;~T4_E~0 := 2; 345#L597true assume 1 == ~E_M~0;~E_M~0 := 2; 12#L602true assume 1 == ~E_1~0;~E_1~0 := 2; 267#L607true assume 1 == ~E_2~0;~E_2~0 := 2; 227#L612true assume 1 == ~E_3~0;~E_3~0 := 2; 411#L617true assume 1 == ~E_4~0;~E_4~0 := 2; 228#L623true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 144#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 446#L404-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 405#L414-1true assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 174#L822true assume !(0 == start_simulation_~tmp~3#1); 49#L833true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 178#L386true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 103#L404true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 455#L414true assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 27#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 369#L779true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 220#L785true assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 351#L835true assume !(0 != start_simulation_~tmp___0~1#1); 244#L803true [2024-11-17 08:52:00,249 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:00,249 INFO L85 PathProgramCache]: Analyzing trace with hash 1381072353, now seen corresponding path program 1 times [2024-11-17 08:52:00,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:00,258 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479850269] [2024-11-17 08:52:00,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:00,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:00,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:00,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:00,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:00,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479850269] [2024-11-17 08:52:00,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [479850269] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:00,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:00,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:00,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36294303] [2024-11-17 08:52:00,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:00,522 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:00,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:00,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1442950735, now seen corresponding path program 1 times [2024-11-17 08:52:00,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:00,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796750205] [2024-11-17 08:52:00,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:00,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:00,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:00,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:00,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:00,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796750205] [2024-11-17 08:52:00,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796750205] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:00,611 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:00,611 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:00,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109890740] [2024-11-17 08:52:00,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:00,613 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:00,613 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:00,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:00,641 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:00,643 INFO L87 Difference]: Start difference. First operand has 462 states, 461 states have (on average 1.4967462039045554) internal successors, (690), 461 states have internal predecessors, (690), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:00,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:00,712 INFO L93 Difference]: Finished difference Result 455 states and 667 transitions. [2024-11-17 08:52:00,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 455 states and 667 transitions. [2024-11-17 08:52:00,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:00,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 455 states to 449 states and 661 transitions. [2024-11-17 08:52:00,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2024-11-17 08:52:00,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2024-11-17 08:52:00,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 661 transitions. [2024-11-17 08:52:00,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:00,743 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 661 transitions. [2024-11-17 08:52:00,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 661 transitions. [2024-11-17 08:52:00,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2024-11-17 08:52:00,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.4721603563474388) internal successors, (661), 448 states have internal predecessors, (661), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:00,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 661 transitions. [2024-11-17 08:52:00,785 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449 states and 661 transitions. [2024-11-17 08:52:00,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:00,790 INFO L425 stractBuchiCegarLoop]: Abstraction has 449 states and 661 transitions. [2024-11-17 08:52:00,791 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:00,791 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 661 transitions. [2024-11-17 08:52:00,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:00,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:00,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:00,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:00,796 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:00,797 INFO L745 eck$LassoCheckResult]: Stem: 1374#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 991#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 992#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1286#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1082#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 950#L358 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 951#L363 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1128#L368 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1108#L373 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1109#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1317#L514-1 assume !(0 == ~M_E~0); 1318#L519-1 assume !(0 == ~T1_E~0); 1011#L524-1 assume !(0 == ~T2_E~0); 1012#L529-1 assume !(0 == ~T3_E~0); 1124#L534-1 assume !(0 == ~T4_E~0); 1330#L539-1 assume !(0 == ~E_M~0); 1331#L544-1 assume !(0 == ~E_1~0); 1355#L549-1 assume !(0 == ~E_2~0); 1356#L554-1 assume !(0 == ~E_3~0); 1007#L559-1 assume !(0 == ~E_4~0); 963#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 964#L250-7 assume 1 == ~m_pc~0; 1364#L251-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1141#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 987#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 988#L637-7 assume !(0 != activate_threads_~tmp~1#1); 1296#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1332#L269-7 assume 1 == ~t1_pc~0; 966#L270-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 967#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 939#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 940#L645-7 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1135#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1136#L288-7 assume 1 == ~t2_pc~0; 1217#L289-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1359#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1095#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1096#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 1026#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1027#L307-7 assume 1 == ~t3_pc~0; 1348#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1221#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1290#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1232#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 1233#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1258#L326-7 assume 1 == ~t4_pc~0; 1370#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1205#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1152#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1125#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 935#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 936#L572-1 assume !(1 == ~M_E~0); 1020#L577-1 assume !(1 == ~T1_E~0); 1021#L582-1 assume !(1 == ~T2_E~0); 1315#L587-1 assume !(1 == ~T3_E~0); 1319#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 952#L597-1 assume !(1 == ~E_M~0); 953#L602-1 assume !(1 == ~E_1~0); 1179#L607-1 assume !(1 == ~E_2~0); 1180#L612-1 assume !(1 == ~E_3~0); 1122#L617-1 assume !(1 == ~E_4~0); 1123#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 1297#L803 [2024-11-17 08:52:00,797 INFO L747 eck$LassoCheckResult]: Loop: 1297#L803 assume true; 1037#L803-1 assume !false; 1038#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 969#L423 assume true; 970#L423-1 assume !false; 1292#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1293#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1257#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1214#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1215#L428 assume !(0 != eval_~tmp~0#1); 1271#L431 assume true; 1272#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1018#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1019#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 1065#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1225#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1351#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1349#L534 assume !(0 == ~T4_E~0); 1325#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 1326#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 1024#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 1025#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 1176#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 1177#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1354#L250-1 assume 1 == ~m_pc~0; 1312#L251-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1299#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1300#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1051#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1052#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1352#L269-1 assume 1 == ~t1_pc~0; 957#L270-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 958#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1353#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1105#L645-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1106#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1198#L288-1 assume !(1 == ~t2_pc~0); 928#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 927#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1189#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1321#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1301#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1302#L307-1 assume !(1 == ~t3_pc~0); 1138#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1139#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1358#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1337#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1242#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1243#L326-1 assume !(1 == ~t4_pc~0); 1248#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1249#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1084#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1003#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1004#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1227#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 1196#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1197#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1362#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1294#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1295#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 948#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 949#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 1283#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 1284#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 1285#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1169#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1132#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1369#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1212#L822 assume !(0 == start_simulation_~tmp~3#1); 1022#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1023#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1070#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1107#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 981#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 982#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1274#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1275#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1297#L803 [2024-11-17 08:52:00,798 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:00,799 INFO L85 PathProgramCache]: Analyzing trace with hash -983275838, now seen corresponding path program 1 times [2024-11-17 08:52:00,799 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:00,799 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2061993924] [2024-11-17 08:52:00,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:00,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:00,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:00,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:00,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:00,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2061993924] [2024-11-17 08:52:00,890 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2061993924] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:00,890 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:00,891 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:00,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654775689] [2024-11-17 08:52:00,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:00,891 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:00,892 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:00,892 INFO L85 PathProgramCache]: Analyzing trace with hash -264488071, now seen corresponding path program 1 times [2024-11-17 08:52:00,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:00,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625531251] [2024-11-17 08:52:00,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:00,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:00,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625531251] [2024-11-17 08:52:01,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625531251] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:01,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [207996418] [2024-11-17 08:52:01,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,067 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:01,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:01,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:01,068 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:01,069 INFO L87 Difference]: Start difference. First operand 449 states and 661 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:01,092 INFO L93 Difference]: Finished difference Result 449 states and 660 transitions. [2024-11-17 08:52:01,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 660 transitions. [2024-11-17 08:52:01,096 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:01,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 660 transitions. [2024-11-17 08:52:01,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2024-11-17 08:52:01,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2024-11-17 08:52:01,103 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 660 transitions. [2024-11-17 08:52:01,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:01,108 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 660 transitions. [2024-11-17 08:52:01,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 660 transitions. [2024-11-17 08:52:01,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2024-11-17 08:52:01,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.469933184855234) internal successors, (660), 448 states have internal predecessors, (660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 660 transitions. [2024-11-17 08:52:01,127 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449 states and 660 transitions. [2024-11-17 08:52:01,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:01,129 INFO L425 stractBuchiCegarLoop]: Abstraction has 449 states and 660 transitions. [2024-11-17 08:52:01,130 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:01,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 660 transitions. [2024-11-17 08:52:01,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:01,133 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:01,133 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:01,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,135 INFO L745 eck$LassoCheckResult]: Stem: 2281#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1898#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1899#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2193#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1989#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1857#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1858#L363 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2035#L368 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2015#L373 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2016#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2224#L514-1 assume !(0 == ~M_E~0); 2225#L519-1 assume !(0 == ~T1_E~0); 1918#L524-1 assume !(0 == ~T2_E~0); 1919#L529-1 assume !(0 == ~T3_E~0); 2031#L534-1 assume !(0 == ~T4_E~0); 2237#L539-1 assume !(0 == ~E_M~0); 2238#L544-1 assume !(0 == ~E_1~0); 2262#L549-1 assume !(0 == ~E_2~0); 2263#L554-1 assume !(0 == ~E_3~0); 1914#L559-1 assume !(0 == ~E_4~0); 1870#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1871#L250-7 assume 1 == ~m_pc~0; 2271#L251-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2048#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1894#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1895#L637-7 assume !(0 != activate_threads_~tmp~1#1); 2203#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2239#L269-7 assume 1 == ~t1_pc~0; 1873#L270-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1874#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1846#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1847#L645-7 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2042#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2043#L288-7 assume 1 == ~t2_pc~0; 2124#L289-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2266#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2002#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2003#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 1933#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1934#L307-7 assume 1 == ~t3_pc~0; 2255#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2128#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2197#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2139#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 2140#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2165#L326-7 assume 1 == ~t4_pc~0; 2277#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2112#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2059#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2032#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 1842#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1843#L572-1 assume !(1 == ~M_E~0); 1927#L577-1 assume !(1 == ~T1_E~0); 1928#L582-1 assume !(1 == ~T2_E~0); 2222#L587-1 assume !(1 == ~T3_E~0); 2226#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1859#L597-1 assume !(1 == ~E_M~0); 1860#L602-1 assume !(1 == ~E_1~0); 2086#L607-1 assume !(1 == ~E_2~0); 2087#L612-1 assume !(1 == ~E_3~0); 2029#L617-1 assume !(1 == ~E_4~0); 2030#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 2204#L803 [2024-11-17 08:52:01,136 INFO L747 eck$LassoCheckResult]: Loop: 2204#L803 assume true; 1944#L803-1 assume !false; 1945#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1876#L423 assume true; 1877#L423-1 assume !false; 2199#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2200#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2164#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2121#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2122#L428 assume !(0 != eval_~tmp~0#1); 2178#L431 assume true; 2179#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1925#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1926#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 1972#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2132#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2258#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2256#L534 assume !(0 == ~T4_E~0); 2232#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 2233#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 1931#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 1932#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 2083#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 2084#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2261#L250-1 assume 1 == ~m_pc~0; 2219#L251-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2206#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2207#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1958#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1959#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2259#L269-1 assume 1 == ~t1_pc~0; 1864#L270-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1865#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2260#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2012#L645-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2013#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2105#L288-1 assume 1 == ~t2_pc~0; 1833#L289-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1834#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2096#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2228#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2208#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2209#L307-1 assume 1 == ~t3_pc~0; 2215#L308-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2046#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2265#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2244#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2149#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2150#L326-1 assume 1 == ~t4_pc~0; 2154#L327-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2156#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1991#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1910#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1911#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2134#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 2103#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2104#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2269#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2201#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2202#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 1855#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 1856#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 2190#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 2191#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 2192#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2076#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2039#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2276#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2119#L822 assume !(0 == start_simulation_~tmp~3#1); 1929#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1930#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1977#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2014#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 1888#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1889#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2181#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2182#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2204#L803 [2024-11-17 08:52:01,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1613734463, now seen corresponding path program 1 times [2024-11-17 08:52:01,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955586917] [2024-11-17 08:52:01,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955586917] [2024-11-17 08:52:01,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955586917] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,191 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:01,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221272769] [2024-11-17 08:52:01,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,191 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:01,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,192 INFO L85 PathProgramCache]: Analyzing trace with hash -577706768, now seen corresponding path program 1 times [2024-11-17 08:52:01,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965220742] [2024-11-17 08:52:01,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,287 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,288 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965220742] [2024-11-17 08:52:01,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965220742] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,288 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,288 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:01,288 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1744064191] [2024-11-17 08:52:01,288 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,289 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:01,289 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:01,289 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:01,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:01,289 INFO L87 Difference]: Start difference. First operand 449 states and 660 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:01,305 INFO L93 Difference]: Finished difference Result 449 states and 659 transitions. [2024-11-17 08:52:01,305 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 659 transitions. [2024-11-17 08:52:01,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:01,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 659 transitions. [2024-11-17 08:52:01,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2024-11-17 08:52:01,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2024-11-17 08:52:01,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 659 transitions. [2024-11-17 08:52:01,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:01,313 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 659 transitions. [2024-11-17 08:52:01,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 659 transitions. [2024-11-17 08:52:01,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2024-11-17 08:52:01,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.4677060133630289) internal successors, (659), 448 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 659 transitions. [2024-11-17 08:52:01,325 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449 states and 659 transitions. [2024-11-17 08:52:01,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:01,326 INFO L425 stractBuchiCegarLoop]: Abstraction has 449 states and 659 transitions. [2024-11-17 08:52:01,327 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:01,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 659 transitions. [2024-11-17 08:52:01,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:01,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:01,329 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:01,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,333 INFO L745 eck$LassoCheckResult]: Stem: 3188#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2805#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2806#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3100#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2896#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2764#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2765#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2942#L368 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2922#L373 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2923#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3131#L514-1 assume !(0 == ~M_E~0); 3132#L519-1 assume !(0 == ~T1_E~0); 2825#L524-1 assume !(0 == ~T2_E~0); 2826#L529-1 assume !(0 == ~T3_E~0); 2938#L534-1 assume !(0 == ~T4_E~0); 3144#L539-1 assume !(0 == ~E_M~0); 3145#L544-1 assume !(0 == ~E_1~0); 3169#L549-1 assume !(0 == ~E_2~0); 3170#L554-1 assume !(0 == ~E_3~0); 2821#L559-1 assume !(0 == ~E_4~0); 2777#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2778#L250-7 assume 1 == ~m_pc~0; 3178#L251-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2955#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2801#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2802#L637-7 assume !(0 != activate_threads_~tmp~1#1); 3110#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3146#L269-7 assume 1 == ~t1_pc~0; 2780#L270-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2781#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2753#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2754#L645-7 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2949#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2950#L288-7 assume 1 == ~t2_pc~0; 3031#L289-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3173#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2909#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2910#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 2840#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2841#L307-7 assume 1 == ~t3_pc~0; 3162#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3035#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3104#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3046#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 3047#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3072#L326-7 assume 1 == ~t4_pc~0; 3184#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3019#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2966#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2939#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 2749#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2750#L572-1 assume !(1 == ~M_E~0); 2834#L577-1 assume !(1 == ~T1_E~0); 2835#L582-1 assume !(1 == ~T2_E~0); 3129#L587-1 assume !(1 == ~T3_E~0); 3133#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2766#L597-1 assume !(1 == ~E_M~0); 2767#L602-1 assume !(1 == ~E_1~0); 2993#L607-1 assume !(1 == ~E_2~0); 2994#L612-1 assume !(1 == ~E_3~0); 2936#L617-1 assume !(1 == ~E_4~0); 2937#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 3111#L803 [2024-11-17 08:52:01,334 INFO L747 eck$LassoCheckResult]: Loop: 3111#L803 assume true; 2851#L803-1 assume !false; 2852#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2783#L423 assume true; 2784#L423-1 assume !false; 3106#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3107#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3071#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3028#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3029#L428 assume !(0 != eval_~tmp~0#1); 3085#L431 assume true; 3086#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2832#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2833#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 2879#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3039#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3165#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3163#L534 assume !(0 == ~T4_E~0); 3139#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 3140#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 2838#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 2839#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 2990#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 2991#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3168#L250-1 assume 1 == ~m_pc~0; 3126#L251-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3113#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3114#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2865#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2866#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3166#L269-1 assume 1 == ~t1_pc~0; 2771#L270-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2772#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3167#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2919#L645-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2920#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3012#L288-1 assume 1 == ~t2_pc~0; 2740#L289-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2741#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3003#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3135#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3115#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3116#L307-1 assume 1 == ~t3_pc~0; 3122#L308-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2953#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3172#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3151#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3056#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3057#L326-1 assume 1 == ~t4_pc~0; 3061#L327-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3063#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2898#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2817#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2818#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3041#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 3010#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3011#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3176#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3108#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3109#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 2762#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 2763#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 3097#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 3098#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 3099#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2983#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2946#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3183#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3026#L822 assume !(0 == start_simulation_~tmp~3#1); 2836#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2837#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2884#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2921#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2795#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2796#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3088#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3089#L835 assume !(0 != start_simulation_~tmp___0~1#1); 3111#L803 [2024-11-17 08:52:01,336 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1634071838, now seen corresponding path program 1 times [2024-11-17 08:52:01,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353717712] [2024-11-17 08:52:01,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353717712] [2024-11-17 08:52:01,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353717712] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:01,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2009994113] [2024-11-17 08:52:01,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,388 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:01,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,388 INFO L85 PathProgramCache]: Analyzing trace with hash -577706768, now seen corresponding path program 2 times [2024-11-17 08:52:01,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992835216] [2024-11-17 08:52:01,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992835216] [2024-11-17 08:52:01,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992835216] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,469 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:01,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [493052357] [2024-11-17 08:52:01,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,469 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:01,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:01,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:01,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:01,470 INFO L87 Difference]: Start difference. First operand 449 states and 659 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:01,482 INFO L93 Difference]: Finished difference Result 449 states and 658 transitions. [2024-11-17 08:52:01,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 658 transitions. [2024-11-17 08:52:01,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:01,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 658 transitions. [2024-11-17 08:52:01,489 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2024-11-17 08:52:01,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2024-11-17 08:52:01,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 658 transitions. [2024-11-17 08:52:01,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:01,490 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 658 transitions. [2024-11-17 08:52:01,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 658 transitions. [2024-11-17 08:52:01,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2024-11-17 08:52:01,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.465478841870824) internal successors, (658), 448 states have internal predecessors, (658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 658 transitions. [2024-11-17 08:52:01,498 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449 states and 658 transitions. [2024-11-17 08:52:01,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:01,501 INFO L425 stractBuchiCegarLoop]: Abstraction has 449 states and 658 transitions. [2024-11-17 08:52:01,501 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:01,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 658 transitions. [2024-11-17 08:52:01,504 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:01,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:01,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:01,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,507 INFO L745 eck$LassoCheckResult]: Stem: 4095#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3712#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3713#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4007#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3803#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 3671#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3672#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3849#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3829#L373 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3830#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4038#L514-1 assume !(0 == ~M_E~0); 4039#L519-1 assume !(0 == ~T1_E~0); 3732#L524-1 assume !(0 == ~T2_E~0); 3733#L529-1 assume !(0 == ~T3_E~0); 3845#L534-1 assume !(0 == ~T4_E~0); 4051#L539-1 assume !(0 == ~E_M~0); 4052#L544-1 assume !(0 == ~E_1~0); 4076#L549-1 assume !(0 == ~E_2~0); 4077#L554-1 assume !(0 == ~E_3~0); 3728#L559-1 assume !(0 == ~E_4~0); 3684#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3685#L250-7 assume 1 == ~m_pc~0; 4085#L251-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3862#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3708#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3709#L637-7 assume !(0 != activate_threads_~tmp~1#1); 4017#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4053#L269-7 assume 1 == ~t1_pc~0; 3687#L270-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3688#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3660#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3661#L645-7 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3856#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3857#L288-7 assume 1 == ~t2_pc~0; 3938#L289-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4080#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3816#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3817#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 3747#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3748#L307-7 assume 1 == ~t3_pc~0; 4069#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3942#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4011#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3953#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 3954#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3979#L326-7 assume 1 == ~t4_pc~0; 4091#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3926#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3873#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3846#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 3656#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3657#L572-1 assume !(1 == ~M_E~0); 3741#L577-1 assume !(1 == ~T1_E~0); 3742#L582-1 assume !(1 == ~T2_E~0); 4036#L587-1 assume !(1 == ~T3_E~0); 4040#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3673#L597-1 assume !(1 == ~E_M~0); 3674#L602-1 assume !(1 == ~E_1~0); 3900#L607-1 assume !(1 == ~E_2~0); 3901#L612-1 assume !(1 == ~E_3~0); 3843#L617-1 assume !(1 == ~E_4~0); 3844#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 4018#L803 [2024-11-17 08:52:01,508 INFO L747 eck$LassoCheckResult]: Loop: 4018#L803 assume true; 3758#L803-1 assume !false; 3759#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3690#L423 assume true; 3691#L423-1 assume !false; 4013#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4014#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3978#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3935#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3936#L428 assume !(0 != eval_~tmp~0#1); 3992#L431 assume true; 3993#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3739#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3740#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 3786#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3946#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4072#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4070#L534 assume !(0 == ~T4_E~0); 4046#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 4047#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 3745#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 3746#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 3897#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 3898#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4075#L250-1 assume 1 == ~m_pc~0; 4033#L251-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4020#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4021#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3772#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3773#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4073#L269-1 assume !(1 == ~t1_pc~0); 3680#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 3679#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4074#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3826#L645-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3827#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3919#L288-1 assume !(1 == ~t2_pc~0); 3649#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 3648#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3910#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4042#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4022#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4023#L307-1 assume !(1 == ~t3_pc~0); 3859#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 3860#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4079#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4058#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3963#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3964#L326-1 assume 1 == ~t4_pc~0; 3968#L327-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3970#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3805#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3724#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3725#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3948#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 3917#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3918#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4083#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4015#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4016#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 3669#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 3670#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 4004#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 4005#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 4006#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3890#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3853#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4090#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3933#L822 assume !(0 == start_simulation_~tmp~3#1); 3743#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3744#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3791#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3828#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 3702#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3703#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3995#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3996#L835 assume !(0 != start_simulation_~tmp___0~1#1); 4018#L803 [2024-11-17 08:52:01,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,510 INFO L85 PathProgramCache]: Analyzing trace with hash 1967502753, now seen corresponding path program 1 times [2024-11-17 08:52:01,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188147606] [2024-11-17 08:52:01,511 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,568 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,568 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188147606] [2024-11-17 08:52:01,568 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188147606] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,568 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,568 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:01,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1063074614] [2024-11-17 08:52:01,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,569 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:01,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,569 INFO L85 PathProgramCache]: Analyzing trace with hash -1424396103, now seen corresponding path program 1 times [2024-11-17 08:52:01,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438043139] [2024-11-17 08:52:01,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438043139] [2024-11-17 08:52:01,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438043139] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,663 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:01,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885044616] [2024-11-17 08:52:01,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,664 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:01,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:01,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:01,664 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:01,664 INFO L87 Difference]: Start difference. First operand 449 states and 658 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:01,685 INFO L93 Difference]: Finished difference Result 449 states and 657 transitions. [2024-11-17 08:52:01,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 657 transitions. [2024-11-17 08:52:01,687 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:01,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 657 transitions. [2024-11-17 08:52:01,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2024-11-17 08:52:01,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2024-11-17 08:52:01,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 657 transitions. [2024-11-17 08:52:01,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:01,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 657 transitions. [2024-11-17 08:52:01,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 657 transitions. [2024-11-17 08:52:01,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2024-11-17 08:52:01,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 449 states, 449 states have (on average 1.4632516703786191) internal successors, (657), 448 states have internal predecessors, (657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 657 transitions. [2024-11-17 08:52:01,698 INFO L240 hiAutomatonCegarLoop]: Abstraction has 449 states and 657 transitions. [2024-11-17 08:52:01,698 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:01,699 INFO L425 stractBuchiCegarLoop]: Abstraction has 449 states and 657 transitions. [2024-11-17 08:52:01,699 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:01,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 449 states and 657 transitions. [2024-11-17 08:52:01,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 382 [2024-11-17 08:52:01,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:01,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:01,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,705 INFO L745 eck$LassoCheckResult]: Stem: 5002#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4619#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4620#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4914#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4710#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4578#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4579#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4756#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4736#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4737#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4945#L514-1 assume !(0 == ~M_E~0); 4946#L519-1 assume !(0 == ~T1_E~0); 4639#L524-1 assume !(0 == ~T2_E~0); 4640#L529-1 assume !(0 == ~T3_E~0); 4752#L534-1 assume !(0 == ~T4_E~0); 4958#L539-1 assume !(0 == ~E_M~0); 4959#L544-1 assume !(0 == ~E_1~0); 4983#L549-1 assume !(0 == ~E_2~0); 4984#L554-1 assume !(0 == ~E_3~0); 4635#L559-1 assume !(0 == ~E_4~0); 4591#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4592#L250-7 assume 1 == ~m_pc~0; 4992#L251-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4769#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4615#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4616#L637-7 assume !(0 != activate_threads_~tmp~1#1); 4924#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4960#L269-7 assume 1 == ~t1_pc~0; 4594#L270-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4595#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4567#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4568#L645-7 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4763#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4764#L288-7 assume 1 == ~t2_pc~0; 4845#L289-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4987#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4723#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4724#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 4654#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4655#L307-7 assume 1 == ~t3_pc~0; 4976#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4849#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4918#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4860#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 4861#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4886#L326-7 assume 1 == ~t4_pc~0; 4998#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4833#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4780#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4753#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 4563#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4564#L572-1 assume !(1 == ~M_E~0); 4648#L577-1 assume !(1 == ~T1_E~0); 4649#L582-1 assume !(1 == ~T2_E~0); 4943#L587-1 assume !(1 == ~T3_E~0); 4947#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4580#L597-1 assume !(1 == ~E_M~0); 4581#L602-1 assume !(1 == ~E_1~0); 4807#L607-1 assume !(1 == ~E_2~0); 4808#L612-1 assume !(1 == ~E_3~0); 4750#L617-1 assume !(1 == ~E_4~0); 4751#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 4925#L803 [2024-11-17 08:52:01,705 INFO L747 eck$LassoCheckResult]: Loop: 4925#L803 assume true; 4665#L803-1 assume !false; 4666#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4597#L423 assume true; 4598#L423-1 assume !false; 4920#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4921#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4885#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4842#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4843#L428 assume !(0 != eval_~tmp~0#1); 4899#L431 assume true; 4900#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4646#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4647#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 4693#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4853#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4979#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4977#L534 assume !(0 == ~T4_E~0); 4953#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 4954#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 4652#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 4653#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 4804#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 4805#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4982#L250-1 assume 1 == ~m_pc~0; 4940#L251-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4927#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4928#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4679#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4680#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4980#L269-1 assume 1 == ~t1_pc~0; 4585#L270-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4586#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4981#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4733#L645-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4734#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4826#L288-1 assume 1 == ~t2_pc~0; 4554#L289-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4555#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4817#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4949#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4929#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4930#L307-1 assume 1 == ~t3_pc~0; 4936#L308-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4767#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4986#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4965#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4870#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4871#L326-1 assume 1 == ~t4_pc~0; 4875#L327-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4877#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4712#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4631#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4632#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4855#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 4824#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4825#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4990#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4922#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4923#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 4576#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 4577#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 4911#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 4912#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 4913#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4797#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4760#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4997#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4840#L822 assume !(0 == start_simulation_~tmp~3#1); 4650#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4651#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4698#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4735#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4609#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4610#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4902#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4903#L835 assume !(0 != start_simulation_~tmp___0~1#1); 4925#L803 [2024-11-17 08:52:01,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1529493250, now seen corresponding path program 1 times [2024-11-17 08:52:01,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581547148] [2024-11-17 08:52:01,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581547148] [2024-11-17 08:52:01,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581547148] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:01,763 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103308384] [2024-11-17 08:52:01,763 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,763 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:01,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,764 INFO L85 PathProgramCache]: Analyzing trace with hash -577706768, now seen corresponding path program 3 times [2024-11-17 08:52:01,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027162269] [2024-11-17 08:52:01,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027162269] [2024-11-17 08:52:01,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027162269] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:01,819 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818174328] [2024-11-17 08:52:01,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,820 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:01,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:01,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:01,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:01,820 INFO L87 Difference]: Start difference. First operand 449 states and 657 transitions. cyclomatic complexity: 209 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:01,895 INFO L93 Difference]: Finished difference Result 819 states and 1183 transitions. [2024-11-17 08:52:01,895 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 819 states and 1183 transitions. [2024-11-17 08:52:01,900 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 751 [2024-11-17 08:52:01,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 819 states to 819 states and 1183 transitions. [2024-11-17 08:52:01,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 819 [2024-11-17 08:52:01,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 819 [2024-11-17 08:52:01,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 819 states and 1183 transitions. [2024-11-17 08:52:01,905 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:01,905 INFO L218 hiAutomatonCegarLoop]: Abstraction has 819 states and 1183 transitions. [2024-11-17 08:52:01,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 819 states and 1183 transitions. [2024-11-17 08:52:01,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 819 to 785. [2024-11-17 08:52:01,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 785 states, 785 states have (on average 1.4471337579617833) internal successors, (1136), 784 states have internal predecessors, (1136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 785 states to 785 states and 1136 transitions. [2024-11-17 08:52:01,922 INFO L240 hiAutomatonCegarLoop]: Abstraction has 785 states and 1136 transitions. [2024-11-17 08:52:01,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:01,924 INFO L425 stractBuchiCegarLoop]: Abstraction has 785 states and 1136 transitions. [2024-11-17 08:52:01,924 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:52:01,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 785 states and 1136 transitions. [2024-11-17 08:52:01,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 717 [2024-11-17 08:52:01,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:01,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:01,929 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,929 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,930 INFO L745 eck$LassoCheckResult]: Stem: 6295#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5896#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5897#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6191#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5987#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 5855#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5856#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6032#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6013#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6014#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6225#L514-1 assume !(0 == ~M_E~0); 6226#L519-1 assume !(0 == ~T1_E~0); 5916#L524-1 assume !(0 == ~T2_E~0); 5917#L529-1 assume !(0 == ~T3_E~0); 6028#L534-1 assume !(0 == ~T4_E~0); 6238#L539-1 assume !(0 == ~E_M~0); 6239#L544-1 assume !(0 == ~E_1~0); 6265#L549-1 assume !(0 == ~E_2~0); 6266#L554-1 assume !(0 == ~E_3~0); 5912#L559-1 assume !(0 == ~E_4~0); 5868#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5869#L250-7 assume !(1 == ~m_pc~0); 6045#L260-7 is_master_triggered_~__retres1~0#1 := 0; 6046#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5892#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5893#L637-7 assume !(0 != activate_threads_~tmp~1#1); 6201#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6240#L269-7 assume 1 == ~t1_pc~0; 5871#L270-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5872#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5844#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5845#L645-7 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6040#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6041#L288-7 assume 1 == ~t2_pc~0; 6122#L289-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6271#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6000#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6001#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 5931#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5932#L307-7 assume 1 == ~t3_pc~0; 6257#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6126#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6195#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6136#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 6137#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6163#L326-7 assume 1 == ~t4_pc~0; 6285#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6109#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6057#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6029#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 5840#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5841#L572-1 assume !(1 == ~M_E~0); 5925#L577-1 assume !(1 == ~T1_E~0); 5926#L582-1 assume !(1 == ~T2_E~0); 6223#L587-1 assume !(1 == ~T3_E~0); 6227#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5857#L597-1 assume !(1 == ~E_M~0); 5858#L602-1 assume !(1 == ~E_1~0); 6083#L607-1 assume !(1 == ~E_2~0); 6084#L612-1 assume !(1 == ~E_3~0); 6026#L617-1 assume !(1 == ~E_4~0); 6027#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 6243#L803 [2024-11-17 08:52:01,930 INFO L747 eck$LassoCheckResult]: Loop: 6243#L803 assume true; 6374#L803-1 assume !false; 6370#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6366#L423 assume true; 6358#L423-1 assume !false; 6352#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6345#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6339#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6335#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6331#L428 assume !(0 != eval_~tmp~0#1); 6176#L431 assume true; 6177#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5923#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5924#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 5970#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6130#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6260#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6258#L534 assume !(0 == ~T4_E~0); 6233#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 6234#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 5929#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 5930#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 6080#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 6081#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6263#L250-1 assume !(1 == ~m_pc~0); 6264#L260-1 is_master_triggered_~__retres1~0#1 := 0; 6204#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6205#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5956#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5957#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6261#L269-1 assume 1 == ~t1_pc~0; 5862#L270-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5863#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6262#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6010#L645-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6011#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6102#L288-1 assume 1 == ~t2_pc~0; 5831#L289-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5832#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6090#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6229#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6208#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6209#L307-1 assume 1 == ~t3_pc~0; 6215#L308-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6044#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6268#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6246#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6147#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6148#L326-1 assume 1 == ~t4_pc~0; 6152#L327-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6154#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5989#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5908#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5909#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6132#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 6100#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6101#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6276#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6199#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6200#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 5853#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 5854#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 6188#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 6189#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 6190#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6073#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6036#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6284#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 6116#L822 assume !(0 == start_simulation_~tmp~3#1); 6118#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6479#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6476#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6414#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 6407#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6401#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6394#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6388#L835 assume !(0 != start_simulation_~tmp___0~1#1); 6243#L803 [2024-11-17 08:52:01,931 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,931 INFO L85 PathProgramCache]: Analyzing trace with hash 965640261, now seen corresponding path program 1 times [2024-11-17 08:52:01,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582697318] [2024-11-17 08:52:01,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,971 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582697318] [2024-11-17 08:52:01,971 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582697318] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,971 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:01,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796456788] [2024-11-17 08:52:01,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,972 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:01,972 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,972 INFO L85 PathProgramCache]: Analyzing trace with hash 253387187, now seen corresponding path program 1 times [2024-11-17 08:52:01,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741527163] [2024-11-17 08:52:01,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741527163] [2024-11-17 08:52:02,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741527163] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897360958] [2024-11-17 08:52:02,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,023 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,023 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:02,023 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:02,024 INFO L87 Difference]: Start difference. First operand 785 states and 1136 transitions. cyclomatic complexity: 353 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,080 INFO L93 Difference]: Finished difference Result 1415 states and 2030 transitions. [2024-11-17 08:52:02,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1415 states and 2030 transitions. [2024-11-17 08:52:02,089 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1342 [2024-11-17 08:52:02,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1415 states to 1415 states and 2030 transitions. [2024-11-17 08:52:02,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1415 [2024-11-17 08:52:02,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1415 [2024-11-17 08:52:02,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1415 states and 2030 transitions. [2024-11-17 08:52:02,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,099 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1415 states and 2030 transitions. [2024-11-17 08:52:02,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1415 states and 2030 transitions. [2024-11-17 08:52:02,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1415 to 1407. [2024-11-17 08:52:02,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1407 states, 1407 states have (on average 1.4371002132196162) internal successors, (2022), 1406 states have internal predecessors, (2022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1407 states to 1407 states and 2022 transitions. [2024-11-17 08:52:02,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1407 states and 2022 transitions. [2024-11-17 08:52:02,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:02,124 INFO L425 stractBuchiCegarLoop]: Abstraction has 1407 states and 2022 transitions. [2024-11-17 08:52:02,124 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:52:02,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1407 states and 2022 transitions. [2024-11-17 08:52:02,131 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1334 [2024-11-17 08:52:02,131 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:02,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:02,132 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,132 INFO L745 eck$LassoCheckResult]: Stem: 8535#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8101#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8102#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8407#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8195#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 8064#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8065#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8241#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8222#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8223#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8443#L514-1 assume !(0 == ~M_E~0); 8444#L519-1 assume !(0 == ~T1_E~0); 8123#L524-1 assume !(0 == ~T2_E~0); 8124#L529-1 assume !(0 == ~T3_E~0); 8236#L534-1 assume !(0 == ~T4_E~0); 8458#L539-1 assume !(0 == ~E_M~0); 8459#L544-1 assume !(0 == ~E_1~0); 8497#L549-1 assume !(0 == ~E_2~0); 8498#L554-1 assume !(0 == ~E_3~0); 8119#L559-1 assume !(0 == ~E_4~0); 8076#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8077#L250-7 assume !(1 == ~m_pc~0); 8254#L260-7 is_master_triggered_~__retres1~0#1 := 0; 8255#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8097#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8098#L637-7 assume !(0 != activate_threads_~tmp~1#1); 8418#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8460#L269-7 assume !(1 == ~t1_pc~0); 8461#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 8411#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8053#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8054#L645-7 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8249#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8250#L288-7 assume 1 == ~t2_pc~0; 8333#L289-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8503#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8209#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8210#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 8138#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8139#L307-7 assume 1 == ~t3_pc~0; 8482#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8337#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8412#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8349#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 8350#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8377#L326-7 assume 1 == ~t4_pc~0; 8522#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8320#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8266#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8237#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 8049#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8050#L572-1 assume !(1 == ~M_E~0); 8132#L577-1 assume !(1 == ~T1_E~0); 8133#L582-1 assume !(1 == ~T2_E~0); 8440#L587-1 assume !(1 == ~T3_E~0); 8445#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8066#L597-1 assume !(1 == ~E_M~0); 8067#L602-1 assume !(1 == ~E_1~0); 8292#L607-1 assume !(1 == ~E_2~0); 8293#L612-1 assume !(1 == ~E_3~0); 8234#L617-1 assume !(1 == ~E_4~0); 8235#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 8466#L803 [2024-11-17 08:52:02,133 INFO L747 eck$LassoCheckResult]: Loop: 8466#L803 assume true; 8604#L803-1 assume !false; 8595#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8591#L423 assume true; 8589#L423-1 assume !false; 8587#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8579#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8575#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8573#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8569#L428 assume !(0 != eval_~tmp~0#1); 8570#L431 assume true; 9199#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9197#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9195#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 9193#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9191#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9188#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9186#L534 assume !(0 == ~T4_E~0); 9184#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 9182#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 9180#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 9178#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 9176#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 9174#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9172#L250-1 assume !(1 == ~m_pc~0); 9170#L260-1 is_master_triggered_~__retres1~0#1 := 0; 9168#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9166#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9164#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9162#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9160#L269-1 assume !(1 == ~t1_pc~0); 9158#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 9157#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9156#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9147#L645-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9146#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9137#L288-1 assume !(1 == ~t2_pc~0); 9134#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 9131#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9129#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9127#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9124#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8984#L307-1 assume !(1 == ~t3_pc~0); 8980#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 8978#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8976#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8974#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8972#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8970#L326-1 assume !(1 == ~t4_pc~0); 8965#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 8963#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8961#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8959#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8957#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8954#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 8952#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8950#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8948#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8946#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8944#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 8942#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 8940#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 8938#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 8936#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 8934#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8919#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8914#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8911#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 8907#L822 assume !(0 == start_simulation_~tmp~3#1); 8903#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8836#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8829#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8823#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 8817#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8813#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8809#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8620#L835 assume !(0 != start_simulation_~tmp___0~1#1); 8466#L803 [2024-11-17 08:52:02,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,134 INFO L85 PathProgramCache]: Analyzing trace with hash 640137160, now seen corresponding path program 1 times [2024-11-17 08:52:02,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115087086] [2024-11-17 08:52:02,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,213 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,213 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115087086] [2024-11-17 08:52:02,217 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115087086] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550929561] [2024-11-17 08:52:02,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,218 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:02,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,218 INFO L85 PathProgramCache]: Analyzing trace with hash 609272639, now seen corresponding path program 1 times [2024-11-17 08:52:02,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269470894] [2024-11-17 08:52:02,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269470894] [2024-11-17 08:52:02,293 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1269470894] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,293 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,293 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069645381] [2024-11-17 08:52:02,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,294 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:02,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:02,295 INFO L87 Difference]: Start difference. First operand 1407 states and 2022 transitions. cyclomatic complexity: 619 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,465 INFO L93 Difference]: Finished difference Result 1446 states and 2049 transitions. [2024-11-17 08:52:02,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2049 transitions. [2024-11-17 08:52:02,473 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1373 [2024-11-17 08:52:02,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2049 transitions. [2024-11-17 08:52:02,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2024-11-17 08:52:02,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2024-11-17 08:52:02,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2049 transitions. [2024-11-17 08:52:02,483 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,483 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1446 states and 2049 transitions. [2024-11-17 08:52:02,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2049 transitions. [2024-11-17 08:52:02,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2024-11-17 08:52:02,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4170124481327802) internal successors, (2049), 1445 states have internal predecessors, (2049), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2049 transitions. [2024-11-17 08:52:02,506 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1446 states and 2049 transitions. [2024-11-17 08:52:02,507 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:02,509 INFO L425 stractBuchiCegarLoop]: Abstraction has 1446 states and 2049 transitions. [2024-11-17 08:52:02,509 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:52:02,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2049 transitions. [2024-11-17 08:52:02,515 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1373 [2024-11-17 08:52:02,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:02,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:02,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,517 INFO L745 eck$LassoCheckResult]: Stem: 11423#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 10965#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10966#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11283#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11063#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 10928#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10929#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11109#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11090#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11091#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11322#L514-1 assume !(0 == ~M_E~0); 11323#L519-1 assume !(0 == ~T1_E~0); 10987#L524-1 assume !(0 == ~T2_E~0); 10988#L529-1 assume !(0 == ~T3_E~0); 11104#L534-1 assume !(0 == ~T4_E~0); 11337#L539-1 assume !(0 == ~E_M~0); 11338#L544-1 assume !(0 == ~E_1~0); 11374#L549-1 assume !(0 == ~E_2~0); 11375#L554-1 assume !(0 == ~E_3~0); 10983#L559-1 assume !(0 == ~E_4~0); 10940#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10941#L250-7 assume !(1 == ~m_pc~0); 11123#L260-7 is_master_triggered_~__retres1~0#1 := 0; 11124#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10961#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10962#L637-7 assume !(0 != activate_threads_~tmp~1#1); 11294#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11339#L269-7 assume !(1 == ~t1_pc~0); 11340#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 11287#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10917#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10918#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 11117#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11118#L288-7 assume 1 == ~t2_pc~0; 11203#L289-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11380#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11076#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11077#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 11003#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11004#L307-7 assume 1 == ~t3_pc~0; 11362#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11206#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11288#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11216#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 11217#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11248#L326-7 assume 1 == ~t4_pc~0; 11406#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11188#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11135#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11105#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 10913#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10914#L572-1 assume !(1 == ~M_E~0); 10997#L577-1 assume !(1 == ~T1_E~0); 10998#L582-1 assume !(1 == ~T2_E~0); 11319#L587-1 assume !(1 == ~T3_E~0); 11324#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10935#L597-1 assume !(1 == ~E_M~0); 10936#L602-1 assume !(1 == ~E_1~0); 11161#L607-1 assume !(1 == ~E_2~0); 11162#L612-1 assume !(1 == ~E_3~0); 11102#L617-1 assume !(1 == ~E_4~0); 11103#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 11295#L803 [2024-11-17 08:52:02,517 INFO L747 eck$LassoCheckResult]: Loop: 11295#L803 assume true; 11015#L803-1 assume !false; 11016#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10943#L423 assume true; 10944#L423-1 assume !false; 11290#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11291#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11247#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11198#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11199#L428 assume !(0 != eval_~tmp~0#1); 11420#L431 assume true; 12349#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12348#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12347#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 12346#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12345#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12344#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11363#L534 assume !(0 == ~T4_E~0); 11330#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 11331#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 11001#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 11002#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 11158#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 11159#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11370#L250-1 assume !(1 == ~m_pc~0); 11371#L260-1 is_master_triggered_~__retres1~0#1 := 0; 11298#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11299#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11308#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12341#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12334#L269-1 assume !(1 == ~t1_pc~0); 12333#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 12332#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12331#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12330#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 12329#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12328#L288-1 assume !(1 == ~t2_pc~0); 12326#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 12325#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12324#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12322#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12321#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12320#L307-1 assume !(1 == ~t3_pc~0); 12318#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 12317#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12316#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12315#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12314#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12313#L326-1 assume !(1 == ~t4_pc~0); 12311#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 12309#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12307#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12305#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12303#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11379#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 11179#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11180#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11394#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11292#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11293#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 10926#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 10927#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 11321#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 11411#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 11282#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11151#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11113#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11405#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 11195#L822 assume !(0 == start_simulation_~tmp~3#1); 11197#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12116#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11088#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11089#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 10955#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10956#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11266#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 11267#L835 assume !(0 != start_simulation_~tmp___0~1#1); 11295#L803 [2024-11-17 08:52:02,517 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,517 INFO L85 PathProgramCache]: Analyzing trace with hash 990937097, now seen corresponding path program 1 times [2024-11-17 08:52:02,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108482454] [2024-11-17 08:52:02,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,559 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108482454] [2024-11-17 08:52:02,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108482454] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,559 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,559 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:02,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [407749072] [2024-11-17 08:52:02,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,560 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:02,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,560 INFO L85 PathProgramCache]: Analyzing trace with hash 160576000, now seen corresponding path program 1 times [2024-11-17 08:52:02,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953430098] [2024-11-17 08:52:02,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,608 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [953430098] [2024-11-17 08:52:02,608 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [953430098] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,608 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,608 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055837967] [2024-11-17 08:52:02,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,608 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,609 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:02,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:02,609 INFO L87 Difference]: Start difference. First operand 1446 states and 2049 transitions. cyclomatic complexity: 607 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,671 INFO L93 Difference]: Finished difference Result 2644 states and 3720 transitions. [2024-11-17 08:52:02,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2644 states and 3720 transitions. [2024-11-17 08:52:02,686 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2560 [2024-11-17 08:52:02,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2644 states to 2644 states and 3720 transitions. [2024-11-17 08:52:02,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2644 [2024-11-17 08:52:02,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2644 [2024-11-17 08:52:02,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2644 states and 3720 transitions. [2024-11-17 08:52:02,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2644 states and 3720 transitions. [2024-11-17 08:52:02,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2644 states and 3720 transitions. [2024-11-17 08:52:02,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2644 to 2628. [2024-11-17 08:52:02,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2628 states, 2628 states have (on average 1.4094368340943684) internal successors, (3704), 2627 states have internal predecessors, (3704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2628 states to 2628 states and 3704 transitions. [2024-11-17 08:52:02,747 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2628 states and 3704 transitions. [2024-11-17 08:52:02,747 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:02,748 INFO L425 stractBuchiCegarLoop]: Abstraction has 2628 states and 3704 transitions. [2024-11-17 08:52:02,748 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:52:02,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2628 states and 3704 transitions. [2024-11-17 08:52:02,772 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2544 [2024-11-17 08:52:02,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:02,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:02,774 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,775 INFO L745 eck$LassoCheckResult]: Stem: 15515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 15064#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 15065#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15374#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15163#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 15027#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15028#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15206#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15187#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15188#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15410#L514-1 assume !(0 == ~M_E~0); 15411#L519-1 assume !(0 == ~T1_E~0); 15086#L524-1 assume !(0 == ~T2_E~0); 15087#L529-1 assume !(0 == ~T3_E~0); 15202#L534-1 assume !(0 == ~T4_E~0); 15423#L539-1 assume !(0 == ~E_M~0); 15424#L544-1 assume !(0 == ~E_1~0); 15463#L549-1 assume !(0 == ~E_2~0); 15464#L554-1 assume !(0 == ~E_3~0); 15082#L559-1 assume !(0 == ~E_4~0); 15039#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15040#L250-7 assume !(1 == ~m_pc~0); 15218#L260-7 is_master_triggered_~__retres1~0#1 := 0; 15219#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15060#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15061#L637-7 assume !(0 != activate_threads_~tmp~1#1); 15385#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15425#L269-7 assume !(1 == ~t1_pc~0); 15426#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 15378#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15016#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15017#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 15213#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15214#L288-7 assume !(1 == ~t2_pc~0); 15301#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 15469#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15174#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15175#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 15102#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15103#L307-7 assume 1 == ~t3_pc~0; 15453#L308-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15304#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15379#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15315#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 15316#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15343#L326-7 assume 1 == ~t4_pc~0; 15496#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15289#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15232#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15203#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 15012#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15013#L572-1 assume !(1 == ~M_E~0); 15096#L577-1 assume !(1 == ~T1_E~0); 15097#L582-1 assume !(1 == ~T2_E~0); 15406#L587-1 assume !(1 == ~T3_E~0); 15412#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15029#L597-1 assume !(1 == ~E_M~0); 15030#L602-1 assume !(1 == ~E_1~0); 15258#L607-1 assume !(1 == ~E_2~0); 15259#L612-1 assume !(1 == ~E_3~0); 15200#L617-1 assume !(1 == ~E_4~0); 15201#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 15433#L803 [2024-11-17 08:52:02,775 INFO L747 eck$LassoCheckResult]: Loop: 15433#L803 assume true; 16889#L803-1 assume !false; 16883#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16879#L423 assume true; 16877#L423-1 assume !false; 16875#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15508#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15342#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15298#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15299#L428 assume !(0 != eval_~tmp~0#1); 15513#L431 assume true; 17042#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17040#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17038#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 17036#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17034#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17032#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17030#L534 assume !(0 == ~T4_E~0); 17028#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 17026#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 17024#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 17022#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 17020#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 17018#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17016#L250-1 assume !(1 == ~m_pc~0); 17014#L260-1 is_master_triggered_~__retres1~0#1 := 0; 17011#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17009#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17007#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17005#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17003#L269-1 assume !(1 == ~t1_pc~0); 17001#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 16998#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16996#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16994#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 16992#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16990#L288-1 assume !(1 == ~t2_pc~0); 16988#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 16986#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16984#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16982#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16980#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16978#L307-1 assume 1 == ~t3_pc~0; 16976#L308-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16973#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16971#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16969#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16968#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16967#L326-1 assume !(1 == ~t4_pc~0); 16965#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 16964#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16962#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16960#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16958#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16956#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 16954#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16952#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16950#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16948#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16946#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 16944#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 16942#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 16940#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 16938#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 16936#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16926#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16923#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16921#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 16918#L822 assume !(0 == start_simulation_~tmp~3#1); 16915#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16905#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16902#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16900#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 16899#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16898#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16895#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 16892#L835 assume !(0 != start_simulation_~tmp___0~1#1); 15433#L803 [2024-11-17 08:52:02,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,777 INFO L85 PathProgramCache]: Analyzing trace with hash -2101455412, now seen corresponding path program 1 times [2024-11-17 08:52:02,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312775557] [2024-11-17 08:52:02,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312775557] [2024-11-17 08:52:02,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312775557] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:02,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769829684] [2024-11-17 08:52:02,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,831 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:02,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,831 INFO L85 PathProgramCache]: Analyzing trace with hash 486079101, now seen corresponding path program 1 times [2024-11-17 08:52:02,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126143011] [2024-11-17 08:52:02,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126143011] [2024-11-17 08:52:02,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126143011] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304079332] [2024-11-17 08:52:02,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,884 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,884 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,884 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:02,884 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:02,884 INFO L87 Difference]: Start difference. First operand 2628 states and 3704 transitions. cyclomatic complexity: 1084 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,036 INFO L93 Difference]: Finished difference Result 5968 states and 8347 transitions. [2024-11-17 08:52:03,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5968 states and 8347 transitions. [2024-11-17 08:52:03,075 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5813 [2024-11-17 08:52:03,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5968 states to 5968 states and 8347 transitions. [2024-11-17 08:52:03,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5968 [2024-11-17 08:52:03,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5968 [2024-11-17 08:52:03,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5968 states and 8347 transitions. [2024-11-17 08:52:03,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:03,121 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5968 states and 8347 transitions. [2024-11-17 08:52:03,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5968 states and 8347 transitions. [2024-11-17 08:52:03,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5968 to 4811. [2024-11-17 08:52:03,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4811 states, 4811 states have (on average 1.4053211390563292) internal successors, (6761), 4810 states have internal predecessors, (6761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4811 states to 4811 states and 6761 transitions. [2024-11-17 08:52:03,204 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4811 states and 6761 transitions. [2024-11-17 08:52:03,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:03,205 INFO L425 stractBuchiCegarLoop]: Abstraction has 4811 states and 6761 transitions. [2024-11-17 08:52:03,206 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:52:03,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4811 states and 6761 transitions. [2024-11-17 08:52:03,221 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4708 [2024-11-17 08:52:03,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,222 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,222 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,223 INFO L745 eck$LassoCheckResult]: Stem: 24132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 23672#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23673#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23987#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23770#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 23635#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23636#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23813#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23795#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23796#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24025#L514-1 assume !(0 == ~M_E~0); 24026#L519-1 assume !(0 == ~T1_E~0); 23694#L524-1 assume !(0 == ~T2_E~0); 23695#L529-1 assume !(0 == ~T3_E~0); 23809#L534-1 assume !(0 == ~T4_E~0); 24040#L539-1 assume !(0 == ~E_M~0); 24041#L544-1 assume !(0 == ~E_1~0); 24075#L549-1 assume !(0 == ~E_2~0); 24076#L554-1 assume !(0 == ~E_3~0); 23690#L559-1 assume !(0 == ~E_4~0); 23647#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23648#L250-7 assume !(1 == ~m_pc~0); 23826#L260-7 is_master_triggered_~__retres1~0#1 := 0; 23827#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23668#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23669#L637-7 assume !(0 != activate_threads_~tmp~1#1); 23999#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24042#L269-7 assume !(1 == ~t1_pc~0); 24043#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 23991#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23624#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23625#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 23821#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23822#L288-7 assume !(1 == ~t2_pc~0); 23909#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 24079#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23782#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23783#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 23710#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23711#L307-7 assume !(1 == ~t3_pc~0); 23911#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 23912#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23992#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23922#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 23923#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23957#L326-7 assume 1 == ~t4_pc~0; 24115#L327-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23895#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23840#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23810#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 23620#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23621#L572-1 assume !(1 == ~M_E~0); 23704#L577-1 assume !(1 == ~T1_E~0); 23705#L582-1 assume !(1 == ~T2_E~0); 24023#L587-1 assume !(1 == ~T3_E~0); 24027#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23637#L597-1 assume !(1 == ~E_M~0); 23638#L602-1 assume !(1 == ~E_1~0); 23867#L607-1 assume !(1 == ~E_2~0); 23868#L612-1 assume !(1 == ~E_3~0); 23807#L617-1 assume !(1 == ~E_4~0); 23808#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 24050#L803 [2024-11-17 08:52:03,223 INFO L747 eck$LassoCheckResult]: Loop: 24050#L803 assume true; 27814#L803-1 assume !false; 27515#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27509#L423 assume true; 27507#L423-1 assume !false; 27498#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27464#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27461#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 27458#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27455#L428 assume !(0 != eval_~tmp~0#1); 27456#L431 assume true; 27961#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27959#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27957#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 27955#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27952#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27950#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27948#L534 assume !(0 == ~T4_E~0); 27946#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 27944#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 27943#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 27942#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 27941#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 27940#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27939#L250-1 assume !(1 == ~m_pc~0); 27937#L260-1 is_master_triggered_~__retres1~0#1 := 0; 27935#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27933#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27931#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27929#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27927#L269-1 assume !(1 == ~t1_pc~0); 27925#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 27923#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27921#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27919#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 27917#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27915#L288-1 assume !(1 == ~t2_pc~0); 27913#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 27911#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27909#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27907#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27905#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27903#L307-1 assume !(1 == ~t3_pc~0); 25058#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 27901#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27899#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27897#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27895#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27893#L326-1 assume !(1 == ~t4_pc~0); 27890#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 27887#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27885#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27883#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27881#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27879#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 27877#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27875#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27873#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27871#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27869#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 27867#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 27865#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 27863#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 27861#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 27859#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27854#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27853#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 27852#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 27848#L822 assume !(0 == start_simulation_~tmp~3#1); 27845#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 27835#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 27832#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 27830#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 27828#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27826#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27825#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 27819#L835 assume !(0 != start_simulation_~tmp___0~1#1); 24050#L803 [2024-11-17 08:52:03,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,223 INFO L85 PathProgramCache]: Analyzing trace with hash -1075545649, now seen corresponding path program 1 times [2024-11-17 08:52:03,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [924798384] [2024-11-17 08:52:03,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [924798384] [2024-11-17 08:52:03,286 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [924798384] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,286 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,287 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:03,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [313226845] [2024-11-17 08:52:03,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,287 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:03,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,288 INFO L85 PathProgramCache]: Analyzing trace with hash 160576000, now seen corresponding path program 2 times [2024-11-17 08:52:03,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125712653] [2024-11-17 08:52:03,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125712653] [2024-11-17 08:52:03,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125712653] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,348 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,349 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:03,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832361287] [2024-11-17 08:52:03,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,349 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:03,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:03,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:03,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:03,350 INFO L87 Difference]: Start difference. First operand 4811 states and 6761 transitions. cyclomatic complexity: 1958 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,442 INFO L93 Difference]: Finished difference Result 8878 states and 12438 transitions. [2024-11-17 08:52:03,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8878 states and 12438 transitions. [2024-11-17 08:52:03,490 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8704 [2024-11-17 08:52:03,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8878 states to 8878 states and 12438 transitions. [2024-11-17 08:52:03,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8878 [2024-11-17 08:52:03,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8878 [2024-11-17 08:52:03,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8878 states and 12438 transitions. [2024-11-17 08:52:03,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:03,547 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8878 states and 12438 transitions. [2024-11-17 08:52:03,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8878 states and 12438 transitions. [2024-11-17 08:52:03,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8878 to 8814. [2024-11-17 08:52:03,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8814 states, 8814 states have (on average 1.403902881778988) internal successors, (12374), 8813 states have internal predecessors, (12374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8814 states to 8814 states and 12374 transitions. [2024-11-17 08:52:03,673 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8814 states and 12374 transitions. [2024-11-17 08:52:03,673 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:03,674 INFO L425 stractBuchiCegarLoop]: Abstraction has 8814 states and 12374 transitions. [2024-11-17 08:52:03,674 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:52:03,674 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8814 states and 12374 transitions. [2024-11-17 08:52:03,700 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8640 [2024-11-17 08:52:03,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,701 INFO L745 eck$LassoCheckResult]: Stem: 37822#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 37371#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 37372#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37674#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37464#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 37333#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37334#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37509#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37491#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37492#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37718#L514-1 assume !(0 == ~M_E~0); 37719#L519-1 assume !(0 == ~T1_E~0); 37391#L524-1 assume !(0 == ~T2_E~0); 37392#L529-1 assume !(0 == ~T3_E~0); 37505#L534-1 assume !(0 == ~T4_E~0); 37734#L539-1 assume !(0 == ~E_M~0); 37735#L544-1 assume !(0 == ~E_1~0); 37768#L549-1 assume !(0 == ~E_2~0); 37769#L554-1 assume !(0 == ~E_3~0); 37387#L559-1 assume !(0 == ~E_4~0); 37346#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37347#L250-7 assume !(1 == ~m_pc~0); 37524#L260-7 is_master_triggered_~__retres1~0#1 := 0; 37525#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37367#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 37368#L637-7 assume !(0 != activate_threads_~tmp~1#1); 37686#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37736#L269-7 assume !(1 == ~t1_pc~0); 37737#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 37678#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37322#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37323#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 37516#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37517#L288-7 assume !(1 == ~t2_pc~0); 37603#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 37774#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37478#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37479#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 37407#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37408#L307-7 assume !(1 == ~t3_pc~0); 37604#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 37605#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37679#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37616#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 37617#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37644#L326-7 assume !(1 == ~t4_pc~0); 37587#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 37588#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37534#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37506#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 37318#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37319#L572-1 assume !(1 == ~M_E~0); 37401#L577-1 assume !(1 == ~T1_E~0); 37402#L582-1 assume !(1 == ~T2_E~0); 37716#L587-1 assume !(1 == ~T3_E~0); 37720#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37341#L597-1 assume !(1 == ~E_M~0); 37342#L602-1 assume !(1 == ~E_1~0); 37561#L607-1 assume !(1 == ~E_2~0); 37562#L612-1 assume !(1 == ~E_3~0); 37503#L617-1 assume !(1 == ~E_4~0); 37504#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 37744#L803 [2024-11-17 08:52:03,701 INFO L747 eck$LassoCheckResult]: Loop: 37744#L803 assume true; 43527#L803-1 assume !false; 43521#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43512#L423 assume true; 43506#L423-1 assume !false; 43501#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43490#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43483#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43479#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 43472#L428 assume !(0 != eval_~tmp~0#1); 43473#L431 assume true; 43743#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43739#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43734#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 43727#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43726#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43725#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43724#L534 assume !(0 == ~T4_E~0); 43722#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 43691#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 43688#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 43685#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 43682#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 43679#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43676#L250-1 assume !(1 == ~m_pc~0); 43673#L260-1 is_master_triggered_~__retres1~0#1 := 0; 43672#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43671#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43669#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43667#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43665#L269-1 assume !(1 == ~t1_pc~0); 43663#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 43661#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43659#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43657#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 43655#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43653#L288-1 assume !(1 == ~t2_pc~0); 43651#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 43649#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43647#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43645#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43643#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43641#L307-1 assume !(1 == ~t3_pc~0); 42603#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 43638#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43636#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43634#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43633#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43631#L326-1 assume !(1 == ~t4_pc~0); 43629#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 43627#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43625#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43623#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43621#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43619#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 43617#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43615#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43613#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43611#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43609#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 43607#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 43605#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 43603#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 43601#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 43599#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43591#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43589#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43587#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 43585#L822 assume !(0 == start_simulation_~tmp~3#1); 43580#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 43564#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 43558#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 43553#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 43548#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43544#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43540#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 43535#L835 assume !(0 != start_simulation_~tmp___0~1#1); 37744#L803 [2024-11-17 08:52:03,702 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,702 INFO L85 PathProgramCache]: Analyzing trace with hash 1298832402, now seen corresponding path program 1 times [2024-11-17 08:52:03,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,702 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311843863] [2024-11-17 08:52:03,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,774 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [311843863] [2024-11-17 08:52:03,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [311843863] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,775 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:03,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289224449] [2024-11-17 08:52:03,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,775 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:03,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,775 INFO L85 PathProgramCache]: Analyzing trace with hash 160576000, now seen corresponding path program 3 times [2024-11-17 08:52:03,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895070878] [2024-11-17 08:52:03,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895070878] [2024-11-17 08:52:03,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895070878] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,821 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:03,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283326054] [2024-11-17 08:52:03,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,822 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:03,822 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:03,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:03,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:03,823 INFO L87 Difference]: Start difference. First operand 8814 states and 12374 transitions. cyclomatic complexity: 3576 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,946 INFO L93 Difference]: Finished difference Result 17626 states and 24628 transitions. [2024-11-17 08:52:03,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17626 states and 24628 transitions. [2024-11-17 08:52:04,024 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17248 [2024-11-17 08:52:04,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17626 states to 17626 states and 24628 transitions. [2024-11-17 08:52:04,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17626 [2024-11-17 08:52:04,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17626 [2024-11-17 08:52:04,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17626 states and 24628 transitions. [2024-11-17 08:52:04,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:04,110 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17626 states and 24628 transitions. [2024-11-17 08:52:04,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17626 states and 24628 transitions. [2024-11-17 08:52:04,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17626 to 17626. [2024-11-17 08:52:04,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17626 states, 17626 states have (on average 1.3972540565074323) internal successors, (24628), 17625 states have internal predecessors, (24628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17626 states to 17626 states and 24628 transitions. [2024-11-17 08:52:04,476 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17626 states and 24628 transitions. [2024-11-17 08:52:04,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:04,592 INFO L425 stractBuchiCegarLoop]: Abstraction has 17626 states and 24628 transitions. [2024-11-17 08:52:04,592 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:52:04,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17626 states and 24628 transitions. [2024-11-17 08:52:04,648 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17248 [2024-11-17 08:52:04,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:04,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:04,649 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,650 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,650 INFO L745 eck$LassoCheckResult]: Stem: 64340#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 63822#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 63823#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64147#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63924#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 63785#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63786#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63972#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63951#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63952#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64194#L514-1 assume 0 == ~M_E~0;~M_E~0 := 1; 64195#L519-1 assume !(0 == ~T1_E~0); 64278#L524-1 assume !(0 == ~T2_E~0); 63965#L529-1 assume !(0 == ~T3_E~0); 63966#L534-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64282#L539-1 assume !(0 == ~E_M~0); 64382#L544-1 assume !(0 == ~E_1~0); 64381#L549-1 assume !(0 == ~E_2~0); 64380#L554-1 assume !(0 == ~E_3~0); 64379#L559-1 assume !(0 == ~E_4~0); 64378#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64377#L250-7 assume !(1 == ~m_pc~0); 64376#L260-7 is_master_triggered_~__retres1~0#1 := 0; 64375#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64374#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 64373#L637-7 assume !(0 != activate_threads_~tmp~1#1); 64372#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64371#L269-7 assume !(1 == ~t1_pc~0); 64370#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 64369#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64368#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 64367#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 64366#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64365#L288-7 assume !(1 == ~t2_pc~0); 64364#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 64363#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64362#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 64361#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 64360#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64359#L307-7 assume !(1 == ~t3_pc~0); 64358#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 64357#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64356#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64355#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 64354#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64353#L326-7 assume !(1 == ~t4_pc~0); 64352#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 64351#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64350#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64349#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 64348#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64347#L572-1 assume !(1 == ~M_E~0); 64346#L577-1 assume !(1 == ~T1_E~0); 64345#L582-1 assume !(1 == ~T2_E~0); 64344#L587-1 assume !(1 == ~T3_E~0); 64343#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63787#L597-1 assume !(1 == ~E_M~0); 63788#L602-1 assume !(1 == ~E_1~0); 64029#L607-1 assume !(1 == ~E_2~0); 64030#L612-1 assume !(1 == ~E_3~0); 63963#L617-1 assume !(1 == ~E_4~0); 63964#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 64225#L803 [2024-11-17 08:52:04,650 INFO L747 eck$LassoCheckResult]: Loop: 64225#L803 assume true; 67106#L803-1 assume !false; 67100#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66878#L423 assume true; 66873#L423-1 assume !false; 66872#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66546#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66542#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66540#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 66537#L428 assume !(0 != eval_~tmp~0#1); 66538#L431 assume true; 67308#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 67306#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 67304#L514 assume 0 == ~M_E~0;~M_E~0 := 1; 67300#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67298#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67296#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67293#L534 assume !(0 == ~T4_E~0); 67291#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 67289#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 67288#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 67286#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 67284#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 67282#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67280#L250-1 assume !(1 == ~m_pc~0); 67278#L260-1 is_master_triggered_~__retres1~0#1 := 0; 67276#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67274#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 67272#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 67270#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67268#L269-1 assume !(1 == ~t1_pc~0); 67266#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 67264#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67262#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 67260#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 67259#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67258#L288-1 assume !(1 == ~t2_pc~0); 67257#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 67255#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67253#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67251#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 67249#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67247#L307-1 assume !(1 == ~t3_pc~0); 66375#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 67244#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67242#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67240#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 67238#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67236#L326-1 assume !(1 == ~t4_pc~0); 67234#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 67232#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67230#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67228#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 67225#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67223#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 67221#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67219#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67217#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67215#L592 assume !(1 == ~T4_E~0); 67211#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 67209#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 67207#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 67205#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 67203#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 67201#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 67191#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 67188#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 67186#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 67184#L822 assume !(0 == start_simulation_~tmp~3#1); 67181#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 67169#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 67167#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 67166#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 67143#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 67133#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 67124#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 67116#L835 assume !(0 != start_simulation_~tmp___0~1#1); 64225#L803 [2024-11-17 08:52:04,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,651 INFO L85 PathProgramCache]: Analyzing trace with hash -439918636, now seen corresponding path program 1 times [2024-11-17 08:52:04,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177294619] [2024-11-17 08:52:04,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177294619] [2024-11-17 08:52:04,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177294619] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:04,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [115451796] [2024-11-17 08:52:04,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,679 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:04,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,679 INFO L85 PathProgramCache]: Analyzing trace with hash -683895871, now seen corresponding path program 1 times [2024-11-17 08:52:04,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83200624] [2024-11-17 08:52:04,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [83200624] [2024-11-17 08:52:04,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [83200624] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:04,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856891783] [2024-11-17 08:52:04,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,721 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:04,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:04,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:04,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:04,722 INFO L87 Difference]: Start difference. First operand 17626 states and 24628 transitions. cyclomatic complexity: 7034 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:04,905 INFO L93 Difference]: Finished difference Result 26621 states and 37236 transitions. [2024-11-17 08:52:04,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26621 states and 37236 transitions. [2024-11-17 08:52:05,047 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26176 [2024-11-17 08:52:05,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26621 states to 26621 states and 37236 transitions. [2024-11-17 08:52:05,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26621 [2024-11-17 08:52:05,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26621 [2024-11-17 08:52:05,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26621 states and 37236 transitions. [2024-11-17 08:52:05,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:05,223 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26621 states and 37236 transitions. [2024-11-17 08:52:05,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26621 states and 37236 transitions. [2024-11-17 08:52:05,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26621 to 19335. [2024-11-17 08:52:05,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19335 states, 19335 states have (on average 1.4031031807602792) internal successors, (27129), 19334 states have internal predecessors, (27129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19335 states to 19335 states and 27129 transitions. [2024-11-17 08:52:05,791 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19335 states and 27129 transitions. [2024-11-17 08:52:05,792 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:05,792 INFO L425 stractBuchiCegarLoop]: Abstraction has 19335 states and 27129 transitions. [2024-11-17 08:52:05,792 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:52:05,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19335 states and 27129 transitions. [2024-11-17 08:52:05,963 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 19008 [2024-11-17 08:52:05,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:05,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:05,964 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,964 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,964 INFO L745 eck$LassoCheckResult]: Stem: 108563#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 108078#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 108079#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 108392#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108178#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 108041#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 108042#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108222#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108202#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 108203#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108433#L514-1 assume !(0 == ~M_E~0); 108434#L519-1 assume !(0 == ~T1_E~0); 108101#L524-1 assume !(0 == ~T2_E~0); 108102#L529-1 assume !(0 == ~T3_E~0); 108218#L534-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108452#L539-1 assume !(0 == ~E_M~0); 108453#L544-1 assume !(0 == ~E_1~0); 108495#L549-1 assume !(0 == ~E_2~0); 108496#L554-1 assume !(0 == ~E_3~0); 108096#L559-1 assume !(0 == ~E_4~0); 108097#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108518#L250-7 assume !(1 == ~m_pc~0); 108235#L260-7 is_master_triggered_~__retres1~0#1 := 0; 108236#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108576#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 108575#L637-7 assume !(0 != activate_threads_~tmp~1#1); 108528#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108529#L269-7 assume !(1 == ~t1_pc~0); 108537#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 108396#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108397#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 108514#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 108230#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108231#L288-7 assume !(1 == ~t2_pc~0); 108499#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 108500#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108189#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 108190#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 108560#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108555#L307-7 assume !(1 == ~t3_pc~0); 108556#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 108485#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108398#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 108399#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 108364#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108365#L326-7 assume !(1 == ~t4_pc~0); 108304#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 108305#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108570#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 108569#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 108568#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108158#L572-1 assume !(1 == ~M_E~0); 108159#L577-1 assume !(1 == ~T1_E~0); 108567#L582-1 assume !(1 == ~T2_E~0); 108437#L587-1 assume !(1 == ~T3_E~0); 108438#L592-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 108043#L597-1 assume !(1 == ~E_M~0); 108044#L602-1 assume !(1 == ~E_1~0); 108279#L607-1 assume !(1 == ~E_2~0); 108280#L612-1 assume !(1 == ~E_3~0); 108216#L617-1 assume !(1 == ~E_4~0); 108217#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 108462#L803 [2024-11-17 08:52:05,965 INFO L747 eck$LassoCheckResult]: Loop: 108462#L803 assume true; 112284#L803-1 assume !false; 112280#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112227#L423 assume true; 112275#L423-1 assume !false; 112273#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 112269#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 112265#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 112263#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 112258#L428 assume !(0 != eval_~tmp~0#1); 112259#L431 assume true; 112489#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112484#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112479#L514 assume !(0 == ~M_E~0); 112474#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 112470#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 112465#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 112461#L534 assume 0 == ~T4_E~0;~T4_E~0 := 1; 112460#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 112459#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 112458#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 112457#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 112456#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 112455#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112454#L250-1 assume !(1 == ~m_pc~0); 112453#L260-1 is_master_triggered_~__retres1~0#1 := 0; 112452#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112451#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 112450#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 112449#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112448#L269-1 assume !(1 == ~t1_pc~0); 112447#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 112446#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112445#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 112444#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 112443#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112442#L288-1 assume !(1 == ~t2_pc~0); 112441#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 112440#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112439#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 112438#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112437#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112436#L307-1 assume !(1 == ~t3_pc~0); 111600#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 112435#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112434#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112433#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112432#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112431#L326-1 assume !(1 == ~t4_pc~0); 112430#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 112429#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112428#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112427#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 112426#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112425#L572 assume !(1 == ~M_E~0); 110550#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 112424#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112423#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112421#L592 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112419#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 112417#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 112415#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 112414#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 112413#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 112411#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 112405#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 112404#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 112403#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 110538#L822 assume !(0 == start_simulation_~tmp~3#1); 110539#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 112312#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 112306#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 112302#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 112298#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 112295#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112292#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 112289#L835 assume !(0 != start_simulation_~tmp___0~1#1); 108462#L803 [2024-11-17 08:52:05,971 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,972 INFO L85 PathProgramCache]: Analyzing trace with hash 329251379, now seen corresponding path program 1 times [2024-11-17 08:52:05,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272445100] [2024-11-17 08:52:05,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272445100] [2024-11-17 08:52:06,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [272445100] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:06,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18813825] [2024-11-17 08:52:06,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,012 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:06,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,013 INFO L85 PathProgramCache]: Analyzing trace with hash -870251583, now seen corresponding path program 1 times [2024-11-17 08:52:06,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204195026] [2024-11-17 08:52:06,013 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204195026] [2024-11-17 08:52:06,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [204195026] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323694034] [2024-11-17 08:52:06,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,056 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:06,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:06,057 INFO L87 Difference]: Start difference. First operand 19335 states and 27129 transitions. cyclomatic complexity: 7810 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,207 INFO L93 Difference]: Finished difference Result 23694 states and 32978 transitions. [2024-11-17 08:52:06,207 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23694 states and 32978 transitions. [2024-11-17 08:52:06,324 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23296 [2024-11-17 08:52:06,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23694 states to 23694 states and 32978 transitions. [2024-11-17 08:52:06,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23694 [2024-11-17 08:52:06,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23694 [2024-11-17 08:52:06,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23694 states and 32978 transitions. [2024-11-17 08:52:06,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23694 states and 32978 transitions. [2024-11-17 08:52:06,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23694 states and 32978 transitions. [2024-11-17 08:52:06,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23694 to 16414. [2024-11-17 08:52:06,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16414 states, 16414 states have (on average 1.396003411721701) internal successors, (22914), 16413 states have internal predecessors, (22914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16414 states to 16414 states and 22914 transitions. [2024-11-17 08:52:06,866 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16414 states and 22914 transitions. [2024-11-17 08:52:06,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:06,867 INFO L425 stractBuchiCegarLoop]: Abstraction has 16414 states and 22914 transitions. [2024-11-17 08:52:06,867 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:52:06,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16414 states and 22914 transitions. [2024-11-17 08:52:06,917 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16128 [2024-11-17 08:52:06,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:06,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:06,918 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,919 INFO L745 eck$LassoCheckResult]: Stem: 151580#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 151119#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 151120#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 151430#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151217#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 151082#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 151083#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 151263#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 151243#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 151244#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 151471#L514-1 assume !(0 == ~M_E~0); 151472#L519-1 assume !(0 == ~T1_E~0); 151141#L524-1 assume !(0 == ~T2_E~0); 151142#L529-1 assume !(0 == ~T3_E~0); 151258#L534-1 assume !(0 == ~T4_E~0); 151487#L539-1 assume !(0 == ~E_M~0); 151488#L544-1 assume !(0 == ~E_1~0); 151524#L549-1 assume !(0 == ~E_2~0); 151525#L554-1 assume !(0 == ~E_3~0); 151137#L559-1 assume !(0 == ~E_4~0); 151094#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151095#L250-7 assume !(1 == ~m_pc~0); 151279#L260-7 is_master_triggered_~__retres1~0#1 := 0; 151280#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151115#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 151116#L637-7 assume !(0 != activate_threads_~tmp~1#1); 151442#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151489#L269-7 assume !(1 == ~t1_pc~0); 151490#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 151434#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 151071#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 151072#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 151271#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151272#L288-7 assume !(1 == ~t2_pc~0); 151362#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 151528#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 151230#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 151231#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 151157#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151158#L307-7 assume !(1 == ~t3_pc~0); 151363#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 151364#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151435#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 151375#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 151376#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 151404#L326-7 assume !(1 == ~t4_pc~0); 151346#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 151347#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 151289#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 151259#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 151067#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151068#L572-1 assume !(1 == ~M_E~0); 151151#L577-1 assume !(1 == ~T1_E~0); 151152#L582-1 assume !(1 == ~T2_E~0); 151469#L587-1 assume !(1 == ~T3_E~0); 151473#L592-1 assume !(1 == ~T4_E~0); 151089#L597-1 assume !(1 == ~E_M~0); 151090#L602-1 assume !(1 == ~E_1~0); 151319#L607-1 assume !(1 == ~E_2~0); 151320#L612-1 assume !(1 == ~E_3~0); 151256#L617-1 assume !(1 == ~E_4~0); 151257#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 151496#L803 [2024-11-17 08:52:06,919 INFO L747 eck$LassoCheckResult]: Loop: 151496#L803 assume true; 154440#L803-1 assume !false; 154436#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 154432#L423 assume true; 154430#L423-1 assume !false; 154429#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 154411#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 154403#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 154401#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 154398#L428 assume !(0 != eval_~tmp~0#1); 154396#L431 assume true; 154394#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154392#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 154390#L514 assume !(0 == ~M_E~0); 154370#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 154363#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 154357#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 154352#L534 assume !(0 == ~T4_E~0); 154348#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 154340#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 154336#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 154332#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 154326#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 154321#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154318#L250-1 assume !(1 == ~m_pc~0); 154315#L260-1 is_master_triggered_~__retres1~0#1 := 0; 154312#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154305#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 154302#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 154299#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154295#L269-1 assume !(1 == ~t1_pc~0); 154292#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 154289#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154286#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 154283#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 154280#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 154277#L288-1 assume !(1 == ~t2_pc~0); 154274#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 154271#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154268#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 154265#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 154262#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 154259#L307-1 assume !(1 == ~t3_pc~0); 153782#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 154253#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154249#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 154245#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 154241#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154238#L326-1 assume !(1 == ~t4_pc~0); 154235#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 154232#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154229#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 154225#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 154221#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154217#L572 assume !(1 == ~M_E~0); 153231#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 154210#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 154207#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 154204#L592 assume !(1 == ~T4_E~0); 154201#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 154198#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 154195#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 154192#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 154189#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 154187#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 154180#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 154177#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 154175#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 153450#L822 assume !(0 == start_simulation_~tmp~3#1); 153451#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 154457#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 154454#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 154451#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 154449#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 154447#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 154445#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 154443#L835 assume !(0 != start_simulation_~tmp___0~1#1); 151496#L803 [2024-11-17 08:52:06,919 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,919 INFO L85 PathProgramCache]: Analyzing trace with hash -2108631213, now seen corresponding path program 1 times [2024-11-17 08:52:06,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,919 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230615656] [2024-11-17 08:52:06,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:06,932 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:06,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:06,988 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:06,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,990 INFO L85 PathProgramCache]: Analyzing trace with hash -1613811487, now seen corresponding path program 1 times [2024-11-17 08:52:06,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164555941] [2024-11-17 08:52:06,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1164555941] [2024-11-17 08:52:07,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1164555941] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,045 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,045 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:07,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [16440780] [2024-11-17 08:52:07,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,045 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:07,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:07,046 INFO L87 Difference]: Start difference. First operand 16414 states and 22914 transitions. cyclomatic complexity: 6516 Second operand has 5 states, 5 states have (on average 15.4) internal successors, (77), 5 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,150 INFO L93 Difference]: Finished difference Result 16862 states and 23362 transitions. [2024-11-17 08:52:07,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16862 states and 23362 transitions. [2024-11-17 08:52:07,414 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16576 [2024-11-17 08:52:07,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16862 states to 16862 states and 23362 transitions. [2024-11-17 08:52:07,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16862 [2024-11-17 08:52:07,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16862 [2024-11-17 08:52:07,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16862 states and 23362 transitions. [2024-11-17 08:52:07,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,496 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16862 states and 23362 transitions. [2024-11-17 08:52:07,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16862 states and 23362 transitions. [2024-11-17 08:52:07,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16862 to 16606. [2024-11-17 08:52:07,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16606 states, 16606 states have (on average 1.3914247862218476) internal successors, (23106), 16605 states have internal predecessors, (23106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16606 states to 16606 states and 23106 transitions. [2024-11-17 08:52:07,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16606 states and 23106 transitions. [2024-11-17 08:52:07,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:07,827 INFO L425 stractBuchiCegarLoop]: Abstraction has 16606 states and 23106 transitions. [2024-11-17 08:52:07,827 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:52:07,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16606 states and 23106 transitions. [2024-11-17 08:52:07,888 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16320 [2024-11-17 08:52:07,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,890 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,890 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,890 INFO L745 eck$LassoCheckResult]: Stem: 184900#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 184404#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 184405#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 184735#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 184499#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 184366#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 184367#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 184547#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 184527#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 184528#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 184778#L514-1 assume !(0 == ~M_E~0); 184779#L519-1 assume !(0 == ~T1_E~0); 184424#L524-1 assume !(0 == ~T2_E~0); 184425#L529-1 assume !(0 == ~T3_E~0); 184542#L534-1 assume !(0 == ~T4_E~0); 184794#L539-1 assume !(0 == ~E_M~0); 184795#L544-1 assume !(0 == ~E_1~0); 184838#L549-1 assume !(0 == ~E_2~0); 184839#L554-1 assume !(0 == ~E_3~0); 184420#L559-1 assume !(0 == ~E_4~0); 184379#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 184380#L250-7 assume !(1 == ~m_pc~0); 184561#L260-7 is_master_triggered_~__retres1~0#1 := 0; 184562#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 184400#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 184401#L637-7 assume !(0 != activate_threads_~tmp~1#1); 184748#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 184796#L269-7 assume !(1 == ~t1_pc~0); 184797#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 184739#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 184355#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 184356#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 184555#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 184556#L288-7 assume !(1 == ~t2_pc~0); 184650#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 184846#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 184514#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 184515#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 184440#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 184441#L307-7 assume !(1 == ~t3_pc~0); 184652#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 184653#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 184740#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 184664#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 184665#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 184696#L326-7 assume !(1 == ~t4_pc~0); 184633#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 184634#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 184574#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 184543#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 184351#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184352#L572-1 assume !(1 == ~M_E~0); 184434#L577-1 assume !(1 == ~T1_E~0); 184435#L582-1 assume !(1 == ~T2_E~0); 184773#L587-1 assume !(1 == ~T3_E~0); 184780#L592-1 assume !(1 == ~T4_E~0); 184368#L597-1 assume !(1 == ~E_M~0); 184369#L602-1 assume !(1 == ~E_1~0); 184604#L607-1 assume !(1 == ~E_2~0); 184605#L612-1 assume !(1 == ~E_3~0); 184540#L617-1 assume !(1 == ~E_4~0); 184541#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 184804#L803 [2024-11-17 08:52:07,891 INFO L747 eck$LassoCheckResult]: Loop: 184804#L803 assume true; 189148#L803-1 assume !false; 189146#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 189144#L423 assume true; 189143#L423-1 assume !false; 189142#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 189139#L386-2 assume !(0 == ~m_st~0); 189140#L390-2 assume !(0 == ~t1_st~0); 189141#L394-2 assume !(0 == ~t2_st~0); 189136#L398-2 assume !(0 == ~t3_st~0); 189137#L402-2 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 189138#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 189127#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 189128#L428 assume !(0 != eval_~tmp~0#1); 189565#L431 assume true; 189564#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 189563#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 189561#L514 assume !(0 == ~M_E~0); 189559#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 189557#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 189555#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 189553#L534 assume !(0 == ~T4_E~0); 189551#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 189549#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 189547#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 189545#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 189544#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 189543#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189542#L250-1 assume !(1 == ~m_pc~0); 189541#L260-1 is_master_triggered_~__retres1~0#1 := 0; 189540#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189538#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 189537#L637-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 189536#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189534#L269-1 assume !(1 == ~t1_pc~0); 189532#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 189530#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189528#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 189526#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 189524#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189522#L288-1 assume !(1 == ~t2_pc~0); 189520#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 189518#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189516#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 189514#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 189512#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189299#L307-1 assume !(1 == ~t3_pc~0); 189298#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 189296#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189294#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 189292#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 189290#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189288#L326-1 assume !(1 == ~t4_pc~0); 189286#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 189284#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189282#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 189280#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 189278#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189276#L572 assume !(1 == ~M_E~0); 189272#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 189270#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 189268#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 189266#L592 assume !(1 == ~T4_E~0); 189265#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 189263#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 189262#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 189260#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 189258#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 189257#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 189252#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 189245#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 189242#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 189239#L822 assume !(0 == start_simulation_~tmp~3#1); 189237#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 189233#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 189230#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 189154#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 189153#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 189152#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 189151#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 189150#L835 assume !(0 != start_simulation_~tmp___0~1#1); 184804#L803 [2024-11-17 08:52:07,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,891 INFO L85 PathProgramCache]: Analyzing trace with hash -2108631213, now seen corresponding path program 2 times [2024-11-17 08:52:07,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732857793] [2024-11-17 08:52:07,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:07,904 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:07,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:07,922 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:07,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,924 INFO L85 PathProgramCache]: Analyzing trace with hash -2031581967, now seen corresponding path program 1 times [2024-11-17 08:52:07,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944328816] [2024-11-17 08:52:07,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944328816] [2024-11-17 08:52:08,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944328816] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414605426] [2024-11-17 08:52:08,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,023 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,023 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:08,023 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:08,023 INFO L87 Difference]: Start difference. First operand 16606 states and 23106 transitions. cyclomatic complexity: 6516 Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,221 INFO L93 Difference]: Finished difference Result 17038 states and 23425 transitions. [2024-11-17 08:52:08,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17038 states and 23425 transitions. [2024-11-17 08:52:08,309 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16752 [2024-11-17 08:52:08,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17038 states to 17038 states and 23425 transitions. [2024-11-17 08:52:08,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17038 [2024-11-17 08:52:08,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17038 [2024-11-17 08:52:08,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17038 states and 23425 transitions. [2024-11-17 08:52:08,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,555 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17038 states and 23425 transitions. [2024-11-17 08:52:08,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17038 states and 23425 transitions. [2024-11-17 08:52:08,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17038 to 17038. [2024-11-17 08:52:08,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17038 states, 17038 states have (on average 1.3748679422467425) internal successors, (23425), 17037 states have internal predecessors, (23425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17038 states to 17038 states and 23425 transitions. [2024-11-17 08:52:08,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17038 states and 23425 transitions. [2024-11-17 08:52:08,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:08,732 INFO L425 stractBuchiCegarLoop]: Abstraction has 17038 states and 23425 transitions. [2024-11-17 08:52:08,732 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:52:08,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17038 states and 23425 transitions. [2024-11-17 08:52:08,784 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16752 [2024-11-17 08:52:08,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,786 INFO L745 eck$LassoCheckResult]: Stem: 218543#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 218055#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 218056#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 218375#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 218152#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 218018#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 218019#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 218196#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 218177#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 218178#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 218419#L514-1 assume !(0 == ~M_E~0); 218420#L519-1 assume !(0 == ~T1_E~0); 218077#L524-1 assume !(0 == ~T2_E~0); 218078#L529-1 assume !(0 == ~T3_E~0); 218192#L534-1 assume !(0 == ~T4_E~0); 218436#L539-1 assume !(0 == ~E_M~0); 218437#L544-1 assume !(0 == ~E_1~0); 218475#L549-1 assume !(0 == ~E_2~0); 218476#L554-1 assume !(0 == ~E_3~0); 218073#L559-1 assume !(0 == ~E_4~0); 218030#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 218031#L250-7 assume !(1 == ~m_pc~0); 218209#L260-7 is_master_triggered_~__retres1~0#1 := 0; 218210#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 218051#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 218052#L637-7 assume !(0 != activate_threads_~tmp~1#1); 218388#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 218438#L269-7 assume !(1 == ~t1_pc~0); 218439#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 218379#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 218007#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 218008#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 218204#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 218205#L288-7 assume !(1 == ~t2_pc~0); 218295#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 218481#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 218164#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 218165#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 218093#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 218094#L307-7 assume !(1 == ~t3_pc~0); 218297#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 218298#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 218380#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 218309#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 218310#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 218342#L326-7 assume !(1 == ~t4_pc~0); 218278#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 218279#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 218221#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 218193#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 218003#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 218004#L572-1 assume !(1 == ~M_E~0); 218087#L577-1 assume !(1 == ~T1_E~0); 218088#L582-1 assume !(1 == ~T2_E~0); 218415#L587-1 assume !(1 == ~T3_E~0); 218421#L592-1 assume !(1 == ~T4_E~0); 218020#L597-1 assume !(1 == ~E_M~0); 218021#L602-1 assume !(1 == ~E_1~0); 218249#L607-1 assume !(1 == ~E_2~0); 218250#L612-1 assume !(1 == ~E_3~0); 218190#L617-1 assume !(1 == ~E_4~0); 218191#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 218448#L803 [2024-11-17 08:52:08,786 INFO L747 eck$LassoCheckResult]: Loop: 218448#L803 assume true; 225910#L803-1 assume !false; 225909#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 221900#L423 assume true; 225908#L423-1 assume !false; 225907#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 225904#L386-2 assume !(0 == ~m_st~0); 225905#L390-2 assume !(0 == ~t1_st~0); 225906#L394-2 assume !(0 == ~t2_st~0); 225903#L398-2 assume !(0 == ~t3_st~0); 225902#L402-2 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 225900#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 225896#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 225895#L428 assume !(0 != eval_~tmp~0#1); 225894#L431 assume true; 225893#L507 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 225892#L346 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 225891#L514 assume !(0 == ~M_E~0); 225890#L519 assume 0 == ~T1_E~0;~T1_E~0 := 1; 225889#L524 assume 0 == ~T2_E~0;~T2_E~0 := 1; 225888#L529 assume 0 == ~T3_E~0;~T3_E~0 := 1; 225887#L534 assume !(0 == ~T4_E~0); 225886#L539 assume 0 == ~E_M~0;~E_M~0 := 1; 225885#L544 assume 0 == ~E_1~0;~E_1~0 := 1; 225884#L549 assume 0 == ~E_2~0;~E_2~0 := 1; 225883#L554 assume 0 == ~E_3~0;~E_3~0 := 1; 225882#L559 assume 0 == ~E_4~0;~E_4~0 := 1; 225881#L565 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 225880#L250-1 assume !(1 == ~m_pc~0); 225879#L260-1 is_master_triggered_~__retres1~0#1 := 0; 225878#L253-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 225877#L262-1 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 225876#L637-1 assume !(0 != activate_threads_~tmp~1#1); 225875#L643-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 225874#L269-1 assume !(1 == ~t1_pc~0); 225873#L279-1 is_transmit1_triggered_~__retres1~1#1 := 0; 225872#L272-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 225871#L281-1 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 225870#L645-1 assume !(0 != activate_threads_~tmp___0~0#1); 225869#L651-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 225868#L288-1 assume !(1 == ~t2_pc~0); 225867#L298-1 is_transmit2_triggered_~__retres1~2#1 := 0; 225866#L291-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 225865#L300-1 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 225864#L653-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 225863#L659-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 225862#L307-1 assume !(1 == ~t3_pc~0); 220745#L317-1 is_transmit3_triggered_~__retres1~3#1 := 0; 225861#L310-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 225860#L319-1 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 225859#L661-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 225858#L667-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 225857#L326-1 assume !(1 == ~t4_pc~0); 225856#L336-1 is_transmit4_triggered_~__retres1~4#1 := 0; 225855#L329-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 225854#L338-1 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 225852#L669-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 225850#L675-1 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 225848#L572 assume !(1 == ~M_E~0); 225764#L577 assume 1 == ~T1_E~0;~T1_E~0 := 2; 225845#L582 assume 1 == ~T2_E~0;~T2_E~0 := 2; 225843#L587 assume 1 == ~T3_E~0;~T3_E~0 := 2; 225841#L592 assume !(1 == ~T4_E~0); 225839#L597 assume 1 == ~E_M~0;~E_M~0 := 2; 225837#L602 assume 1 == ~E_1~0;~E_1~0 := 2; 225835#L607 assume 1 == ~E_2~0;~E_2~0 := 2; 225833#L612 assume 1 == ~E_3~0;~E_3~0 := 2; 225831#L617 assume 1 == ~E_4~0;~E_4~0 := 2; 225829#L623 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 225823#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 225821#L404-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 225819#L414-1 assume true;start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 225816#L822 assume !(0 == start_simulation_~tmp~3#1); 225817#L833 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 225918#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 225916#L404 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 225915#L414 assume true;stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 225914#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 225913#L779 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 225912#L785 assume true;start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 225911#L835 assume !(0 != start_simulation_~tmp___0~1#1); 218448#L803 [2024-11-17 08:52:08,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,787 INFO L85 PathProgramCache]: Analyzing trace with hash -2108631213, now seen corresponding path program 3 times [2024-11-17 08:52:08,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974841751] [2024-11-17 08:52:08,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:08,798 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:08,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:08,904 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:08,904 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,908 INFO L85 PathProgramCache]: Analyzing trace with hash -2039341326, now seen corresponding path program 1 times [2024-11-17 08:52:08,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825723170] [2024-11-17 08:52:08,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [825723170] [2024-11-17 08:52:08,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [825723170] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:08,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385170298] [2024-11-17 08:52:08,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,949 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:08,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:08,950 INFO L87 Difference]: Start difference. First operand 17038 states and 23425 transitions. cyclomatic complexity: 6403 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:09,055 INFO L93 Difference]: Finished difference Result 26293 states and 35476 transitions. [2024-11-17 08:52:09,055 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26293 states and 35476 transitions. [2024-11-17 08:52:09,174 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25914 [2024-11-17 08:52:09,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26293 states to 26293 states and 35476 transitions. [2024-11-17 08:52:09,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26293 [2024-11-17 08:52:09,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26293 [2024-11-17 08:52:09,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26293 states and 35476 transitions. [2024-11-17 08:52:09,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:09,329 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26293 states and 35476 transitions. [2024-11-17 08:52:09,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26293 states and 35476 transitions. [2024-11-17 08:52:09,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26293 to 25349. [2024-11-17 08:52:09,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25349 states, 25349 states have (on average 1.352794982050574) internal successors, (34292), 25348 states have internal predecessors, (34292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25349 states to 25349 states and 34292 transitions. [2024-11-17 08:52:09,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25349 states and 34292 transitions. [2024-11-17 08:52:09,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:09,784 INFO L425 stractBuchiCegarLoop]: Abstraction has 25349 states and 34292 transitions. [2024-11-17 08:52:09,784 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:52:09,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25349 states and 34292 transitions. [2024-11-17 08:52:10,027 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 24970 [2024-11-17 08:52:10,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:10,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:10,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:10,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:10,029 INFO L745 eck$LassoCheckResult]: Stem: 261879#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 261392#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 261393#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 261708#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 261488#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 261355#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 261356#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 261533#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 261513#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 261514#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 261753#L514-1 assume !(0 == ~M_E~0); 261754#L519-1 assume !(0 == ~T1_E~0); 261414#L524-1 assume !(0 == ~T2_E~0); 261415#L529-1 assume !(0 == ~T3_E~0); 261528#L534-1 assume !(0 == ~T4_E~0); 261771#L539-1 assume !(0 == ~E_M~0); 261772#L544-1 assume !(0 == ~E_1~0); 261815#L549-1 assume !(0 == ~E_2~0); 261816#L554-1 assume !(0 == ~E_3~0); 261410#L559-1 assume !(0 == ~E_4~0); 261367#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 261368#L250-7 assume !(1 == ~m_pc~0); 261547#L260-7 is_master_triggered_~__retres1~0#1 := 0; 261548#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 261388#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 261389#L637-7 assume !(0 != activate_threads_~tmp~1#1); 261721#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 261773#L269-7 assume !(1 == ~t1_pc~0); 261774#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 261712#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 261344#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 261345#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 261542#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 261543#L288-7 assume !(1 == ~t2_pc~0); 261634#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 261821#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 261499#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 261500#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 261430#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 261431#L307-7 assume !(1 == ~t3_pc~0); 261637#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 261638#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 261713#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 261649#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 261650#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 261679#L326-7 assume !(1 == ~t4_pc~0); 261618#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 261619#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 261562#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261529#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 261340#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261341#L572-1 assume !(1 == ~M_E~0); 261424#L577-1 assume !(1 == ~T1_E~0); 261425#L582-1 assume !(1 == ~T2_E~0); 261749#L587-1 assume !(1 == ~T3_E~0); 261757#L592-1 assume !(1 == ~T4_E~0); 261357#L597-1 assume !(1 == ~E_M~0); 261358#L602-1 assume !(1 == ~E_1~0); 261591#L607-1 assume !(1 == ~E_2~0); 261592#L612-1 assume !(1 == ~E_3~0); 261526#L617-1 assume !(1 == ~E_4~0); 261527#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 261782#L803 assume true; 263920#L803-1 assume !false; 263921#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 263909#L423 [2024-11-17 08:52:10,030 INFO L747 eck$LassoCheckResult]: Loop: 263909#L423 assume true; 263910#L423-1 assume !false; 263544#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 263545#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 264316#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 264315#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 264313#L428 assume 0 != eval_~tmp~0#1; 264311#L433-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 264309#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 264308#L433 havoc eval_~tmp_ndt_1~0#1; 264305#L447-1 assume !(0 == ~t1_st~0); 264301#L461-1 assume !(0 == ~t2_st~0); 264298#L475-1 assume !(0 == ~t3_st~0); 264299#L489-1 assume !(0 == ~t4_st~0); 263909#L423 [2024-11-17 08:52:10,030 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:10,030 INFO L85 PathProgramCache]: Analyzing trace with hash -40079268, now seen corresponding path program 1 times [2024-11-17 08:52:10,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:10,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1704151558] [2024-11-17 08:52:10,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:10,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:10,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:10,045 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:10,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:10,063 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:10,064 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:10,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1978972455, now seen corresponding path program 1 times [2024-11-17 08:52:10,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:10,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464662072] [2024-11-17 08:52:10,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:10,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:10,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:10,069 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:10,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:10,073 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:10,077 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:10,077 INFO L85 PathProgramCache]: Analyzing trace with hash 1644949058, now seen corresponding path program 1 times [2024-11-17 08:52:10,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:10,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500287394] [2024-11-17 08:52:10,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:10,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:10,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:10,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:10,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:10,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500287394] [2024-11-17 08:52:10,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500287394] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:10,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:10,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:10,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555556088] [2024-11-17 08:52:10,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:10,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:10,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:10,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:10,209 INFO L87 Difference]: Start difference. First operand 25349 states and 34292 transitions. cyclomatic complexity: 8968 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:10,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:10,330 INFO L93 Difference]: Finished difference Result 29043 states and 38708 transitions. [2024-11-17 08:52:10,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29043 states and 38708 transitions. [2024-11-17 08:52:10,481 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 28628 [2024-11-17 08:52:10,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29043 states to 29043 states and 38708 transitions. [2024-11-17 08:52:10,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29043 [2024-11-17 08:52:10,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29043 [2024-11-17 08:52:10,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29043 states and 38708 transitions. [2024-11-17 08:52:10,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:10,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29043 states and 38708 transitions. [2024-11-17 08:52:10,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29043 states and 38708 transitions. [2024-11-17 08:52:10,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29043 to 27671. [2024-11-17 08:52:10,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27671 states, 27671 states have (on average 1.337139966029417) internal successors, (37000), 27670 states have internal predecessors, (37000), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:11,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27671 states to 27671 states and 37000 transitions. [2024-11-17 08:52:11,033 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27671 states and 37000 transitions. [2024-11-17 08:52:11,034 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:11,034 INFO L425 stractBuchiCegarLoop]: Abstraction has 27671 states and 37000 transitions. [2024-11-17 08:52:11,034 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:52:11,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27671 states and 37000 transitions. [2024-11-17 08:52:11,138 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 27256 [2024-11-17 08:52:11,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:11,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:11,139 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:11,139 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:11,140 INFO L745 eck$LassoCheckResult]: Stem: 316293#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 315793#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 315794#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 316112#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 315887#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 315755#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 315756#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 315933#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 315913#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 315914#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 316154#L514-1 assume !(0 == ~M_E~0); 316155#L519-1 assume !(0 == ~T1_E~0); 315813#L524-1 assume !(0 == ~T2_E~0); 315814#L529-1 assume !(0 == ~T3_E~0); 315928#L534-1 assume !(0 == ~T4_E~0); 316173#L539-1 assume !(0 == ~E_M~0); 316174#L544-1 assume !(0 == ~E_1~0); 316217#L549-1 assume !(0 == ~E_2~0); 316218#L554-1 assume !(0 == ~E_3~0); 315809#L559-1 assume !(0 == ~E_4~0); 315768#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 315769#L250-7 assume !(1 == ~m_pc~0); 315945#L260-7 is_master_triggered_~__retres1~0#1 := 0; 315946#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 315789#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 315790#L637-7 assume !(0 != activate_threads_~tmp~1#1); 316124#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 316175#L269-7 assume !(1 == ~t1_pc~0); 316176#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 316116#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 315744#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 315745#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 315940#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315941#L288-7 assume !(1 == ~t2_pc~0); 316030#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 316223#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 315900#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 315901#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 315829#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 315830#L307-7 assume !(1 == ~t3_pc~0); 316032#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 316033#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 316117#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 316045#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 316046#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 316079#L326-7 assume !(1 == ~t4_pc~0); 316013#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 316014#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 315956#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315929#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 315740#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 315741#L572-1 assume !(1 == ~M_E~0); 315823#L577-1 assume !(1 == ~T1_E~0); 315824#L582-1 assume !(1 == ~T2_E~0); 316150#L587-1 assume !(1 == ~T3_E~0); 316156#L592-1 assume !(1 == ~T4_E~0); 315757#L597-1 assume !(1 == ~E_M~0); 315758#L602-1 assume !(1 == ~E_1~0); 315984#L607-1 assume !(1 == ~E_2~0); 315985#L612-1 assume !(1 == ~E_3~0); 315926#L617-1 assume !(1 == ~E_4~0); 315927#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 316184#L803 assume true; 322283#L803-1 assume !false; 322281#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 322278#L423 [2024-11-17 08:52:11,140 INFO L747 eck$LassoCheckResult]: Loop: 322278#L423 assume true; 322274#L423-1 assume !false; 322271#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 322268#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 322266#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 322264#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 322263#L428 assume 0 != eval_~tmp~0#1; 322259#L433-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 322257#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 322254#L433 havoc eval_~tmp_ndt_1~0#1; 322251#L447-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 322247#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 322249#L447 havoc eval_~tmp_ndt_2~0#1; 322288#L461-1 assume !(0 == ~t2_st~0); 322285#L475-1 assume !(0 == ~t3_st~0); 322279#L489-1 assume !(0 == ~t4_st~0); 322278#L423 [2024-11-17 08:52:11,140 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:11,141 INFO L85 PathProgramCache]: Analyzing trace with hash -40079268, now seen corresponding path program 2 times [2024-11-17 08:52:11,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:11,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272427588] [2024-11-17 08:52:11,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:11,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:11,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:11,153 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:11,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:11,169 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:11,170 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:11,170 INFO L85 PathProgramCache]: Analyzing trace with hash -826265637, now seen corresponding path program 1 times [2024-11-17 08:52:11,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:11,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749111926] [2024-11-17 08:52:11,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:11,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:11,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:11,175 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:11,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:11,178 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:11,179 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:11,179 INFO L85 PathProgramCache]: Analyzing trace with hash 299797046, now seen corresponding path program 1 times [2024-11-17 08:52:11,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:11,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230768816] [2024-11-17 08:52:11,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:11,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:11,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:11,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:11,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:11,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230768816] [2024-11-17 08:52:11,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230768816] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:11,227 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:11,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:11,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862354234] [2024-11-17 08:52:11,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:11,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:11,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:11,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:11,295 INFO L87 Difference]: Start difference. First operand 27671 states and 37000 transitions. cyclomatic complexity: 9355 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:11,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:11,637 INFO L93 Difference]: Finished difference Result 32807 states and 43453 transitions. [2024-11-17 08:52:11,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32807 states and 43453 transitions. [2024-11-17 08:52:11,793 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 32312 [2024-11-17 08:52:11,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32807 states to 32807 states and 43453 transitions. [2024-11-17 08:52:11,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32807 [2024-11-17 08:52:11,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32807 [2024-11-17 08:52:11,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32807 states and 43453 transitions. [2024-11-17 08:52:11,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:11,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32807 states and 43453 transitions. [2024-11-17 08:52:11,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32807 states and 43453 transitions. [2024-11-17 08:52:12,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32807 to 31511. [2024-11-17 08:52:12,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31511 states, 31511 states have (on average 1.3287106089936846) internal successors, (41869), 31510 states have internal predecessors, (41869), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31511 states to 31511 states and 41869 transitions. [2024-11-17 08:52:12,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31511 states and 41869 transitions. [2024-11-17 08:52:12,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:12,318 INFO L425 stractBuchiCegarLoop]: Abstraction has 31511 states and 41869 transitions. [2024-11-17 08:52:12,318 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:52:12,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31511 states and 41869 transitions. [2024-11-17 08:52:12,415 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 31016 [2024-11-17 08:52:12,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:12,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:12,416 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:12,416 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:12,416 INFO L745 eck$LassoCheckResult]: Stem: 376794#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 376279#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 376280#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 376601#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 376377#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 376241#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 376242#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 376424#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 376403#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 376404#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 376644#L514-1 assume !(0 == ~M_E~0); 376645#L519-1 assume !(0 == ~T1_E~0); 376299#L524-1 assume !(0 == ~T2_E~0); 376300#L529-1 assume !(0 == ~T3_E~0); 376419#L534-1 assume !(0 == ~T4_E~0); 376661#L539-1 assume !(0 == ~E_M~0); 376662#L544-1 assume !(0 == ~E_1~0); 376712#L549-1 assume !(0 == ~E_2~0); 376713#L554-1 assume !(0 == ~E_3~0); 376295#L559-1 assume !(0 == ~E_4~0); 376254#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 376255#L250-7 assume !(1 == ~m_pc~0); 376438#L260-7 is_master_triggered_~__retres1~0#1 := 0; 376439#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 376275#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 376276#L637-7 assume !(0 != activate_threads_~tmp~1#1); 376614#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 376663#L269-7 assume !(1 == ~t1_pc~0); 376664#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 376605#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 376230#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 376231#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 376433#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 376434#L288-7 assume !(1 == ~t2_pc~0); 376522#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 376720#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 376389#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 376390#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 376315#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 376316#L307-7 assume !(1 == ~t3_pc~0); 376524#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 376525#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 376606#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 376537#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 376538#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 376569#L326-7 assume !(1 == ~t4_pc~0); 376507#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 376508#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 376451#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 376420#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 376226#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 376227#L572-1 assume !(1 == ~M_E~0); 376309#L577-1 assume !(1 == ~T1_E~0); 376310#L582-1 assume !(1 == ~T2_E~0); 376640#L587-1 assume !(1 == ~T3_E~0); 376647#L592-1 assume !(1 == ~T4_E~0); 376243#L597-1 assume !(1 == ~E_M~0); 376244#L602-1 assume !(1 == ~E_1~0); 376481#L607-1 assume !(1 == ~E_2~0); 376482#L612-1 assume !(1 == ~E_3~0); 376417#L617-1 assume !(1 == ~E_4~0); 376418#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 376674#L803 assume true; 382958#L803-1 assume !false; 382952#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 382947#L423 [2024-11-17 08:52:12,417 INFO L747 eck$LassoCheckResult]: Loop: 382947#L423 assume true; 382943#L423-1 assume !false; 382938#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 382933#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 382929#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 382925#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 382922#L428 assume 0 != eval_~tmp~0#1; 382918#L433-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 382912#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 382909#L433 havoc eval_~tmp_ndt_1~0#1; 382906#L447-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 382903#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 382900#L447 havoc eval_~tmp_ndt_2~0#1; 382896#L461-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 382891#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 382879#L461 havoc eval_~tmp_ndt_3~0#1; 382872#L475-1 assume !(0 == ~t3_st~0); 382873#L489-1 assume !(0 == ~t4_st~0); 382947#L423 [2024-11-17 08:52:12,417 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,417 INFO L85 PathProgramCache]: Analyzing trace with hash -40079268, now seen corresponding path program 3 times [2024-11-17 08:52:12,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869295690] [2024-11-17 08:52:12,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:12,428 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:12,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:12,442 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:12,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,442 INFO L85 PathProgramCache]: Analyzing trace with hash 529348647, now seen corresponding path program 1 times [2024-11-17 08:52:12,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178958902] [2024-11-17 08:52:12,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:12,447 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:12,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:12,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:12,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,451 INFO L85 PathProgramCache]: Analyzing trace with hash 343828418, now seen corresponding path program 1 times [2024-11-17 08:52:12,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867024076] [2024-11-17 08:52:12,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:12,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:12,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:12,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867024076] [2024-11-17 08:52:12,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867024076] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:12,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:12,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:12,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932187460] [2024-11-17 08:52:12,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:12,560 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:12,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:12,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:12,561 INFO L87 Difference]: Start difference. First operand 31511 states and 41869 transitions. cyclomatic complexity: 10384 Second operand has 3 states, 3 states have (on average 27.666666666666668) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:12,983 INFO L93 Difference]: Finished difference Result 57327 states and 75756 transitions. [2024-11-17 08:52:12,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57327 states and 75756 transitions. [2024-11-17 08:52:13,249 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 56441 [2024-11-17 08:52:13,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57327 states to 57327 states and 75756 transitions. [2024-11-17 08:52:13,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57327 [2024-11-17 08:52:13,475 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57327 [2024-11-17 08:52:13,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57327 states and 75756 transitions. [2024-11-17 08:52:13,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:13,535 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57327 states and 75756 transitions. [2024-11-17 08:52:13,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57327 states and 75756 transitions. [2024-11-17 08:52:14,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57327 to 56223. [2024-11-17 08:52:14,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56223 states, 56223 states have (on average 1.324369030467958) internal successors, (74460), 56222 states have internal predecessors, (74460), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:14,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56223 states to 56223 states and 74460 transitions. [2024-11-17 08:52:14,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56223 states and 74460 transitions. [2024-11-17 08:52:14,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:14,402 INFO L425 stractBuchiCegarLoop]: Abstraction has 56223 states and 74460 transitions. [2024-11-17 08:52:14,402 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:52:14,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56223 states and 74460 transitions. [2024-11-17 08:52:14,553 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 55337 [2024-11-17 08:52:14,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:14,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:14,554 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:14,554 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:14,554 INFO L745 eck$LassoCheckResult]: Stem: 465663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 465125#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 465126#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 465455#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 465224#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 465087#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 465088#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 465270#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 465250#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 465251#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 465504#L514-1 assume !(0 == ~M_E~0); 465505#L519-1 assume !(0 == ~T1_E~0); 465145#L524-1 assume !(0 == ~T2_E~0); 465146#L529-1 assume !(0 == ~T3_E~0); 465265#L534-1 assume !(0 == ~T4_E~0); 465523#L539-1 assume !(0 == ~E_M~0); 465524#L544-1 assume !(0 == ~E_1~0); 465572#L549-1 assume !(0 == ~E_2~0); 465573#L554-1 assume !(0 == ~E_3~0); 465141#L559-1 assume !(0 == ~E_4~0); 465100#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 465101#L250-7 assume !(1 == ~m_pc~0); 465284#L260-7 is_master_triggered_~__retres1~0#1 := 0; 465285#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 465121#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 465122#L637-7 assume !(0 != activate_threads_~tmp~1#1); 465469#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 465525#L269-7 assume !(1 == ~t1_pc~0); 465526#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 465459#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 465076#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 465077#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 465278#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 465279#L288-7 assume !(1 == ~t2_pc~0); 465373#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 465580#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 465236#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 465237#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 465161#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 465162#L307-7 assume !(1 == ~t3_pc~0); 465375#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 465376#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 465460#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 465388#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 465389#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 465422#L326-7 assume !(1 == ~t4_pc~0); 465356#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 465357#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 465297#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 465266#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 465072#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 465073#L572-1 assume !(1 == ~M_E~0); 465155#L577-1 assume !(1 == ~T1_E~0); 465156#L582-1 assume !(1 == ~T2_E~0); 465498#L587-1 assume !(1 == ~T3_E~0); 465506#L592-1 assume !(1 == ~T4_E~0); 465089#L597-1 assume !(1 == ~E_M~0); 465090#L602-1 assume !(1 == ~E_1~0); 465328#L607-1 assume !(1 == ~E_2~0); 465329#L612-1 assume !(1 == ~E_3~0); 465263#L617-1 assume !(1 == ~E_4~0); 465264#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 465534#L803 assume true; 476584#L803-1 assume !false; 476581#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 476545#L423 [2024-11-17 08:52:14,555 INFO L747 eck$LassoCheckResult]: Loop: 476545#L423 assume true; 476539#L423-1 assume !false; 476538#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 476536#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 476534#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 476532#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 476530#L428 assume 0 != eval_~tmp~0#1; 476528#L433-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 476525#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 476523#L433 havoc eval_~tmp_ndt_1~0#1; 476521#L447-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 476514#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 476515#L447 havoc eval_~tmp_ndt_2~0#1; 476657#L461-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 476654#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 476653#L461 havoc eval_~tmp_ndt_3~0#1; 476590#L475-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 476586#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 476585#L475 havoc eval_~tmp_ndt_4~0#1; 476579#L489-1 assume !(0 == ~t4_st~0); 476545#L423 [2024-11-17 08:52:14,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:14,555 INFO L85 PathProgramCache]: Analyzing trace with hash -40079268, now seen corresponding path program 4 times [2024-11-17 08:52:14,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:14,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858359161] [2024-11-17 08:52:14,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:14,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:14,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,564 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:14,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,574 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:14,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:14,575 INFO L85 PathProgramCache]: Analyzing trace with hash 1897970651, now seen corresponding path program 1 times [2024-11-17 08:52:14,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:14,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155597072] [2024-11-17 08:52:14,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:14,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:14,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,579 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:14,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,582 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:14,582 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:14,582 INFO L85 PathProgramCache]: Analyzing trace with hash -293310282, now seen corresponding path program 1 times [2024-11-17 08:52:14,582 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:14,582 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127737170] [2024-11-17 08:52:14,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:14,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:14,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:14,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:14,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:14,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127737170] [2024-11-17 08:52:14,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127737170] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:14,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:14,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:14,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1009546640] [2024-11-17 08:52:14,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:14,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:14,687 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:14,687 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:14,687 INFO L87 Difference]: Start difference. First operand 56223 states and 74460 transitions. cyclomatic complexity: 18263 Second operand has 3 states, 2 states have (on average 42.5) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:14,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:14,881 INFO L93 Difference]: Finished difference Result 67133 states and 88052 transitions. [2024-11-17 08:52:14,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67133 states and 88052 transitions. [2024-11-17 08:52:15,538 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 66127 [2024-11-17 08:52:15,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67133 states to 67133 states and 88052 transitions. [2024-11-17 08:52:15,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67133 [2024-11-17 08:52:15,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67133 [2024-11-17 08:52:15,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67133 states and 88052 transitions. [2024-11-17 08:52:15,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:15,766 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67133 states and 88052 transitions. [2024-11-17 08:52:15,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67133 states and 88052 transitions. [2024-11-17 08:52:16,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67133 to 66173. [2024-11-17 08:52:16,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66173 states, 66173 states have (on average 1.3161259123811826) internal successors, (87092), 66172 states have internal predecessors, (87092), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:16,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66173 states to 66173 states and 87092 transitions. [2024-11-17 08:52:16,532 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66173 states and 87092 transitions. [2024-11-17 08:52:16,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:16,532 INFO L425 stractBuchiCegarLoop]: Abstraction has 66173 states and 87092 transitions. [2024-11-17 08:52:16,533 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:52:16,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66173 states and 87092 transitions. [2024-11-17 08:52:17,087 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 65167 [2024-11-17 08:52:17,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:17,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:17,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:17,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:17,090 INFO L745 eck$LassoCheckResult]: Stem: 589006#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 588488#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 588489#L766 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 588807#L346-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 588587#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 588451#L358 assume 1 == ~t1_i~0;~t1_st~0 := 0; 588452#L363 assume 1 == ~t2_i~0;~t2_st~0 := 0; 588637#L368 assume 1 == ~t3_i~0;~t3_st~0 := 0; 588616#L373 assume 1 == ~t4_i~0;~t4_st~0 := 0; 588617#L379 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 588856#L514-1 assume !(0 == ~M_E~0); 588857#L519-1 assume !(0 == ~T1_E~0); 588511#L524-1 assume !(0 == ~T2_E~0); 588512#L529-1 assume !(0 == ~T3_E~0); 588632#L534-1 assume !(0 == ~T4_E~0); 588872#L539-1 assume !(0 == ~E_M~0); 588873#L544-1 assume !(0 == ~E_1~0); 588918#L549-1 assume !(0 == ~E_2~0); 588919#L554-1 assume !(0 == ~E_3~0); 588507#L559-1 assume !(0 == ~E_4~0); 588463#L565-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 588464#L250-7 assume !(1 == ~m_pc~0); 588652#L260-7 is_master_triggered_~__retres1~0#1 := 0; 588653#L253-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 588484#L262-7 assume true;activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 588485#L637-7 assume !(0 != activate_threads_~tmp~1#1); 588819#L643-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 588874#L269-7 assume !(1 == ~t1_pc~0); 588875#L279-7 is_transmit1_triggered_~__retres1~1#1 := 0; 588811#L272-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 588440#L281-7 assume true;activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 588441#L645-7 assume !(0 != activate_threads_~tmp___0~0#1); 588644#L651-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 588645#L288-7 assume !(1 == ~t2_pc~0); 588732#L298-7 is_transmit2_triggered_~__retres1~2#1 := 0; 588924#L291-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 588602#L300-7 assume true;activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 588603#L653-7 assume !(0 != activate_threads_~tmp___1~0#1); 588527#L659-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 588528#L307-7 assume !(1 == ~t3_pc~0); 588733#L317-7 is_transmit3_triggered_~__retres1~3#1 := 0; 588734#L310-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 588812#L319-7 assume true;activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 588747#L661-7 assume !(0 != activate_threads_~tmp___2~0#1); 588748#L667-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 588777#L326-7 assume !(1 == ~t4_pc~0); 588717#L336-7 is_transmit4_triggered_~__retres1~4#1 := 0; 588718#L329-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 588662#L338-7 assume true;activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 588633#L669-7 assume !(0 != activate_threads_~tmp___3~0#1); 588436#L675-7 assume true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 588437#L572-1 assume !(1 == ~M_E~0); 588521#L577-1 assume !(1 == ~T1_E~0); 588522#L582-1 assume !(1 == ~T2_E~0); 588853#L587-1 assume !(1 == ~T3_E~0); 588858#L592-1 assume !(1 == ~T4_E~0); 588458#L597-1 assume !(1 == ~E_M~0); 588459#L602-1 assume !(1 == ~E_1~0); 588691#L607-1 assume !(1 == ~E_2~0); 588692#L612-1 assume !(1 == ~E_3~0); 588630#L617-1 assume !(1 == ~E_4~0); 588631#L623-1 assume true;assume { :end_inline_reset_delta_events } true; 588884#L803 assume true; 603632#L803-1 assume !false; 603629#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 603627#L423 [2024-11-17 08:52:17,091 INFO L747 eck$LassoCheckResult]: Loop: 603627#L423 assume true; 603624#L423-1 assume !false; 603622#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 603619#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 603616#L404-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 603614#L414-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 603613#L428 assume 0 != eval_~tmp~0#1; 603611#L433-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 603609#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 603608#L433 havoc eval_~tmp_ndt_1~0#1; 603606#L447-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 603603#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 603601#L447 havoc eval_~tmp_ndt_2~0#1; 603599#L461-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 603596#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 603594#L461 havoc eval_~tmp_ndt_3~0#1; 603592#L475-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 603589#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 603587#L475 havoc eval_~tmp_ndt_4~0#1; 603585#L489-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 603582#L492 assume !(0 != eval_~tmp_ndt_5~0#1); 603583#L489 havoc eval_~tmp_ndt_5~0#1; 603627#L423 [2024-11-17 08:52:17,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:17,091 INFO L85 PathProgramCache]: Analyzing trace with hash -40079268, now seen corresponding path program 5 times [2024-11-17 08:52:17,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:17,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706125894] [2024-11-17 08:52:17,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:17,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:17,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,104 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:17,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,114 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:17,115 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:17,115 INFO L85 PathProgramCache]: Analyzing trace with hash -1411295449, now seen corresponding path program 1 times [2024-11-17 08:52:17,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:17,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039277846] [2024-11-17 08:52:17,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:17,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:17,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,119 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:17,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,121 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:17,122 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:17,122 INFO L85 PathProgramCache]: Analyzing trace with hash 1596670274, now seen corresponding path program 1 times [2024-11-17 08:52:17,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:17,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892763275] [2024-11-17 08:52:17,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:17,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:17,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,131 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:17,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,145 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:18,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:18,256 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:18,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:18,444 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.11 08:52:18 BoogieIcfgContainer [2024-11-17 08:52:18,445 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-17 08:52:18,445 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-17 08:52:18,445 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-17 08:52:18,446 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-17 08:52:18,446 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:00" (3/4) ... [2024-11-17 08:52:18,448 INFO L140 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-17 08:52:18,529 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-17 08:52:18,529 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-17 08:52:18,530 INFO L158 Benchmark]: Toolchain (without parser) took 20125.86ms. Allocated memory was 161.5MB in the beginning and 11.3GB in the end (delta: 11.1GB). Free memory was 113.0MB in the beginning and 10.1GB in the end (delta: -9.9GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2024-11-17 08:52:18,530 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 100.7MB. Free memory is still 67.2MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-17 08:52:18,530 INFO L158 Benchmark]: CACSL2BoogieTranslator took 417.01ms. Allocated memory is still 161.5MB. Free memory was 113.0MB in the beginning and 94.9MB in the end (delta: 18.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-17 08:52:18,530 INFO L158 Benchmark]: Boogie Procedure Inliner took 67.00ms. Allocated memory is still 161.5MB. Free memory was 94.9MB in the beginning and 90.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-17 08:52:18,531 INFO L158 Benchmark]: Boogie Preprocessor took 83.13ms. Allocated memory is still 161.5MB. Free memory was 90.8MB in the beginning and 86.6MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-17 08:52:18,531 INFO L158 Benchmark]: IcfgBuilder took 1105.84ms. Allocated memory is still 161.5MB. Free memory was 86.6MB in the beginning and 71.1MB in the end (delta: 15.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-17 08:52:18,531 INFO L158 Benchmark]: BuchiAutomizer took 18362.84ms. Allocated memory was 161.5MB in the beginning and 11.3GB in the end (delta: 11.1GB). Free memory was 71.1MB in the beginning and 10.1GB in the end (delta: -10.0GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. [2024-11-17 08:52:18,531 INFO L158 Benchmark]: Witness Printer took 84.18ms. Allocated memory is still 11.3GB. Free memory was 10.1GB in the beginning and 10.1GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-17 08:52:18,533 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 100.7MB. Free memory is still 67.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 417.01ms. Allocated memory is still 161.5MB. Free memory was 113.0MB in the beginning and 94.9MB in the end (delta: 18.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 67.00ms. Allocated memory is still 161.5MB. Free memory was 94.9MB in the beginning and 90.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 83.13ms. Allocated memory is still 161.5MB. Free memory was 90.8MB in the beginning and 86.6MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * IcfgBuilder took 1105.84ms. Allocated memory is still 161.5MB. Free memory was 86.6MB in the beginning and 71.1MB in the end (delta: 15.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 18362.84ms. Allocated memory was 161.5MB in the beginning and 11.3GB in the end (delta: 11.1GB). Free memory was 71.1MB in the beginning and 10.1GB in the end (delta: -10.0GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. * Witness Printer took 84.18ms. Allocated memory is still 11.3GB. Free memory was 10.1GB in the beginning and 10.1GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 66173 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 18.1s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 4.3s. Construction of modules took 0.8s. Büchi inclusion checks took 11.2s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 5.1s AutomataMinimizationTime, 21 MinimizatonAttempts, 21777 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 3.4s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12543 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12543 mSDsluCounter, 27290 SdHoareTripleChecker+Invalid, 0.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 13213 mSDsCounter, 233 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 649 IncrementalHoareTripleChecker+Invalid, 882 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 233 mSolverCounterUnsat, 14077 mSDtfsCounter, 649 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN0 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 423]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 423]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-17 08:52:18,571 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)