./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:51:58,775 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:51:58,850 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:51:58,856 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:51:58,857 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:51:58,858 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:51:58,882 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:51:58,883 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:51:58,884 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:51:58,885 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:51:58,885 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:51:58,886 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:51:58,887 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:51:58,889 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:51:58,889 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:51:58,890 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:51:58,890 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:51:58,890 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:51:58,890 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:51:58,891 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:51:58,894 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:51:58,895 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:51:58,895 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:51:58,895 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:51:58,895 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:51:58,896 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:51:58,896 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:51:58,896 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:51:58,896 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:51:58,897 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:51:58,897 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:51:58,897 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:51:58,897 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:51:58,898 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:51:58,898 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:51:58,898 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:51:58,898 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:51:58,899 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:51:58,899 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:51:58,899 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:51:58,900 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2024-11-17 08:51:59,166 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:51:59,190 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:51:59,194 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:51:59,195 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:51:59,196 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:51:59,197 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2024-11-17 08:52:00,566 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:52:00,848 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:52:00,850 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2024-11-17 08:52:00,867 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/425405547/e59db7daf7744eef9aa34c96609034e9/FLAGba6a50172 [2024-11-17 08:52:01,132 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/425405547/e59db7daf7744eef9aa34c96609034e9 [2024-11-17 08:52:01,134 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:52:01,135 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:52:01,136 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:01,136 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:52:01,140 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:52:01,141 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,142 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4c190091 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01, skipping insertion in model container [2024-11-17 08:52:01,142 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,181 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:52:01,453 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:01,470 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:52:01,513 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:01,537 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:52:01,537 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01 WrapperNode [2024-11-17 08:52:01,538 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:01,538 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:01,538 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:52:01,539 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:52:01,545 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,553 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,607 INFO L138 Inliner]: procedures = 36, calls = 45, calls flagged for inlining = 40, calls inlined = 80, statements flattened = 1080 [2024-11-17 08:52:01,611 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:01,611 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:52:01,612 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:52:01,612 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:52:01,635 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,636 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,644 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,673 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:52:01,673 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,673 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,688 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,690 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,692 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,695 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,699 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:52:01,700 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:52:01,700 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:52:01,700 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:52:01,701 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (1/1) ... [2024-11-17 08:52:01,709 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:01,721 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:01,735 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:01,737 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:52:01,775 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:52:01,775 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:52:01,775 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:52:01,776 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:52:01,853 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:52:01,855 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:02,843 INFO L? ?]: Removed 198 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:02,844 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:02,873 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:02,873 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:02,875 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:02 BoogieIcfgContainer [2024-11-17 08:52:02,875 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:02,876 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:02,876 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:02,881 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:02,881 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:02,882 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:52:01" (1/3) ... [2024-11-17 08:52:02,883 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@42d81fd3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:02, skipping insertion in model container [2024-11-17 08:52:02,883 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:02,883 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:01" (2/3) ... [2024-11-17 08:52:02,883 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@42d81fd3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:02, skipping insertion in model container [2024-11-17 08:52:02,883 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:02,883 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:02" (3/3) ... [2024-11-17 08:52:02,885 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2024-11-17 08:52:02,954 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:02,954 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:02,954 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:02,954 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:02,954 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:02,955 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:02,955 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:02,955 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:02,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 470 states, 469 states have (on average 1.4989339019189765) internal successors, (703), 469 states have internal predecessors, (703), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 398 [2024-11-17 08:52:03,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,016 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,016 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:03,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 470 states, 469 states have (on average 1.4989339019189765) internal successors, (703), 469 states have internal predecessors, (703), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 398 [2024-11-17 08:52:03,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,036 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,036 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,044 INFO L745 eck$LassoCheckResult]: Stem: 457#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 29#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 123#L778true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 396#L358-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 234#L370true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 368#L375true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 177#L380true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 370#L385true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 315#L391true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 309#L526-1true assume !(0 == ~M_E~0); 241#L531-1true assume !(0 == ~T1_E~0); 186#L536-1true assume !(0 == ~T2_E~0); 301#L541-1true assume !(0 == ~T3_E~0); 182#L546-1true assume !(0 == ~T4_E~0); 253#L551-1true assume !(0 == ~E_M~0); 160#L556-1true assume !(0 == ~E_1~0); 196#L561-1true assume !(0 == ~E_2~0); 165#L566-1true assume !(0 == ~E_3~0); 403#L571-1true assume !(0 == ~E_4~0); 43#L577-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28#L262-7true assume 1 == ~m_pc~0; 352#L263-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 318#L265-7true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 441#L274-7true assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 398#L649-7true assume !(0 != activate_threads_~tmp~1#1); 245#L655-7true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8#L281-7true assume 1 == ~t1_pc~0; 355#L282-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 244#L284-7true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 220#L293-7true assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 209#L657-7true assume !(0 != activate_threads_~tmp___0~0#1); 382#L663-7true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92#L300-7true assume 1 == ~t2_pc~0; 150#L301-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60#L303-7true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 456#L312-7true assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 263#L665-7true assume !(0 != activate_threads_~tmp___1~0#1); 467#L671-7true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240#L319-7true assume 1 == ~t3_pc~0; 230#L320-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45#L322-7true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 397#L331-7true assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20#L673-7true assume !(0 != activate_threads_~tmp___2~0#1); 110#L679-7true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131#L338-7true assume 1 == ~t4_pc~0; 38#L339-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 216#L341-7true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 454#L350-7true assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 271#L681-7true assume !(0 != activate_threads_~tmp___3~0#1); 302#L687-7true assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78#L584-1true assume !(1 == ~M_E~0); 89#L589-1true assume !(1 == ~T1_E~0); 275#L594-1true assume !(1 == ~T2_E~0); 145#L599-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 17#L604-1true assume !(1 == ~T4_E~0); 12#L609-1true assume !(1 == ~E_M~0); 71#L614-1true assume !(1 == ~E_1~0); 119#L619-1true assume !(1 == ~E_2~0); 188#L624-1true assume !(1 == ~E_3~0); 426#L629-1true assume !(1 == ~E_4~0); 356#L635-1true assume true;assume { :end_inline_reset_delta_events } true; 179#L815true [2024-11-17 08:52:03,046 INFO L747 eck$LassoCheckResult]: Loop: 179#L815true assume true; 260#L815-1true assume !false; 140#start_simulation_while_6_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 200#L435true assume !true; 290#L443true assume true; 189#L519true assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15#L358true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 197#L526true assume 0 == ~M_E~0;~M_E~0 := 1; 40#L531true assume 0 == ~T1_E~0;~T1_E~0 := 1; 170#L536true assume 0 == ~T2_E~0;~T2_E~0 := 1; 308#L541true assume 0 == ~T3_E~0;~T3_E~0 := 1; 36#L546true assume !(0 == ~T4_E~0); 141#L551true assume 0 == ~E_M~0;~E_M~0 := 1; 461#L556true assume 0 == ~E_1~0;~E_1~0 := 1; 62#L561true assume 0 == ~E_2~0;~E_2~0 := 1; 94#L566true assume 0 == ~E_3~0;~E_3~0 := 1; 344#L571true assume 0 == ~E_4~0;~E_4~0 := 1; 169#L577true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 257#L262-1true assume 1 == ~m_pc~0; 227#L263-1true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 214#L265-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 424#L274-1true assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 300#L649-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 147#L655-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 324#L281-1true assume 1 == ~t1_pc~0; 413#L282-1true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46#L284-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 334#L293-1true assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 80#L657-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 154#L663-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281#L300-1true assume 1 == ~t2_pc~0; 328#L301-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 202#L303-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32#L312-1true assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 264#L665-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 274#L671-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336#L319-1true assume !(1 == ~t3_pc~0); 283#L329-1true is_transmit3_triggered_~__retres1~3#1 := 0; 357#L322-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 259#L331-1true assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 224#L673-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 314#L679-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83#L338-1true assume !(1 == ~t4_pc~0); 431#L348-1true is_transmit4_triggered_~__retres1~4#1 := 0; 354#L341-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 401#L350-1true assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 338#L681-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 341#L687-1true assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 399#L584true assume 1 == ~M_E~0;~M_E~0 := 2; 122#L589true assume 1 == ~T1_E~0;~T1_E~0 := 2; 439#L594true assume 1 == ~T2_E~0;~T2_E~0 := 2; 164#L599true assume 1 == ~T3_E~0;~T3_E~0 := 2; 155#L604true assume 1 == ~T4_E~0;~T4_E~0 := 2; 307#L609true assume 1 == ~E_M~0;~E_M~0 := 2; 148#L614true assume 1 == ~E_1~0;~E_1~0 := 2; 184#L619true assume 1 == ~E_2~0;~E_2~0 := 2; 388#L624true assume 1 == ~E_3~0;~E_3~0 := 2; 280#L629true assume 1 == ~E_4~0;~E_4~0 := 2; 26#L635true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 266#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 369#L416-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 312#L426-1true assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 99#L834true assume !(0 == start_simulation_~tmp~3#1); 343#L845true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 453#L398true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 250#L416true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 213#L426true assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 299#L789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267#L791true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191#L797true assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 206#L847true assume !(0 != start_simulation_~tmp___0~1#1); 179#L815true [2024-11-17 08:52:03,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,053 INFO L85 PathProgramCache]: Analyzing trace with hash 206510788, now seen corresponding path program 1 times [2024-11-17 08:52:03,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025364471] [2024-11-17 08:52:03,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025364471] [2024-11-17 08:52:03,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025364471] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,350 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:03,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760567175] [2024-11-17 08:52:03,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,356 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:03,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,357 INFO L85 PathProgramCache]: Analyzing trace with hash -1253522481, now seen corresponding path program 1 times [2024-11-17 08:52:03,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115189602] [2024-11-17 08:52:03,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115189602] [2024-11-17 08:52:03,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115189602] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:03,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83668119] [2024-11-17 08:52:03,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,405 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:03,406 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:03,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:03,440 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:03,442 INFO L87 Difference]: Start difference. First operand has 470 states, 469 states have (on average 1.4989339019189765) internal successors, (703), 469 states have internal predecessors, (703), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,490 INFO L93 Difference]: Finished difference Result 461 states and 677 transitions. [2024-11-17 08:52:03,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 461 states and 677 transitions. [2024-11-17 08:52:03,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:03,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 461 states to 454 states and 670 transitions. [2024-11-17 08:52:03,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2024-11-17 08:52:03,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2024-11-17 08:52:03,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 670 transitions. [2024-11-17 08:52:03,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:03,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 670 transitions. [2024-11-17 08:52:03,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 670 transitions. [2024-11-17 08:52:03,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2024-11-17 08:52:03,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 454 states, 454 states have (on average 1.475770925110132) internal successors, (670), 453 states have internal predecessors, (670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 670 transitions. [2024-11-17 08:52:03,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 454 states and 670 transitions. [2024-11-17 08:52:03,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:03,565 INFO L425 stractBuchiCegarLoop]: Abstraction has 454 states and 670 transitions. [2024-11-17 08:52:03,565 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:03,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 670 transitions. [2024-11-17 08:52:03,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:03,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,571 INFO L745 eck$LassoCheckResult]: Stem: 1393#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 998#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 999#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1165#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1042#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1043#L370 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1297#L375 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1225#L380 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1226#L385 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1358#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1353#L526-1 assume !(0 == ~M_E~0); 1303#L531-1 assume !(0 == ~T1_E~0); 1238#L536-1 assume !(0 == ~T2_E~0); 1239#L541-1 assume !(0 == ~T3_E~0); 1233#L546-1 assume !(0 == ~T4_E~0); 1234#L551-1 assume !(0 == ~E_M~0); 1204#L556-1 assume !(0 == ~E_1~0); 1205#L561-1 assume !(0 == ~E_2~0); 1212#L566-1 assume !(0 == ~E_3~0); 1213#L571-1 assume !(0 == ~E_4~0); 1028#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 995#L262-7 assume 1 == ~m_pc~0; 996#L263-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1301#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1359#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1384#L649-7 assume !(0 != activate_threads_~tmp~1#1); 1310#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 952#L281-7 assume 1 == ~t1_pc~0; 953#L282-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1309#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1277#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1266#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 1267#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1110#L300-7 assume 1 == ~t2_pc~0; 1111#L301-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1059#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1060#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1322#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 1323#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1302#L319-7 assume 1 == ~t3_pc~0; 1292#L320-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1029#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1030#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 979#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 980#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1143#L338-7 assume 1 == ~t4_pc~0; 1016#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1017#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1275#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1330#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 1331#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1085#L584-1 assume !(1 == ~M_E~0); 1086#L589-1 assume !(1 == ~T1_E~0); 1106#L594-1 assume !(1 == ~T2_E~0); 1191#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 973#L604-1 assume !(1 == ~T4_E~0); 963#L609-1 assume !(1 == ~E_M~0); 964#L614-1 assume !(1 == ~E_1~0); 1078#L619-1 assume !(1 == ~E_2~0); 1158#L624-1 assume !(1 == ~E_3~0); 1241#L629-1 assume !(1 == ~E_4~0); 1375#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 1228#L815 [2024-11-17 08:52:03,571 INFO L747 eck$LassoCheckResult]: Loop: 1228#L815 assume true; 1229#L815-1 assume !false; 1184#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1185#L435 assume true; 1254#L435-1 assume !false; 1311#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1312#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1236#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1327#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1328#L440 assume !(0 != eval_~tmp~0#1); 1345#L443 assume true; 1242#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 969#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 970#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 1021#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1022#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1219#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1012#L546 assume !(0 == ~T4_E~0); 1013#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 1186#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 1062#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 1063#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 1115#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 1217#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1218#L262-1 assume 1 == ~m_pc~0; 1288#L263-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1273#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1274#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1348#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1192#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1193#L281-1 assume !(1 == ~t1_pc~0); 1200#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1031#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1032#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1089#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1090#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1197#L300-1 assume 1 == ~t2_pc~0; 1341#L301-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1257#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1004#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1005#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1324#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1334#L319-1 assume 1 == ~t3_pc~0; 1317#L320-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1318#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1321#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1283#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1284#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1094#L338-1 assume 1 == ~t4_pc~0; 1095#L339-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1124#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1374#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1364#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1365#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1368#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 1163#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1164#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1211#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1198#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1199#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 1194#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 1195#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 1237#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 1340#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 992#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 993#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1126#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1355#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1121#L834 assume !(0 == start_simulation_~tmp~3#1); 1123#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1370#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1082#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1271#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1272#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1326#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1244#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1245#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1228#L815 [2024-11-17 08:52:03,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,573 INFO L85 PathProgramCache]: Analyzing trace with hash 2137129893, now seen corresponding path program 1 times [2024-11-17 08:52:03,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836200957] [2024-11-17 08:52:03,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,662 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836200957] [2024-11-17 08:52:03,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836200957] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,662 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:03,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230091789] [2024-11-17 08:52:03,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,663 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:03,665 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,665 INFO L85 PathProgramCache]: Analyzing trace with hash 440307507, now seen corresponding path program 1 times [2024-11-17 08:52:03,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095553353] [2024-11-17 08:52:03,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095553353] [2024-11-17 08:52:03,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095553353] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:03,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938741749] [2024-11-17 08:52:03,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,791 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:03,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:03,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:03,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:03,793 INFO L87 Difference]: Start difference. First operand 454 states and 670 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,822 INFO L93 Difference]: Finished difference Result 454 states and 669 transitions. [2024-11-17 08:52:03,822 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 669 transitions. [2024-11-17 08:52:03,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:03,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 669 transitions. [2024-11-17 08:52:03,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2024-11-17 08:52:03,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2024-11-17 08:52:03,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 669 transitions. [2024-11-17 08:52:03,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:03,859 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 669 transitions. [2024-11-17 08:52:03,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 669 transitions. [2024-11-17 08:52:03,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2024-11-17 08:52:03,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 454 states, 454 states have (on average 1.473568281938326) internal successors, (669), 453 states have internal predecessors, (669), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 669 transitions. [2024-11-17 08:52:03,893 INFO L240 hiAutomatonCegarLoop]: Abstraction has 454 states and 669 transitions. [2024-11-17 08:52:03,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:03,897 INFO L425 stractBuchiCegarLoop]: Abstraction has 454 states and 669 transitions. [2024-11-17 08:52:03,897 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:03,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 669 transitions. [2024-11-17 08:52:03,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:03,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,907 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,908 INFO L745 eck$LassoCheckResult]: Stem: 2310#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1915#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1916#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2082#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1959#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1960#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2214#L375 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2142#L380 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2143#L385 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2275#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2270#L526-1 assume !(0 == ~M_E~0); 2220#L531-1 assume !(0 == ~T1_E~0); 2155#L536-1 assume !(0 == ~T2_E~0); 2156#L541-1 assume !(0 == ~T3_E~0); 2150#L546-1 assume !(0 == ~T4_E~0); 2151#L551-1 assume !(0 == ~E_M~0); 2121#L556-1 assume !(0 == ~E_1~0); 2122#L561-1 assume !(0 == ~E_2~0); 2129#L566-1 assume !(0 == ~E_3~0); 2130#L571-1 assume !(0 == ~E_4~0); 1945#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1912#L262-7 assume 1 == ~m_pc~0; 1913#L263-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2218#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2276#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2301#L649-7 assume !(0 != activate_threads_~tmp~1#1); 2227#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1869#L281-7 assume 1 == ~t1_pc~0; 1870#L282-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2226#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2194#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2183#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 2184#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2027#L300-7 assume 1 == ~t2_pc~0; 2028#L301-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1976#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1977#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2239#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 2240#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2219#L319-7 assume 1 == ~t3_pc~0; 2209#L320-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1946#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1947#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1896#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 1897#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2060#L338-7 assume 1 == ~t4_pc~0; 1933#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1934#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2192#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2247#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 2248#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2002#L584-1 assume !(1 == ~M_E~0); 2003#L589-1 assume !(1 == ~T1_E~0); 2023#L594-1 assume !(1 == ~T2_E~0); 2108#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1890#L604-1 assume !(1 == ~T4_E~0); 1880#L609-1 assume !(1 == ~E_M~0); 1881#L614-1 assume !(1 == ~E_1~0); 1995#L619-1 assume !(1 == ~E_2~0); 2075#L624-1 assume !(1 == ~E_3~0); 2158#L629-1 assume !(1 == ~E_4~0); 2292#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 2145#L815 [2024-11-17 08:52:03,908 INFO L747 eck$LassoCheckResult]: Loop: 2145#L815 assume true; 2146#L815-1 assume !false; 2101#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2102#L435 assume true; 2171#L435-1 assume !false; 2228#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2229#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2153#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2244#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2245#L440 assume !(0 != eval_~tmp~0#1); 2262#L443 assume true; 2159#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1886#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1887#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 1938#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1939#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2136#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1929#L546 assume !(0 == ~T4_E~0); 1930#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 2103#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 1979#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 1980#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 2032#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 2134#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2135#L262-1 assume 1 == ~m_pc~0; 2205#L263-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2190#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2191#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2265#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2109#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2110#L281-1 assume !(1 == ~t1_pc~0); 2117#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1948#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1949#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2006#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2007#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2114#L300-1 assume 1 == ~t2_pc~0; 2258#L301-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2174#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1921#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1922#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2241#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2251#L319-1 assume 1 == ~t3_pc~0; 2234#L320-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2235#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2238#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2200#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2201#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2011#L338-1 assume 1 == ~t4_pc~0; 2012#L339-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2041#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2291#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2281#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2282#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2285#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 2080#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2081#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2128#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2115#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2116#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 2111#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 2112#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 2154#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 2257#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 1909#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1910#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2043#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2272#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2038#L834 assume !(0 == start_simulation_~tmp~3#1); 2040#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2287#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1999#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2188#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2189#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2243#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2161#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2162#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2145#L815 [2024-11-17 08:52:03,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1506671268, now seen corresponding path program 1 times [2024-11-17 08:52:03,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744533620] [2024-11-17 08:52:03,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,003 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744533620] [2024-11-17 08:52:04,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744533620] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,004 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:04,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505760996] [2024-11-17 08:52:04,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,006 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:04,007 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,007 INFO L85 PathProgramCache]: Analyzing trace with hash 440307507, now seen corresponding path program 2 times [2024-11-17 08:52:04,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663543156] [2024-11-17 08:52:04,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663543156] [2024-11-17 08:52:04,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1663543156] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:04,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2135828125] [2024-11-17 08:52:04,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,117 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:04,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:04,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:04,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:04,118 INFO L87 Difference]: Start difference. First operand 454 states and 669 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:04,131 INFO L93 Difference]: Finished difference Result 454 states and 668 transitions. [2024-11-17 08:52:04,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 668 transitions. [2024-11-17 08:52:04,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:04,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 668 transitions. [2024-11-17 08:52:04,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2024-11-17 08:52:04,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2024-11-17 08:52:04,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 668 transitions. [2024-11-17 08:52:04,138 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:04,138 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 668 transitions. [2024-11-17 08:52:04,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 668 transitions. [2024-11-17 08:52:04,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2024-11-17 08:52:04,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 454 states, 454 states have (on average 1.47136563876652) internal successors, (668), 453 states have internal predecessors, (668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 668 transitions. [2024-11-17 08:52:04,148 INFO L240 hiAutomatonCegarLoop]: Abstraction has 454 states and 668 transitions. [2024-11-17 08:52:04,148 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:04,149 INFO L425 stractBuchiCegarLoop]: Abstraction has 454 states and 668 transitions. [2024-11-17 08:52:04,150 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:04,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 668 transitions. [2024-11-17 08:52:04,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:04,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:04,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:04,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,155 INFO L745 eck$LassoCheckResult]: Stem: 3227#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2832#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2833#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2999#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2876#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2877#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3131#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3059#L380 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3060#L385 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3192#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3187#L526-1 assume !(0 == ~M_E~0); 3137#L531-1 assume !(0 == ~T1_E~0); 3072#L536-1 assume !(0 == ~T2_E~0); 3073#L541-1 assume !(0 == ~T3_E~0); 3067#L546-1 assume !(0 == ~T4_E~0); 3068#L551-1 assume !(0 == ~E_M~0); 3038#L556-1 assume !(0 == ~E_1~0); 3039#L561-1 assume !(0 == ~E_2~0); 3046#L566-1 assume !(0 == ~E_3~0); 3047#L571-1 assume !(0 == ~E_4~0); 2862#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2829#L262-7 assume 1 == ~m_pc~0; 2830#L263-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3135#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3193#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3218#L649-7 assume !(0 != activate_threads_~tmp~1#1); 3144#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2786#L281-7 assume 1 == ~t1_pc~0; 2787#L282-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3143#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3111#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3100#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 3101#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2944#L300-7 assume 1 == ~t2_pc~0; 2945#L301-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2893#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2894#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3156#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 3157#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3136#L319-7 assume 1 == ~t3_pc~0; 3126#L320-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2863#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2864#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2813#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 2814#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2977#L338-7 assume 1 == ~t4_pc~0; 2850#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2851#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3109#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3164#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 3165#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2919#L584-1 assume !(1 == ~M_E~0); 2920#L589-1 assume !(1 == ~T1_E~0); 2940#L594-1 assume !(1 == ~T2_E~0); 3025#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2807#L604-1 assume !(1 == ~T4_E~0); 2797#L609-1 assume !(1 == ~E_M~0); 2798#L614-1 assume !(1 == ~E_1~0); 2912#L619-1 assume !(1 == ~E_2~0); 2992#L624-1 assume !(1 == ~E_3~0); 3075#L629-1 assume !(1 == ~E_4~0); 3209#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 3062#L815 [2024-11-17 08:52:04,156 INFO L747 eck$LassoCheckResult]: Loop: 3062#L815 assume true; 3063#L815-1 assume !false; 3018#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3019#L435 assume true; 3088#L435-1 assume !false; 3145#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3146#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3070#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3161#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3162#L440 assume !(0 != eval_~tmp~0#1); 3179#L443 assume true; 3076#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2803#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2804#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 2855#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2856#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3053#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2846#L546 assume !(0 == ~T4_E~0); 2847#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 3020#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 2896#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 2897#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 2949#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 3051#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3052#L262-1 assume 1 == ~m_pc~0; 3122#L263-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3107#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3108#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3182#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3026#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3027#L281-1 assume !(1 == ~t1_pc~0); 3034#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 2865#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2866#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2923#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2924#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3031#L300-1 assume 1 == ~t2_pc~0; 3175#L301-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3091#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2838#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2839#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3158#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3168#L319-1 assume !(1 == ~t3_pc~0); 3153#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 3152#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3155#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3117#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3118#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2928#L338-1 assume 1 == ~t4_pc~0; 2929#L339-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2958#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3208#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3198#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3199#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3202#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 2997#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2998#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3045#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3032#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3033#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 3028#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 3029#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 3071#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 3174#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 2826#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2827#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2960#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3189#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2955#L834 assume !(0 == start_simulation_~tmp~3#1); 2957#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3204#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2916#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3105#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3106#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3160#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3078#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3079#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3062#L815 [2024-11-17 08:52:04,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1486333893, now seen corresponding path program 1 times [2024-11-17 08:52:04,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115892968] [2024-11-17 08:52:04,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,214 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115892968] [2024-11-17 08:52:04,214 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115892968] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,215 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,215 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:04,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28076793] [2024-11-17 08:52:04,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,215 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:04,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,216 INFO L85 PathProgramCache]: Analyzing trace with hash 114804406, now seen corresponding path program 1 times [2024-11-17 08:52:04,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420222375] [2024-11-17 08:52:04,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [420222375] [2024-11-17 08:52:04,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [420222375] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:04,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787770623] [2024-11-17 08:52:04,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,303 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:04,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:04,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:04,303 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:04,303 INFO L87 Difference]: Start difference. First operand 454 states and 668 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:04,318 INFO L93 Difference]: Finished difference Result 454 states and 667 transitions. [2024-11-17 08:52:04,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 667 transitions. [2024-11-17 08:52:04,321 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:04,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 667 transitions. [2024-11-17 08:52:04,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2024-11-17 08:52:04,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2024-11-17 08:52:04,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 667 transitions. [2024-11-17 08:52:04,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:04,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 667 transitions. [2024-11-17 08:52:04,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 667 transitions. [2024-11-17 08:52:04,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2024-11-17 08:52:04,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 454 states, 454 states have (on average 1.4691629955947136) internal successors, (667), 453 states have internal predecessors, (667), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 667 transitions. [2024-11-17 08:52:04,335 INFO L240 hiAutomatonCegarLoop]: Abstraction has 454 states and 667 transitions. [2024-11-17 08:52:04,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:04,336 INFO L425 stractBuchiCegarLoop]: Abstraction has 454 states and 667 transitions. [2024-11-17 08:52:04,336 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:04,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 667 transitions. [2024-11-17 08:52:04,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:04,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:04,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:04,343 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,343 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,344 INFO L745 eck$LassoCheckResult]: Stem: 4144#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3749#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3750#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3916#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3793#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3794#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4048#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3976#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3977#L385 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4109#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4104#L526-1 assume !(0 == ~M_E~0); 4054#L531-1 assume !(0 == ~T1_E~0); 3989#L536-1 assume !(0 == ~T2_E~0); 3990#L541-1 assume !(0 == ~T3_E~0); 3984#L546-1 assume !(0 == ~T4_E~0); 3985#L551-1 assume !(0 == ~E_M~0); 3955#L556-1 assume !(0 == ~E_1~0); 3956#L561-1 assume !(0 == ~E_2~0); 3963#L566-1 assume !(0 == ~E_3~0); 3964#L571-1 assume !(0 == ~E_4~0); 3779#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3746#L262-7 assume 1 == ~m_pc~0; 3747#L263-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4052#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4110#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4135#L649-7 assume !(0 != activate_threads_~tmp~1#1); 4061#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3703#L281-7 assume 1 == ~t1_pc~0; 3704#L282-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4060#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4028#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4017#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 4018#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3861#L300-7 assume 1 == ~t2_pc~0; 3862#L301-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3810#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3811#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4073#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 4074#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4053#L319-7 assume 1 == ~t3_pc~0; 4043#L320-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3780#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3781#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3730#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 3731#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3894#L338-7 assume 1 == ~t4_pc~0; 3767#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3768#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4026#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4081#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 4082#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3836#L584-1 assume !(1 == ~M_E~0); 3837#L589-1 assume !(1 == ~T1_E~0); 3857#L594-1 assume !(1 == ~T2_E~0); 3942#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3724#L604-1 assume !(1 == ~T4_E~0); 3714#L609-1 assume !(1 == ~E_M~0); 3715#L614-1 assume !(1 == ~E_1~0); 3829#L619-1 assume !(1 == ~E_2~0); 3909#L624-1 assume !(1 == ~E_3~0); 3992#L629-1 assume !(1 == ~E_4~0); 4126#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 3979#L815 [2024-11-17 08:52:04,344 INFO L747 eck$LassoCheckResult]: Loop: 3979#L815 assume true; 3980#L815-1 assume !false; 3935#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3936#L435 assume true; 4005#L435-1 assume !false; 4062#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4063#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3987#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4078#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4079#L440 assume !(0 != eval_~tmp~0#1); 4096#L443 assume true; 3993#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3720#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3721#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 3772#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3773#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3970#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3763#L546 assume !(0 == ~T4_E~0); 3764#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 3937#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 3813#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 3814#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 3866#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 3968#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3969#L262-1 assume 1 == ~m_pc~0; 4039#L263-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4024#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4025#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4099#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3943#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3944#L281-1 assume 1 == ~t1_pc~0; 4112#L282-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3782#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3783#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3840#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3841#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3948#L300-1 assume 1 == ~t2_pc~0; 4092#L301-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4008#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3755#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3756#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4075#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4085#L319-1 assume 1 == ~t3_pc~0; 4068#L320-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4069#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4072#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4034#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4035#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3845#L338-1 assume 1 == ~t4_pc~0; 3846#L339-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3875#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4125#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4115#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4116#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4119#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 3914#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3915#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3962#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3949#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3950#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 3945#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 3946#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 3988#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 4091#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 3743#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3744#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3877#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4106#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3872#L834 assume !(0 == start_simulation_~tmp~3#1); 3874#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4121#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3833#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4022#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4023#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4077#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3995#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3996#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3979#L815 [2024-11-17 08:52:04,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,344 INFO L85 PathProgramCache]: Analyzing trace with hash 792941188, now seen corresponding path program 1 times [2024-11-17 08:52:04,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561643749] [2024-11-17 08:52:04,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561643749] [2024-11-17 08:52:04,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561643749] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:04,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956227325] [2024-11-17 08:52:04,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,375 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:04,375 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,375 INFO L85 PathProgramCache]: Analyzing trace with hash 397640752, now seen corresponding path program 1 times [2024-11-17 08:52:04,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295755835] [2024-11-17 08:52:04,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,438 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [295755835] [2024-11-17 08:52:04,438 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [295755835] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:04,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301611910] [2024-11-17 08:52:04,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,439 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:04,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:04,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:04,440 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:04,440 INFO L87 Difference]: Start difference. First operand 454 states and 667 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:04,453 INFO L93 Difference]: Finished difference Result 454 states and 666 transitions. [2024-11-17 08:52:04,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454 states and 666 transitions. [2024-11-17 08:52:04,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:04,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454 states to 454 states and 666 transitions. [2024-11-17 08:52:04,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454 [2024-11-17 08:52:04,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454 [2024-11-17 08:52:04,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454 states and 666 transitions. [2024-11-17 08:52:04,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:04,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454 states and 666 transitions. [2024-11-17 08:52:04,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454 states and 666 transitions. [2024-11-17 08:52:04,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454 to 454. [2024-11-17 08:52:04,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 454 states, 454 states have (on average 1.4669603524229076) internal successors, (666), 453 states have internal predecessors, (666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 666 transitions. [2024-11-17 08:52:04,467 INFO L240 hiAutomatonCegarLoop]: Abstraction has 454 states and 666 transitions. [2024-11-17 08:52:04,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:04,468 INFO L425 stractBuchiCegarLoop]: Abstraction has 454 states and 666 transitions. [2024-11-17 08:52:04,469 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:04,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 454 states and 666 transitions. [2024-11-17 08:52:04,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 387 [2024-11-17 08:52:04,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:04,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:04,474 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,474 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,475 INFO L745 eck$LassoCheckResult]: Stem: 5061#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4666#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4667#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4833#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4710#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4711#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4965#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4893#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4894#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5026#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5021#L526-1 assume !(0 == ~M_E~0); 4971#L531-1 assume !(0 == ~T1_E~0); 4906#L536-1 assume !(0 == ~T2_E~0); 4907#L541-1 assume !(0 == ~T3_E~0); 4901#L546-1 assume !(0 == ~T4_E~0); 4902#L551-1 assume !(0 == ~E_M~0); 4872#L556-1 assume !(0 == ~E_1~0); 4873#L561-1 assume !(0 == ~E_2~0); 4880#L566-1 assume !(0 == ~E_3~0); 4881#L571-1 assume !(0 == ~E_4~0); 4696#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4663#L262-7 assume 1 == ~m_pc~0; 4664#L263-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4969#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5027#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5052#L649-7 assume !(0 != activate_threads_~tmp~1#1); 4978#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4620#L281-7 assume 1 == ~t1_pc~0; 4621#L282-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4977#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4945#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4934#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 4935#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4778#L300-7 assume 1 == ~t2_pc~0; 4779#L301-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4727#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4728#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4990#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 4991#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4970#L319-7 assume 1 == ~t3_pc~0; 4960#L320-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4697#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4698#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4647#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 4648#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4811#L338-7 assume 1 == ~t4_pc~0; 4684#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4685#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4943#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4998#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 4999#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4753#L584-1 assume !(1 == ~M_E~0); 4754#L589-1 assume !(1 == ~T1_E~0); 4774#L594-1 assume !(1 == ~T2_E~0); 4859#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4641#L604-1 assume !(1 == ~T4_E~0); 4631#L609-1 assume !(1 == ~E_M~0); 4632#L614-1 assume !(1 == ~E_1~0); 4746#L619-1 assume !(1 == ~E_2~0); 4826#L624-1 assume !(1 == ~E_3~0); 4909#L629-1 assume !(1 == ~E_4~0); 5043#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 4896#L815 [2024-11-17 08:52:04,475 INFO L747 eck$LassoCheckResult]: Loop: 4896#L815 assume true; 4897#L815-1 assume !false; 4852#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4853#L435 assume true; 4922#L435-1 assume !false; 4979#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4980#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4904#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4995#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4996#L440 assume !(0 != eval_~tmp~0#1); 5013#L443 assume true; 4910#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4637#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4638#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 4689#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4690#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4887#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4680#L546 assume !(0 == ~T4_E~0); 4681#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 4854#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 4730#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 4731#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 4783#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 4885#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4886#L262-1 assume 1 == ~m_pc~0; 4956#L263-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4941#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4942#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5016#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4860#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4861#L281-1 assume !(1 == ~t1_pc~0); 4868#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 4699#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4700#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4757#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4758#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4865#L300-1 assume 1 == ~t2_pc~0; 5009#L301-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4925#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4672#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4673#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4992#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5002#L319-1 assume 1 == ~t3_pc~0; 4985#L320-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4986#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4989#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4951#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4952#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4762#L338-1 assume 1 == ~t4_pc~0; 4763#L339-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4792#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5042#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5032#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5033#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5036#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 4831#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4832#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4879#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4866#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4867#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 4862#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 4863#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 4905#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 5008#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 4660#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4661#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4794#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5023#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4789#L834 assume !(0 == start_simulation_~tmp~3#1); 4791#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5038#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4750#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4939#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4940#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4994#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4912#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4913#L847 assume !(0 != start_simulation_~tmp___0~1#1); 4896#L815 [2024-11-17 08:52:04,476 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,476 INFO L85 PathProgramCache]: Analyzing trace with hash 354931685, now seen corresponding path program 1 times [2024-11-17 08:52:04,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926295330] [2024-11-17 08:52:04,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,529 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,529 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926295330] [2024-11-17 08:52:04,529 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926295330] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,529 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:04,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585936166] [2024-11-17 08:52:04,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,530 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:04,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,530 INFO L85 PathProgramCache]: Analyzing trace with hash 440307507, now seen corresponding path program 3 times [2024-11-17 08:52:04,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,531 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535726270] [2024-11-17 08:52:04,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,626 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535726270] [2024-11-17 08:52:04,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535726270] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:04,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700821591] [2024-11-17 08:52:04,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,628 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:04,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:04,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:04,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:04,629 INFO L87 Difference]: Start difference. First operand 454 states and 666 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:04,704 INFO L93 Difference]: Finished difference Result 824 states and 1192 transitions. [2024-11-17 08:52:04,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 824 states and 1192 transitions. [2024-11-17 08:52:04,709 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 756 [2024-11-17 08:52:04,713 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 824 states to 824 states and 1192 transitions. [2024-11-17 08:52:04,714 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 824 [2024-11-17 08:52:04,714 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 824 [2024-11-17 08:52:04,714 INFO L73 IsDeterministic]: Start isDeterministic. Operand 824 states and 1192 transitions. [2024-11-17 08:52:04,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:04,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 824 states and 1192 transitions. [2024-11-17 08:52:04,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 824 states and 1192 transitions. [2024-11-17 08:52:04,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 824 to 790. [2024-11-17 08:52:04,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 790 states, 790 states have (on average 1.4493670886075949) internal successors, (1145), 789 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 790 states and 1145 transitions. [2024-11-17 08:52:04,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 790 states and 1145 transitions. [2024-11-17 08:52:04,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:04,736 INFO L425 stractBuchiCegarLoop]: Abstraction has 790 states and 1145 transitions. [2024-11-17 08:52:04,736 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:52:04,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 790 states and 1145 transitions. [2024-11-17 08:52:04,740 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 722 [2024-11-17 08:52:04,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:04,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:04,741 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,741 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,743 INFO L745 eck$LassoCheckResult]: Stem: 6361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5952#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5953#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6118#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5996#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 5997#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6252#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6180#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6181#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6317#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6312#L526-1 assume !(0 == ~M_E~0); 6258#L531-1 assume !(0 == ~T1_E~0); 6193#L536-1 assume !(0 == ~T2_E~0); 6194#L541-1 assume !(0 == ~T3_E~0); 6188#L546-1 assume !(0 == ~T4_E~0); 6189#L551-1 assume !(0 == ~E_M~0); 6160#L556-1 assume !(0 == ~E_1~0); 6161#L561-1 assume !(0 == ~E_2~0); 6167#L566-1 assume !(0 == ~E_3~0); 6168#L571-1 assume !(0 == ~E_4~0); 5982#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5950#L262-7 assume !(1 == ~m_pc~0); 5951#L272-7 is_master_triggered_~__retres1~0#1 := 0; 6256#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6318#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6347#L649-7 assume !(0 != activate_threads_~tmp~1#1); 6266#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5907#L281-7 assume 1 == ~t1_pc~0; 5908#L282-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6265#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6233#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6222#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 6223#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6063#L300-7 assume 1 == ~t2_pc~0; 6064#L301-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6012#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6013#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6279#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 6280#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6257#L319-7 assume 1 == ~t3_pc~0; 6247#L320-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5983#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5984#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5934#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 5935#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6096#L338-7 assume 1 == ~t4_pc~0; 5970#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5971#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6231#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6287#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 6288#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6038#L584-1 assume !(1 == ~M_E~0); 6039#L589-1 assume !(1 == ~T1_E~0); 6059#L594-1 assume !(1 == ~T2_E~0); 6147#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5928#L604-1 assume !(1 == ~T4_E~0); 5918#L609-1 assume !(1 == ~E_M~0); 5919#L614-1 assume !(1 == ~E_1~0); 6031#L619-1 assume !(1 == ~E_2~0); 6111#L624-1 assume !(1 == ~E_3~0); 6196#L629-1 assume !(1 == ~E_4~0); 6336#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 6183#L815 [2024-11-17 08:52:04,744 INFO L747 eck$LassoCheckResult]: Loop: 6183#L815 assume true; 6184#L815-1 assume !false; 6140#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6141#L435 assume true; 6209#L435-1 assume !false; 6267#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6268#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6191#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6284#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6285#L440 assume !(0 != eval_~tmp~0#1); 6302#L443 assume true; 6197#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5924#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5925#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 5975#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5976#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6174#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5966#L546 assume !(0 == ~T4_E~0); 5967#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 6142#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 6015#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 6016#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 6068#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 6172#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6173#L262-1 assume !(1 == ~m_pc~0); 6276#L272-1 is_master_triggered_~__retres1~0#1 := 0; 6648#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6647#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6646#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6642#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6641#L281-1 assume 1 == ~t1_pc~0; 6640#L282-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6638#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6637#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6636#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6635#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6634#L300-1 assume !(1 == ~t2_pc~0); 6632#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 6631#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6630#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6629#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6628#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6627#L319-1 assume !(1 == ~t3_pc~0); 6625#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 6624#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6623#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6622#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6621#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6620#L338-1 assume !(1 == ~t4_pc~0); 6618#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 6617#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6616#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6323#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6324#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6615#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 6614#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6613#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6612#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6611#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6610#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 6609#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 6608#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 6607#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 6297#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 5947#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5948#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6079#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6314#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6074#L834 assume !(0 == start_simulation_~tmp~3#1); 6076#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6330#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6035#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6227#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 6228#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6283#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6199#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6200#L847 assume !(0 != start_simulation_~tmp___0~1#1); 6183#L815 [2024-11-17 08:52:04,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,745 INFO L85 PathProgramCache]: Analyzing trace with hash -208921304, now seen corresponding path program 1 times [2024-11-17 08:52:04,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55373463] [2024-11-17 08:52:04,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55373463] [2024-11-17 08:52:04,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55373463] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:04,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619216218] [2024-11-17 08:52:04,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,785 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:04,785 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1541953404, now seen corresponding path program 1 times [2024-11-17 08:52:04,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307355682] [2024-11-17 08:52:04,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307355682] [2024-11-17 08:52:04,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307355682] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:04,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144583750] [2024-11-17 08:52:04,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,838 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:04,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:04,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:04,839 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:04,839 INFO L87 Difference]: Start difference. First operand 790 states and 1145 transitions. cyclomatic complexity: 357 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:04,900 INFO L93 Difference]: Finished difference Result 1425 states and 2048 transitions. [2024-11-17 08:52:04,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1425 states and 2048 transitions. [2024-11-17 08:52:04,908 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1352 [2024-11-17 08:52:04,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1425 states to 1425 states and 2048 transitions. [2024-11-17 08:52:04,916 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1425 [2024-11-17 08:52:04,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1425 [2024-11-17 08:52:04,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1425 states and 2048 transitions. [2024-11-17 08:52:04,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:04,919 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1425 states and 2048 transitions. [2024-11-17 08:52:04,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1425 states and 2048 transitions. [2024-11-17 08:52:04,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1425 to 1417. [2024-11-17 08:52:04,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1417 states, 1417 states have (on average 1.4396612561750177) internal successors, (2040), 1416 states have internal predecessors, (2040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1417 states to 1417 states and 2040 transitions. [2024-11-17 08:52:04,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1417 states and 2040 transitions. [2024-11-17 08:52:04,943 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:04,945 INFO L425 stractBuchiCegarLoop]: Abstraction has 1417 states and 2040 transitions. [2024-11-17 08:52:04,945 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:52:04,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1417 states and 2040 transitions. [2024-11-17 08:52:04,951 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1344 [2024-11-17 08:52:04,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:04,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:04,953 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,953 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,954 INFO L745 eck$LassoCheckResult]: Stem: 8626#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8175#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8176#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8343#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8218#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 8219#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8488#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8408#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8409#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8558#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8551#L526-1 assume !(0 == ~M_E~0); 8496#L531-1 assume !(0 == ~T1_E~0); 8422#L536-1 assume !(0 == ~T2_E~0); 8423#L541-1 assume !(0 == ~T3_E~0); 8416#L546-1 assume !(0 == ~T4_E~0); 8417#L551-1 assume !(0 == ~E_M~0); 8387#L556-1 assume !(0 == ~E_1~0); 8388#L561-1 assume !(0 == ~E_2~0); 8394#L566-1 assume !(0 == ~E_3~0); 8395#L571-1 assume !(0 == ~E_4~0); 8205#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8173#L262-7 assume !(1 == ~m_pc~0); 8174#L272-7 is_master_triggered_~__retres1~0#1 := 0; 8494#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8559#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8597#L649-7 assume !(0 != activate_threads_~tmp~1#1); 8503#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8131#L281-7 assume !(1 == ~t1_pc~0); 8132#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 8502#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8467#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8455#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 8456#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8287#L300-7 assume 1 == ~t2_pc~0; 8288#L301-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8234#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8235#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8516#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 8517#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8495#L319-7 assume 1 == ~t3_pc~0; 8483#L320-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8206#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8207#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8157#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 8158#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8321#L338-7 assume 1 == ~t4_pc~0; 8193#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8194#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8464#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8525#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 8526#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8262#L584-1 assume !(1 == ~M_E~0); 8263#L589-1 assume !(1 == ~T1_E~0); 8283#L594-1 assume !(1 == ~T2_E~0); 8374#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8151#L604-1 assume !(1 == ~T4_E~0); 8141#L609-1 assume !(1 == ~E_M~0); 8142#L614-1 assume !(1 == ~E_1~0); 8255#L619-1 assume !(1 == ~E_2~0); 8336#L624-1 assume !(1 == ~E_3~0); 8425#L629-1 assume !(1 == ~E_4~0); 8578#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 8411#L815 [2024-11-17 08:52:04,954 INFO L747 eck$LassoCheckResult]: Loop: 8411#L815 assume true; 8412#L815-1 assume !false; 8366#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8367#L435 assume true; 8441#L435-1 assume !false; 8504#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8505#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8419#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8522#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8523#L440 assume !(0 != eval_~tmp~0#1); 8542#L443 assume true; 8426#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8147#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8148#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 8198#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8199#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8402#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8189#L546 assume !(0 == ~T4_E~0); 8190#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 8368#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 8237#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 8238#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 8292#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 8400#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8401#L262-1 assume !(1 == ~m_pc~0); 8513#L272-1 is_master_triggered_~__retres1~0#1 := 0; 8462#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8463#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8546#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8375#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8376#L281-1 assume !(1 == ~t1_pc~0); 8383#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 8208#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8209#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8266#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8267#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8380#L300-1 assume 1 == ~t2_pc~0; 8537#L301-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8444#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8181#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8182#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8518#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8529#L319-1 assume !(1 == ~t3_pc~0); 8512#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 8511#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8514#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8472#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8473#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8271#L338-1 assume 1 == ~t4_pc~0; 8272#L339-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8303#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8577#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8564#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8565#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8568#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 8341#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8342#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8393#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8381#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8382#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 8377#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 8378#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 8420#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 8536#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 8170#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8171#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8305#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8555#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8300#L834 assume !(0 == start_simulation_~tmp~3#1); 8302#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 9315#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 9312#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9303#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9296#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9291#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9286#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9281#L847 assume !(0 != start_simulation_~tmp___0~1#1); 8411#L815 [2024-11-17 08:52:04,954 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,954 INFO L85 PathProgramCache]: Analyzing trace with hash -534424405, now seen corresponding path program 1 times [2024-11-17 08:52:04,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [6377010] [2024-11-17 08:52:04,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [6377010] [2024-11-17 08:52:05,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [6377010] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:05,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554193852] [2024-11-17 08:52:05,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,020 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:05,020 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,020 INFO L85 PathProgramCache]: Analyzing trace with hash 945898361, now seen corresponding path program 1 times [2024-11-17 08:52:05,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,020 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593371126] [2024-11-17 08:52:05,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593371126] [2024-11-17 08:52:05,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593371126] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:05,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067070543] [2024-11-17 08:52:05,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,078 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:05,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:05,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:05,079 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:05,079 INFO L87 Difference]: Start difference. First operand 1417 states and 2040 transitions. cyclomatic complexity: 627 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:05,146 INFO L93 Difference]: Finished difference Result 2592 states and 3705 transitions. [2024-11-17 08:52:05,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2592 states and 3705 transitions. [2024-11-17 08:52:05,160 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2508 [2024-11-17 08:52:05,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2592 states to 2592 states and 3705 transitions. [2024-11-17 08:52:05,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2592 [2024-11-17 08:52:05,176 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2592 [2024-11-17 08:52:05,176 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2592 states and 3705 transitions. [2024-11-17 08:52:05,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:05,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2592 states and 3705 transitions. [2024-11-17 08:52:05,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2592 states and 3705 transitions. [2024-11-17 08:52:05,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2592 to 2576. [2024-11-17 08:52:05,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2576 states, 2576 states have (on average 1.4320652173913044) internal successors, (3689), 2575 states have internal predecessors, (3689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2576 states to 2576 states and 3689 transitions. [2024-11-17 08:52:05,271 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2576 states and 3689 transitions. [2024-11-17 08:52:05,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:05,273 INFO L425 stractBuchiCegarLoop]: Abstraction has 2576 states and 3689 transitions. [2024-11-17 08:52:05,274 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:52:05,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2576 states and 3689 transitions. [2024-11-17 08:52:05,284 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2492 [2024-11-17 08:52:05,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:05,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:05,285 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,285 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,286 INFO L745 eck$LassoCheckResult]: Stem: 12646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12194#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12195#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12363#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12237#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 12238#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12504#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12428#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12429#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12570#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12563#L526-1 assume !(0 == ~M_E~0); 12510#L531-1 assume !(0 == ~T1_E~0); 12441#L536-1 assume !(0 == ~T2_E~0); 12442#L541-1 assume !(0 == ~T3_E~0); 12436#L546-1 assume !(0 == ~T4_E~0); 12437#L551-1 assume !(0 == ~E_M~0); 12409#L556-1 assume !(0 == ~E_1~0); 12410#L561-1 assume !(0 == ~E_2~0); 12416#L566-1 assume !(0 == ~E_3~0); 12417#L571-1 assume !(0 == ~E_4~0); 12224#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12192#L262-7 assume !(1 == ~m_pc~0); 12193#L272-7 is_master_triggered_~__retres1~0#1 := 0; 12508#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12571#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12618#L649-7 assume !(0 != activate_threads_~tmp~1#1); 12518#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12148#L281-7 assume !(1 == ~t1_pc~0); 12149#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 12517#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12481#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12470#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 12471#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12305#L300-7 assume !(1 == ~t2_pc~0); 12306#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 12253#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12254#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12530#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 12531#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12509#L319-7 assume 1 == ~t3_pc~0; 12499#L320-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12225#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12226#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12174#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 12175#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12340#L338-7 assume 1 == ~t4_pc~0; 12212#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12213#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12479#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12538#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 12539#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12279#L584-1 assume !(1 == ~M_E~0); 12280#L589-1 assume !(1 == ~T1_E~0); 12301#L594-1 assume !(1 == ~T2_E~0); 12393#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12168#L604-1 assume !(1 == ~T4_E~0); 12158#L609-1 assume !(1 == ~E_M~0); 12159#L614-1 assume !(1 == ~E_1~0); 12272#L619-1 assume !(1 == ~E_2~0); 12356#L624-1 assume !(1 == ~E_3~0); 12444#L629-1 assume !(1 == ~E_4~0); 12602#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 12603#L815 [2024-11-17 08:52:05,286 INFO L747 eck$LassoCheckResult]: Loop: 12603#L815 assume true; 14399#L815-1 assume !false; 14396#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12642#L435 assume true; 14392#L435-1 assume !false; 14389#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14058#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14053#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14049#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14041#L440 assume !(0 != eval_~tmp~0#1); 14042#L443 assume true; 14614#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14612#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14610#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 12217#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12218#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12423#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12208#L546 assume !(0 == ~T4_E~0); 12209#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 12387#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 12647#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 14550#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 12593#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 12421#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12422#L262-1 assume !(1 == ~m_pc~0); 12528#L272-1 is_master_triggered_~__retres1~0#1 := 0; 12477#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12478#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12557#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12394#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12395#L281-1 assume !(1 == ~t1_pc~0); 12578#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 14539#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14537#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14535#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14533#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14531#L300-1 assume !(1 == ~t2_pc~0); 14529#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 14527#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14525#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14523#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14521#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14519#L319-1 assume !(1 == ~t3_pc~0); 14515#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 14513#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14475#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14474#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14464#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14452#L338-1 assume !(1 == ~t4_pc~0); 12320#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 12321#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12601#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12584#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12585#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12588#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 12361#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12362#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12415#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12400#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12401#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 12396#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 12397#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 12440#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 12549#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 12187#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12188#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12323#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12567#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12316#L834 assume !(0 == start_simulation_~tmp~3#1); 12318#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14415#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14412#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14410#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 14408#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14406#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14404#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 14402#L847 assume !(0 != start_simulation_~tmp___0~1#1); 12603#L815 [2024-11-17 08:52:05,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,287 INFO L85 PathProgramCache]: Analyzing trace with hash 668150382, now seen corresponding path program 1 times [2024-11-17 08:52:05,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261041330] [2024-11-17 08:52:05,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [261041330] [2024-11-17 08:52:05,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [261041330] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:05,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268466903] [2024-11-17 08:52:05,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,331 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:05,332 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1584620159, now seen corresponding path program 1 times [2024-11-17 08:52:05,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455495940] [2024-11-17 08:52:05,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455495940] [2024-11-17 08:52:05,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455495940] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:05,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265369368] [2024-11-17 08:52:05,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,378 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:05,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:05,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:05,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:05,379 INFO L87 Difference]: Start difference. First operand 2576 states and 3689 transitions. cyclomatic complexity: 1121 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:05,545 INFO L93 Difference]: Finished difference Result 5859 states and 8322 transitions. [2024-11-17 08:52:05,545 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5859 states and 8322 transitions. [2024-11-17 08:52:05,585 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5704 [2024-11-17 08:52:05,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5859 states to 5859 states and 8322 transitions. [2024-11-17 08:52:05,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5859 [2024-11-17 08:52:05,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5859 [2024-11-17 08:52:05,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5859 states and 8322 transitions. [2024-11-17 08:52:05,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:05,635 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5859 states and 8322 transitions. [2024-11-17 08:52:05,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5859 states and 8322 transitions. [2024-11-17 08:52:05,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5859 to 4719. [2024-11-17 08:52:05,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4719 states, 4719 states have (on average 1.427844882390337) internal successors, (6738), 4718 states have internal predecessors, (6738), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4719 states to 4719 states and 6738 transitions. [2024-11-17 08:52:05,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4719 states and 6738 transitions. [2024-11-17 08:52:05,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:05,723 INFO L425 stractBuchiCegarLoop]: Abstraction has 4719 states and 6738 transitions. [2024-11-17 08:52:05,723 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:52:05,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4719 states and 6738 transitions. [2024-11-17 08:52:05,741 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4616 [2024-11-17 08:52:05,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:05,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:05,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,743 INFO L745 eck$LassoCheckResult]: Stem: 21121#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 20640#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20641#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20815#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20685#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 20686#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20961#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20883#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20884#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21039#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21033#L526-1 assume !(0 == ~M_E~0); 20969#L531-1 assume !(0 == ~T1_E~0); 20897#L536-1 assume !(0 == ~T2_E~0); 20898#L541-1 assume !(0 == ~T3_E~0); 20891#L546-1 assume !(0 == ~T4_E~0); 20892#L551-1 assume !(0 == ~E_M~0); 20862#L556-1 assume !(0 == ~E_1~0); 20863#L561-1 assume !(0 == ~E_2~0); 20869#L566-1 assume !(0 == ~E_3~0); 20870#L571-1 assume !(0 == ~E_4~0); 20670#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20638#L262-7 assume !(1 == ~m_pc~0); 20639#L272-7 is_master_triggered_~__retres1~0#1 := 0; 20966#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21040#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21090#L649-7 assume !(0 != activate_threads_~tmp~1#1); 20975#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20595#L281-7 assume !(1 == ~t1_pc~0); 20596#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 20974#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20942#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20929#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 20930#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20758#L300-7 assume !(1 == ~t2_pc~0); 20759#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 20700#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20701#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20988#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 20989#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20967#L319-7 assume !(1 == ~t3_pc~0); 20968#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 20671#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20672#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20620#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 20621#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20792#L338-7 assume 1 == ~t4_pc~0; 20658#L339-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20659#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20938#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20998#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 20999#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20732#L584-1 assume !(1 == ~M_E~0); 20733#L589-1 assume !(1 == ~T1_E~0); 20754#L594-1 assume !(1 == ~T2_E~0); 20845#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20615#L604-1 assume !(1 == ~T4_E~0); 20605#L609-1 assume !(1 == ~E_M~0); 20606#L614-1 assume !(1 == ~E_1~0); 20719#L619-1 assume !(1 == ~E_2~0); 20808#L624-1 assume !(1 == ~E_3~0); 20901#L629-1 assume !(1 == ~E_4~0); 21068#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 21069#L815 [2024-11-17 08:52:05,743 INFO L747 eck$LassoCheckResult]: Loop: 21069#L815 assume true; 24636#L815-1 assume !false; 24595#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24587#L435 assume true; 24585#L435-1 assume !false; 24566#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24557#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24541#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24515#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 24509#L440 assume !(0 != eval_~tmp~0#1); 24510#L443 assume true; 25302#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25301#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25300#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 25299#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25298#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25297#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20654#L546 assume !(0 == ~T4_E~0); 20655#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 20840#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 20703#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 20704#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 20763#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 21064#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25224#L262-1 assume !(1 == ~m_pc~0); 25220#L272-1 is_master_triggered_~__retres1~0#1 := 0; 20936#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20937#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21023#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20846#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20847#L281-1 assume !(1 == ~t1_pc~0); 21046#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 25144#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25143#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25142#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25141#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25140#L300-1 assume !(1 == ~t2_pc~0); 25139#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 25138#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25102#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20990#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20991#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21000#L319-1 assume !(1 == ~t3_pc~0); 24879#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 24877#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24875#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24873#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24871#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24869#L338-1 assume !(1 == ~t4_pc~0); 24866#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 24864#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24862#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24859#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24857#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24855#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 24853#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24851#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24849#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24847#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24845#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 24843#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 24841#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 24839#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 24837#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 24835#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24825#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24816#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24808#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 24770#L834 assume !(0 == start_simulation_~tmp~3#1); 24748#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 24731#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 24728#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 24726#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 24724#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24722#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24720#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 24709#L847 assume !(0 != start_simulation_~tmp___0~1#1); 21069#L815 [2024-11-17 08:52:05,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1694060145, now seen corresponding path program 1 times [2024-11-17 08:52:05,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077504852] [2024-11-17 08:52:05,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077504852] [2024-11-17 08:52:05,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077504852] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:05,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779675773] [2024-11-17 08:52:05,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,834 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:05,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,835 INFO L85 PathProgramCache]: Analyzing trace with hash 1584620159, now seen corresponding path program 2 times [2024-11-17 08:52:05,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269230248] [2024-11-17 08:52:05,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [269230248] [2024-11-17 08:52:05,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [269230248] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:05,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [768200157] [2024-11-17 08:52:05,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,900 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:05,900 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:05,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:05,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:05,901 INFO L87 Difference]: Start difference. First operand 4719 states and 6738 transitions. cyclomatic complexity: 2027 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,002 INFO L93 Difference]: Finished difference Result 8718 states and 12407 transitions. [2024-11-17 08:52:06,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8718 states and 12407 transitions. [2024-11-17 08:52:06,064 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8544 [2024-11-17 08:52:06,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8718 states to 8718 states and 12407 transitions. [2024-11-17 08:52:06,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8718 [2024-11-17 08:52:06,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8718 [2024-11-17 08:52:06,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8718 states and 12407 transitions. [2024-11-17 08:52:06,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,147 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8718 states and 12407 transitions. [2024-11-17 08:52:06,154 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8718 states and 12407 transitions. [2024-11-17 08:52:06,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8718 to 8654. [2024-11-17 08:52:06,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8654 states, 8654 states have (on average 1.4262768661890455) internal successors, (12343), 8653 states have internal predecessors, (12343), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8654 states to 8654 states and 12343 transitions. [2024-11-17 08:52:06,299 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8654 states and 12343 transitions. [2024-11-17 08:52:06,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:06,301 INFO L425 stractBuchiCegarLoop]: Abstraction has 8654 states and 12343 transitions. [2024-11-17 08:52:06,301 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:52:06,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8654 states and 12343 transitions. [2024-11-17 08:52:06,335 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8480 [2024-11-17 08:52:06,336 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:06,336 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:06,337 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,337 INFO L745 eck$LassoCheckResult]: Stem: 34565#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34084#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34085#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34252#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34126#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 34127#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34394#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34320#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34321#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34472#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34464#L526-1 assume !(0 == ~M_E~0); 34404#L531-1 assume !(0 == ~T1_E~0); 34333#L536-1 assume !(0 == ~T2_E~0); 34334#L541-1 assume !(0 == ~T3_E~0); 34328#L546-1 assume !(0 == ~T4_E~0); 34329#L551-1 assume !(0 == ~E_M~0); 34299#L556-1 assume !(0 == ~E_1~0); 34300#L561-1 assume !(0 == ~E_2~0); 34306#L566-1 assume !(0 == ~E_3~0); 34307#L571-1 assume !(0 == ~E_4~0); 34111#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34082#L262-7 assume !(1 == ~m_pc~0); 34083#L272-7 is_master_triggered_~__retres1~0#1 := 0; 34401#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34473#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34519#L649-7 assume !(0 != activate_threads_~tmp~1#1); 34411#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34041#L281-7 assume !(1 == ~t1_pc~0); 34042#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 34410#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34375#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34363#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 34364#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34195#L300-7 assume !(1 == ~t2_pc~0); 34196#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 34140#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34141#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34424#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 34425#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34402#L319-7 assume !(1 == ~t3_pc~0); 34403#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 34112#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34113#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34066#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 34067#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34230#L338-7 assume !(1 == ~t4_pc~0); 34215#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 34216#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34373#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34435#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 34436#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34171#L584-1 assume !(1 == ~M_E~0); 34172#L589-1 assume !(1 == ~T1_E~0); 34191#L594-1 assume !(1 == ~T2_E~0); 34284#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34061#L604-1 assume !(1 == ~T4_E~0); 34051#L609-1 assume !(1 == ~E_M~0); 34052#L614-1 assume !(1 == ~E_1~0); 34160#L619-1 assume !(1 == ~E_2~0); 34245#L624-1 assume !(1 == ~E_3~0); 34336#L629-1 assume !(1 == ~E_4~0); 34501#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 34502#L815 [2024-11-17 08:52:06,337 INFO L747 eck$LassoCheckResult]: Loop: 34502#L815 assume true; 37167#L815-1 assume !false; 37154#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37144#L435 assume true; 37136#L435-1 assume !false; 37130#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36860#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36857#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 36855#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 36842#L440 assume !(0 != eval_~tmp~0#1); 36843#L443 assume true; 38857#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38855#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38853#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 38852#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38851#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38850#L541 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38849#L546 assume !(0 == ~T4_E~0); 38847#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 38844#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 38843#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 38842#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 38841#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 38840#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38839#L262-1 assume !(1 == ~m_pc~0); 38838#L272-1 is_master_triggered_~__retres1~0#1 := 0; 38836#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38834#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 38832#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38830#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38828#L281-1 assume !(1 == ~t1_pc~0); 38826#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 38824#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38822#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38820#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38818#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38816#L300-1 assume !(1 == ~t2_pc~0); 38814#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 38812#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38810#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38807#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38805#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37569#L319-1 assume !(1 == ~t3_pc~0); 37567#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 37565#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37563#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37562#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37560#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37558#L338-1 assume !(1 == ~t4_pc~0); 37556#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 37554#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37552#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37550#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37548#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37546#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 37544#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37542#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37522#L599 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37515#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37510#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 37505#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 37500#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 37493#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 37487#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 37482#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 37472#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 37464#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 37457#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 37451#L834 assume !(0 == start_simulation_~tmp~3#1); 37446#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 37183#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 37180#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 37178#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 37176#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37174#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37172#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 37170#L847 assume !(0 != start_simulation_~tmp___0~1#1); 34502#L815 [2024-11-17 08:52:06,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,338 INFO L85 PathProgramCache]: Analyzing trace with hash -226529100, now seen corresponding path program 1 times [2024-11-17 08:52:06,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052802466] [2024-11-17 08:52:06,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052802466] [2024-11-17 08:52:06,386 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052802466] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,386 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,386 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:06,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597818023] [2024-11-17 08:52:06,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,386 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:06,386 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,386 INFO L85 PathProgramCache]: Analyzing trace with hash 1584620159, now seen corresponding path program 3 times [2024-11-17 08:52:06,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549058172] [2024-11-17 08:52:06,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,435 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549058172] [2024-11-17 08:52:06,435 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549058172] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,435 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104960324] [2024-11-17 08:52:06,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,436 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,436 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,436 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:06,436 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:06,436 INFO L87 Difference]: Start difference. First operand 8654 states and 12343 transitions. cyclomatic complexity: 3705 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,619 INFO L93 Difference]: Finished difference Result 17306 states and 24567 transitions. [2024-11-17 08:52:06,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17306 states and 24567 transitions. [2024-11-17 08:52:06,706 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 16928 [2024-11-17 08:52:06,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17306 states to 17306 states and 24567 transitions. [2024-11-17 08:52:06,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17306 [2024-11-17 08:52:06,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17306 [2024-11-17 08:52:06,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17306 states and 24567 transitions. [2024-11-17 08:52:06,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17306 states and 24567 transitions. [2024-11-17 08:52:06,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17306 states and 24567 transitions. [2024-11-17 08:52:07,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17306 to 17306. [2024-11-17 08:52:07,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17306 states, 17306 states have (on average 1.4195654686235988) internal successors, (24567), 17305 states have internal predecessors, (24567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17306 states to 17306 states and 24567 transitions. [2024-11-17 08:52:07,275 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17306 states and 24567 transitions. [2024-11-17 08:52:07,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:07,276 INFO L425 stractBuchiCegarLoop]: Abstraction has 17306 states and 24567 transitions. [2024-11-17 08:52:07,276 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:52:07,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17306 states and 24567 transitions. [2024-11-17 08:52:07,338 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 16928 [2024-11-17 08:52:07,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,340 INFO L745 eck$LassoCheckResult]: Stem: 60562#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 60059#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 60060#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60228#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60101#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 60102#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60377#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60296#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60297#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60470#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60460#L526-1 assume 0 == ~M_E~0;~M_E~0 := 1; 60461#L531-1 assume !(0 == ~T1_E~0); 60309#L536-1 assume !(0 == ~T2_E~0); 60310#L541-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60450#L546-1 assume !(0 == ~T4_E~0); 60606#L551-1 assume !(0 == ~E_M~0); 60605#L556-1 assume !(0 == ~E_1~0); 60604#L561-1 assume !(0 == ~E_2~0); 60603#L566-1 assume !(0 == ~E_3~0); 60602#L571-1 assume !(0 == ~E_4~0); 60601#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60600#L262-7 assume !(1 == ~m_pc~0); 60599#L272-7 is_master_triggered_~__retres1~0#1 := 0; 60598#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60597#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 60596#L649-7 assume !(0 != activate_threads_~tmp~1#1); 60595#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60594#L281-7 assume !(1 == ~t1_pc~0); 60593#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 60592#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60591#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60590#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 60589#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60588#L300-7 assume !(1 == ~t2_pc~0); 60587#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 60586#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60585#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60584#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 60583#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60582#L319-7 assume !(1 == ~t3_pc~0); 60581#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 60580#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60579#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60578#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 60577#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60576#L338-7 assume !(1 == ~t4_pc~0); 60575#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 60574#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60573#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60572#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 60571#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60570#L584-1 assume !(1 == ~M_E~0); 60569#L589-1 assume !(1 == ~T1_E~0); 60568#L594-1 assume !(1 == ~T2_E~0); 60566#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60567#L604-1 assume !(1 == ~T4_E~0); 66097#L609-1 assume !(1 == ~E_M~0); 66091#L614-1 assume !(1 == ~E_1~0); 66089#L619-1 assume !(1 == ~E_2~0); 66087#L624-1 assume !(1 == ~E_3~0); 66085#L629-1 assume !(1 == ~E_4~0); 66081#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 66078#L815 [2024-11-17 08:52:07,340 INFO L747 eck$LassoCheckResult]: Loop: 66078#L815 assume true; 66074#L815-1 assume !false; 66071#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66067#L435 assume true; 66064#L435-1 assume !false; 66062#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66054#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66051#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66049#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 66046#L440 assume !(0 != eval_~tmp~0#1); 66047#L443 assume true; 60314#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60315#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60328#L526 assume 0 == ~M_E~0;~M_E~0 := 1; 60329#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76856#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76853#L541 assume !(0 == ~T3_E~0); 76854#L546 assume !(0 == ~T4_E~0); 77049#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 77048#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 77047#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 77046#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 77045#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 77044#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77043#L262-1 assume !(1 == ~m_pc~0); 77042#L272-1 is_master_triggered_~__retres1~0#1 := 0; 77041#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77040#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77039#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77038#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77037#L281-1 assume !(1 == ~t1_pc~0); 77034#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 77032#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77030#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77028#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77026#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77024#L300-1 assume !(1 == ~t2_pc~0); 77021#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 77019#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77017#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75218#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72529#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66165#L319-1 assume !(1 == ~t3_pc~0); 66163#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 66161#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66159#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66157#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66155#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66153#L338-1 assume !(1 == ~t4_pc~0); 66151#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 66147#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66145#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 66143#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66141#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66139#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 66137#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66135#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66133#L599 assume !(1 == ~T3_E~0); 66130#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66128#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 66126#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 66124#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 66122#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 66120#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 66118#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66108#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66106#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66104#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 66102#L834 assume !(0 == start_simulation_~tmp~3#1); 66100#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66093#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66090#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66088#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 66086#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66084#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66083#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 66082#L847 assume !(0 != start_simulation_~tmp___0~1#1); 66078#L815 [2024-11-17 08:52:07,340 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,340 INFO L85 PathProgramCache]: Analyzing trace with hash -987939756, now seen corresponding path program 1 times [2024-11-17 08:52:07,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211872290] [2024-11-17 08:52:07,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,369 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211872290] [2024-11-17 08:52:07,369 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211872290] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,369 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,369 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:07,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1970120157] [2024-11-17 08:52:07,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,369 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:07,370 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,370 INFO L85 PathProgramCache]: Analyzing trace with hash 9099615, now seen corresponding path program 1 times [2024-11-17 08:52:07,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744163238] [2024-11-17 08:52:07,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744163238] [2024-11-17 08:52:07,415 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744163238] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:07,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618403459] [2024-11-17 08:52:07,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,415 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:07,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:07,416 INFO L87 Difference]: Start difference. First operand 17306 states and 24567 transitions. cyclomatic complexity: 7293 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,641 INFO L93 Difference]: Finished difference Result 26142 states and 37144 transitions. [2024-11-17 08:52:07,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26142 states and 37144 transitions. [2024-11-17 08:52:07,756 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25696 [2024-11-17 08:52:07,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26142 states to 26142 states and 37144 transitions. [2024-11-17 08:52:07,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26142 [2024-11-17 08:52:07,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26142 [2024-11-17 08:52:07,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26142 states and 37144 transitions. [2024-11-17 08:52:08,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,029 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26142 states and 37144 transitions. [2024-11-17 08:52:08,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26142 states and 37144 transitions. [2024-11-17 08:52:08,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26142 to 18967. [2024-11-17 08:52:08,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18967 states, 18967 states have (on average 1.4253703801339168) internal successors, (27035), 18966 states have internal predecessors, (27035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18967 states to 18967 states and 27035 transitions. [2024-11-17 08:52:08,391 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18967 states and 27035 transitions. [2024-11-17 08:52:08,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,392 INFO L425 stractBuchiCegarLoop]: Abstraction has 18967 states and 27035 transitions. [2024-11-17 08:52:08,392 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:52:08,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18967 states and 27035 transitions. [2024-11-17 08:52:08,530 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18640 [2024-11-17 08:52:08,531 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,531 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,532 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,533 INFO L745 eck$LassoCheckResult]: Stem: 104039#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 103514#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 103515#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103691#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103556#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 103557#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 103835#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 103752#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103753#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 103930#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 103921#L526-1 assume !(0 == ~M_E~0); 103844#L531-1 assume !(0 == ~T1_E~0); 103769#L536-1 assume !(0 == ~T2_E~0); 103770#L541-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 103761#L546-1 assume !(0 == ~T4_E~0); 103762#L551-1 assume !(0 == ~E_M~0); 103734#L556-1 assume !(0 == ~E_1~0); 103735#L561-1 assume !(0 == ~E_2~0); 103740#L566-1 assume !(0 == ~E_3~0); 103741#L571-1 assume !(0 == ~E_4~0); 103541#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103542#L262-7 assume !(1 == ~m_pc~0); 103840#L272-7 is_master_triggered_~__retres1~0#1 := 0; 103841#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104027#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 104028#L649-7 assume !(0 != activate_threads_~tmp~1#1); 104049#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103471#L281-7 assume !(1 == ~t1_pc~0); 103472#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 104048#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 103814#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 103815#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 103978#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103979#L300-7 assume !(1 == ~t2_pc~0); 103933#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 103934#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104038#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 103868#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 103869#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104046#L319-7 assume !(1 == ~t3_pc~0); 103890#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 103891#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103986#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 103987#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 103668#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103669#L338-7 assume !(1 == ~t4_pc~0); 103703#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 103811#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103812#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 103876#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 103877#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103604#L584-1 assume !(1 == ~M_E~0); 103605#L589-1 assume !(1 == ~T1_E~0); 103881#L594-1 assume !(1 == ~T2_E~0); 103882#L599-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 103491#L604-1 assume !(1 == ~T4_E~0); 103481#L609-1 assume !(1 == ~E_M~0); 103482#L614-1 assume !(1 == ~E_1~0); 103595#L619-1 assume !(1 == ~E_2~0); 103684#L624-1 assume !(1 == ~E_3~0); 103772#L629-1 assume !(1 == ~E_4~0); 103964#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 103965#L815 [2024-11-17 08:52:08,534 INFO L747 eck$LassoCheckResult]: Loop: 103965#L815 assume true; 117432#L815-1 assume !false; 117423#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 117419#L435 assume true; 117417#L435-1 assume !false; 117415#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 117408#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 117405#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 117403#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 117400#L440 assume !(0 != eval_~tmp~0#1); 117401#L443 assume true; 117790#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117788#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 117786#L526 assume !(0 == ~M_E~0); 117784#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117782#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117779#L541 assume !(0 == ~T3_E~0); 117776#L546 assume !(0 == ~T4_E~0); 117774#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 117772#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 117770#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 117768#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 117766#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 117764#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117762#L262-1 assume !(1 == ~m_pc~0); 117760#L272-1 is_master_triggered_~__retres1~0#1 := 0; 117758#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117756#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 117754#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 117752#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117750#L281-1 assume !(1 == ~t1_pc~0); 117748#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 117746#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117744#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 117742#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117740#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117738#L300-1 assume !(1 == ~t2_pc~0); 117736#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 117734#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117732#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 117730#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117728#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117726#L319-1 assume !(1 == ~t3_pc~0); 115182#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 117724#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117722#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 117720#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117718#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117716#L338-1 assume !(1 == ~t4_pc~0); 117714#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 117711#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117709#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 117707#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117705#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117703#L584 assume !(1 == ~M_E~0); 108481#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117701#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117699#L599 assume !(1 == ~T3_E~0); 117695#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 117693#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 117691#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 117689#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 117687#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 117685#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 117683#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 117670#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 117668#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 117667#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 109049#L834 assume !(0 == start_simulation_~tmp~3#1); 109050#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 117468#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 117460#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 117454#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 117448#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117445#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 117442#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 117439#L847 assume !(0 != start_simulation_~tmp___0~1#1); 103965#L815 [2024-11-17 08:52:08,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,534 INFO L85 PathProgramCache]: Analyzing trace with hash -218769741, now seen corresponding path program 1 times [2024-11-17 08:52:08,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763828532] [2024-11-17 08:52:08,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,574 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763828532] [2024-11-17 08:52:08,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1763828532] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,574 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,574 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:08,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402623074] [2024-11-17 08:52:08,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,575 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,575 INFO L85 PathProgramCache]: Analyzing trace with hash -920816001, now seen corresponding path program 1 times [2024-11-17 08:52:08,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585707641] [2024-11-17 08:52:08,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585707641] [2024-11-17 08:52:08,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585707641] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,620 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601680026] [2024-11-17 08:52:08,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,620 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,621 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,621 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:08,621 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:08,621 INFO L87 Difference]: Start difference. First operand 18967 states and 27035 transitions. cyclomatic complexity: 8084 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,787 INFO L93 Difference]: Finished difference Result 23310 states and 32947 transitions. [2024-11-17 08:52:08,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23310 states and 32947 transitions. [2024-11-17 08:52:08,879 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22912 [2024-11-17 08:52:08,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23310 states to 23310 states and 32947 transitions. [2024-11-17 08:52:08,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23310 [2024-11-17 08:52:08,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23310 [2024-11-17 08:52:08,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23310 states and 32947 transitions. [2024-11-17 08:52:08,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,983 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23310 states and 32947 transitions. [2024-11-17 08:52:09,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23310 states and 32947 transitions. [2024-11-17 08:52:09,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23310 to 16142. [2024-11-17 08:52:09,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16142 states, 16142 states have (on average 1.4176062445793582) internal successors, (22883), 16141 states have internal predecessors, (22883), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16142 states to 16142 states and 22883 transitions. [2024-11-17 08:52:09,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16142 states and 22883 transitions. [2024-11-17 08:52:09,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:09,321 INFO L425 stractBuchiCegarLoop]: Abstraction has 16142 states and 22883 transitions. [2024-11-17 08:52:09,322 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:52:09,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16142 states and 22883 transitions. [2024-11-17 08:52:09,379 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15856 [2024-11-17 08:52:09,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:09,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:09,380 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,380 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,381 INFO L745 eck$LassoCheckResult]: Stem: 146291#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 145802#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 145803#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 145973#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145845#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 145846#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 146121#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 146038#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 146039#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 146198#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 146194#L526-1 assume !(0 == ~M_E~0); 146128#L531-1 assume !(0 == ~T1_E~0); 146052#L536-1 assume !(0 == ~T2_E~0); 146053#L541-1 assume !(0 == ~T3_E~0); 146047#L546-1 assume !(0 == ~T4_E~0); 146048#L551-1 assume !(0 == ~E_M~0); 146019#L556-1 assume !(0 == ~E_1~0); 146020#L561-1 assume !(0 == ~E_2~0); 146027#L566-1 assume !(0 == ~E_3~0); 146028#L571-1 assume !(0 == ~E_4~0); 145829#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145800#L262-7 assume !(1 == ~m_pc~0); 145801#L272-7 is_master_triggered_~__retres1~0#1 := 0; 146125#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 146199#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 146257#L649-7 assume !(0 != activate_threads_~tmp~1#1); 146134#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145759#L281-7 assume !(1 == ~t1_pc~0); 145760#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 146133#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 146099#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 146086#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 146087#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 145913#L300-7 assume !(1 == ~t2_pc~0); 145914#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 145861#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145862#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 146148#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 146149#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 146126#L319-7 assume !(1 == ~t3_pc~0); 146127#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 145830#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145831#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 145784#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 145785#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145950#L338-7 assume !(1 == ~t4_pc~0); 145935#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 145936#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 146095#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 146159#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 146160#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145889#L584-1 assume !(1 == ~M_E~0); 145890#L589-1 assume !(1 == ~T1_E~0); 145909#L594-1 assume !(1 == ~T2_E~0); 146005#L599-1 assume !(1 == ~T3_E~0); 145779#L604-1 assume !(1 == ~T4_E~0); 145769#L609-1 assume !(1 == ~E_M~0); 145770#L614-1 assume !(1 == ~E_1~0); 145880#L619-1 assume !(1 == ~E_2~0); 145966#L624-1 assume !(1 == ~E_3~0); 146055#L629-1 assume !(1 == ~E_4~0); 146232#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 146233#L815 [2024-11-17 08:52:09,381 INFO L747 eck$LassoCheckResult]: Loop: 146233#L815 assume true; 151610#L815-1 assume !false; 151607#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 151604#L435 assume true; 151603#L435-1 assume !false; 151602#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 151596#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 151593#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 151591#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 151588#L440 assume !(0 != eval_~tmp~0#1); 151585#L443 assume true; 151583#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 151581#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 151579#L526 assume !(0 == ~M_E~0); 151577#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 151575#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 151572#L541 assume !(0 == ~T3_E~0); 151570#L546 assume !(0 == ~T4_E~0); 151568#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 151566#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 151564#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 151562#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 151560#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 151558#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151556#L262-1 assume !(1 == ~m_pc~0); 151554#L272-1 is_master_triggered_~__retres1~0#1 := 0; 151552#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151551#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 151550#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 151547#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151544#L281-1 assume !(1 == ~t1_pc~0); 151542#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 151540#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 151538#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 151536#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 151535#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151532#L300-1 assume !(1 == ~t2_pc~0); 151531#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 151530#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 151529#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 151528#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 151527#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151526#L319-1 assume !(1 == ~t3_pc~0); 151144#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 151523#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151521#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 151519#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 151517#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 151515#L338-1 assume !(1 == ~t4_pc~0); 151513#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 151511#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 151509#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 151507#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 151505#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151503#L584 assume !(1 == ~M_E~0); 150423#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 151499#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 151497#L599 assume !(1 == ~T3_E~0); 151495#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 151493#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 151491#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 151488#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 151485#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 151481#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 151480#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 151474#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 151473#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 151472#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 150473#L834 assume !(0 == start_simulation_~tmp~3#1); 150474#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 151630#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 151628#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 151626#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 151625#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 151622#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 151618#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 151614#L847 assume !(0 != start_simulation_~tmp___0~1#1); 146233#L815 [2024-11-17 08:52:09,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,381 INFO L85 PathProgramCache]: Analyzing trace with hash 1516281235, now seen corresponding path program 1 times [2024-11-17 08:52:09,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865941373] [2024-11-17 08:52:09,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:09,393 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:09,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:09,445 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:09,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,452 INFO L85 PathProgramCache]: Analyzing trace with hash -920816001, now seen corresponding path program 2 times [2024-11-17 08:52:09,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934581300] [2024-11-17 08:52:09,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934581300] [2024-11-17 08:52:09,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934581300] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,520 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:09,520 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823279780] [2024-11-17 08:52:09,520 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,520 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:09,521 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:09,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:09,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:09,521 INFO L87 Difference]: Start difference. First operand 16142 states and 22883 transitions. cyclomatic complexity: 6757 Second operand has 5 states, 5 states have (on average 15.4) internal successors, (77), 5 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:09,744 INFO L93 Difference]: Finished difference Result 16590 states and 23331 transitions. [2024-11-17 08:52:09,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16590 states and 23331 transitions. [2024-11-17 08:52:09,817 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16304 [2024-11-17 08:52:09,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16590 states to 16590 states and 23331 transitions. [2024-11-17 08:52:09,863 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16590 [2024-11-17 08:52:09,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16590 [2024-11-17 08:52:09,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16590 states and 23331 transitions. [2024-11-17 08:52:09,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:09,884 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16590 states and 23331 transitions. [2024-11-17 08:52:09,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16590 states and 23331 transitions. [2024-11-17 08:52:10,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16590 to 16334. [2024-11-17 08:52:10,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16334 states, 16334 states have (on average 1.4126974409207786) internal successors, (23075), 16333 states have internal predecessors, (23075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:10,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16334 states to 16334 states and 23075 transitions. [2024-11-17 08:52:10,147 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16334 states and 23075 transitions. [2024-11-17 08:52:10,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:10,148 INFO L425 stractBuchiCegarLoop]: Abstraction has 16334 states and 23075 transitions. [2024-11-17 08:52:10,148 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:52:10,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16334 states and 23075 transitions. [2024-11-17 08:52:10,195 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16048 [2024-11-17 08:52:10,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:10,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:10,196 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:10,196 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:10,197 INFO L745 eck$LassoCheckResult]: Stem: 179046#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 178544#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 178545#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 178712#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 178586#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 178587#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 178860#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 178780#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 178781#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 178937#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 178929#L526-1 assume !(0 == ~M_E~0); 178868#L531-1 assume !(0 == ~T1_E~0); 178795#L536-1 assume !(0 == ~T2_E~0); 178796#L541-1 assume !(0 == ~T3_E~0); 178789#L546-1 assume !(0 == ~T4_E~0); 178790#L551-1 assume !(0 == ~E_M~0); 178761#L556-1 assume !(0 == ~E_1~0); 178762#L561-1 assume !(0 == ~E_2~0); 178768#L566-1 assume !(0 == ~E_3~0); 178769#L571-1 assume !(0 == ~E_4~0); 178571#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 178542#L262-7 assume !(1 == ~m_pc~0); 178543#L272-7 is_master_triggered_~__retres1~0#1 := 0; 178865#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178938#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179002#L649-7 assume !(0 != activate_threads_~tmp~1#1); 178874#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 178499#L281-7 assume !(1 == ~t1_pc~0); 178500#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 178873#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178842#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 178828#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 178829#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178654#L300-7 assume !(1 == ~t2_pc~0); 178655#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 178601#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178602#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 178888#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 178889#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 178866#L319-7 assume !(1 == ~t3_pc~0); 178867#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 178572#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 178573#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 178524#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 178525#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178689#L338-7 assume !(1 == ~t4_pc~0); 178674#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 178675#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178838#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 178897#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 178898#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178630#L584-1 assume !(1 == ~M_E~0); 178631#L589-1 assume !(1 == ~T1_E~0); 178650#L594-1 assume !(1 == ~T2_E~0); 178745#L599-1 assume !(1 == ~T3_E~0); 178519#L604-1 assume !(1 == ~T4_E~0); 178509#L609-1 assume !(1 == ~E_M~0); 178510#L614-1 assume !(1 == ~E_1~0); 178619#L619-1 assume !(1 == ~E_2~0); 178705#L624-1 assume !(1 == ~E_3~0); 178798#L629-1 assume !(1 == ~E_4~0); 178971#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 178972#L815 [2024-11-17 08:52:10,198 INFO L747 eck$LassoCheckResult]: Loop: 178972#L815 assume true; 183065#L815-1 assume !false; 183060#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 183057#L435 assume true; 181466#L435-1 assume !false; 181450#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 181451#L398-2 assume !(0 == ~m_st~0); 182958#L402-2 assume !(0 == ~t1_st~0); 182959#L406-2 assume !(0 == ~t2_st~0); 182960#L410-2 assume !(0 == ~t3_st~0); 182956#L414-2 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 180959#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 180960#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 185080#L440 assume !(0 != eval_~tmp~0#1); 185081#L443 assume true; 185073#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 185074#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 185069#L526 assume !(0 == ~M_E~0); 185070#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 185060#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 185061#L541 assume !(0 == ~T3_E~0); 185056#L546 assume !(0 == ~T4_E~0); 185057#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 185051#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 185052#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 185045#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 185046#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 185039#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185040#L262-1 assume !(1 == ~m_pc~0); 185033#L272-1 is_master_triggered_~__retres1~0#1 := 0; 185034#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185027#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 185028#L649-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 185023#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185024#L281-1 assume !(1 == ~t1_pc~0); 185013#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 185014#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 184604#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 184605#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 183623#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 183624#L300-1 assume !(1 == ~t2_pc~0); 183615#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 183616#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183610#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 183611#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 183607#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 183601#L319-1 assume !(1 == ~t3_pc~0); 183599#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 183597#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 183595#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 183593#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 183591#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183589#L338-1 assume !(1 == ~t4_pc~0); 183587#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 183585#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 183584#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 183582#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 183577#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183575#L584 assume !(1 == ~M_E~0); 183571#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 183569#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 183568#L599 assume !(1 == ~T3_E~0); 183567#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 183566#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 183559#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 183556#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 183553#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 183552#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 183551#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 183546#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 183138#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 183136#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 183134#L834 assume !(0 == start_simulation_~tmp~3#1); 183135#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 183207#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 183204#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 183078#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 183076#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 183074#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 183072#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 183070#L847 assume !(0 != start_simulation_~tmp___0~1#1); 178972#L815 [2024-11-17 08:52:10,198 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:10,198 INFO L85 PathProgramCache]: Analyzing trace with hash 1516281235, now seen corresponding path program 2 times [2024-11-17 08:52:10,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:10,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46385000] [2024-11-17 08:52:10,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:10,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:10,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:10,207 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:10,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:10,223 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:10,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:10,223 INFO L85 PathProgramCache]: Analyzing trace with hash -596121841, now seen corresponding path program 1 times [2024-11-17 08:52:10,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:10,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083567426] [2024-11-17 08:52:10,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:10,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:10,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:10,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:10,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:10,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083567426] [2024-11-17 08:52:10,297 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083567426] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:10,297 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:10,297 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:10,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232018856] [2024-11-17 08:52:10,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:10,298 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:10,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:10,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:10,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:10,298 INFO L87 Difference]: Start difference. First operand 16334 states and 23075 transitions. cyclomatic complexity: 6757 Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:10,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:10,470 INFO L93 Difference]: Finished difference Result 16766 states and 23394 transitions. [2024-11-17 08:52:10,470 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16766 states and 23394 transitions. [2024-11-17 08:52:10,729 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16480 [2024-11-17 08:52:10,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16766 states to 16766 states and 23394 transitions. [2024-11-17 08:52:10,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16766 [2024-11-17 08:52:10,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16766 [2024-11-17 08:52:10,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16766 states and 23394 transitions. [2024-11-17 08:52:10,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:10,824 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16766 states and 23394 transitions. [2024-11-17 08:52:10,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16766 states and 23394 transitions. [2024-11-17 08:52:10,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16766 to 16766. [2024-11-17 08:52:10,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16766 states, 16766 states have (on average 1.3953238697363712) internal successors, (23394), 16765 states have internal predecessors, (23394), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:11,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16766 states to 16766 states and 23394 transitions. [2024-11-17 08:52:11,001 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16766 states and 23394 transitions. [2024-11-17 08:52:11,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:11,002 INFO L425 stractBuchiCegarLoop]: Abstraction has 16766 states and 23394 transitions. [2024-11-17 08:52:11,002 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:52:11,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16766 states and 23394 transitions. [2024-11-17 08:52:11,187 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16480 [2024-11-17 08:52:11,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:11,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:11,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:11,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:11,189 INFO L745 eck$LassoCheckResult]: Stem: 212149#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 211652#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 211653#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 211823#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 211694#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 211695#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 211964#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 211887#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 211888#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 212053#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 212046#L526-1 assume !(0 == ~M_E~0); 211973#L531-1 assume !(0 == ~T1_E~0); 211902#L536-1 assume !(0 == ~T2_E~0); 211903#L541-1 assume !(0 == ~T3_E~0); 211895#L546-1 assume !(0 == ~T4_E~0); 211896#L551-1 assume !(0 == ~E_M~0); 211869#L556-1 assume !(0 == ~E_1~0); 211870#L561-1 assume !(0 == ~E_2~0); 211876#L566-1 assume !(0 == ~E_3~0); 211877#L571-1 assume !(0 == ~E_4~0); 211679#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 211650#L262-7 assume !(1 == ~m_pc~0); 211651#L272-7 is_master_triggered_~__retres1~0#1 := 0; 211970#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 212054#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 212116#L649-7 assume !(0 != activate_threads_~tmp~1#1); 211980#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 211607#L281-7 assume !(1 == ~t1_pc~0); 211608#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 211979#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 211946#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 211932#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 211933#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 211763#L300-7 assume !(1 == ~t2_pc~0); 211764#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 211709#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 211710#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 211997#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 211998#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 211971#L319-7 assume !(1 == ~t3_pc~0); 211972#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 211680#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 211681#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 211632#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 211633#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 211801#L338-7 assume !(1 == ~t4_pc~0); 211786#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 211787#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 211942#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 212007#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 212008#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 211740#L584-1 assume !(1 == ~M_E~0); 211741#L589-1 assume !(1 == ~T1_E~0); 211759#L594-1 assume !(1 == ~T2_E~0); 211853#L599-1 assume !(1 == ~T3_E~0); 211627#L604-1 assume !(1 == ~T4_E~0); 211617#L609-1 assume !(1 == ~E_M~0); 211618#L614-1 assume !(1 == ~E_1~0); 211728#L619-1 assume !(1 == ~E_2~0); 211816#L624-1 assume !(1 == ~E_3~0); 211905#L629-1 assume !(1 == ~E_4~0); 212084#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 212085#L815 [2024-11-17 08:52:11,190 INFO L747 eck$LassoCheckResult]: Loop: 212085#L815 assume true; 221320#L815-1 assume !false; 221315#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 221311#L435 assume true; 221308#L435-1 assume !false; 221304#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 221296#L398-2 assume !(0 == ~m_st~0); 221297#L402-2 assume !(0 == ~t1_st~0); 221298#L406-2 assume !(0 == ~t2_st~0); 221299#L410-2 assume !(0 == ~t3_st~0); 221294#L414-2 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 221295#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 217126#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 217127#L440 assume !(0 != eval_~tmp~0#1); 222073#L443 assume true; 224829#L519 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 224828#L358 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 224827#L526 assume !(0 == ~M_E~0); 224826#L531 assume 0 == ~T1_E~0;~T1_E~0 := 1; 224825#L536 assume 0 == ~T2_E~0;~T2_E~0 := 1; 224824#L541 assume !(0 == ~T3_E~0); 224823#L546 assume !(0 == ~T4_E~0); 224822#L551 assume 0 == ~E_M~0;~E_M~0 := 1; 224821#L556 assume 0 == ~E_1~0;~E_1~0 := 1; 224820#L561 assume 0 == ~E_2~0;~E_2~0 := 1; 224819#L566 assume 0 == ~E_3~0;~E_3~0 := 1; 224818#L571 assume 0 == ~E_4~0;~E_4~0 := 1; 224817#L577 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224816#L262-1 assume !(1 == ~m_pc~0); 224815#L272-1 is_master_triggered_~__retres1~0#1 := 0; 224814#L265-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224813#L274-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 224812#L649-1 assume !(0 != activate_threads_~tmp~1#1); 224811#L655-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 224810#L281-1 assume !(1 == ~t1_pc~0); 224809#L291-1 is_transmit1_triggered_~__retres1~1#1 := 0; 224808#L284-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 224807#L293-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 224806#L657-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 224805#L663-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 224804#L300-1 assume !(1 == ~t2_pc~0); 224803#L310-1 is_transmit2_triggered_~__retres1~2#1 := 0; 224802#L303-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222010#L312-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 221683#L665-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 221473#L671-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 221417#L319-1 assume !(1 == ~t3_pc~0); 221413#L329-1 is_transmit3_triggered_~__retres1~3#1 := 0; 221409#L322-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221405#L331-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 221401#L673-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 221396#L679-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221393#L338-1 assume !(1 == ~t4_pc~0); 221390#L348-1 is_transmit4_triggered_~__retres1~4#1 := 0; 221387#L341-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221384#L350-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 221381#L681-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 221378#L687-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 221375#L584 assume !(1 == ~M_E~0); 221371#L589 assume 1 == ~T1_E~0;~T1_E~0 := 2; 221369#L594 assume 1 == ~T2_E~0;~T2_E~0 := 2; 221367#L599 assume !(1 == ~T3_E~0); 221365#L604 assume 1 == ~T4_E~0;~T4_E~0 := 2; 221362#L609 assume 1 == ~E_M~0;~E_M~0 := 2; 221360#L614 assume 1 == ~E_1~0;~E_1~0 := 2; 221358#L619 assume 1 == ~E_2~0;~E_2~0 := 2; 221356#L624 assume 1 == ~E_3~0;~E_3~0 := 2; 221354#L629 assume 1 == ~E_4~0;~E_4~0 := 2; 221352#L635 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 221346#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 221344#L416-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 221342#L426-1 assume true;start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 221339#L834 assume !(0 == start_simulation_~tmp~3#1); 221337#L845 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 221333#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 221331#L416 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 221330#L426 assume true;stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 221329#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 221328#L791 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 221327#L797 assume true;start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 221325#L847 assume !(0 != start_simulation_~tmp___0~1#1); 212085#L815 [2024-11-17 08:52:11,190 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:11,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1516281235, now seen corresponding path program 3 times [2024-11-17 08:52:11,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:11,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434129762] [2024-11-17 08:52:11,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:11,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:11,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:11,211 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:11,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:11,243 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:11,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:11,244 INFO L85 PathProgramCache]: Analyzing trace with hash -603881200, now seen corresponding path program 1 times [2024-11-17 08:52:11,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:11,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872943132] [2024-11-17 08:52:11,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:11,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:11,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:11,288 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:11,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:11,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872943132] [2024-11-17 08:52:11,289 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872943132] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:11,289 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:11,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:11,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478858245] [2024-11-17 08:52:11,289 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:11,290 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:11,290 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:11,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:11,290 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:11,291 INFO L87 Difference]: Start difference. First operand 16766 states and 23394 transitions. cyclomatic complexity: 6644 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:11,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:11,418 INFO L93 Difference]: Finished difference Result 25721 states and 35221 transitions. [2024-11-17 08:52:11,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25721 states and 35221 transitions. [2024-11-17 08:52:11,561 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25342 [2024-11-17 08:52:11,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25721 states to 25721 states and 35221 transitions. [2024-11-17 08:52:11,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25721 [2024-11-17 08:52:11,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25721 [2024-11-17 08:52:11,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25721 states and 35221 transitions. [2024-11-17 08:52:11,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:11,843 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25721 states and 35221 transitions. [2024-11-17 08:52:11,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25721 states and 35221 transitions. [2024-11-17 08:52:12,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25721 to 24825. [2024-11-17 08:52:12,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24825 states, 24825 states have (on average 1.3723665659617321) internal successors, (34069), 24824 states have internal predecessors, (34069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24825 states to 24825 states and 34069 transitions. [2024-11-17 08:52:12,102 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24825 states and 34069 transitions. [2024-11-17 08:52:12,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:12,102 INFO L425 stractBuchiCegarLoop]: Abstraction has 24825 states and 34069 transitions. [2024-11-17 08:52:12,103 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:52:12,103 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24825 states and 34069 transitions. [2024-11-17 08:52:12,370 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 24446 [2024-11-17 08:52:12,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:12,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:12,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:12,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:12,371 INFO L745 eck$LassoCheckResult]: Stem: 254626#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 254144#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 254145#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 254310#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 254184#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 254185#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 254456#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 254375#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 254376#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 254533#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 254526#L526-1 assume !(0 == ~M_E~0); 254465#L531-1 assume !(0 == ~T1_E~0); 254393#L536-1 assume !(0 == ~T2_E~0); 254394#L541-1 assume !(0 == ~T3_E~0); 254385#L546-1 assume !(0 == ~T4_E~0); 254386#L551-1 assume !(0 == ~E_M~0); 254355#L556-1 assume !(0 == ~E_1~0); 254356#L561-1 assume !(0 == ~E_2~0); 254362#L566-1 assume !(0 == ~E_3~0); 254363#L571-1 assume !(0 == ~E_4~0); 254171#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 254142#L262-7 assume !(1 == ~m_pc~0); 254143#L272-7 is_master_triggered_~__retres1~0#1 := 0; 254462#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 254534#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 254592#L649-7 assume !(0 != activate_threads_~tmp~1#1); 254471#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 254101#L281-7 assume !(1 == ~t1_pc~0); 254102#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 254470#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 254435#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 254424#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 254425#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 254252#L300-7 assume !(1 == ~t2_pc~0); 254253#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 254200#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 254201#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 254483#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 254484#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 254463#L319-7 assume !(1 == ~t3_pc~0); 254464#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 254172#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 254173#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 254126#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 254127#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 254288#L338-7 assume !(1 == ~t4_pc~0); 254273#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 254274#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 254433#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 254491#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 254492#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254226#L584-1 assume !(1 == ~M_E~0); 254227#L589-1 assume !(1 == ~T1_E~0); 254248#L594-1 assume !(1 == ~T2_E~0); 254342#L599-1 assume !(1 == ~T3_E~0); 254121#L604-1 assume !(1 == ~T4_E~0); 254111#L609-1 assume !(1 == ~E_M~0); 254112#L614-1 assume !(1 == ~E_1~0); 254219#L619-1 assume !(1 == ~E_2~0); 254303#L624-1 assume !(1 == ~E_3~0); 254396#L629-1 assume !(1 == ~E_4~0); 254564#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 254565#L815 assume true; 258557#L815-1 assume !false; 258549#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 258541#L435 [2024-11-17 08:52:12,371 INFO L747 eck$LassoCheckResult]: Loop: 258541#L435 assume true; 258536#L435-1 assume !false; 258531#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 258525#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 258521#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 258515#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 258510#L440 assume 0 != eval_~tmp~0#1; 258506#L445-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 258500#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 258494#L445 havoc eval_~tmp_ndt_1~0#1; 258487#L459-1 assume !(0 == ~t1_st~0); 258480#L473-1 assume !(0 == ~t2_st~0); 258481#L487-1 assume !(0 == ~t3_st~0); 258547#L501-1 assume !(0 == ~t4_st~0); 258541#L435 [2024-11-17 08:52:12,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1363949674, now seen corresponding path program 1 times [2024-11-17 08:52:12,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24077818] [2024-11-17 08:52:12,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:12,382 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:12,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:12,407 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:12,408 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,408 INFO L85 PathProgramCache]: Analyzing trace with hash -1912162087, now seen corresponding path program 1 times [2024-11-17 08:52:12,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210657580] [2024-11-17 08:52:12,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,409 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:12,413 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:12,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:12,416 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:12,417 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,417 INFO L85 PathProgramCache]: Analyzing trace with hash -2070968958, now seen corresponding path program 1 times [2024-11-17 08:52:12,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259937134] [2024-11-17 08:52:12,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:12,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:12,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:12,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259937134] [2024-11-17 08:52:12,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259937134] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:12,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:12,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:12,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530614826] [2024-11-17 08:52:12,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:12,527 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:12,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:12,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:12,528 INFO L87 Difference]: Start difference. First operand 24825 states and 34069 transitions. cyclomatic complexity: 9269 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:12,637 INFO L93 Difference]: Finished difference Result 28182 states and 38060 transitions. [2024-11-17 08:52:12,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28182 states and 38060 transitions. [2024-11-17 08:52:12,762 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 27767 [2024-11-17 08:52:12,992 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28182 states to 28182 states and 38060 transitions. [2024-11-17 08:52:12,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28182 [2024-11-17 08:52:13,007 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28182 [2024-11-17 08:52:13,007 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28182 states and 38060 transitions. [2024-11-17 08:52:13,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:13,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28182 states and 38060 transitions. [2024-11-17 08:52:13,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28182 states and 38060 transitions. [2024-11-17 08:52:13,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28182 to 26810. [2024-11-17 08:52:13,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26810 states, 26810 states have (on average 1.3559119731443492) internal successors, (36352), 26809 states have internal predecessors, (36352), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:13,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26810 states to 26810 states and 36352 transitions. [2024-11-17 08:52:13,468 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26810 states and 36352 transitions. [2024-11-17 08:52:13,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:13,469 INFO L425 stractBuchiCegarLoop]: Abstraction has 26810 states and 36352 transitions. [2024-11-17 08:52:13,469 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:52:13,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26810 states and 36352 transitions. [2024-11-17 08:52:13,559 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 26395 [2024-11-17 08:52:13,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:13,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:13,560 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:13,560 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:13,561 INFO L745 eck$LassoCheckResult]: Stem: 307664#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 307159#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 307160#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 307335#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 307200#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 307201#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 307486#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 307404#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 307405#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 307569#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 307563#L526-1 assume !(0 == ~M_E~0); 307494#L531-1 assume !(0 == ~T1_E~0); 307420#L536-1 assume !(0 == ~T2_E~0); 307421#L541-1 assume !(0 == ~T3_E~0); 307413#L546-1 assume !(0 == ~T4_E~0); 307414#L551-1 assume !(0 == ~E_M~0); 307383#L556-1 assume !(0 == ~E_1~0); 307384#L561-1 assume !(0 == ~E_2~0); 307389#L566-1 assume !(0 == ~E_3~0); 307390#L571-1 assume !(0 == ~E_4~0); 307186#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 307157#L262-7 assume !(1 == ~m_pc~0); 307158#L272-7 is_master_triggered_~__retres1~0#1 := 0; 307491#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 307570#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 307630#L649-7 assume !(0 != activate_threads_~tmp~1#1); 307501#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 307116#L281-7 assume !(1 == ~t1_pc~0); 307117#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 307500#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 307466#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 307451#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 307452#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 307273#L300-7 assume !(1 == ~t2_pc~0); 307274#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 307216#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307217#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 307516#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 307517#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307492#L319-7 assume !(1 == ~t3_pc~0); 307493#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 307187#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 307188#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 307141#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 307142#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 307311#L338-7 assume !(1 == ~t4_pc~0); 307296#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 307297#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 307460#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 307525#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 307526#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307247#L584-1 assume !(1 == ~M_E~0); 307248#L589-1 assume !(1 == ~T1_E~0); 307269#L594-1 assume !(1 == ~T2_E~0); 307367#L599-1 assume !(1 == ~T3_E~0); 307136#L604-1 assume !(1 == ~T4_E~0); 307126#L609-1 assume !(1 == ~E_M~0); 307127#L614-1 assume !(1 == ~E_1~0); 307236#L619-1 assume !(1 == ~E_2~0); 307328#L624-1 assume !(1 == ~E_3~0); 307424#L629-1 assume !(1 == ~E_4~0); 307602#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 307603#L815 assume true; 308903#L815-1 assume !false; 308825#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 308821#L435 [2024-11-17 08:52:13,561 INFO L747 eck$LassoCheckResult]: Loop: 308821#L435 assume true; 308819#L435-1 assume !false; 308818#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 308815#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 308812#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 308803#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 308802#L440 assume 0 != eval_~tmp~0#1; 308800#L445-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 308796#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 308755#L445 havoc eval_~tmp_ndt_1~0#1; 308697#L459-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 308695#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 308692#L459 havoc eval_~tmp_ndt_2~0#1; 308690#L473-1 assume !(0 == ~t2_st~0); 308691#L487-1 assume !(0 == ~t3_st~0); 308823#L501-1 assume !(0 == ~t4_st~0); 308821#L435 [2024-11-17 08:52:13,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:13,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1363949674, now seen corresponding path program 2 times [2024-11-17 08:52:13,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:13,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84644753] [2024-11-17 08:52:13,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:13,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:13,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:13,577 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:13,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:13,592 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:13,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:13,593 INFO L85 PathProgramCache]: Analyzing trace with hash 709954317, now seen corresponding path program 1 times [2024-11-17 08:52:13,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:13,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073834170] [2024-11-17 08:52:13,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:13,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:13,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:13,597 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:13,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:13,601 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:13,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:13,602 INFO L85 PathProgramCache]: Analyzing trace with hash -1579593354, now seen corresponding path program 1 times [2024-11-17 08:52:13,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:13,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976605657] [2024-11-17 08:52:13,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:13,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:13,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:13,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:13,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:13,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976605657] [2024-11-17 08:52:13,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976605657] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:13,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:13,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:13,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420795444] [2024-11-17 08:52:13,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:13,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:13,724 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:13,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:13,724 INFO L87 Difference]: Start difference. First operand 26810 states and 36352 transitions. cyclomatic complexity: 9568 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:13,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:13,850 INFO L93 Difference]: Finished difference Result 31910 states and 42837 transitions. [2024-11-17 08:52:13,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31910 states and 42837 transitions. [2024-11-17 08:52:14,012 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 31415 [2024-11-17 08:52:14,117 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31910 states to 31910 states and 42837 transitions. [2024-11-17 08:52:14,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31910 [2024-11-17 08:52:14,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31910 [2024-11-17 08:52:14,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31910 states and 42837 transitions. [2024-11-17 08:52:14,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:14,176 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31910 states and 42837 transitions. [2024-11-17 08:52:14,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31910 states and 42837 transitions. [2024-11-17 08:52:14,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31910 to 30614. [2024-11-17 08:52:14,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30614 states, 30614 states have (on average 1.347520742144117) internal successors, (41253), 30613 states have internal predecessors, (41253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:14,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30614 states to 30614 states and 41253 transitions. [2024-11-17 08:52:14,609 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30614 states and 41253 transitions. [2024-11-17 08:52:14,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:14,610 INFO L425 stractBuchiCegarLoop]: Abstraction has 30614 states and 41253 transitions. [2024-11-17 08:52:14,610 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:52:14,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30614 states and 41253 transitions. [2024-11-17 08:52:14,943 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 30119 [2024-11-17 08:52:14,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:14,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:14,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:14,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:14,944 INFO L745 eck$LassoCheckResult]: Stem: 366415#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 365889#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 365890#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 366063#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 365929#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 365930#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 366220#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 366132#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 366133#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 366310#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 366299#L526-1 assume !(0 == ~M_E~0); 366228#L531-1 assume !(0 == ~T1_E~0); 366150#L536-1 assume !(0 == ~T2_E~0); 366151#L541-1 assume !(0 == ~T3_E~0); 366141#L546-1 assume !(0 == ~T4_E~0); 366142#L551-1 assume !(0 == ~E_M~0); 366111#L556-1 assume !(0 == ~E_1~0); 366112#L561-1 assume !(0 == ~E_2~0); 366118#L566-1 assume !(0 == ~E_3~0); 366119#L571-1 assume !(0 == ~E_4~0); 365916#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 365887#L262-7 assume !(1 == ~m_pc~0); 365888#L272-7 is_master_triggered_~__retres1~0#1 := 0; 366225#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 366313#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 366378#L649-7 assume !(0 != activate_threads_~tmp~1#1); 366234#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 365844#L281-7 assume !(1 == ~t1_pc~0); 365845#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 366233#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366197#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 366183#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 366184#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 366001#L300-7 assume !(1 == ~t2_pc~0); 366002#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 365945#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 365946#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 366251#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 366252#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 366226#L319-7 assume !(1 == ~t3_pc~0); 366227#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 365917#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 365918#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 365869#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 365870#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 366039#L338-7 assume !(1 == ~t4_pc~0); 366024#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 366025#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 366192#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 366261#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 366262#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 365975#L584-1 assume !(1 == ~M_E~0); 365976#L589-1 assume !(1 == ~T1_E~0); 365997#L594-1 assume !(1 == ~T2_E~0); 366094#L599-1 assume !(1 == ~T3_E~0); 365864#L604-1 assume !(1 == ~T4_E~0); 365854#L609-1 assume !(1 == ~E_M~0); 365855#L614-1 assume !(1 == ~E_1~0); 365968#L619-1 assume !(1 == ~E_2~0); 366056#L624-1 assume !(1 == ~E_3~0); 366154#L629-1 assume !(1 == ~E_4~0); 366352#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 366353#L815 assume true; 376696#L815-1 assume !false; 376688#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 376689#L435 [2024-11-17 08:52:14,948 INFO L747 eck$LassoCheckResult]: Loop: 376689#L435 assume true; 376680#L435-1 assume !false; 376681#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 378699#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 378697#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 378695#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 378693#L440 assume 0 != eval_~tmp~0#1; 378690#L445-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 378687#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 378685#L445 havoc eval_~tmp_ndt_1~0#1; 378683#L459-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 378680#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 378681#L459 havoc eval_~tmp_ndt_2~0#1; 378730#L473-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 378728#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 378726#L473 havoc eval_~tmp_ndt_3~0#1; 378723#L487-1 assume !(0 == ~t3_st~0); 378707#L501-1 assume !(0 == ~t4_st~0); 376689#L435 [2024-11-17 08:52:14,948 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:14,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1363949674, now seen corresponding path program 3 times [2024-11-17 08:52:14,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:14,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738589270] [2024-11-17 08:52:14,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:14,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:14,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,956 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:14,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,971 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:14,972 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:14,972 INFO L85 PathProgramCache]: Analyzing trace with hash -632025383, now seen corresponding path program 1 times [2024-11-17 08:52:14,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:14,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426363083] [2024-11-17 08:52:14,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:14,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:14,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,975 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:14,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,978 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:14,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:14,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1864081662, now seen corresponding path program 1 times [2024-11-17 08:52:14,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:14,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302650822] [2024-11-17 08:52:14,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:14,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:14,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:15,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:15,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:15,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302650822] [2024-11-17 08:52:15,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302650822] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:15,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:15,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:15,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083086158] [2024-11-17 08:52:15,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:15,076 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:15,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:15,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:15,077 INFO L87 Difference]: Start difference. First operand 30614 states and 41253 transitions. cyclomatic complexity: 10665 Second operand has 3 states, 3 states have (on average 27.666666666666668) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:15,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:15,252 INFO L93 Difference]: Finished difference Result 55821 states and 74786 transitions. [2024-11-17 08:52:15,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55821 states and 74786 transitions. [2024-11-17 08:52:15,511 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 54935 [2024-11-17 08:52:15,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55821 states to 55821 states and 74786 transitions. [2024-11-17 08:52:15,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55821 [2024-11-17 08:52:15,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55821 [2024-11-17 08:52:15,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55821 states and 74786 transitions. [2024-11-17 08:52:15,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:15,764 INFO L218 hiAutomatonCegarLoop]: Abstraction has 55821 states and 74786 transitions. [2024-11-17 08:52:15,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55821 states and 74786 transitions. [2024-11-17 08:52:16,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55821 to 54717. [2024-11-17 08:52:16,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54717 states, 54717 states have (on average 1.3430926403128827) internal successors, (73490), 54716 states have internal predecessors, (73490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:16,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54717 states to 54717 states and 73490 transitions. [2024-11-17 08:52:16,652 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54717 states and 73490 transitions. [2024-11-17 08:52:16,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:16,653 INFO L425 stractBuchiCegarLoop]: Abstraction has 54717 states and 73490 transitions. [2024-11-17 08:52:16,653 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:52:16,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54717 states and 73490 transitions. [2024-11-17 08:52:16,787 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 53831 [2024-11-17 08:52:16,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:16,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:16,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:16,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:16,788 INFO L745 eck$LassoCheckResult]: Stem: 452863#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 452330#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 452331#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 452505#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 452370#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 452371#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 452658#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 452577#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 452578#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 452755#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 452745#L526-1 assume !(0 == ~M_E~0); 452665#L531-1 assume !(0 == ~T1_E~0); 452591#L536-1 assume !(0 == ~T2_E~0); 452592#L541-1 assume !(0 == ~T3_E~0); 452585#L546-1 assume !(0 == ~T4_E~0); 452586#L551-1 assume !(0 == ~E_M~0); 452552#L556-1 assume !(0 == ~E_1~0); 452553#L561-1 assume !(0 == ~E_2~0); 452560#L566-1 assume !(0 == ~E_3~0); 452561#L571-1 assume !(0 == ~E_4~0); 452357#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 452328#L262-7 assume !(1 == ~m_pc~0); 452329#L272-7 is_master_triggered_~__retres1~0#1 := 0; 452662#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 452757#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 452821#L649-7 assume !(0 != activate_threads_~tmp~1#1); 452672#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 452287#L281-7 assume !(1 == ~t1_pc~0); 452288#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 452671#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 452635#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 452624#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 452625#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 452445#L300-7 assume !(1 == ~t2_pc~0); 452446#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 452386#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 452387#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 452688#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 452689#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 452663#L319-7 assume !(1 == ~t3_pc~0); 452664#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 452358#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 452359#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 452312#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 452313#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 452482#L338-7 assume !(1 == ~t4_pc~0); 452467#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 452468#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 452633#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 452696#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 452697#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 452416#L584-1 assume !(1 == ~M_E~0); 452417#L589-1 assume !(1 == ~T1_E~0); 452441#L594-1 assume !(1 == ~T2_E~0); 452535#L599-1 assume !(1 == ~T3_E~0); 452307#L604-1 assume !(1 == ~T4_E~0); 452297#L609-1 assume !(1 == ~E_M~0); 452298#L614-1 assume !(1 == ~E_1~0); 452407#L619-1 assume !(1 == ~E_2~0); 452498#L624-1 assume !(1 == ~E_3~0); 452595#L629-1 assume !(1 == ~E_4~0); 452792#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 452793#L815 assume true; 476825#L815-1 assume !false; 476818#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 476814#L435 [2024-11-17 08:52:16,788 INFO L747 eck$LassoCheckResult]: Loop: 476814#L435 assume true; 476812#L435-1 assume !false; 476810#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 476807#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 476804#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 476802#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 476800#L440 assume 0 != eval_~tmp~0#1; 476796#L445-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 476792#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 476790#L445 havoc eval_~tmp_ndt_1~0#1; 476788#L459-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 476785#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 476783#L459 havoc eval_~tmp_ndt_2~0#1; 476782#L473-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 476780#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 476781#L473 havoc eval_~tmp_ndt_3~0#1; 476833#L487-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 476830#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 476828#L487 havoc eval_~tmp_ndt_4~0#1; 476816#L501-1 assume !(0 == ~t4_st~0); 476814#L435 [2024-11-17 08:52:16,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:16,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1363949674, now seen corresponding path program 4 times [2024-11-17 08:52:16,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:16,789 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058825118] [2024-11-17 08:52:16,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:16,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:16,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:16,797 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:16,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:16,807 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:16,807 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:16,808 INFO L85 PathProgramCache]: Analyzing trace with hash -1785942515, now seen corresponding path program 1 times [2024-11-17 08:52:16,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:16,808 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985898696] [2024-11-17 08:52:16,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:16,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:16,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:16,812 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:16,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:16,814 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:16,815 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:16,815 INFO L85 PathProgramCache]: Analyzing trace with hash -381052938, now seen corresponding path program 1 times [2024-11-17 08:52:16,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:16,815 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664942698] [2024-11-17 08:52:16,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:16,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:16,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:16,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:16,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:16,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664942698] [2024-11-17 08:52:16,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664942698] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:16,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:16,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:16,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361006973] [2024-11-17 08:52:16,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:16,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:16,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:16,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:16,914 INFO L87 Difference]: Start difference. First operand 54717 states and 73490 transitions. cyclomatic complexity: 18799 Second operand has 3 states, 2 states have (on average 42.5) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:17,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:17,108 INFO L93 Difference]: Finished difference Result 65459 states and 87098 transitions. [2024-11-17 08:52:17,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65459 states and 87098 transitions. [2024-11-17 08:52:17,744 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 64453 [2024-11-17 08:52:17,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65459 states to 65459 states and 87098 transitions. [2024-11-17 08:52:17,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65459 [2024-11-17 08:52:17,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65459 [2024-11-17 08:52:17,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65459 states and 87098 transitions. [2024-11-17 08:52:17,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:17,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65459 states and 87098 transitions. [2024-11-17 08:52:17,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65459 states and 87098 transitions. [2024-11-17 08:52:18,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65459 to 64499. [2024-11-17 08:52:18,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64499 states, 64499 states have (on average 1.3354935735437758) internal successors, (86138), 64498 states have internal predecessors, (86138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:18,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64499 states to 64499 states and 86138 transitions. [2024-11-17 08:52:18,874 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64499 states and 86138 transitions. [2024-11-17 08:52:18,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:18,875 INFO L425 stractBuchiCegarLoop]: Abstraction has 64499 states and 86138 transitions. [2024-11-17 08:52:18,875 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:52:18,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64499 states and 86138 transitions. [2024-11-17 08:52:19,067 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 63493 [2024-11-17 08:52:19,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:19,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:19,068 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:19,068 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:19,068 INFO L745 eck$LassoCheckResult]: Stem: 573047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 572514#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 572515#L778 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 572687#L358-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 572557#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 572558#L370 assume 1 == ~t1_i~0;~t1_st~0 := 0; 572844#L375 assume 1 == ~t2_i~0;~t2_st~0 := 0; 572761#L380 assume 1 == ~t3_i~0;~t3_st~0 := 0; 572762#L385 assume 1 == ~t4_i~0;~t4_st~0 := 0; 572936#L391 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 572930#L526-1 assume !(0 == ~M_E~0); 572852#L531-1 assume !(0 == ~T1_E~0); 572775#L536-1 assume !(0 == ~T2_E~0); 572776#L541-1 assume !(0 == ~T3_E~0); 572770#L546-1 assume !(0 == ~T4_E~0); 572771#L551-1 assume !(0 == ~E_M~0); 572737#L556-1 assume !(0 == ~E_1~0); 572738#L561-1 assume !(0 == ~E_2~0); 572744#L566-1 assume !(0 == ~E_3~0); 572745#L571-1 assume !(0 == ~E_4~0); 572541#L577-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 572512#L262-7 assume !(1 == ~m_pc~0); 572513#L272-7 is_master_triggered_~__retres1~0#1 := 0; 572849#L265-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 572937#L274-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 573008#L649-7 assume !(0 != activate_threads_~tmp~1#1); 572859#L655-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 572471#L281-7 assume !(1 == ~t1_pc~0); 572472#L291-7 is_transmit1_triggered_~__retres1~1#1 := 0; 572858#L284-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 572824#L293-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 572810#L657-7 assume !(0 != activate_threads_~tmp___0~0#1); 572811#L663-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 572627#L300-7 assume !(1 == ~t2_pc~0); 572628#L310-7 is_transmit2_triggered_~__retres1~2#1 := 0; 572572#L303-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 572573#L312-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 572874#L665-7 assume !(0 != activate_threads_~tmp___1~0#1); 572875#L671-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 572850#L319-7 assume !(1 == ~t3_pc~0); 572851#L329-7 is_transmit3_triggered_~__retres1~3#1 := 0; 572542#L322-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 572543#L331-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 572496#L673-7 assume !(0 != activate_threads_~tmp___2~0#1); 572497#L679-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 572663#L338-7 assume !(1 == ~t4_pc~0); 572648#L348-7 is_transmit4_triggered_~__retres1~4#1 := 0; 572649#L341-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 572819#L350-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 572885#L681-7 assume !(0 != activate_threads_~tmp___3~0#1); 572886#L687-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 572599#L584-1 assume !(1 == ~M_E~0); 572600#L589-1 assume !(1 == ~T1_E~0); 572623#L594-1 assume !(1 == ~T2_E~0); 572718#L599-1 assume !(1 == ~T3_E~0); 572491#L604-1 assume !(1 == ~T4_E~0); 572481#L609-1 assume !(1 == ~E_M~0); 572482#L614-1 assume !(1 == ~E_1~0); 572590#L619-1 assume !(1 == ~E_2~0); 572680#L624-1 assume !(1 == ~E_3~0); 572779#L629-1 assume !(1 == ~E_4~0); 572978#L635-1 assume true;assume { :end_inline_reset_delta_events } true; 572979#L815 assume true; 601377#L815-1 assume !false; 601369#start_simulation_while_6_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 601361#L435 [2024-11-17 08:52:19,068 INFO L747 eck$LassoCheckResult]: Loop: 601361#L435 assume true; 601354#L435-1 assume !false; 601347#eval_while_5_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 601341#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 601167#L416-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 601162#L426-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 601160#L440 assume 0 != eval_~tmp~0#1; 601156#L445-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 601151#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 601153#L445 havoc eval_~tmp_ndt_1~0#1; 601458#L459-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 601455#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 601453#L459 havoc eval_~tmp_ndt_2~0#1; 601427#L473-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 601420#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 601413#L473 havoc eval_~tmp_ndt_3~0#1; 601405#L487-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 601397#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 601390#L487 havoc eval_~tmp_ndt_4~0#1; 601384#L501-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 601378#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 601370#L501 havoc eval_~tmp_ndt_5~0#1; 601361#L435 [2024-11-17 08:52:19,069 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:19,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1363949674, now seen corresponding path program 5 times [2024-11-17 08:52:19,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:19,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765392409] [2024-11-17 08:52:19,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:19,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:19,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,081 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:19,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,098 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:19,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:19,099 INFO L85 PathProgramCache]: Analyzing trace with hash 1696171225, now seen corresponding path program 1 times [2024-11-17 08:52:19,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:19,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269109954] [2024-11-17 08:52:19,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:19,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:19,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,105 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:19,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,109 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:19,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:19,109 INFO L85 PathProgramCache]: Analyzing trace with hash -1119643518, now seen corresponding path program 1 times [2024-11-17 08:52:19,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:19,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485937907] [2024-11-17 08:52:19,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:19,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:19,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,122 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:19,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,140 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:20,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:20,394 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:20,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:20,594 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.11 08:52:20 BoogieIcfgContainer [2024-11-17 08:52:20,595 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-17 08:52:20,596 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-17 08:52:20,596 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-17 08:52:20,596 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-17 08:52:20,597 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:02" (3/4) ... [2024-11-17 08:52:20,599 INFO L140 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-17 08:52:20,691 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-17 08:52:20,691 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-17 08:52:20,692 INFO L158 Benchmark]: Toolchain (without parser) took 19556.95ms. Allocated memory was 167.8MB in the beginning and 11.5GB in the end (delta: 11.3GB). Free memory was 135.2MB in the beginning and 10.1GB in the end (delta: -9.9GB). Peak memory consumption was 1.4GB. Max. memory is 16.1GB. [2024-11-17 08:52:20,692 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 167.8MB. Free memory is still 138.7MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-17 08:52:20,692 INFO L158 Benchmark]: CACSL2BoogieTranslator took 401.85ms. Allocated memory is still 167.8MB. Free memory was 135.2MB in the beginning and 117.2MB in the end (delta: 18.0MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2024-11-17 08:52:20,693 INFO L158 Benchmark]: Boogie Procedure Inliner took 72.49ms. Allocated memory is still 167.8MB. Free memory was 117.2MB in the beginning and 113.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-17 08:52:20,693 INFO L158 Benchmark]: Boogie Preprocessor took 87.80ms. Allocated memory is still 167.8MB. Free memory was 113.0MB in the beginning and 108.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-17 08:52:20,693 INFO L158 Benchmark]: IcfgBuilder took 1175.49ms. Allocated memory was 167.8MB in the beginning and 209.7MB in the end (delta: 41.9MB). Free memory was 108.8MB in the beginning and 160.1MB in the end (delta: -51.3MB). Peak memory consumption was 57.9MB. Max. memory is 16.1GB. [2024-11-17 08:52:20,694 INFO L158 Benchmark]: BuchiAutomizer took 17718.37ms. Allocated memory was 209.7MB in the beginning and 11.5GB in the end (delta: 11.3GB). Free memory was 160.1MB in the beginning and 10.1GB in the end (delta: -9.9GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. [2024-11-17 08:52:20,694 INFO L158 Benchmark]: Witness Printer took 95.66ms. Allocated memory is still 11.5GB. Free memory was 10.1GB in the beginning and 10.1GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-17 08:52:20,695 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 167.8MB. Free memory is still 138.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 401.85ms. Allocated memory is still 167.8MB. Free memory was 135.2MB in the beginning and 117.2MB in the end (delta: 18.0MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 72.49ms. Allocated memory is still 167.8MB. Free memory was 117.2MB in the beginning and 113.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 87.80ms. Allocated memory is still 167.8MB. Free memory was 113.0MB in the beginning and 108.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * IcfgBuilder took 1175.49ms. Allocated memory was 167.8MB in the beginning and 209.7MB in the end (delta: 41.9MB). Free memory was 108.8MB in the beginning and 160.1MB in the end (delta: -51.3MB). Peak memory consumption was 57.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 17718.37ms. Allocated memory was 209.7MB in the beginning and 11.5GB in the end (delta: 11.3GB). Free memory was 160.1MB in the beginning and 10.1GB in the end (delta: -9.9GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. * Witness Printer took 95.66ms. Allocated memory is still 11.5GB. Free memory was 10.1GB in the beginning and 10.1GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (20 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 64499 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 17.5s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 4.2s. Construction of modules took 0.6s. Büchi inclusion checks took 10.9s. Highest rank in rank-based complementation 0. Minimization of det autom 20. Minimization of nondet autom 0. Automata minimization 5.0s AutomataMinimizationTime, 20 MinimizatonAttempts, 21489 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 3.4s Buchi closure took 0.4s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12755 SdHoareTripleChecker+Valid, 0.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12755 mSDsluCounter, 25362 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 11634 mSDsCounter, 210 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 508 IncrementalHoareTripleChecker+Invalid, 718 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 210 mSolverCounterUnsat, 13728 mSDtfsCounter, 508 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN0 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE !(\read(tmp_ndt_1)) [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE !(\read(tmp_ndt_2)) [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE !(\read(tmp_ndt_3)) [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE !(\read(tmp_ndt_4)) [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-17 08:52:20,730 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)