./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:51:58,452 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:51:58,516 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:51:58,520 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:51:58,520 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:51:58,521 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:51:58,544 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:51:58,544 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:51:58,545 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:51:58,545 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:51:58,546 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:51:58,546 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:51:58,547 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:51:58,548 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:51:58,548 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:51:58,549 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:51:58,549 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:51:58,549 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:51:58,549 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:51:58,549 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:51:58,550 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:51:58,551 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:51:58,551 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:51:58,552 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:51:58,553 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:51:58,553 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:51:58,553 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:51:58,553 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:51:58,554 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:51:58,554 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:51:58,554 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:51:58,554 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:51:58,554 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:51:58,554 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:51:58,554 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:51:58,555 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:51:58,555 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:51:58,555 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:51:58,555 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:51:58,555 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:51:58,555 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 [2024-11-17 08:51:58,728 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:51:58,748 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:51:58,751 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:51:58,752 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:51:58,752 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:51:58,753 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2024-11-17 08:51:59,916 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:52:00,090 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:52:00,091 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2024-11-17 08:52:00,105 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/893cf18dc/e5758804611449e7b99c035999b5b0e7/FLAG151271907 [2024-11-17 08:52:00,119 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/893cf18dc/e5758804611449e7b99c035999b5b0e7 [2024-11-17 08:52:00,121 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:52:00,125 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:52:00,126 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:00,126 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:52:00,137 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:52:00,138 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,138 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ff6fd3b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00, skipping insertion in model container [2024-11-17 08:52:00,138 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,170 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:52:00,438 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:00,453 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:52:00,496 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:00,511 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:52:00,512 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00 WrapperNode [2024-11-17 08:52:00,512 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:00,512 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:00,513 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:52:00,513 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:52:00,517 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,525 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,564 INFO L138 Inliner]: procedures = 38, calls = 47, calls flagged for inlining = 42, calls inlined = 95, statements flattened = 1346 [2024-11-17 08:52:00,565 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:00,565 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:52:00,565 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:52:00,565 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:52:00,574 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,575 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,580 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,595 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:52:00,595 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,596 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,612 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,614 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,615 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,617 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,620 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:52:00,621 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:52:00,621 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:52:00,621 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:52:00,622 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (1/1) ... [2024-11-17 08:52:00,626 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:00,639 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:00,658 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:00,660 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:52:00,689 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:52:00,689 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:52:00,689 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:52:00,689 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:52:00,753 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:52:00,755 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:01,543 INFO L? ?]: Removed 252 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:01,543 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:01,576 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:01,577 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:01,578 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:01 BoogieIcfgContainer [2024-11-17 08:52:01,578 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:01,579 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:01,580 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:01,583 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:01,584 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:01,584 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:52:00" (1/3) ... [2024-11-17 08:52:01,585 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1d187a8c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:01, skipping insertion in model container [2024-11-17 08:52:01,586 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:01,586 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:00" (2/3) ... [2024-11-17 08:52:01,586 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1d187a8c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:01, skipping insertion in model container [2024-11-17 08:52:01,587 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:01,587 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:01" (3/3) ... [2024-11-17 08:52:01,588 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2024-11-17 08:52:01,658 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:01,658 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:01,658 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:01,658 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:01,658 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:01,659 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:01,659 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:01,659 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:01,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 588 states, 587 states have (on average 1.495741056218058) internal successors, (878), 587 states have internal predecessors, (878), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 504 [2024-11-17 08:52:01,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:01,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:01,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,702 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:01,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 588 states, 587 states have (on average 1.495741056218058) internal successors, (878), 587 states have internal predecessors, (878), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:01,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 504 [2024-11-17 08:52:01,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:01,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:01,712 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,712 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:01,718 INFO L745 eck$LassoCheckResult]: Stem: 580#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 29#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 237#L891true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96#L407-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 583#L414true assume !(1 == ~m_i~0);~m_st~0 := 2; 2#L419true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 573#L424true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 257#L429true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 318#L434true assume 1 == ~t4_i~0;~t4_st~0 := 0; 221#L439true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 339#L445true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 196#L599-1true assume !(0 == ~M_E~0); 16#L604-1true assume !(0 == ~T1_E~0); 12#L609-1true assume !(0 == ~T2_E~0); 86#L614-1true assume !(0 == ~T3_E~0); 157#L619-1true assume !(0 == ~T4_E~0); 259#L624-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 533#L629-1true assume !(0 == ~E_M~0); 61#L634-1true assume !(0 == ~E_1~0); 351#L639-1true assume !(0 == ~E_2~0); 417#L644-1true assume !(0 == ~E_3~0); 369#L649-1true assume !(0 == ~E_4~0); 41#L654-1true assume !(0 == ~E_5~0); 295#L660-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 401#L292-8true assume !(1 == ~m_pc~0); 127#L302-8true is_master_triggered_~__retres1~0#1 := 0; 258#L295-8true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182#L304-8true assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 90#L743-8true assume !(0 != activate_threads_~tmp~1#1); 101#L749-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 466#L311-8true assume 1 == ~t1_pc~0; 84#L312-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 581#L314-8true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 141#L323-8true assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 175#L751-8true assume !(0 != activate_threads_~tmp___0~0#1); 302#L757-8true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 467#L330-8true assume 1 == ~t2_pc~0; 226#L331-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 288#L333-8true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 208#L342-8true assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 517#L759-8true assume !(0 != activate_threads_~tmp___1~0#1); 505#L765-8true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73#L349-8true assume 1 == ~t3_pc~0; 222#L350-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91#L352-8true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299#L361-8true assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 418#L767-8true assume !(0 != activate_threads_~tmp___2~0#1); 285#L773-8true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 121#L368-8true assume !(1 == ~t4_pc~0); 465#L378-8true is_transmit4_triggered_~__retres1~4#1 := 0; 458#L371-8true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65#L380-8true assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 332#L775-8true assume !(0 != activate_threads_~tmp___3~0#1); 509#L781-8true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8#L387-8true assume 1 == ~t5_pc~0; 185#L388-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 166#L390-8true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 586#L399-8true assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 83#L783-8true assume !(0 != activate_threads_~tmp___4~0#1); 343#L789-8true assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 276#L667-1true assume !(1 == ~M_E~0); 361#L672-1true assume !(1 == ~T1_E~0); 148#L677-1true assume !(1 == ~T2_E~0); 328#L682-1true assume !(1 == ~T3_E~0); 419#L687-1true assume !(1 == ~T4_E~0); 482#L692-1true assume !(1 == ~T5_E~0); 319#L697-1true assume !(1 == ~E_M~0); 554#L702-1true assume !(1 == ~E_1~0); 366#L707-1true assume !(1 == ~E_2~0); 240#L712-1true assume !(1 == ~E_3~0); 358#L717-1true assume !(1 == ~E_4~0); 337#L722-1true assume !(1 == ~E_5~0); 490#L728-1true assume true;assume { :end_inline_reset_delta_events } true; 232#L928true [2024-11-17 08:52:01,720 INFO L747 eck$LassoCheckResult]: Loop: 232#L928true assume true; 560#L928-1true assume !false; 539#start_simulation_while_7_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 249#L494true assume !true; 40#L502true assume true; 317#L592true assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15#L407true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 227#L599true assume 0 == ~M_E~0;~M_E~0 := 1; 205#L604true assume !(0 == ~T1_E~0); 378#L609true assume 0 == ~T2_E~0;~T2_E~0 := 1; 198#L614true assume 0 == ~T3_E~0;~T3_E~0 := 1; 251#L619true assume 0 == ~T4_E~0;~T4_E~0 := 1; 478#L624true assume 0 == ~T5_E~0;~T5_E~0 := 1; 345#L629true assume 0 == ~E_M~0;~E_M~0 := 1; 551#L634true assume 0 == ~E_1~0;~E_1~0 := 1; 474#L639true assume 0 == ~E_2~0;~E_2~0 := 1; 278#L644true assume !(0 == ~E_3~0); 503#L649true assume 0 == ~E_4~0;~E_4~0 := 1; 113#L654true assume 0 == ~E_5~0;~E_5~0 := 1; 549#L660true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31#L292-1true assume 1 == ~m_pc~0; 408#L293-1true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 405#L295-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 402#L304-1true assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 585#L743-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 352#L749-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 228#L311-1true assume 1 == ~t1_pc~0; 34#L312-1true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 499#L314-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 391#L323-1true assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 154#L751-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 142#L757-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9#L330-1true assume 1 == ~t2_pc~0; 329#L331-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 282#L333-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6#L342-1true assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174#L759-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 532#L765-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 184#L349-1true assume !(1 == ~t3_pc~0); 544#L359-1true is_transmit3_triggered_~__retres1~3#1 := 0; 389#L352-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171#L361-1true assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 494#L767-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 140#L773-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 561#L368-1true assume 1 == ~t4_pc~0; 487#L369-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 165#L371-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 445#L380-1true assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 209#L775-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14#L781-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 384#L387-1true assume 1 == ~t5_pc~0; 558#L388-1true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 275#L390-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 426#L399-1true assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123#L783-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 495#L789-1true assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 197#L667true assume 1 == ~M_E~0;~M_E~0 := 2; 411#L672true assume 1 == ~T1_E~0;~T1_E~0 := 2; 307#L677true assume 1 == ~T2_E~0;~T2_E~0 := 2; 520#L682true assume 1 == ~T3_E~0;~T3_E~0 := 2; 52#L687true assume 1 == ~T4_E~0;~T4_E~0 := 2; 195#L692true assume 1 == ~T5_E~0;~T5_E~0 := 2; 193#L697true assume 1 == ~E_M~0;~E_M~0 := 2; 181#L702true assume 1 == ~E_1~0;~E_1~0 := 2; 529#L707true assume 1 == ~E_2~0;~E_2~0 := 2; 510#L712true assume 1 == ~E_3~0;~E_3~0 := 2; 24#L717true assume 1 == ~E_4~0;~E_4~0 := 2; 362#L722true assume 1 == ~E_5~0;~E_5~0 := 2; 69#L728true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 471#L452-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 451#L474-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 531#L485-1true assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 212#L947true assume !(0 == start_simulation_~tmp~3#1); 415#L958true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 524#L452true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55#L474true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 95#L485true assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 396#L902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 459#L904true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 316#L910true assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 303#L960true assume !(0 != start_simulation_~tmp___0~1#1); 232#L928true [2024-11-17 08:52:01,724 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,725 INFO L85 PathProgramCache]: Analyzing trace with hash -1627326071, now seen corresponding path program 1 times [2024-11-17 08:52:01,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688651715] [2024-11-17 08:52:01,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688651715] [2024-11-17 08:52:01,934 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [688651715] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,934 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,934 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:01,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1298820627] [2024-11-17 08:52:01,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,938 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:01,940 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:01,940 INFO L85 PathProgramCache]: Analyzing trace with hash 976943755, now seen corresponding path program 1 times [2024-11-17 08:52:01,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:01,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105610926] [2024-11-17 08:52:01,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:01,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:01,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:01,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:01,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:01,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105610926] [2024-11-17 08:52:01,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1105610926] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:01,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:01,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:01,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423520886] [2024-11-17 08:52:01,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:01,992 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:01,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:02,016 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:02,018 INFO L87 Difference]: Start difference. First operand has 588 states, 587 states have (on average 1.495741056218058) internal successors, (878), 587 states have internal predecessors, (878), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,066 INFO L93 Difference]: Finished difference Result 580 states and 852 transitions. [2024-11-17 08:52:02,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 580 states and 852 transitions. [2024-11-17 08:52:02,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 580 states to 574 states and 846 transitions. [2024-11-17 08:52:02,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 574 [2024-11-17 08:52:02,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 574 [2024-11-17 08:52:02,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 574 states and 846 transitions. [2024-11-17 08:52:02,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 574 states and 846 transitions. [2024-11-17 08:52:02,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 574 states and 846 transitions. [2024-11-17 08:52:02,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 574 to 574. [2024-11-17 08:52:02,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 574 states, 574 states have (on average 1.4738675958188154) internal successors, (846), 573 states have internal predecessors, (846), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 846 transitions. [2024-11-17 08:52:02,129 INFO L240 hiAutomatonCegarLoop]: Abstraction has 574 states and 846 transitions. [2024-11-17 08:52:02,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:02,133 INFO L425 stractBuchiCegarLoop]: Abstraction has 574 states and 846 transitions. [2024-11-17 08:52:02,133 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:02,133 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 574 states and 846 transitions. [2024-11-17 08:52:02,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:02,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:02,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,138 INFO L745 eck$LassoCheckResult]: Stem: 1750#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1233#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1234#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1373#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1374#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1179#L419 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1180#L424 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1591#L429 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1592#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1552#L439 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1553#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1523#L599-1 assume !(0 == ~M_E~0); 1208#L604-1 assume !(0 == ~T1_E~0); 1199#L609-1 assume !(0 == ~T2_E~0); 1200#L614-1 assume !(0 == ~T3_E~0); 1356#L619-1 assume !(0 == ~T4_E~0); 1471#L624-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1593#L629-1 assume !(0 == ~E_M~0); 1301#L634-1 assume !(0 == ~E_1~0); 1302#L639-1 assume !(0 == ~E_2~0); 1675#L644-1 assume !(0 == ~E_3~0); 1685#L649-1 assume !(0 == ~E_4~0); 1260#L654-1 assume !(0 == ~E_5~0); 1261#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1627#L292-8 assume !(1 == ~m_pc~0); 1426#L302-8 is_master_triggered_~__retres1~0#1 := 0; 1427#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1508#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1365#L743-8 assume !(0 != activate_threads_~tmp~1#1); 1366#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1381#L311-8 assume 1 == ~t1_pc~0; 1350#L312-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1351#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1449#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1450#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 1498#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1632#L330-8 assume 1 == ~t2_pc~0; 1557#L331-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1182#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1539#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1540#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 1738#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1327#L349-8 assume 1 == ~t3_pc~0; 1328#L350-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1367#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1368#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1630#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 1622#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1412#L368-8 assume !(1 == ~t4_pc~0); 1257#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1256#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1309#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1310#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 1658#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1191#L387-8 assume 1 == ~t5_pc~0; 1192#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1484#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1485#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1348#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 1349#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1612#L667-1 assume !(1 == ~M_E~0); 1613#L672-1 assume !(1 == ~T1_E~0); 1457#L677-1 assume !(1 == ~T2_E~0); 1458#L682-1 assume !(1 == ~T3_E~0); 1656#L687-1 assume !(1 == ~T4_E~0); 1709#L692-1 assume !(1 == ~T5_E~0); 1644#L697-1 assume !(1 == ~E_M~0); 1645#L702-1 assume !(1 == ~E_1~0); 1681#L707-1 assume !(1 == ~E_2~0); 1571#L712-1 assume !(1 == ~E_3~0); 1572#L717-1 assume !(1 == ~E_4~0); 1661#L722-1 assume !(1 == ~E_5~0); 1662#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 1564#L928 [2024-11-17 08:52:02,138 INFO L747 eck$LassoCheckResult]: Loop: 1564#L928 assume true; 1565#L928-1 assume !false; 1749#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1274#L494 assume true; 1405#L494-1 assume !false; 1406#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1545#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1504#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1578#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1266#L499 assume !(0 != eval_~tmp~0#1); 1258#L502 assume true; 1259#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1206#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1207#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 1533#L604 assume !(0 == ~T1_E~0); 1534#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1526#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1527#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1587#L624 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1668#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 1669#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 1730#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 1614#L644 assume !(0 == ~E_3~0); 1615#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 1397#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 1398#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1236#L292-1 assume 1 == ~m_pc~0; 1237#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1496#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1702#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1703#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1676#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1558#L311-1 assume 1 == ~t1_pc~0; 1244#L312-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1245#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1697#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1467#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1453#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1194#L330-1 assume !(1 == ~t2_pc~0); 1195#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1529#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1185#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1186#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1497#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1511#L349-1 assume 1 == ~t3_pc~0; 1512#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1696#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1493#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1494#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1445#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1446#L368-1 assume 1 == ~t4_pc~0; 1736#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1481#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1482#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1537#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1204#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1205#L387-1 assume !(1 == ~t5_pc~0); 1385#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1386#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1611#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1415#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1416#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1524#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 1525#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1638#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1639#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1287#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1288#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1519#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 1506#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 1507#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 1741#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 1224#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 1225#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 1318#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1319#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1243#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1723#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1541#L947 assume !(0 == start_simulation_~tmp~3#1); 1223#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1707#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1291#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1292#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 1370#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1700#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1643#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1633#L960 assume !(0 != start_simulation_~tmp___0~1#1); 1564#L928 [2024-11-17 08:52:02,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1381012984, now seen corresponding path program 1 times [2024-11-17 08:52:02,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697793999] [2024-11-17 08:52:02,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,184 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697793999] [2024-11-17 08:52:02,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697793999] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:02,185 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636053501] [2024-11-17 08:52:02,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,185 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:02,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1804575765, now seen corresponding path program 1 times [2024-11-17 08:52:02,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931258515] [2024-11-17 08:52:02,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,293 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,293 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931258515] [2024-11-17 08:52:02,294 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [931258515] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,294 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,294 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,294 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432802385] [2024-11-17 08:52:02,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,294 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,295 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,295 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:02,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:02,295 INFO L87 Difference]: Start difference. First operand 574 states and 846 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,314 INFO L93 Difference]: Finished difference Result 574 states and 845 transitions. [2024-11-17 08:52:02,314 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 574 states and 845 transitions. [2024-11-17 08:52:02,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 574 states to 574 states and 845 transitions. [2024-11-17 08:52:02,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 574 [2024-11-17 08:52:02,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 574 [2024-11-17 08:52:02,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 574 states and 845 transitions. [2024-11-17 08:52:02,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 574 states and 845 transitions. [2024-11-17 08:52:02,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 574 states and 845 transitions. [2024-11-17 08:52:02,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 574 to 574. [2024-11-17 08:52:02,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 574 states, 574 states have (on average 1.4721254355400697) internal successors, (845), 573 states have internal predecessors, (845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 845 transitions. [2024-11-17 08:52:02,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 574 states and 845 transitions. [2024-11-17 08:52:02,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:02,338 INFO L425 stractBuchiCegarLoop]: Abstraction has 574 states and 845 transitions. [2024-11-17 08:52:02,338 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:02,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 574 states and 845 transitions. [2024-11-17 08:52:02,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:02,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:02,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,342 INFO L745 eck$LassoCheckResult]: Stem: 2907#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2391#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2392#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2530#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2531#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 2336#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2337#L424 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2748#L429 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2749#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2709#L439 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2710#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2680#L599-1 assume !(0 == ~M_E~0); 2365#L604-1 assume !(0 == ~T1_E~0); 2356#L609-1 assume !(0 == ~T2_E~0); 2357#L614-1 assume !(0 == ~T3_E~0); 2513#L619-1 assume !(0 == ~T4_E~0); 2628#L624-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2750#L629-1 assume !(0 == ~E_M~0); 2458#L634-1 assume !(0 == ~E_1~0); 2459#L639-1 assume !(0 == ~E_2~0); 2833#L644-1 assume !(0 == ~E_3~0); 2842#L649-1 assume !(0 == ~E_4~0); 2417#L654-1 assume !(0 == ~E_5~0); 2418#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2784#L292-8 assume !(1 == ~m_pc~0); 2583#L302-8 is_master_triggered_~__retres1~0#1 := 0; 2584#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2667#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2522#L743-8 assume !(0 != activate_threads_~tmp~1#1); 2523#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2540#L311-8 assume 1 == ~t1_pc~0; 2507#L312-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2508#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2606#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2607#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 2655#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2789#L330-8 assume 1 == ~t2_pc~0; 2715#L331-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2339#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2696#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2697#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 2895#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2484#L349-8 assume 1 == ~t3_pc~0; 2485#L350-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2524#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2525#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2788#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 2779#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2569#L368-8 assume !(1 == ~t4_pc~0); 2414#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 2413#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2469#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2470#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 2815#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2351#L387-8 assume 1 == ~t5_pc~0; 2352#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2641#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2642#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2505#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 2506#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2769#L667-1 assume !(1 == ~M_E~0); 2770#L672-1 assume !(1 == ~T1_E~0); 2614#L677-1 assume !(1 == ~T2_E~0); 2615#L682-1 assume !(1 == ~T3_E~0); 2813#L687-1 assume !(1 == ~T4_E~0); 2866#L692-1 assume !(1 == ~T5_E~0); 2801#L697-1 assume !(1 == ~E_M~0); 2802#L702-1 assume !(1 == ~E_1~0); 2838#L707-1 assume !(1 == ~E_2~0); 2728#L712-1 assume !(1 == ~E_3~0); 2729#L717-1 assume !(1 == ~E_4~0); 2818#L722-1 assume !(1 == ~E_5~0); 2819#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 2721#L928 [2024-11-17 08:52:02,342 INFO L747 eck$LassoCheckResult]: Loop: 2721#L928 assume true; 2722#L928-1 assume !false; 2906#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2434#L494 assume true; 2562#L494-1 assume !false; 2563#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2702#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2661#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2735#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2423#L499 assume !(0 != eval_~tmp~0#1); 2415#L502 assume true; 2416#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2363#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2364#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 2690#L604 assume !(0 == ~T1_E~0); 2691#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2683#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2684#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2745#L624 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2825#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 2826#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 2887#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 2771#L644 assume !(0 == ~E_3~0); 2772#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 2554#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 2555#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2393#L292-1 assume 1 == ~m_pc~0; 2394#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2654#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2859#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2860#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2832#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2714#L311-1 assume 1 == ~t1_pc~0; 2401#L312-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2402#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2854#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2624#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2608#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2346#L330-1 assume !(1 == ~t2_pc~0); 2347#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 2685#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2342#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2343#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2653#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2668#L349-1 assume 1 == ~t3_pc~0; 2669#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2853#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2650#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2651#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2602#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2603#L368-1 assume 1 == ~t4_pc~0; 2893#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2638#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2640#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2694#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2361#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2362#L387-1 assume 1 == ~t5_pc~0; 2852#L388-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2543#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2768#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2572#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2573#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2681#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 2682#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2795#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2796#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2444#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2445#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2676#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 2663#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 2664#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 2898#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 2381#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 2382#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 2475#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2476#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2400#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2880#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2698#L947 assume !(0 == start_simulation_~tmp~3#1); 2380#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2864#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2448#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2449#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 2527#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2857#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2800#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2790#L960 assume !(0 != start_simulation_~tmp___0~1#1); 2721#L928 [2024-11-17 08:52:02,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,343 INFO L85 PathProgramCache]: Analyzing trace with hash 289500585, now seen corresponding path program 1 times [2024-11-17 08:52:02,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [645748076] [2024-11-17 08:52:02,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [645748076] [2024-11-17 08:52:02,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [645748076] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,408 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:02,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587742196] [2024-11-17 08:52:02,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,410 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:02,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1476408082, now seen corresponding path program 1 times [2024-11-17 08:52:02,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815250515] [2024-11-17 08:52:02,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,484 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815250515] [2024-11-17 08:52:02,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815250515] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,484 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,484 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,484 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602380617] [2024-11-17 08:52:02,484 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,484 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,485 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:02,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:02,485 INFO L87 Difference]: Start difference. First operand 574 states and 845 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,495 INFO L93 Difference]: Finished difference Result 574 states and 844 transitions. [2024-11-17 08:52:02,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 574 states and 844 transitions. [2024-11-17 08:52:02,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,501 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 574 states to 574 states and 844 transitions. [2024-11-17 08:52:02,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 574 [2024-11-17 08:52:02,501 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 574 [2024-11-17 08:52:02,502 INFO L73 IsDeterministic]: Start isDeterministic. Operand 574 states and 844 transitions. [2024-11-17 08:52:02,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 574 states and 844 transitions. [2024-11-17 08:52:02,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 574 states and 844 transitions. [2024-11-17 08:52:02,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 574 to 574. [2024-11-17 08:52:02,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 574 states, 574 states have (on average 1.470383275261324) internal successors, (844), 573 states have internal predecessors, (844), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 844 transitions. [2024-11-17 08:52:02,512 INFO L240 hiAutomatonCegarLoop]: Abstraction has 574 states and 844 transitions. [2024-11-17 08:52:02,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:02,513 INFO L425 stractBuchiCegarLoop]: Abstraction has 574 states and 844 transitions. [2024-11-17 08:52:02,513 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:02,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 574 states and 844 transitions. [2024-11-17 08:52:02,515 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:02,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:02,517 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,517 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,518 INFO L745 eck$LassoCheckResult]: Stem: 4064#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3548#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3549#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3687#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3688#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 3493#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3494#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3905#L429 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3906#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3866#L439 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3867#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3837#L599-1 assume !(0 == ~M_E~0); 3522#L604-1 assume !(0 == ~T1_E~0); 3513#L609-1 assume !(0 == ~T2_E~0); 3514#L614-1 assume !(0 == ~T3_E~0); 3670#L619-1 assume !(0 == ~T4_E~0); 3785#L624-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3907#L629-1 assume !(0 == ~E_M~0); 3617#L634-1 assume !(0 == ~E_1~0); 3618#L639-1 assume !(0 == ~E_2~0); 3990#L644-1 assume !(0 == ~E_3~0); 3999#L649-1 assume !(0 == ~E_4~0); 3574#L654-1 assume !(0 == ~E_5~0); 3575#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3941#L292-8 assume !(1 == ~m_pc~0); 3741#L302-8 is_master_triggered_~__retres1~0#1 := 0; 3742#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3824#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3679#L743-8 assume !(0 != activate_threads_~tmp~1#1); 3680#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3697#L311-8 assume 1 == ~t1_pc~0; 3664#L312-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3665#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3763#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3764#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 3812#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3946#L330-8 assume 1 == ~t2_pc~0; 3872#L331-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3496#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3853#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3854#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 4052#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3641#L349-8 assume 1 == ~t3_pc~0; 3642#L350-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3681#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3682#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3945#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 3936#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3726#L368-8 assume !(1 == ~t4_pc~0); 3571#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 3570#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3626#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3627#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 3972#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3508#L387-8 assume 1 == ~t5_pc~0; 3509#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3798#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3799#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3662#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 3663#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3926#L667-1 assume !(1 == ~M_E~0); 3927#L672-1 assume !(1 == ~T1_E~0); 3771#L677-1 assume !(1 == ~T2_E~0); 3772#L682-1 assume !(1 == ~T3_E~0); 3970#L687-1 assume !(1 == ~T4_E~0); 4023#L692-1 assume !(1 == ~T5_E~0); 3958#L697-1 assume !(1 == ~E_M~0); 3959#L702-1 assume !(1 == ~E_1~0); 3995#L707-1 assume !(1 == ~E_2~0); 3885#L712-1 assume !(1 == ~E_3~0); 3886#L717-1 assume !(1 == ~E_4~0); 3975#L722-1 assume !(1 == ~E_5~0); 3976#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 3878#L928 [2024-11-17 08:52:02,519 INFO L747 eck$LassoCheckResult]: Loop: 3878#L928 assume true; 3879#L928-1 assume !false; 4063#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3591#L494 assume true; 3720#L494-1 assume !false; 3721#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3859#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3818#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3892#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3580#L499 assume !(0 != eval_~tmp~0#1); 3572#L502 assume true; 3573#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3520#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3521#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 3847#L604 assume !(0 == ~T1_E~0); 3848#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3840#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3841#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3902#L624 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3982#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 3983#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 4043#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 3928#L644 assume !(0 == ~E_3~0); 3929#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 3711#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 3712#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3550#L292-1 assume !(1 == ~m_pc~0); 3552#L302-1 is_master_triggered_~__retres1~0#1 := 0; 3810#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4015#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4016#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3989#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3871#L311-1 assume 1 == ~t1_pc~0; 3558#L312-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3559#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4011#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3781#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3765#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3503#L330-1 assume !(1 == ~t2_pc~0); 3504#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 3842#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3499#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3500#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3811#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3825#L349-1 assume 1 == ~t3_pc~0; 3826#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4010#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3807#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3808#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3759#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3760#L368-1 assume 1 == ~t4_pc~0; 4050#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3795#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3797#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3851#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3518#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3519#L387-1 assume !(1 == ~t5_pc~0); 3701#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 3702#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3925#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3729#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3730#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3838#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 3839#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3952#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3953#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3601#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3602#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3833#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 3820#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 3821#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 4055#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 3538#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 3539#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 3632#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3633#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3557#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4037#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3855#L947 assume !(0 == start_simulation_~tmp~3#1); 3537#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4021#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3605#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3606#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 3684#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4014#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3957#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3947#L960 assume !(0 != start_simulation_~tmp___0~1#1); 3878#L928 [2024-11-17 08:52:02,519 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,520 INFO L85 PathProgramCache]: Analyzing trace with hash 897577448, now seen corresponding path program 1 times [2024-11-17 08:52:02,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [468450874] [2024-11-17 08:52:02,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,556 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,557 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [468450874] [2024-11-17 08:52:02,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [468450874] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,557 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,557 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:02,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980524230] [2024-11-17 08:52:02,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,557 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:02,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,558 INFO L85 PathProgramCache]: Analyzing trace with hash 436055512, now seen corresponding path program 1 times [2024-11-17 08:52:02,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447553891] [2024-11-17 08:52:02,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,636 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447553891] [2024-11-17 08:52:02,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1447553891] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,636 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589943117] [2024-11-17 08:52:02,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,637 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,637 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,637 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:02,637 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:02,637 INFO L87 Difference]: Start difference. First operand 574 states and 844 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,646 INFO L93 Difference]: Finished difference Result 574 states and 843 transitions. [2024-11-17 08:52:02,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 574 states and 843 transitions. [2024-11-17 08:52:02,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 574 states to 574 states and 843 transitions. [2024-11-17 08:52:02,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 574 [2024-11-17 08:52:02,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 574 [2024-11-17 08:52:02,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 574 states and 843 transitions. [2024-11-17 08:52:02,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,652 INFO L218 hiAutomatonCegarLoop]: Abstraction has 574 states and 843 transitions. [2024-11-17 08:52:02,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 574 states and 843 transitions. [2024-11-17 08:52:02,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 574 to 574. [2024-11-17 08:52:02,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 574 states, 574 states have (on average 1.4686411149825784) internal successors, (843), 573 states have internal predecessors, (843), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 843 transitions. [2024-11-17 08:52:02,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 574 states and 843 transitions. [2024-11-17 08:52:02,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:02,662 INFO L425 stractBuchiCegarLoop]: Abstraction has 574 states and 843 transitions. [2024-11-17 08:52:02,663 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:02,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 574 states and 843 transitions. [2024-11-17 08:52:02,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:02,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:02,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,668 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,669 INFO L745 eck$LassoCheckResult]: Stem: 5221#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4705#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4706#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4844#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4845#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 4650#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4651#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5062#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5063#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5023#L439 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5024#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4994#L599-1 assume !(0 == ~M_E~0); 4681#L604-1 assume !(0 == ~T1_E~0); 4670#L609-1 assume !(0 == ~T2_E~0); 4671#L614-1 assume !(0 == ~T3_E~0); 4827#L619-1 assume !(0 == ~T4_E~0); 4942#L624-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5064#L629-1 assume !(0 == ~E_M~0); 4774#L634-1 assume !(0 == ~E_1~0); 4775#L639-1 assume !(0 == ~E_2~0); 5147#L644-1 assume !(0 == ~E_3~0); 5156#L649-1 assume !(0 == ~E_4~0); 4731#L654-1 assume !(0 == ~E_5~0); 4732#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5098#L292-8 assume !(1 == ~m_pc~0); 4897#L302-8 is_master_triggered_~__retres1~0#1 := 0; 4898#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4979#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4836#L743-8 assume !(0 != activate_threads_~tmp~1#1); 4837#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4852#L311-8 assume 1 == ~t1_pc~0; 4821#L312-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4822#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4920#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4921#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 4969#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5103#L330-8 assume 1 == ~t2_pc~0; 5028#L331-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4653#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5008#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5009#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 5209#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4798#L349-8 assume 1 == ~t3_pc~0; 4799#L350-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4838#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4839#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5101#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 5093#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4883#L368-8 assume !(1 == ~t4_pc~0); 4728#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 4727#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4780#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4781#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 5129#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4660#L387-8 assume 1 == ~t5_pc~0; 4661#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4955#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4956#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4819#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 4820#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5083#L667-1 assume !(1 == ~M_E~0); 5084#L672-1 assume !(1 == ~T1_E~0); 4928#L677-1 assume !(1 == ~T2_E~0); 4929#L682-1 assume !(1 == ~T3_E~0); 5127#L687-1 assume !(1 == ~T4_E~0); 5180#L692-1 assume !(1 == ~T5_E~0); 5115#L697-1 assume !(1 == ~E_M~0); 5116#L702-1 assume !(1 == ~E_1~0); 5152#L707-1 assume !(1 == ~E_2~0); 5042#L712-1 assume !(1 == ~E_3~0); 5043#L717-1 assume !(1 == ~E_4~0); 5132#L722-1 assume !(1 == ~E_5~0); 5133#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 5035#L928 [2024-11-17 08:52:02,669 INFO L747 eck$LassoCheckResult]: Loop: 5035#L928 assume true; 5036#L928-1 assume !false; 5220#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4745#L494 assume true; 4876#L494-1 assume !false; 4877#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5016#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4973#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5047#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4737#L499 assume !(0 != eval_~tmp~0#1); 4729#L502 assume true; 4730#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4677#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4678#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 5004#L604 assume !(0 == ~T1_E~0); 5005#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4997#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4998#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5057#L624 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5139#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 5140#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 5200#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 5085#L644 assume !(0 == ~E_3~0); 5086#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 4868#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 4869#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4707#L292-1 assume 1 == ~m_pc~0; 4708#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4967#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5173#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5174#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5146#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5029#L311-1 assume 1 == ~t1_pc~0; 4715#L312-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4716#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5168#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4938#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4922#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4663#L330-1 assume !(1 == ~t2_pc~0); 4664#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 5000#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4656#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4657#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4968#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4982#L349-1 assume 1 == ~t3_pc~0; 4983#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5167#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4964#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4965#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4918#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4919#L368-1 assume 1 == ~t4_pc~0; 5207#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4952#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4954#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5010#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4675#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4676#L387-1 assume !(1 == ~t5_pc~0); 4858#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 4859#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5082#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4886#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4887#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4995#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 4996#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5109#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5110#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4758#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4759#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4992#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 4977#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 4978#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 5212#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 4695#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 4696#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 4789#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4790#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4714#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5194#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5012#L947 assume !(0 == start_simulation_~tmp~3#1); 4694#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5178#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4762#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4763#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 4843#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5171#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5114#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5104#L960 assume !(0 != start_simulation_~tmp___0~1#1); 5035#L928 [2024-11-17 08:52:02,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,669 INFO L85 PathProgramCache]: Analyzing trace with hash -883922487, now seen corresponding path program 1 times [2024-11-17 08:52:02,670 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,670 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124077810] [2024-11-17 08:52:02,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124077810] [2024-11-17 08:52:02,700 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124077810] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,700 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:02,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [941774350] [2024-11-17 08:52:02,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,700 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:02,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,700 INFO L85 PathProgramCache]: Analyzing trace with hash 1804575765, now seen corresponding path program 2 times [2024-11-17 08:52:02,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345857956] [2024-11-17 08:52:02,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,747 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,747 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345857956] [2024-11-17 08:52:02,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345857956] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,747 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928997011] [2024-11-17 08:52:02,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,756 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:02,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:02,758 INFO L87 Difference]: Start difference. First operand 574 states and 843 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,768 INFO L93 Difference]: Finished difference Result 574 states and 842 transitions. [2024-11-17 08:52:02,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 574 states and 842 transitions. [2024-11-17 08:52:02,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 574 states to 574 states and 842 transitions. [2024-11-17 08:52:02,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 574 [2024-11-17 08:52:02,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 574 [2024-11-17 08:52:02,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 574 states and 842 transitions. [2024-11-17 08:52:02,774 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 574 states and 842 transitions. [2024-11-17 08:52:02,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 574 states and 842 transitions. [2024-11-17 08:52:02,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 574 to 574. [2024-11-17 08:52:02,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 574 states, 574 states have (on average 1.4668989547038327) internal successors, (842), 573 states have internal predecessors, (842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 842 transitions. [2024-11-17 08:52:02,782 INFO L240 hiAutomatonCegarLoop]: Abstraction has 574 states and 842 transitions. [2024-11-17 08:52:02,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:02,784 INFO L425 stractBuchiCegarLoop]: Abstraction has 574 states and 842 transitions. [2024-11-17 08:52:02,784 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:02,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 574 states and 842 transitions. [2024-11-17 08:52:02,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 495 [2024-11-17 08:52:02,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:02,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:02,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:02,789 INFO L745 eck$LassoCheckResult]: Stem: 6378#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5861#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5862#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6001#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6002#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 5805#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5806#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6219#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6220#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6180#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6181#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6151#L599-1 assume !(0 == ~M_E~0); 5836#L604-1 assume !(0 == ~T1_E~0); 5827#L609-1 assume !(0 == ~T2_E~0); 5828#L614-1 assume !(0 == ~T3_E~0); 5984#L619-1 assume !(0 == ~T4_E~0); 6099#L624-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6221#L629-1 assume !(0 == ~E_M~0); 5929#L634-1 assume !(0 == ~E_1~0); 5930#L639-1 assume !(0 == ~E_2~0); 6303#L644-1 assume !(0 == ~E_3~0); 6313#L649-1 assume !(0 == ~E_4~0); 5888#L654-1 assume !(0 == ~E_5~0); 5889#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6255#L292-8 assume !(1 == ~m_pc~0); 6054#L302-8 is_master_triggered_~__retres1~0#1 := 0; 6055#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6136#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5993#L743-8 assume !(0 != activate_threads_~tmp~1#1); 5994#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6009#L311-8 assume 1 == ~t1_pc~0; 5978#L312-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5979#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6077#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6078#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 6126#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6260#L330-8 assume 1 == ~t2_pc~0; 6185#L331-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5810#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6165#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6166#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 6366#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5955#L349-8 assume 1 == ~t3_pc~0; 5956#L350-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5995#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5996#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6258#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 6250#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6040#L368-8 assume !(1 == ~t4_pc~0); 5885#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 5884#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5937#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5938#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 6286#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5817#L387-8 assume 1 == ~t5_pc~0; 5818#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6112#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6113#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5976#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 5977#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6240#L667-1 assume !(1 == ~M_E~0); 6241#L672-1 assume !(1 == ~T1_E~0); 6085#L677-1 assume !(1 == ~T2_E~0); 6086#L682-1 assume !(1 == ~T3_E~0); 6284#L687-1 assume !(1 == ~T4_E~0); 6337#L692-1 assume !(1 == ~T5_E~0); 6272#L697-1 assume !(1 == ~E_M~0); 6273#L702-1 assume !(1 == ~E_1~0); 6309#L707-1 assume !(1 == ~E_2~0); 6199#L712-1 assume !(1 == ~E_3~0); 6200#L717-1 assume !(1 == ~E_4~0); 6289#L722-1 assume !(1 == ~E_5~0); 6290#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 6192#L928 [2024-11-17 08:52:02,789 INFO L747 eck$LassoCheckResult]: Loop: 6192#L928 assume true; 6193#L928-1 assume !false; 6377#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5902#L494 assume true; 6033#L494-1 assume !false; 6034#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6173#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6130#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6204#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5894#L499 assume !(0 != eval_~tmp~0#1); 5886#L502 assume true; 5887#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5834#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5835#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 6161#L604 assume !(0 == ~T1_E~0); 6162#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6154#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6155#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6214#L624 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6296#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 6297#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 6357#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 6242#L644 assume !(0 == ~E_3~0); 6243#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 6025#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 6026#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5864#L292-1 assume 1 == ~m_pc~0; 5865#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6124#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6330#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6331#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6304#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6186#L311-1 assume 1 == ~t1_pc~0; 5872#L312-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5873#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6325#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6095#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6079#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5820#L330-1 assume !(1 == ~t2_pc~0); 5821#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 6157#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5813#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5814#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6125#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6139#L349-1 assume 1 == ~t3_pc~0; 6140#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6324#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6121#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6122#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6075#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6076#L368-1 assume 1 == ~t4_pc~0; 6364#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6109#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6111#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6167#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5832#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5833#L387-1 assume 1 == ~t5_pc~0; 6323#L388-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6016#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6239#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6043#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6044#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6152#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 6153#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6266#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6267#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5915#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5916#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6149#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 6134#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 6135#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 6369#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 5852#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 5853#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 5946#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5947#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5871#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6351#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6169#L947 assume !(0 == start_simulation_~tmp~3#1); 5851#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6335#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5919#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5920#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 6000#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6328#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6271#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6261#L960 assume !(0 != start_simulation_~tmp___0~1#1); 6192#L928 [2024-11-17 08:52:02,790 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,790 INFO L85 PathProgramCache]: Analyzing trace with hash 1290757610, now seen corresponding path program 1 times [2024-11-17 08:52:02,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957607037] [2024-11-17 08:52:02,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957607037] [2024-11-17 08:52:02,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957607037] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:02,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730941633] [2024-11-17 08:52:02,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,850 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:02,851 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:02,851 INFO L85 PathProgramCache]: Analyzing trace with hash 1476408082, now seen corresponding path program 2 times [2024-11-17 08:52:02,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:02,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024452527] [2024-11-17 08:52:02,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:02,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:02,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:02,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:02,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:02,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024452527] [2024-11-17 08:52:02,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024452527] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:02,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:02,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:02,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823077532] [2024-11-17 08:52:02,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:02,907 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:02,907 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:02,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:02,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:02,908 INFO L87 Difference]: Start difference. First operand 574 states and 842 transitions. cyclomatic complexity: 269 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:02,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:02,989 INFO L93 Difference]: Finished difference Result 1025 states and 1494 transitions. [2024-11-17 08:52:02,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1025 states and 1494 transitions. [2024-11-17 08:52:02,994 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 934 [2024-11-17 08:52:02,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1025 states to 1025 states and 1494 transitions. [2024-11-17 08:52:02,998 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1025 [2024-11-17 08:52:02,998 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1025 [2024-11-17 08:52:02,998 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1025 states and 1494 transitions. [2024-11-17 08:52:02,999 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:02,999 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1025 states and 1494 transitions. [2024-11-17 08:52:03,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1025 states and 1494 transitions. [2024-11-17 08:52:03,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1025 to 1025. [2024-11-17 08:52:03,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1025 states, 1025 states have (on average 1.457560975609756) internal successors, (1494), 1024 states have internal predecessors, (1494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1025 states to 1025 states and 1494 transitions. [2024-11-17 08:52:03,016 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1025 states and 1494 transitions. [2024-11-17 08:52:03,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:03,017 INFO L425 stractBuchiCegarLoop]: Abstraction has 1025 states and 1494 transitions. [2024-11-17 08:52:03,017 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:52:03,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1025 states and 1494 transitions. [2024-11-17 08:52:03,021 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 934 [2024-11-17 08:52:03,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,023 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,023 INFO L745 eck$LassoCheckResult]: Stem: 8033#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7472#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7473#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7612#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7613#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 7416#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7417#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7843#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7844#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7796#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7797#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7765#L599-1 assume !(0 == ~M_E~0); 7447#L604-1 assume !(0 == ~T1_E~0); 7438#L609-1 assume !(0 == ~T2_E~0); 7439#L614-1 assume !(0 == ~T3_E~0); 7595#L619-1 assume !(0 == ~T4_E~0); 7713#L624-1 assume !(0 == ~T5_E~0); 7845#L629-1 assume !(0 == ~E_M~0); 7540#L634-1 assume !(0 == ~E_1~0); 7541#L639-1 assume !(0 == ~E_2~0); 7941#L644-1 assume !(0 == ~E_3~0); 7952#L649-1 assume !(0 == ~E_4~0); 7499#L654-1 assume !(0 == ~E_5~0); 7500#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7882#L292-8 assume !(1 == ~m_pc~0); 7666#L302-8 is_master_triggered_~__retres1~0#1 := 0; 7667#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7750#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7604#L743-8 assume !(0 != activate_threads_~tmp~1#1); 7605#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7620#L311-8 assume 1 == ~t1_pc~0; 7589#L312-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7590#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7691#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7692#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 7740#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7888#L330-8 assume 1 == ~t2_pc~0; 7801#L331-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7421#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7779#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7780#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 8017#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7566#L349-8 assume 1 == ~t3_pc~0; 7567#L350-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7606#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7607#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7885#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 7877#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7652#L368-8 assume !(1 == ~t4_pc~0); 7496#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 7495#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7548#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7549#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 7922#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7428#L387-8 assume 1 == ~t5_pc~0; 7429#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7726#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7727#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7587#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 7588#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7864#L667-1 assume 1 == ~M_E~0;~M_E~0 := 2; 7865#L672-1 assume !(1 == ~T1_E~0); 7699#L677-1 assume !(1 == ~T2_E~0); 7700#L682-1 assume !(1 == ~T3_E~0); 7920#L687-1 assume !(1 == ~T4_E~0); 8120#L692-1 assume !(1 == ~T5_E~0); 8010#L697-1 assume !(1 == ~E_M~0); 8118#L702-1 assume !(1 == ~E_1~0); 8117#L707-1 assume !(1 == ~E_2~0); 8116#L712-1 assume !(1 == ~E_3~0); 8115#L717-1 assume !(1 == ~E_4~0); 8114#L722-1 assume !(1 == ~E_5~0); 8112#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 7810#L928 [2024-11-17 08:52:03,024 INFO L747 eck$LassoCheckResult]: Loop: 7810#L928 assume true; 7811#L928-1 assume !false; 8029#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7513#L494 assume true; 7644#L494-1 assume !false; 7645#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7840#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7823#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7824#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8037#L499 assume !(0 != eval_~tmp~0#1); 8036#L502 assume true; 7906#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7445#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7446#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 7775#L604 assume !(0 == ~T1_E~0); 7776#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7768#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7769#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7836#L624 assume !(0 == ~T5_E~0); 7934#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 7935#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 8006#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 7867#L644 assume !(0 == ~E_3~0); 7868#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 7636#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 7637#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7475#L292-1 assume 1 == ~m_pc~0; 7476#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7738#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7971#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7972#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7942#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7804#L311-1 assume 1 == ~t1_pc~0; 7483#L312-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7484#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7965#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7709#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7693#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7431#L330-1 assume !(1 == ~t2_pc~0); 7432#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 7771#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7424#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7425#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7739#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7753#L349-1 assume 1 == ~t3_pc~0; 7754#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7964#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7735#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7736#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7689#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7690#L368-1 assume !(1 == ~t4_pc~0); 8032#L378-1 is_transmit4_triggered_~__retres1~4#1 := 0; 8192#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8189#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8187#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8185#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7962#L387-1 assume !(1 == ~t5_pc~0); 7626#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 7627#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7863#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7655#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7656#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7766#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 7767#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7895#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7896#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7526#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7527#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7763#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 7748#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 7749#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 8020#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 7463#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 7464#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 7557#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7558#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7482#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7997#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7783#L947 assume !(0 == start_simulation_~tmp~3#1); 7462#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7976#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7530#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7531#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 7611#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7969#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7904#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7905#L960 assume !(0 != start_simulation_~tmp___0~1#1); 7810#L928 [2024-11-17 08:52:03,025 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,025 INFO L85 PathProgramCache]: Analyzing trace with hash -2080348054, now seen corresponding path program 1 times [2024-11-17 08:52:03,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288199660] [2024-11-17 08:52:03,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288199660] [2024-11-17 08:52:03,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [288199660] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:03,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841186723] [2024-11-17 08:52:03,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,058 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:03,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,058 INFO L85 PathProgramCache]: Analyzing trace with hash -2012572071, now seen corresponding path program 1 times [2024-11-17 08:52:03,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740778853] [2024-11-17 08:52:03,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740778853] [2024-11-17 08:52:03,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740778853] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:03,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991121050] [2024-11-17 08:52:03,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,102 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:03,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:03,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:03,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:03,102 INFO L87 Difference]: Start difference. First operand 1025 states and 1494 transitions. cyclomatic complexity: 471 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,146 INFO L93 Difference]: Finished difference Result 1853 states and 2673 transitions. [2024-11-17 08:52:03,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1853 states and 2673 transitions. [2024-11-17 08:52:03,153 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1759 [2024-11-17 08:52:03,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1853 states to 1853 states and 2673 transitions. [2024-11-17 08:52:03,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1853 [2024-11-17 08:52:03,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1853 [2024-11-17 08:52:03,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1853 states and 2673 transitions. [2024-11-17 08:52:03,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:03,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1853 states and 2673 transitions. [2024-11-17 08:52:03,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1853 states and 2673 transitions. [2024-11-17 08:52:03,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1853 to 1845. [2024-11-17 08:52:03,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1845 states, 1845 states have (on average 1.4444444444444444) internal successors, (2665), 1844 states have internal predecessors, (2665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1845 states to 1845 states and 2665 transitions. [2024-11-17 08:52:03,185 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1845 states and 2665 transitions. [2024-11-17 08:52:03,188 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:03,189 INFO L425 stractBuchiCegarLoop]: Abstraction has 1845 states and 2665 transitions. [2024-11-17 08:52:03,189 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:52:03,189 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1845 states and 2665 transitions. [2024-11-17 08:52:03,198 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1751 [2024-11-17 08:52:03,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,203 INFO L745 eck$LassoCheckResult]: Stem: 10962#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 10360#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 10361#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10499#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10500#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 10303#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10304#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10734#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10735#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10686#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10687#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10656#L599-1 assume !(0 == ~M_E~0); 10334#L604-1 assume !(0 == ~T1_E~0); 10325#L609-1 assume !(0 == ~T2_E~0); 10326#L614-1 assume !(0 == ~T3_E~0); 10481#L619-1 assume !(0 == ~T4_E~0); 10602#L624-1 assume !(0 == ~T5_E~0); 10736#L629-1 assume !(0 == ~E_M~0); 10428#L634-1 assume !(0 == ~E_1~0); 10429#L639-1 assume !(0 == ~E_2~0); 10827#L644-1 assume !(0 == ~E_3~0); 10845#L649-1 assume !(0 == ~E_4~0); 10387#L654-1 assume !(0 == ~E_5~0); 10388#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10772#L292-8 assume !(1 == ~m_pc~0); 10556#L302-8 is_master_triggered_~__retres1~0#1 := 0; 10557#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10639#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10490#L743-8 assume !(0 != activate_threads_~tmp~1#1); 10491#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10508#L311-8 assume !(1 == ~t1_pc~0); 10902#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 10958#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10580#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10581#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 10629#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10777#L330-8 assume 1 == ~t2_pc~0; 10691#L331-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10308#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10670#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10671#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 10923#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10454#L349-8 assume 1 == ~t3_pc~0; 10455#L350-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10492#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10493#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10775#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 10767#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10542#L368-8 assume !(1 == ~t4_pc~0); 10384#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 10383#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10436#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10437#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 10806#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10315#L387-8 assume 1 == ~t5_pc~0; 10316#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10615#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10616#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10476#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 10477#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10756#L667-1 assume 1 == ~M_E~0;~M_E~0 := 2; 10757#L672-1 assume !(1 == ~T1_E~0); 10588#L677-1 assume !(1 == ~T2_E~0); 10589#L682-1 assume !(1 == ~T3_E~0); 10804#L687-1 assume !(1 == ~T4_E~0); 10876#L692-1 assume !(1 == ~T5_E~0); 10791#L697-1 assume !(1 == ~E_M~0); 10792#L702-1 assume !(1 == ~E_1~0); 11198#L707-1 assume !(1 == ~E_2~0); 11196#L712-1 assume !(1 == ~E_3~0); 11195#L717-1 assume !(1 == ~E_4~0); 10810#L722-1 assume !(1 == ~E_5~0); 10811#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 10702#L928 [2024-11-17 08:52:03,204 INFO L747 eck$LassoCheckResult]: Loop: 10702#L928 assume true; 10703#L928-1 assume !false; 10942#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10402#L494 assume true; 10535#L494-1 assume !false; 10536#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10679#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10633#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 10716#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11140#L499 assume !(0 != eval_~tmp~0#1); 11139#L502 assume true; 11137#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11135#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11132#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 11133#L604 assume !(0 == ~T1_E~0); 11126#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11127#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11119#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11120#L624 assume !(0 == ~T5_E~0); 11113#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 11114#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 11107#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 11108#L644 assume !(0 == ~E_3~0); 11100#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 11101#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 11094#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11095#L292-1 assume !(1 == ~m_pc~0); 11008#L302-1 is_master_triggered_~__retres1~0#1 := 0; 11009#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11002#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11003#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10983#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10984#L311-1 assume !(1 == ~t1_pc~0); 11464#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 11463#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11462#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11461#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11460#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11459#L330-1 assume !(1 == ~t2_pc~0); 11457#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 11456#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11455#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11454#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11453#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11452#L349-1 assume 1 == ~t3_pc~0; 11450#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11449#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11448#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11447#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11446#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11445#L368-1 assume !(1 == ~t4_pc~0); 11443#L378-1 is_transmit4_triggered_~__retres1~4#1 := 0; 11442#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10889#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10672#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10330#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10331#L387-1 assume !(1 == ~t5_pc~0); 10514#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 10515#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10755#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10545#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10546#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10657#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 10658#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10783#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10784#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10415#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10416#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10654#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 10637#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 10638#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 10927#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 10350#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 10351#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 10445#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10446#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10370#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 10894#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 10937#L947 assume !(0 == start_simulation_~tmp~3#1); 10349#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 11376#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10419#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 10420#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 10498#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10864#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10790#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 10778#L960 assume !(0 != start_simulation_~tmp___0~1#1); 10702#L928 [2024-11-17 08:52:03,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,204 INFO L85 PathProgramCache]: Analyzing trace with hash 1517776109, now seen corresponding path program 1 times [2024-11-17 08:52:03,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590752031] [2024-11-17 08:52:03,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590752031] [2024-11-17 08:52:03,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590752031] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,264 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,264 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:03,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704436663] [2024-11-17 08:52:03,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,265 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:03,265 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,265 INFO L85 PathProgramCache]: Analyzing trace with hash 731248671, now seen corresponding path program 1 times [2024-11-17 08:52:03,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205380119] [2024-11-17 08:52:03,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205380119] [2024-11-17 08:52:03,305 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205380119] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,305 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,305 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:03,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [593573745] [2024-11-17 08:52:03,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,306 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:03,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:03,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:03,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:03,306 INFO L87 Difference]: Start difference. First operand 1845 states and 2665 transitions. cyclomatic complexity: 824 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,364 INFO L93 Difference]: Finished difference Result 3393 states and 4861 transitions. [2024-11-17 08:52:03,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3393 states and 4861 transitions. [2024-11-17 08:52:03,377 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3288 [2024-11-17 08:52:03,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3393 states to 3393 states and 4861 transitions. [2024-11-17 08:52:03,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3393 [2024-11-17 08:52:03,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3393 [2024-11-17 08:52:03,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3393 states and 4861 transitions. [2024-11-17 08:52:03,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:03,392 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3393 states and 4861 transitions. [2024-11-17 08:52:03,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3393 states and 4861 transitions. [2024-11-17 08:52:03,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3393 to 3377. [2024-11-17 08:52:03,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3377 states, 3377 states have (on average 1.434705359786793) internal successors, (4845), 3376 states have internal predecessors, (4845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3377 states to 3377 states and 4845 transitions. [2024-11-17 08:52:03,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3377 states and 4845 transitions. [2024-11-17 08:52:03,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:03,432 INFO L425 stractBuchiCegarLoop]: Abstraction has 3377 states and 4845 transitions. [2024-11-17 08:52:03,432 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:52:03,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3377 states and 4845 transitions. [2024-11-17 08:52:03,443 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3272 [2024-11-17 08:52:03,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,444 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,444 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,444 INFO L745 eck$LassoCheckResult]: Stem: 16225#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 15605#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15606#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15745#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15746#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 15550#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15551#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15983#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15984#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15940#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15941#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15905#L599-1 assume !(0 == ~M_E~0); 15580#L604-1 assume !(0 == ~T1_E~0); 15571#L609-1 assume !(0 == ~T2_E~0); 15572#L614-1 assume !(0 == ~T3_E~0); 15728#L619-1 assume !(0 == ~T4_E~0); 15849#L624-1 assume !(0 == ~T5_E~0); 15985#L629-1 assume !(0 == ~E_M~0); 15675#L634-1 assume !(0 == ~E_1~0); 15676#L639-1 assume !(0 == ~E_2~0); 16084#L644-1 assume !(0 == ~E_3~0); 16098#L649-1 assume !(0 == ~E_4~0); 15632#L654-1 assume !(0 == ~E_5~0); 15633#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16024#L292-8 assume !(1 == ~m_pc~0); 15800#L302-8 is_master_triggered_~__retres1~0#1 := 0; 15801#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15886#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15737#L743-8 assume !(0 != activate_threads_~tmp~1#1); 15738#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15753#L311-8 assume !(1 == ~t1_pc~0); 16162#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 16221#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15824#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15825#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 15876#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16029#L330-8 assume !(1 == ~t2_pc~0); 15554#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 15555#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15921#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15922#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 16186#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15701#L349-8 assume 1 == ~t3_pc~0; 15702#L350-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15739#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15740#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16027#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 16019#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15786#L368-8 assume !(1 == ~t4_pc~0); 15629#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 15628#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15683#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15684#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 16063#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15562#L387-8 assume 1 == ~t5_pc~0; 15563#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15862#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15863#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15724#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 15725#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16006#L667-1 assume 1 == ~M_E~0;~M_E~0 := 2; 16007#L672-1 assume !(1 == ~T1_E~0); 18096#L677-1 assume !(1 == ~T2_E~0); 18095#L682-1 assume !(1 == ~T3_E~0); 18094#L687-1 assume !(1 == ~T4_E~0); 18093#L692-1 assume !(1 == ~T5_E~0); 16171#L697-1 assume !(1 == ~E_M~0); 18092#L702-1 assume !(1 == ~E_1~0); 18091#L707-1 assume !(1 == ~E_2~0); 15962#L712-1 assume !(1 == ~E_3~0); 15963#L717-1 assume !(1 == ~E_4~0); 18083#L722-1 assume !(1 == ~E_5~0); 18081#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 18078#L928 [2024-11-17 08:52:03,444 INFO L747 eck$LassoCheckResult]: Loop: 18078#L928 assume true; 18076#L928-1 assume !false; 17999#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17996#L494 assume true; 17994#L494-1 assume !false; 17992#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 17983#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 17982#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 17981#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17976#L499 assume !(0 != eval_~tmp~0#1); 17977#L502 assume true; 18377#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18375#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18373#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 18371#L604 assume !(0 == ~T1_E~0); 18369#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18367#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18365#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18363#L624 assume !(0 == ~T5_E~0); 18361#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 18359#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 18357#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 18355#L644 assume !(0 == ~E_3~0); 18353#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 18351#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 18349#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18346#L292-1 assume !(1 == ~m_pc~0); 18343#L302-1 is_master_triggered_~__retres1~0#1 := 0; 18341#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18339#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18337#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18335#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18333#L311-1 assume !(1 == ~t1_pc~0); 18331#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 18329#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18327#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18325#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18324#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18323#L330-1 assume !(1 == ~t2_pc~0); 18322#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 18321#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18320#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18319#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18318#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18317#L349-1 assume 1 == ~t3_pc~0; 18315#L350-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16114#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15871#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15872#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15822#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15823#L368-1 assume 1 == ~t4_pc~0; 16176#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15859#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15860#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15923#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15924#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18229#L387-1 assume !(1 == ~t5_pc~0); 18226#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 18224#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18222#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18218#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18214#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18209#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 15907#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18208#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18207#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18206#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18205#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15903#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 18204#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 18203#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 18202#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 18201#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 18200#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 18199#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18135#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18134#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18133#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18132#L947 assume !(0 == start_simulation_~tmp~3#1); 17946#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 18106#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 18104#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 18102#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 18099#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18098#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18097#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 18080#L960 assume !(0 != start_simulation_~tmp___0~1#1); 18078#L928 [2024-11-17 08:52:03,445 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,445 INFO L85 PathProgramCache]: Analyzing trace with hash -2053058640, now seen corresponding path program 1 times [2024-11-17 08:52:03,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436024695] [2024-11-17 08:52:03,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [436024695] [2024-11-17 08:52:03,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [436024695] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:03,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31163123] [2024-11-17 08:52:03,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,472 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:03,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,472 INFO L85 PathProgramCache]: Analyzing trace with hash 7116124, now seen corresponding path program 1 times [2024-11-17 08:52:03,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469180136] [2024-11-17 08:52:03,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,507 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,507 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469180136] [2024-11-17 08:52:03,507 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469180136] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,507 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,507 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:03,507 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1970168247] [2024-11-17 08:52:03,507 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,507 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:03,508 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:03,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:03,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:03,508 INFO L87 Difference]: Start difference. First operand 3377 states and 4845 transitions. cyclomatic complexity: 1476 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,573 INFO L93 Difference]: Finished difference Result 6260 states and 8922 transitions. [2024-11-17 08:52:03,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6260 states and 8922 transitions. [2024-11-17 08:52:03,593 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6124 [2024-11-17 08:52:03,612 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6260 states to 6260 states and 8922 transitions. [2024-11-17 08:52:03,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6260 [2024-11-17 08:52:03,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6260 [2024-11-17 08:52:03,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6260 states and 8922 transitions. [2024-11-17 08:52:03,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:03,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6260 states and 8922 transitions. [2024-11-17 08:52:03,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6260 states and 8922 transitions. [2024-11-17 08:52:03,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6260 to 6228. [2024-11-17 08:52:03,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6228 states, 6228 states have (on average 1.4274245343609506) internal successors, (8890), 6227 states have internal predecessors, (8890), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6228 states to 6228 states and 8890 transitions. [2024-11-17 08:52:03,728 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6228 states and 8890 transitions. [2024-11-17 08:52:03,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:03,729 INFO L425 stractBuchiCegarLoop]: Abstraction has 6228 states and 8890 transitions. [2024-11-17 08:52:03,729 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:52:03,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6228 states and 8890 transitions. [2024-11-17 08:52:03,741 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6092 [2024-11-17 08:52:03,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:03,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:03,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:03,742 INFO L745 eck$LassoCheckResult]: Stem: 25883#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 25253#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 25254#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25392#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25393#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 25196#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25197#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25627#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25628#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25584#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25585#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25554#L599-1 assume !(0 == ~M_E~0); 25227#L604-1 assume !(0 == ~T1_E~0); 25218#L609-1 assume !(0 == ~T2_E~0); 25219#L614-1 assume !(0 == ~T3_E~0); 25376#L619-1 assume !(0 == ~T4_E~0); 25498#L624-1 assume !(0 == ~T5_E~0); 25629#L629-1 assume !(0 == ~E_M~0); 25323#L634-1 assume !(0 == ~E_1~0); 25324#L639-1 assume !(0 == ~E_2~0); 25734#L644-1 assume !(0 == ~E_3~0); 25752#L649-1 assume !(0 == ~E_4~0); 25280#L654-1 assume !(0 == ~E_5~0); 25281#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25669#L292-8 assume !(1 == ~m_pc~0); 25445#L302-8 is_master_triggered_~__retres1~0#1 := 0; 25446#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25537#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25384#L743-8 assume !(0 != activate_threads_~tmp~1#1); 25385#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25400#L311-8 assume !(1 == ~t1_pc~0); 25811#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 25879#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25470#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25471#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 25526#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25675#L330-8 assume !(1 == ~t2_pc~0); 25200#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 25201#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25568#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25569#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 25839#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25351#L349-8 assume !(1 == ~t3_pc~0); 25352#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 25386#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25387#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25673#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 25662#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25432#L368-8 assume !(1 == ~t4_pc~0); 25277#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 25276#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25331#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25332#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 25709#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25208#L387-8 assume 1 == ~t5_pc~0; 25209#L388-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25511#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25512#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25372#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 25373#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25650#L667-1 assume 1 == ~M_E~0;~M_E~0 := 2; 25651#L672-1 assume !(1 == ~T1_E~0); 25744#L677-1 assume !(1 == ~T2_E~0); 25706#L682-1 assume !(1 == ~T3_E~0); 25707#L687-1 assume !(1 == ~T4_E~0); 25820#L692-1 assume !(1 == ~T5_E~0); 25821#L697-1 assume !(1 == ~E_M~0); 25862#L702-1 assume !(1 == ~E_1~0); 25863#L707-1 assume !(1 == ~E_2~0); 25605#L712-1 assume !(1 == ~E_3~0); 25606#L717-1 assume !(1 == ~E_4~0); 25713#L722-1 assume !(1 == ~E_5~0); 25714#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 27675#L928 [2024-11-17 08:52:03,742 INFO L747 eck$LassoCheckResult]: Loop: 27675#L928 assume true; 27670#L928-1 assume !false; 27664#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27660#L494 assume true; 27658#L494-1 assume !false; 27656#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 27649#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 27647#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 27645#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 27642#L499 assume !(0 != eval_~tmp~0#1); 27643#L502 assume true; 28124#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28120#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28116#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 28111#L604 assume !(0 == ~T1_E~0); 28106#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28101#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28097#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28087#L624 assume !(0 == ~T5_E~0); 28080#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 28072#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 28065#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 28058#L644 assume !(0 == ~E_3~0); 28050#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 28042#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 28035#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28028#L292-1 assume !(1 == ~m_pc~0); 28022#L302-1 is_master_triggered_~__retres1~0#1 := 0; 28020#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28018#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28016#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28009#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28007#L311-1 assume !(1 == ~t1_pc~0); 28004#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 28000#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27997#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27994#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27991#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27988#L330-1 assume !(1 == ~t2_pc~0); 27980#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 27977#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27974#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27970#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27968#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27965#L349-1 assume !(1 == ~t3_pc~0); 27961#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 27958#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27956#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27952#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27947#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27943#L368-1 assume !(1 == ~t4_pc~0); 27938#L378-1 is_transmit4_triggered_~__retres1~4#1 := 0; 27933#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27929#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27925#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27921#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27917#L387-1 assume !(1 == ~t5_pc~0); 27912#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 27906#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27900#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27895#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27890#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27839#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 27835#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27833#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27831#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27829#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27827#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27823#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 27821#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 27819#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 27817#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 27815#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 27813#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 27811#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 27742#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 27737#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 27731#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 27726#L947 assume !(0 == start_simulation_~tmp~3#1); 27720#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 27711#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 27705#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 27700#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 27694#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27688#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27684#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 27680#L960 assume !(0 != start_simulation_~tmp___0~1#1); 27675#L928 [2024-11-17 08:52:03,742 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,742 INFO L85 PathProgramCache]: Analyzing trace with hash -1724890957, now seen corresponding path program 1 times [2024-11-17 08:52:03,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313989117] [2024-11-17 08:52:03,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,768 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [313989117] [2024-11-17 08:52:03,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [313989117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:03,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717100666] [2024-11-17 08:52:03,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,770 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:03,770 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:03,770 INFO L85 PathProgramCache]: Analyzing trace with hash 34405538, now seen corresponding path program 1 times [2024-11-17 08:52:03,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:03,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [706204387] [2024-11-17 08:52:03,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:03,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:03,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:03,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:03,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:03,799 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [706204387] [2024-11-17 08:52:03,799 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [706204387] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:03,799 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:03,799 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:03,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58738172] [2024-11-17 08:52:03,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:03,800 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:03,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:03,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:03,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:03,800 INFO L87 Difference]: Start difference. First operand 6228 states and 8890 transitions. cyclomatic complexity: 2678 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:03,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:03,870 INFO L93 Difference]: Finished difference Result 11575 states and 16435 transitions. [2024-11-17 08:52:03,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11575 states and 16435 transitions. [2024-11-17 08:52:03,903 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 11360 [2024-11-17 08:52:04,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11575 states to 11575 states and 16435 transitions. [2024-11-17 08:52:04,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11575 [2024-11-17 08:52:04,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11575 [2024-11-17 08:52:04,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11575 states and 16435 transitions. [2024-11-17 08:52:04,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:04,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11575 states and 16435 transitions. [2024-11-17 08:52:04,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11575 states and 16435 transitions. [2024-11-17 08:52:04,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11575 to 11511. [2024-11-17 08:52:04,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11511 states, 11511 states have (on average 1.4222048475371385) internal successors, (16371), 11510 states have internal predecessors, (16371), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11511 states to 11511 states and 16371 transitions. [2024-11-17 08:52:04,186 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11511 states and 16371 transitions. [2024-11-17 08:52:04,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:04,187 INFO L425 stractBuchiCegarLoop]: Abstraction has 11511 states and 16371 transitions. [2024-11-17 08:52:04,187 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:52:04,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11511 states and 16371 transitions. [2024-11-17 08:52:04,214 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 11296 [2024-11-17 08:52:04,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:04,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:04,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,215 INFO L745 eck$LassoCheckResult]: Stem: 43680#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 43063#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 43064#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43196#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43197#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 43010#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43011#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43436#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43437#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43393#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43394#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43358#L599-1 assume !(0 == ~M_E~0); 43039#L604-1 assume !(0 == ~T1_E~0); 43028#L609-1 assume !(0 == ~T2_E~0); 43029#L614-1 assume !(0 == ~T3_E~0); 43180#L619-1 assume !(0 == ~T4_E~0); 43303#L624-1 assume !(0 == ~T5_E~0); 43438#L629-1 assume !(0 == ~E_M~0); 43132#L634-1 assume !(0 == ~E_1~0); 43133#L639-1 assume !(0 == ~E_2~0); 43551#L644-1 assume !(0 == ~E_3~0); 43564#L649-1 assume !(0 == ~E_4~0); 43089#L654-1 assume !(0 == ~E_5~0); 43090#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43483#L292-8 assume !(1 == ~m_pc~0); 43252#L302-8 is_master_triggered_~__retres1~0#1 := 0; 43253#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43342#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43188#L743-8 assume !(0 != activate_threads_~tmp~1#1); 43189#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43207#L311-8 assume !(1 == ~t1_pc~0); 43621#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 43679#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43277#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43278#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 43330#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43488#L330-8 assume !(1 == ~t2_pc~0); 43012#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 43013#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43378#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43379#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 43648#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43156#L349-8 assume !(1 == ~t3_pc~0); 43157#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 43190#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43191#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43487#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 43475#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43237#L368-8 assume !(1 == ~t4_pc~0); 43086#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 43085#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43141#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43142#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 43528#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43024#L387-8 assume !(1 == ~t5_pc~0); 43025#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 43316#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43317#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43176#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 43177#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43463#L667-1 assume 1 == ~M_E~0;~M_E~0 := 2; 43464#L672-1 assume !(1 == ~T1_E~0); 43288#L677-1 assume !(1 == ~T2_E~0); 43289#L682-1 assume !(1 == ~T3_E~0); 43595#L687-1 assume !(1 == ~T4_E~0); 43596#L692-1 assume !(1 == ~T5_E~0); 43509#L697-1 assume !(1 == ~E_M~0); 43510#L702-1 assume !(1 == ~E_1~0); 43559#L707-1 assume !(1 == ~E_2~0); 43560#L712-1 assume !(1 == ~E_3~0); 43555#L717-1 assume !(1 == ~E_4~0); 43556#L722-1 assume !(1 == ~E_5~0); 43636#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 43637#L928 [2024-11-17 08:52:04,216 INFO L747 eck$LassoCheckResult]: Loop: 43637#L928 assume true; 46779#L928-1 assume !false; 46773#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46769#L494 assume true; 46766#L494-1 assume !false; 46763#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 46753#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 46750#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 46747#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46743#L499 assume !(0 != eval_~tmp~0#1); 46744#L502 assume true; 47062#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47059#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47056#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 47052#L604 assume !(0 == ~T1_E~0); 47049#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47046#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47043#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47040#L624 assume !(0 == ~T5_E~0); 47037#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 47033#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 47029#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 47026#L644 assume !(0 == ~E_3~0); 47023#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 47020#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 47017#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47013#L292-1 assume 1 == ~m_pc~0; 47008#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47003#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46999#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46995#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46993#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46991#L311-1 assume !(1 == ~t1_pc~0); 46988#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 46984#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46981#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46978#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46975#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46971#L330-1 assume !(1 == ~t2_pc~0); 46968#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 46965#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46962#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46959#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46956#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46953#L349-1 assume !(1 == ~t3_pc~0); 46950#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 46945#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46941#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46939#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46936#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46932#L368-1 assume !(1 == ~t4_pc~0); 46928#L378-1 is_transmit4_triggered_~__retres1~4#1 := 0; 46925#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46922#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46919#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46916#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46912#L387-1 assume !(1 == ~t5_pc~0); 46909#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 46906#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46903#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46900#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46897#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46894#L667 assume 1 == ~M_E~0;~M_E~0 := 2; 46651#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46889#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46886#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46883#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46880#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46634#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 46875#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 46872#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 46867#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 46862#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 46858#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 46853#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 46841#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 46837#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 46832#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 46828#L947 assume !(0 == start_simulation_~tmp~3#1); 46824#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 46816#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 46811#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 46807#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 46804#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46801#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46798#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 46793#L960 assume !(0 != start_simulation_~tmp___0~1#1); 43637#L928 [2024-11-17 08:52:04,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,216 INFO L85 PathProgramCache]: Analyzing trace with hash -575218122, now seen corresponding path program 1 times [2024-11-17 08:52:04,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321967749] [2024-11-17 08:52:04,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321967749] [2024-11-17 08:52:04,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321967749] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,304 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:04,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160769182] [2024-11-17 08:52:04,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,305 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:04,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1402925791, now seen corresponding path program 1 times [2024-11-17 08:52:04,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737601343] [2024-11-17 08:52:04,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,353 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737601343] [2024-11-17 08:52:04,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737601343] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:04,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012574895] [2024-11-17 08:52:04,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,354 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:04,354 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:04,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:04,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:04,355 INFO L87 Difference]: Start difference. First operand 11511 states and 16371 transitions. cyclomatic complexity: 4892 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:04,426 INFO L93 Difference]: Finished difference Result 16978 states and 24168 transitions. [2024-11-17 08:52:04,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16978 states and 24168 transitions. [2024-11-17 08:52:04,491 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 16704 [2024-11-17 08:52:04,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16978 states to 16978 states and 24168 transitions. [2024-11-17 08:52:04,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16978 [2024-11-17 08:52:04,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16978 [2024-11-17 08:52:04,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16978 states and 24168 transitions. [2024-11-17 08:52:04,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:04,573 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16978 states and 24168 transitions. [2024-11-17 08:52:04,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16978 states and 24168 transitions. [2024-11-17 08:52:04,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16978 to 11691. [2024-11-17 08:52:04,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11691 states, 11691 states have (on average 1.4283636985715507) internal successors, (16699), 11690 states have internal predecessors, (16699), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:04,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11691 states to 11691 states and 16699 transitions. [2024-11-17 08:52:04,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11691 states and 16699 transitions. [2024-11-17 08:52:04,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:04,814 INFO L425 stractBuchiCegarLoop]: Abstraction has 11691 states and 16699 transitions. [2024-11-17 08:52:04,814 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:52:04,814 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11691 states and 16699 transitions. [2024-11-17 08:52:04,840 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11488 [2024-11-17 08:52:04,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:04,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:04,841 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,841 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:04,841 INFO L745 eck$LassoCheckResult]: Stem: 72131#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 71561#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 71562#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71694#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71695#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 71508#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 71509#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 71922#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 71923#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71879#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71880#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71848#L599-1 assume !(0 == ~M_E~0); 71537#L604-1 assume !(0 == ~T1_E~0); 71526#L609-1 assume !(0 == ~T2_E~0); 71527#L614-1 assume !(0 == ~T3_E~0); 71678#L619-1 assume !(0 == ~T4_E~0); 71795#L624-1 assume !(0 == ~T5_E~0); 71924#L629-1 assume !(0 == ~E_M~0); 71629#L634-1 assume !(0 == ~E_1~0); 71630#L639-1 assume !(0 == ~E_2~0); 72019#L644-1 assume !(0 == ~E_3~0); 72030#L649-1 assume !(0 == ~E_4~0); 71587#L654-1 assume !(0 == ~E_5~0); 71588#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71963#L292-8 assume !(1 == ~m_pc~0); 71749#L302-8 is_master_triggered_~__retres1~0#1 := 0; 71750#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71834#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 71686#L743-8 assume !(0 != activate_threads_~tmp~1#1); 71687#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71704#L311-8 assume !(1 == ~t1_pc~0); 72077#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 72127#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71771#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 71772#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 71822#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71968#L330-8 assume !(1 == ~t2_pc~0); 71510#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 71511#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71865#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 71866#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 72098#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71653#L349-8 assume !(1 == ~t3_pc~0); 71654#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 71688#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71689#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 71967#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 71955#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71734#L368-8 assume !(1 == ~t4_pc~0); 71584#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 71583#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71638#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71639#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 71998#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71522#L387-8 assume !(1 == ~t5_pc~0); 71523#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 71808#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71809#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71674#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 71675#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71945#L667-1 assume !(1 == ~M_E~0); 71946#L672-1 assume !(1 == ~T1_E~0); 71781#L677-1 assume !(1 == ~T2_E~0); 71782#L682-1 assume !(1 == ~T3_E~0); 71994#L687-1 assume !(1 == ~T4_E~0); 72057#L692-1 assume !(1 == ~T5_E~0); 71982#L697-1 assume !(1 == ~E_M~0); 71983#L702-1 assume !(1 == ~E_1~0); 72026#L707-1 assume !(1 == ~E_2~0); 71899#L712-1 assume !(1 == ~E_3~0); 71900#L717-1 assume !(1 == ~E_4~0); 72002#L722-1 assume !(1 == ~E_5~0); 72003#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 72091#L928 [2024-11-17 08:52:04,842 INFO L747 eck$LassoCheckResult]: Loop: 72091#L928 assume true; 74331#L928-1 assume !false; 74325#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74321#L494 assume true; 74318#L494-1 assume !false; 74310#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 74302#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 74299#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 74295#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 74291#L499 assume !(0 != eval_~tmp~0#1); 74288#L502 assume true; 74285#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 74282#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74279#L599 assume !(0 == ~M_E~0); 74276#L604 assume !(0 == ~T1_E~0); 74273#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 74270#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74267#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74263#L624 assume !(0 == ~T5_E~0); 74260#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 74257#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 74254#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 74251#L644 assume !(0 == ~E_3~0); 74248#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 74244#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 74241#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74237#L292-1 assume !(1 == ~m_pc~0); 74233#L302-1 is_master_triggered_~__retres1~0#1 := 0; 74230#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74227#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 74224#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 74221#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74218#L311-1 assume !(1 == ~t1_pc~0); 74215#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 74212#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74209#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 74206#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74203#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74200#L330-1 assume !(1 == ~t2_pc~0); 74197#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 74194#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74191#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 74187#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 74184#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74181#L349-1 assume !(1 == ~t3_pc~0); 74178#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 74175#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74172#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 74169#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74166#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74162#L368-1 assume 1 == ~t4_pc~0; 74159#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 74155#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74152#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 74150#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74147#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74143#L387-1 assume !(1 == ~t5_pc~0); 74140#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 74137#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74134#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 74131#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 74128#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74126#L667 assume !(1 == ~M_E~0); 73916#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74121#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74118#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74110#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74107#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 74104#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 74102#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 74100#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 74098#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 74096#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 74094#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 74087#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 74080#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 74078#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 74077#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 74021#L947 assume !(0 == start_simulation_~tmp~3#1); 74022#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 74370#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 74368#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 74366#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 74365#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 74358#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74356#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 74354#L960 assume !(0 != start_simulation_~tmp___0~1#1); 72091#L928 [2024-11-17 08:52:04,842 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,842 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 1 times [2024-11-17 08:52:04,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675202465] [2024-11-17 08:52:04,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:04,850 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:04,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:04,882 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:04,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:04,883 INFO L85 PathProgramCache]: Analyzing trace with hash 1971642367, now seen corresponding path program 1 times [2024-11-17 08:52:04,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:04,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901546787] [2024-11-17 08:52:04,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:04,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:04,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:04,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:04,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:04,924 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1901546787] [2024-11-17 08:52:04,924 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1901546787] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:04,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:04,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:04,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686038485] [2024-11-17 08:52:04,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:04,924 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:04,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:04,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:04,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:04,925 INFO L87 Difference]: Start difference. First operand 11691 states and 16699 transitions. cyclomatic complexity: 5024 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:05,000 INFO L93 Difference]: Finished difference Result 11915 states and 16923 transitions. [2024-11-17 08:52:05,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11915 states and 16923 transitions. [2024-11-17 08:52:05,094 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11712 [2024-11-17 08:52:05,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11915 states to 11915 states and 16923 transitions. [2024-11-17 08:52:05,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11915 [2024-11-17 08:52:05,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11915 [2024-11-17 08:52:05,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11915 states and 16923 transitions. [2024-11-17 08:52:05,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:05,125 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11915 states and 16923 transitions. [2024-11-17 08:52:05,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11915 states and 16923 transitions. [2024-11-17 08:52:05,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11915 to 11787. [2024-11-17 08:52:05,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11787 states, 11787 states have (on average 1.4248748621362517) internal successors, (16795), 11786 states have internal predecessors, (16795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11787 states to 11787 states and 16795 transitions. [2024-11-17 08:52:05,308 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11787 states and 16795 transitions. [2024-11-17 08:52:05,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:05,316 INFO L425 stractBuchiCegarLoop]: Abstraction has 11787 states and 16795 transitions. [2024-11-17 08:52:05,316 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:52:05,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11787 states and 16795 transitions. [2024-11-17 08:52:05,339 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11584 [2024-11-17 08:52:05,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:05,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:05,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,341 INFO L745 eck$LassoCheckResult]: Stem: 95845#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 95173#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 95174#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95315#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95316#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 95120#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95121#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95561#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95562#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95518#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95519#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95485#L599-1 assume !(0 == ~M_E~0); 95149#L604-1 assume !(0 == ~T1_E~0); 95140#L609-1 assume !(0 == ~T2_E~0); 95141#L614-1 assume !(0 == ~T3_E~0); 95295#L619-1 assume !(0 == ~T4_E~0); 95425#L624-1 assume !(0 == ~T5_E~0); 95563#L629-1 assume !(0 == ~E_M~0); 95240#L634-1 assume !(0 == ~E_1~0); 95241#L639-1 assume !(0 == ~E_2~0); 95671#L644-1 assume !(0 == ~E_3~0); 95686#L649-1 assume !(0 == ~E_4~0); 95200#L654-1 assume !(0 == ~E_5~0); 95201#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95611#L292-8 assume !(1 == ~m_pc~0); 95370#L302-8 is_master_triggered_~__retres1~0#1 := 0; 95371#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95466#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 95303#L743-8 assume !(0 != activate_threads_~tmp~1#1); 95304#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95323#L311-8 assume !(1 == ~t1_pc~0); 95751#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 95838#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95399#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 95400#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 95453#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95616#L330-8 assume !(1 == ~t2_pc~0); 95124#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 95125#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95501#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95502#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 95782#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95268#L349-8 assume !(1 == ~t3_pc~0); 95269#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 95305#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95306#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95614#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 95600#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95357#L368-8 assume !(1 == ~t4_pc~0); 95197#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 95196#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95248#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95249#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 95650#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95132#L387-8 assume !(1 == ~t5_pc~0); 95133#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 95438#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95439#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95291#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 95292#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95588#L667-1 assume !(1 == ~M_E~0); 95589#L672-1 assume !(1 == ~T1_E~0); 95410#L677-1 assume !(1 == ~T2_E~0); 95411#L682-1 assume !(1 == ~T3_E~0); 95645#L687-1 assume !(1 == ~T4_E~0); 95720#L692-1 assume !(1 == ~T5_E~0); 95631#L697-1 assume !(1 == ~E_M~0); 95632#L702-1 assume !(1 == ~E_1~0); 95681#L707-1 assume !(1 == ~E_2~0); 95539#L712-1 assume !(1 == ~E_3~0); 95540#L717-1 assume !(1 == ~E_4~0); 95654#L722-1 assume !(1 == ~E_5~0); 95655#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 95768#L928 [2024-11-17 08:52:05,341 INFO L747 eck$LassoCheckResult]: Loop: 95768#L928 assume true; 104683#L928-1 assume !false; 104681#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 104237#L494 assume true; 104678#L494-1 assume !false; 104676#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 104666#L452-2 assume !(0 == ~m_st~0); 104667#L456-2 assume !(0 == ~t1_st~0); 104670#L460-2 assume !(0 == ~t2_st~0); 104671#L464-2 assume !(0 == ~t3_st~0); 104672#L468-2 assume !(0 == ~t4_st~0); 104668#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 104669#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 103883#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 103884#L499 assume !(0 != eval_~tmp~0#1); 105229#L502 assume true; 105227#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105225#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 105223#L599 assume !(0 == ~M_E~0); 105221#L604 assume !(0 == ~T1_E~0); 105219#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 105217#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 105215#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 105213#L624 assume !(0 == ~T5_E~0); 105211#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 105209#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 105207#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 105204#L644 assume !(0 == ~E_3~0); 105202#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 105200#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 105198#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105196#L292-1 assume !(1 == ~m_pc~0); 105193#L302-1 is_master_triggered_~__retres1~0#1 := 0; 105191#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105189#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 105187#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 105185#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105183#L311-1 assume !(1 == ~t1_pc~0); 105181#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 105179#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105177#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 105175#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 105173#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105171#L330-1 assume !(1 == ~t2_pc~0); 105169#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 105167#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105165#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 105163#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 105161#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 105159#L349-1 assume !(1 == ~t3_pc~0); 105157#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 105154#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105152#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 105150#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 105148#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105146#L368-1 assume !(1 == ~t4_pc~0); 105143#L378-1 is_transmit4_triggered_~__retres1~4#1 := 0; 105141#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105139#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 105137#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 105135#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105133#L387-1 assume !(1 == ~t5_pc~0); 105132#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 105131#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105129#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 105127#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 105125#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105123#L667 assume !(1 == ~M_E~0); 105119#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 105117#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 105115#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105113#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 105111#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 105109#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 105107#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 105106#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 105105#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 105104#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 105103#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 105096#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 105090#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 104903#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 104713#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 104709#L947 assume !(0 == start_simulation_~tmp~3#1); 104705#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 104697#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 104695#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 104693#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 104691#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 104690#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104688#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 104686#L960 assume !(0 != start_simulation_~tmp___0~1#1); 95768#L928 [2024-11-17 08:52:05,341 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,341 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 2 times [2024-11-17 08:52:05,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070070340] [2024-11-17 08:52:05,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:05,350 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:05,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:05,367 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:05,367 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,368 INFO L85 PathProgramCache]: Analyzing trace with hash -1428946245, now seen corresponding path program 1 times [2024-11-17 08:52:05,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956525130] [2024-11-17 08:52:05,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956525130] [2024-11-17 08:52:05,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956525130] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:05,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1916918058] [2024-11-17 08:52:05,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,415 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:05,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:05,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:05,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:05,416 INFO L87 Difference]: Start difference. First operand 11787 states and 16795 transitions. cyclomatic complexity: 5024 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:05,566 INFO L93 Difference]: Finished difference Result 12318 states and 17326 transitions. [2024-11-17 08:52:05,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12318 states and 17326 transitions. [2024-11-17 08:52:05,672 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12112 [2024-11-17 08:52:05,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12318 states to 12318 states and 17326 transitions. [2024-11-17 08:52:05,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12318 [2024-11-17 08:52:05,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12318 [2024-11-17 08:52:05,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12318 states and 17326 transitions. [2024-11-17 08:52:05,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:05,729 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12318 states and 17326 transitions. [2024-11-17 08:52:05,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12318 states and 17326 transitions. [2024-11-17 08:52:05,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12318 to 12318. [2024-11-17 08:52:05,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12318 states, 12318 states have (on average 1.406559506413379) internal successors, (17326), 12317 states have internal predecessors, (17326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12318 states to 12318 states and 17326 transitions. [2024-11-17 08:52:05,924 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12318 states and 17326 transitions. [2024-11-17 08:52:05,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:05,925 INFO L425 stractBuchiCegarLoop]: Abstraction has 12318 states and 17326 transitions. [2024-11-17 08:52:05,925 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:52:05,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12318 states and 17326 transitions. [2024-11-17 08:52:05,959 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12112 [2024-11-17 08:52:05,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:05,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:05,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,961 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,961 INFO L745 eck$LassoCheckResult]: Stem: 119903#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 119286#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 119287#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119423#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119424#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 119233#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119234#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119663#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 119664#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119617#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 119618#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119582#L599-1 assume !(0 == ~M_E~0); 119262#L604-1 assume !(0 == ~T1_E~0); 119253#L609-1 assume !(0 == ~T2_E~0); 119254#L614-1 assume !(0 == ~T3_E~0); 119405#L619-1 assume !(0 == ~T4_E~0); 119526#L624-1 assume !(0 == ~T5_E~0); 119666#L629-1 assume !(0 == ~E_M~0); 119354#L634-1 assume !(0 == ~E_1~0); 119355#L639-1 assume !(0 == ~E_2~0); 119770#L644-1 assume !(0 == ~E_3~0); 119783#L649-1 assume !(0 == ~E_4~0); 119313#L654-1 assume !(0 == ~E_5~0); 119314#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119709#L292-8 assume !(1 == ~m_pc~0); 119476#L302-8 is_master_triggered_~__retres1~0#1 := 0; 119477#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119665#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 119413#L743-8 assume !(0 != activate_threads_~tmp~1#1); 119414#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119431#L311-8 assume !(1 == ~t1_pc~0); 119847#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 119899#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119500#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119501#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 119554#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119715#L330-8 assume !(1 == ~t2_pc~0); 119237#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 119238#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119599#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119600#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 119872#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119380#L349-8 assume !(1 == ~t3_pc~0); 119381#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 119415#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119416#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119713#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 119700#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119463#L368-8 assume !(1 == ~t4_pc~0); 119310#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 119309#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119362#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119363#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 119749#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119245#L387-8 assume !(1 == ~t5_pc~0); 119246#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 119540#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119541#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119401#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 119402#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119690#L667-1 assume !(1 == ~M_E~0); 119691#L672-1 assume !(1 == ~T1_E~0); 119511#L677-1 assume !(1 == ~T2_E~0); 119512#L682-1 assume !(1 == ~T3_E~0); 119744#L687-1 assume !(1 == ~T4_E~0); 119818#L692-1 assume !(1 == ~T5_E~0); 119733#L697-1 assume !(1 == ~E_M~0); 119734#L702-1 assume !(1 == ~E_1~0); 119779#L707-1 assume !(1 == ~E_2~0); 119642#L712-1 assume !(1 == ~E_3~0); 119643#L717-1 assume !(1 == ~E_4~0); 119753#L722-1 assume !(1 == ~E_5~0); 119754#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 119860#L928 [2024-11-17 08:52:05,961 INFO L747 eck$LassoCheckResult]: Loop: 119860#L928 assume true; 123549#L928-1 assume !false; 123544#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 123541#L494 assume true; 123539#L494-1 assume !false; 123537#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 123531#L452-2 assume !(0 == ~m_st~0); 123532#L456-2 assume !(0 == ~t1_st~0); 123533#L460-2 assume !(0 == ~t2_st~0); 123534#L464-2 assume !(0 == ~t3_st~0); 123535#L468-2 assume !(0 == ~t4_st~0); 123529#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 123526#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 123523#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 123522#L499 assume !(0 != eval_~tmp~0#1); 123521#L502 assume true; 123520#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123519#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123518#L599 assume !(0 == ~M_E~0); 123517#L604 assume !(0 == ~T1_E~0); 123516#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 123513#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 123510#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123508#L624 assume !(0 == ~T5_E~0); 123506#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 123504#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 123502#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 123499#L644 assume !(0 == ~E_3~0); 123496#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 123493#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 123490#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123488#L292-1 assume 1 == ~m_pc~0; 123485#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 123482#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123479#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123476#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123474#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123472#L311-1 assume !(1 == ~t1_pc~0); 123470#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 123469#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123468#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 123466#L751-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123464#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123462#L330-1 assume !(1 == ~t2_pc~0); 123460#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 123458#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123456#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 123454#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123452#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123450#L349-1 assume !(1 == ~t3_pc~0); 123448#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 123445#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123443#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 123441#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123439#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123437#L368-1 assume 1 == ~t4_pc~0; 123435#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 123431#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123429#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 123426#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 123424#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123422#L387-1 assume !(1 == ~t5_pc~0); 123420#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 123414#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123413#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 123412#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 123411#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123410#L667 assume !(1 == ~M_E~0); 123283#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 123408#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 123407#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123406#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123405#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 123404#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 123403#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 123401#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 123399#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 123397#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 123395#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 123393#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 123386#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 123384#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 123382#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 123379#L947 assume !(0 == start_simulation_~tmp~3#1); 123380#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 123589#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 123583#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 123578#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 123574#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123571#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123567#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 123560#L960 assume !(0 != start_simulation_~tmp___0~1#1); 119860#L928 [2024-11-17 08:52:05,962 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,962 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 3 times [2024-11-17 08:52:05,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4336530] [2024-11-17 08:52:05,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:05,971 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:05,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:05,988 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:05,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,989 INFO L85 PathProgramCache]: Analyzing trace with hash -784558539, now seen corresponding path program 1 times [2024-11-17 08:52:05,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412052669] [2024-11-17 08:52:05,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412052669] [2024-11-17 08:52:06,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412052669] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,052 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,052 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925151355] [2024-11-17 08:52:06,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,054 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,054 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:06,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:06,054 INFO L87 Difference]: Start difference. First operand 12318 states and 17326 transitions. cyclomatic complexity: 5024 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,217 INFO L93 Difference]: Finished difference Result 12606 states and 17533 transitions. [2024-11-17 08:52:06,217 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12606 states and 17533 transitions. [2024-11-17 08:52:06,258 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12400 [2024-11-17 08:52:06,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12606 states to 12606 states and 17533 transitions. [2024-11-17 08:52:06,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12606 [2024-11-17 08:52:06,366 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12606 [2024-11-17 08:52:06,366 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12606 states and 17533 transitions. [2024-11-17 08:52:06,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,370 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12606 states and 17533 transitions. [2024-11-17 08:52:06,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12606 states and 17533 transitions. [2024-11-17 08:52:06,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12606 to 12606. [2024-11-17 08:52:06,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12606 states, 12606 states have (on average 1.3908456290655244) internal successors, (17533), 12605 states have internal predecessors, (17533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12606 states to 12606 states and 17533 transitions. [2024-11-17 08:52:06,471 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12606 states and 17533 transitions. [2024-11-17 08:52:06,472 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:06,472 INFO L425 stractBuchiCegarLoop]: Abstraction has 12606 states and 17533 transitions. [2024-11-17 08:52:06,472 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:52:06,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12606 states and 17533 transitions. [2024-11-17 08:52:06,495 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12400 [2024-11-17 08:52:06,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:06,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:06,496 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,497 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,497 INFO L745 eck$LassoCheckResult]: Stem: 144826#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 144221#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 144222#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 144356#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 144357#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 144165#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 144166#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144594#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144595#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144550#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144551#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 144516#L599-1 assume !(0 == ~M_E~0); 144195#L604-1 assume !(0 == ~T1_E~0); 144186#L609-1 assume !(0 == ~T2_E~0); 144187#L614-1 assume !(0 == ~T3_E~0); 144339#L619-1 assume !(0 == ~T4_E~0); 144464#L624-1 assume !(0 == ~T5_E~0); 144597#L629-1 assume !(0 == ~E_M~0); 144287#L634-1 assume !(0 == ~E_1~0); 144288#L639-1 assume !(0 == ~E_2~0); 144696#L644-1 assume !(0 == ~E_3~0); 144708#L649-1 assume !(0 == ~E_4~0); 144248#L654-1 assume !(0 == ~E_5~0); 144249#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144640#L292-8 assume !(1 == ~m_pc~0); 144410#L302-8 is_master_triggered_~__retres1~0#1 := 0; 144411#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144596#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 144347#L743-8 assume !(0 != activate_threads_~tmp~1#1); 144348#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144364#L311-8 assume !(1 == ~t1_pc~0); 144768#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 144821#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144437#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 144438#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 144491#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144645#L330-8 assume !(1 == ~t2_pc~0); 144169#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 144170#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144533#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144534#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 144794#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144313#L349-8 assume !(1 == ~t3_pc~0); 144314#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 144349#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144350#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144643#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 144630#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144397#L368-8 assume !(1 == ~t4_pc~0); 144245#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 144244#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144295#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144296#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 144677#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144177#L387-8 assume !(1 == ~t5_pc~0); 144178#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 144477#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144478#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 144335#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 144336#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144619#L667-1 assume !(1 == ~M_E~0); 144620#L672-1 assume !(1 == ~T1_E~0); 144448#L677-1 assume !(1 == ~T2_E~0); 144449#L682-1 assume !(1 == ~T3_E~0); 144673#L687-1 assume !(1 == ~T4_E~0); 144742#L692-1 assume !(1 == ~T5_E~0); 144660#L697-1 assume !(1 == ~E_M~0); 144661#L702-1 assume !(1 == ~E_1~0); 144704#L707-1 assume !(1 == ~E_2~0); 144574#L712-1 assume !(1 == ~E_3~0); 144575#L717-1 assume !(1 == ~E_4~0); 144681#L722-1 assume !(1 == ~E_5~0); 144682#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 144783#L928 [2024-11-17 08:52:06,497 INFO L747 eck$LassoCheckResult]: Loop: 144783#L928 assume true; 148258#L928-1 assume !false; 148249#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 148242#L494 assume true; 148235#L494-1 assume !false; 148227#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 148156#L452-2 assume !(0 == ~m_st~0); 148157#L456-2 assume !(0 == ~t1_st~0); 148160#L460-2 assume !(0 == ~t2_st~0); 148161#L464-2 assume !(0 == ~t3_st~0); 148162#L468-2 assume !(0 == ~t4_st~0); 148158#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 148159#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 147459#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 147460#L499 assume !(0 != eval_~tmp~0#1); 148699#L502 assume true; 148692#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 148690#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 148688#L599 assume !(0 == ~M_E~0); 148686#L604 assume !(0 == ~T1_E~0); 148684#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 148682#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 148680#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 148678#L624 assume !(0 == ~T5_E~0); 148676#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 148675#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 148670#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 148668#L644 assume !(0 == ~E_3~0); 148666#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 148664#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 148607#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148543#L292-1 assume 1 == ~m_pc~0; 148535#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 148533#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148531#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 148524#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 148522#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148520#L311-1 assume !(1 == ~t1_pc~0); 148518#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 148515#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148513#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 148511#L751-1 assume !(0 != activate_threads_~tmp___0~0#1); 148509#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148507#L330-1 assume !(1 == ~t2_pc~0); 148505#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 148503#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148501#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 148499#L759-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 148497#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148495#L349-1 assume !(1 == ~t3_pc~0); 148493#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 148491#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148489#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 148487#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 148485#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148483#L368-1 assume !(1 == ~t4_pc~0); 148480#L378-1 is_transmit4_triggered_~__retres1~4#1 := 0; 148478#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 148476#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 148474#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148473#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 148470#L387-1 assume !(1 == ~t5_pc~0); 148468#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 148466#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 148464#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 148462#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 148460#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148458#L667 assume !(1 == ~M_E~0); 148454#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 148452#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 148450#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 148448#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 148445#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 148443#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 148441#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 148439#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 148437#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 148435#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 148433#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 148431#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 148381#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 148372#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 148365#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 148358#L947 assume !(0 == start_simulation_~tmp~3#1); 148353#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 148340#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 148332#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 148322#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 148316#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 148311#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 148304#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 148296#L960 assume !(0 != start_simulation_~tmp___0~1#1); 144783#L928 [2024-11-17 08:52:06,497 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,498 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 4 times [2024-11-17 08:52:06,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686973693] [2024-11-17 08:52:06,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:06,505 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:06,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:06,520 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:06,521 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1072764601, now seen corresponding path program 1 times [2024-11-17 08:52:06,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791251085] [2024-11-17 08:52:06,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1791251085] [2024-11-17 08:52:06,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1791251085] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547027464] [2024-11-17 08:52:06,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,571 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:06,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:06,573 INFO L87 Difference]: Start difference. First operand 12606 states and 17533 transitions. cyclomatic complexity: 4943 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,707 INFO L93 Difference]: Finished difference Result 12894 states and 17740 transitions. [2024-11-17 08:52:06,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12894 states and 17740 transitions. [2024-11-17 08:52:06,745 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12688 [2024-11-17 08:52:06,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12894 states to 12894 states and 17740 transitions. [2024-11-17 08:52:06,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12894 [2024-11-17 08:52:06,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12894 [2024-11-17 08:52:06,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12894 states and 17740 transitions. [2024-11-17 08:52:06,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12894 states and 17740 transitions. [2024-11-17 08:52:06,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12894 states and 17740 transitions. [2024-11-17 08:52:06,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12894 to 12894. [2024-11-17 08:52:07,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12894 states, 12894 states have (on average 1.375833721110594) internal successors, (17740), 12893 states have internal predecessors, (17740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12894 states to 12894 states and 17740 transitions. [2024-11-17 08:52:07,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12894 states and 17740 transitions. [2024-11-17 08:52:07,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:07,026 INFO L425 stractBuchiCegarLoop]: Abstraction has 12894 states and 17740 transitions. [2024-11-17 08:52:07,027 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:52:07,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12894 states and 17740 transitions. [2024-11-17 08:52:07,047 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12688 [2024-11-17 08:52:07,047 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,048 INFO L745 eck$LassoCheckResult]: Stem: 170356#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 169728#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 169729#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169863#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169864#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 169673#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 169674#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 170111#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 170112#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 170065#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 170066#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 170029#L599-1 assume !(0 == ~M_E~0); 169704#L604-1 assume !(0 == ~T1_E~0); 169693#L609-1 assume !(0 == ~T2_E~0); 169694#L614-1 assume !(0 == ~T3_E~0); 169846#L619-1 assume !(0 == ~T4_E~0); 169974#L624-1 assume !(0 == ~T5_E~0); 170114#L629-1 assume !(0 == ~E_M~0); 169796#L634-1 assume !(0 == ~E_1~0); 169797#L639-1 assume !(0 == ~E_2~0); 170221#L644-1 assume !(0 == ~E_3~0); 170232#L649-1 assume !(0 == ~E_4~0); 169754#L654-1 assume !(0 == ~E_5~0); 169755#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 170159#L292-8 assume !(1 == ~m_pc~0); 169921#L302-8 is_master_triggered_~__retres1~0#1 := 0; 169922#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170113#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 169854#L743-8 assume !(0 != activate_threads_~tmp~1#1); 169855#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169873#L311-8 assume !(1 == ~t1_pc~0); 170295#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 170351#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169946#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 169947#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 170002#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170164#L330-8 assume !(1 == ~t2_pc~0); 169677#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 169678#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 170049#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 170050#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 170322#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169820#L349-8 assume !(1 == ~t3_pc~0); 169821#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 169856#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169857#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 170163#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 170148#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169906#L368-8 assume !(1 == ~t4_pc~0); 169751#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 169750#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169805#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 169806#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 170199#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169689#L387-8 assume !(1 == ~t5_pc~0); 169690#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 169987#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169988#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 169842#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 169843#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 170135#L667-1 assume !(1 == ~M_E~0); 170136#L672-1 assume !(1 == ~T1_E~0); 169957#L677-1 assume !(1 == ~T2_E~0); 169958#L682-1 assume !(1 == ~T3_E~0); 170195#L687-1 assume !(1 == ~T4_E~0); 170267#L692-1 assume !(1 == ~T5_E~0); 170182#L697-1 assume !(1 == ~E_M~0); 170183#L702-1 assume !(1 == ~E_1~0); 170228#L707-1 assume !(1 == ~E_2~0); 170088#L712-1 assume !(1 == ~E_3~0); 170089#L717-1 assume !(1 == ~E_4~0); 170204#L722-1 assume !(1 == ~E_5~0); 170205#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 170311#L928 [2024-11-17 08:52:07,048 INFO L747 eck$LassoCheckResult]: Loop: 170311#L928 assume true; 172797#L928-1 assume !false; 172783#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 172780#L494 assume true; 172778#L494-1 assume !false; 172776#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 172774#L452-2 assume !(0 == ~m_st~0); 172772#L456-2 assume !(0 == ~t1_st~0); 172770#L460-2 assume !(0 == ~t2_st~0); 172768#L464-2 assume !(0 == ~t3_st~0); 172764#L468-2 assume !(0 == ~t4_st~0); 172761#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 172759#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 172757#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 172754#L499 assume !(0 != eval_~tmp~0#1); 172752#L502 assume true; 172750#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 172748#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 172746#L599 assume !(0 == ~M_E~0); 172744#L604 assume !(0 == ~T1_E~0); 172742#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 172740#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 172738#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 172736#L624 assume !(0 == ~T5_E~0); 172734#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 172732#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 172730#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 172728#L644 assume !(0 == ~E_3~0); 172726#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 172724#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 172722#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172720#L292-1 assume 1 == ~m_pc~0; 172718#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 172719#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 172846#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 172708#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 172706#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 172704#L311-1 assume !(1 == ~t1_pc~0); 172702#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 172700#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 172698#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 172696#L751-1 assume !(0 != activate_threads_~tmp___0~0#1); 172694#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172692#L330-1 assume !(1 == ~t2_pc~0); 172690#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 172688#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172687#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 172686#L759-1 assume !(0 != activate_threads_~tmp___1~0#1); 172684#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 172682#L349-1 assume !(1 == ~t3_pc~0); 172681#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 172680#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172679#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 172677#L767-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 172674#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 172672#L368-1 assume 1 == ~t4_pc~0; 172670#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 172666#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172664#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 172662#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 172660#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 172658#L387-1 assume !(1 == ~t5_pc~0); 172656#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 172654#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172652#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 172650#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 172648#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172646#L667 assume !(1 == ~M_E~0); 172642#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 172640#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 172638#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 172636#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 172634#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 172632#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 172630#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 172628#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 172626#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 172624#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 172623#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 172622#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 172613#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 172611#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 172609#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 172606#L947 assume !(0 == start_simulation_~tmp~3#1); 172607#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 172813#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 172811#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 172809#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 172807#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 172804#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 172802#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 172800#L960 assume !(0 != start_simulation_~tmp___0~1#1); 170311#L928 [2024-11-17 08:52:07,049 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,049 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 5 times [2024-11-17 08:52:07,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097195400] [2024-11-17 08:52:07,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:07,055 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:07,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:07,064 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:07,065 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,065 INFO L85 PathProgramCache]: Analyzing trace with hash -1352108425, now seen corresponding path program 1 times [2024-11-17 08:52:07,065 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,065 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660939254] [2024-11-17 08:52:07,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,120 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,120 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1660939254] [2024-11-17 08:52:07,120 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1660939254] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,120 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,120 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:07,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320634481] [2024-11-17 08:52:07,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,120 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:07,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:07,121 INFO L87 Difference]: Start difference. First operand 12894 states and 17740 transitions. cyclomatic complexity: 4862 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,261 INFO L93 Difference]: Finished difference Result 13182 states and 17947 transitions. [2024-11-17 08:52:07,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13182 states and 17947 transitions. [2024-11-17 08:52:07,306 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12976 [2024-11-17 08:52:07,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13182 states to 13182 states and 17947 transitions. [2024-11-17 08:52:07,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13182 [2024-11-17 08:52:07,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13182 [2024-11-17 08:52:07,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13182 states and 17947 transitions. [2024-11-17 08:52:07,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13182 states and 17947 transitions. [2024-11-17 08:52:07,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13182 states and 17947 transitions. [2024-11-17 08:52:07,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13182 to 13182. [2024-11-17 08:52:07,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13182 states, 13182 states have (on average 1.3614777727203762) internal successors, (17947), 13181 states have internal predecessors, (17947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13182 states to 13182 states and 17947 transitions. [2024-11-17 08:52:07,446 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13182 states and 17947 transitions. [2024-11-17 08:52:07,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:07,447 INFO L425 stractBuchiCegarLoop]: Abstraction has 13182 states and 17947 transitions. [2024-11-17 08:52:07,447 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:52:07,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13182 states and 17947 transitions. [2024-11-17 08:52:07,582 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12976 [2024-11-17 08:52:07,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,583 INFO L745 eck$LassoCheckResult]: Stem: 196443#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 195811#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 195812#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 195949#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 195950#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 195757#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 195758#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 196194#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 196195#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 196146#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 196147#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 196110#L599-1 assume !(0 == ~M_E~0); 195786#L604-1 assume !(0 == ~T1_E~0); 195777#L609-1 assume !(0 == ~T2_E~0); 195778#L614-1 assume !(0 == ~T3_E~0); 195931#L619-1 assume !(0 == ~T4_E~0); 196054#L624-1 assume !(0 == ~T5_E~0); 196197#L629-1 assume !(0 == ~E_M~0); 195879#L634-1 assume !(0 == ~E_1~0); 195880#L639-1 assume !(0 == ~E_2~0); 196296#L644-1 assume !(0 == ~E_3~0); 196310#L649-1 assume !(0 == ~E_4~0); 195839#L654-1 assume !(0 == ~E_5~0); 195840#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 196238#L292-8 assume !(1 == ~m_pc~0); 196001#L302-8 is_master_triggered_~__retres1~0#1 := 0; 196002#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 196196#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 195940#L743-8 assume !(0 != activate_threads_~tmp~1#1); 195941#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 195957#L311-8 assume !(1 == ~t1_pc~0); 196376#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 196437#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 196025#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 196026#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 196081#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 196243#L330-8 assume !(1 == ~t2_pc~0); 195761#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 195762#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 196129#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 196130#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 196402#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 195905#L349-8 assume !(1 == ~t3_pc~0); 195906#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 195942#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 195943#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 196241#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 196229#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 195988#L368-8 assume !(1 == ~t4_pc~0); 195836#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 195835#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 195887#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 195888#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 196277#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 195769#L387-8 assume !(1 == ~t5_pc~0); 195770#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 196067#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 196068#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 195927#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 195928#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 196218#L667-1 assume !(1 == ~M_E~0); 196219#L672-1 assume !(1 == ~T1_E~0); 196036#L677-1 assume !(1 == ~T2_E~0); 196037#L682-1 assume !(1 == ~T3_E~0); 196272#L687-1 assume !(1 == ~T4_E~0); 196347#L692-1 assume !(1 == ~T5_E~0); 196259#L697-1 assume !(1 == ~E_M~0); 196260#L702-1 assume !(1 == ~E_1~0); 196306#L707-1 assume !(1 == ~E_2~0); 196170#L712-1 assume !(1 == ~E_3~0); 196171#L717-1 assume !(1 == ~E_4~0); 196281#L722-1 assume !(1 == ~E_5~0); 196282#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 196391#L928 [2024-11-17 08:52:07,583 INFO L747 eck$LassoCheckResult]: Loop: 196391#L928 assume true; 199480#L928-1 assume !false; 199475#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 199471#L494 assume true; 199467#L494-1 assume !false; 199463#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 199453#L452-2 assume !(0 == ~m_st~0); 199454#L456-2 assume !(0 == ~t1_st~0); 199457#L460-2 assume !(0 == ~t2_st~0); 199458#L464-2 assume !(0 == ~t3_st~0); 199459#L468-2 assume !(0 == ~t4_st~0); 199455#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 199456#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 198797#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 198798#L499 assume !(0 != eval_~tmp~0#1); 199604#L502 assume true; 199602#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199599#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 199596#L599 assume !(0 == ~M_E~0); 199593#L604 assume !(0 == ~T1_E~0); 199590#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 199588#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 199586#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 199584#L624 assume !(0 == ~T5_E~0); 199582#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 199580#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 199578#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 199576#L644 assume !(0 == ~E_3~0); 199574#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 199572#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 199570#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 199568#L292-1 assume !(1 == ~m_pc~0); 199566#L302-1 is_master_triggered_~__retres1~0#1 := 0; 199563#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 199560#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 199557#L743-1 assume !(0 != activate_threads_~tmp~1#1); 199554#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 199552#L311-1 assume !(1 == ~t1_pc~0); 199549#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 199546#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 199543#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 199539#L751-1 assume !(0 != activate_threads_~tmp___0~0#1); 199536#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199533#L330-1 assume !(1 == ~t2_pc~0); 199530#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 199527#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 199524#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 199521#L759-1 assume !(0 != activate_threads_~tmp___1~0#1); 199518#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 199516#L349-1 assume !(1 == ~t3_pc~0); 199508#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 199503#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199499#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 199496#L767-1 assume !(0 != activate_threads_~tmp___2~0#1); 199493#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 199490#L368-1 assume 1 == ~t4_pc~0; 199487#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 199483#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 199478#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 199473#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 199470#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199466#L387-1 assume !(1 == ~t5_pc~0); 199462#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 199452#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 199449#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 199447#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 199445#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199443#L667 assume !(1 == ~M_E~0); 199089#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 199440#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 199438#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 199436#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 199433#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 199428#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 199423#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 199418#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 199413#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 199409#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 199405#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 199402#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 199378#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 199373#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 199368#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 199362#L947 assume !(0 == start_simulation_~tmp~3#1); 199363#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 199509#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 199504#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 199500#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 199497#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 199494#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 199491#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 199488#L960 assume !(0 != start_simulation_~tmp___0~1#1); 196391#L928 [2024-11-17 08:52:07,584 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,584 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 6 times [2024-11-17 08:52:07,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456623118] [2024-11-17 08:52:07,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:07,591 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:07,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:07,603 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:07,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1282113660, now seen corresponding path program 1 times [2024-11-17 08:52:07,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609770186] [2024-11-17 08:52:07,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609770186] [2024-11-17 08:52:07,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [609770186] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:07,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848895960] [2024-11-17 08:52:07,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,628 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:07,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:07,629 INFO L87 Difference]: Start difference. First operand 13182 states and 17947 transitions. cyclomatic complexity: 4781 Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,690 INFO L93 Difference]: Finished difference Result 24270 states and 32507 transitions. [2024-11-17 08:52:07,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24270 states and 32507 transitions. [2024-11-17 08:52:07,762 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23936 [2024-11-17 08:52:07,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24270 states to 24270 states and 32507 transitions. [2024-11-17 08:52:07,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24270 [2024-11-17 08:52:07,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24270 [2024-11-17 08:52:07,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24270 states and 32507 transitions. [2024-11-17 08:52:07,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,843 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24270 states and 32507 transitions. [2024-11-17 08:52:07,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24270 states and 32507 transitions. [2024-11-17 08:52:07,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24270 to 23006. [2024-11-17 08:52:08,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23006 states, 23006 states have (on average 1.3448230896287925) internal successors, (30939), 23005 states have internal predecessors, (30939), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23006 states to 23006 states and 30939 transitions. [2024-11-17 08:52:08,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23006 states and 30939 transitions. [2024-11-17 08:52:08,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,235 INFO L425 stractBuchiCegarLoop]: Abstraction has 23006 states and 30939 transitions. [2024-11-17 08:52:08,235 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:52:08,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23006 states and 30939 transitions. [2024-11-17 08:52:08,291 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22672 [2024-11-17 08:52:08,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,292 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,292 INFO L745 eck$LassoCheckResult]: Stem: 233916#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 233270#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 233271#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 233406#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 233407#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 233215#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 233216#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 233646#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 233647#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 233602#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 233603#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 233570#L599-1 assume !(0 == ~M_E~0); 233245#L604-1 assume !(0 == ~T1_E~0); 233236#L609-1 assume !(0 == ~T2_E~0); 233237#L614-1 assume !(0 == ~T3_E~0); 233389#L619-1 assume !(0 == ~T4_E~0); 233514#L624-1 assume !(0 == ~T5_E~0); 233649#L629-1 assume !(0 == ~E_M~0); 233338#L634-1 assume !(0 == ~E_1~0); 233339#L639-1 assume !(0 == ~E_2~0); 233759#L644-1 assume !(0 == ~E_3~0); 233773#L649-1 assume !(0 == ~E_4~0); 233296#L654-1 assume !(0 == ~E_5~0); 233297#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233694#L292-8 assume !(1 == ~m_pc~0); 233463#L302-8 is_master_triggered_~__retres1~0#1 := 0; 233464#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233648#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 233397#L743-8 assume !(0 != activate_threads_~tmp~1#1); 233398#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233416#L311-8 assume !(1 == ~t1_pc~0); 233843#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 233913#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233487#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 233488#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 233542#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 233700#L330-8 assume !(1 == ~t2_pc~0); 233219#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 233220#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 233587#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 233588#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 233875#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233362#L349-8 assume !(1 == ~t3_pc~0); 233363#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 233399#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 233400#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 233698#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 233685#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 233449#L368-8 assume !(1 == ~t4_pc~0); 233293#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 233292#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 233347#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 233348#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 233736#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 233232#L387-8 assume !(1 == ~t5_pc~0); 233233#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 233528#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 233529#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 233385#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 233386#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 233673#L667-1 assume !(1 == ~M_E~0); 233674#L672-1 assume !(1 == ~T1_E~0); 233499#L677-1 assume !(1 == ~T2_E~0); 233500#L682-1 assume !(1 == ~T3_E~0); 233731#L687-1 assume !(1 == ~T4_E~0); 233812#L692-1 assume !(1 == ~T5_E~0); 233716#L697-1 assume !(1 == ~E_M~0); 233717#L702-1 assume !(1 == ~E_1~0); 233768#L707-1 assume !(1 == ~E_2~0); 233623#L712-1 assume !(1 == ~E_3~0); 233624#L717-1 assume !(1 == ~E_4~0); 233740#L722-1 assume !(1 == ~E_5~0); 233741#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 233864#L928 [2024-11-17 08:52:08,293 INFO L747 eck$LassoCheckResult]: Loop: 233864#L928 assume true; 236695#L928-1 assume !false; 236686#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 236678#L494 assume true; 236672#L494-1 assume !false; 236666#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 236653#L452-2 assume !(0 == ~m_st~0); 236654#L456-2 assume !(0 == ~t1_st~0); 237134#L460-2 assume !(0 == ~t2_st~0); 237132#L464-2 assume !(0 == ~t3_st~0); 237130#L468-2 assume !(0 == ~t4_st~0); 237127#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 237125#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 237123#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 237120#L499 assume !(0 != eval_~tmp~0#1); 237118#L502 assume true; 237116#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 237114#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 237112#L599 assume !(0 == ~M_E~0); 237109#L604 assume !(0 == ~T1_E~0); 237107#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 237105#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 237103#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 237101#L624 assume !(0 == ~T5_E~0); 237099#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 237097#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 237095#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 237093#L644 assume !(0 == ~E_3~0); 237091#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 237089#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 237087#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 237085#L292-1 assume 1 == ~m_pc~0; 237082#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 237080#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 237077#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 237074#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 237072#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 237069#L311-1 assume !(1 == ~t1_pc~0); 237067#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 237065#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 237063#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 237061#L751-1 assume !(0 != activate_threads_~tmp___0~0#1); 237059#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 237057#L330-1 assume !(1 == ~t2_pc~0); 237055#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 237053#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237051#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 237049#L759-1 assume !(0 != activate_threads_~tmp___1~0#1); 237047#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 237045#L349-1 assume !(1 == ~t3_pc~0); 237043#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 237041#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237039#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 237037#L767-1 assume !(0 != activate_threads_~tmp___2~0#1); 237035#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237032#L368-1 assume 1 == ~t4_pc~0; 237030#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 237027#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 237024#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 237022#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 237020#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 237018#L387-1 assume !(1 == ~t5_pc~0); 237016#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 237014#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 237012#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 237010#L783-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 237008#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 237006#L667 assume !(1 == ~M_E~0); 236931#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 237003#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 237001#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 236999#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 236997#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 236995#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 236993#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 236991#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 236971#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 236953#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 236947#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 236880#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 236874#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 236771#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 236763#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 236759#L947 assume !(0 == start_simulation_~tmp~3#1); 236756#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 236752#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 236750#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 236748#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 236746#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 236723#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 236718#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 236710#L960 assume !(0 != start_simulation_~tmp___0~1#1); 233864#L928 [2024-11-17 08:52:08,293 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,293 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 7 times [2024-11-17 08:52:08,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484210851] [2024-11-17 08:52:08,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:08,301 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:08,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:08,312 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:08,313 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,313 INFO L85 PathProgramCache]: Analyzing trace with hash 2020175288, now seen corresponding path program 1 times [2024-11-17 08:52:08,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55529355] [2024-11-17 08:52:08,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,366 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55529355] [2024-11-17 08:52:08,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55529355] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604240395] [2024-11-17 08:52:08,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,366 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:08,367 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:08,367 INFO L87 Difference]: Start difference. First operand 23006 states and 30939 transitions. cyclomatic complexity: 7949 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,613 INFO L93 Difference]: Finished difference Result 23534 states and 31322 transitions. [2024-11-17 08:52:08,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23534 states and 31322 transitions. [2024-11-17 08:52:08,669 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23200 [2024-11-17 08:52:08,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23534 states to 23534 states and 31322 transitions. [2024-11-17 08:52:08,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23534 [2024-11-17 08:52:08,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23534 [2024-11-17 08:52:08,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23534 states and 31322 transitions. [2024-11-17 08:52:08,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,730 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23534 states and 31322 transitions. [2024-11-17 08:52:08,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23534 states and 31322 transitions. [2024-11-17 08:52:08,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23534 to 23534. [2024-11-17 08:52:08,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23534 states, 23534 states have (on average 1.330925469533441) internal successors, (31322), 23533 states have internal predecessors, (31322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23534 states to 23534 states and 31322 transitions. [2024-11-17 08:52:08,955 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23534 states and 31322 transitions. [2024-11-17 08:52:08,956 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:08,956 INFO L425 stractBuchiCegarLoop]: Abstraction has 23534 states and 31322 transitions. [2024-11-17 08:52:08,956 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:52:08,956 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23534 states and 31322 transitions. [2024-11-17 08:52:09,064 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23200 [2024-11-17 08:52:09,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:09,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:09,065 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,065 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,065 INFO L745 eck$LassoCheckResult]: Stem: 280466#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 279818#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 279819#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 279955#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 279956#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 279765#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 279766#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 280201#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 280202#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 280151#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 280152#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 280117#L599-1 assume !(0 == ~M_E~0); 279795#L604-1 assume !(0 == ~T1_E~0); 279784#L609-1 assume !(0 == ~T2_E~0); 279785#L614-1 assume !(0 == ~T3_E~0); 279938#L619-1 assume !(0 == ~T4_E~0); 280062#L624-1 assume !(0 == ~T5_E~0); 280206#L629-1 assume !(0 == ~E_M~0); 279888#L634-1 assume !(0 == ~E_1~0); 279889#L639-1 assume !(0 == ~E_2~0); 280316#L644-1 assume !(0 == ~E_3~0); 280327#L649-1 assume !(0 == ~E_4~0); 279844#L654-1 assume !(0 == ~E_5~0); 279845#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 280246#L292-8 assume !(1 == ~m_pc~0); 280010#L302-8 is_master_triggered_~__retres1~0#1 := 0; 280011#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 280203#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 279946#L743-8 assume !(0 != activate_threads_~tmp~1#1); 279947#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 279965#L311-8 assume !(1 == ~t1_pc~0); 280401#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 280462#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 280034#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 280035#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 280089#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 280251#L330-8 assume !(1 == ~t2_pc~0); 279767#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 279768#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 280135#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 280136#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 280429#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 279912#L349-8 assume !(1 == ~t3_pc~0); 279913#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 279948#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 279949#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 280250#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 280238#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 279996#L368-8 assume !(1 == ~t4_pc~0); 279841#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 279840#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279897#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 279898#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 280294#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 279780#L387-8 assume !(1 == ~t5_pc~0); 279781#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 280075#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 280076#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 279934#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 279935#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280228#L667-1 assume !(1 == ~M_E~0); 280229#L672-1 assume !(1 == ~T1_E~0); 280045#L677-1 assume !(1 == ~T2_E~0); 280046#L682-1 assume !(1 == ~T3_E~0); 280290#L687-1 assume !(1 == ~T4_E~0); 280367#L692-1 assume !(1 == ~T5_E~0); 280274#L697-1 assume !(1 == ~E_M~0); 280275#L702-1 assume !(1 == ~E_1~0); 280323#L707-1 assume !(1 == ~E_2~0); 280177#L712-1 assume !(1 == ~E_3~0); 280178#L717-1 assume !(1 == ~E_4~0); 280298#L722-1 assume !(1 == ~E_5~0); 280299#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 280418#L928 [2024-11-17 08:52:09,065 INFO L747 eck$LassoCheckResult]: Loop: 280418#L928 assume true; 293315#L928-1 assume !false; 293300#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 293293#L494 assume true; 293287#L494-1 assume !false; 293265#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 293261#L452-2 assume !(0 == ~m_st~0); 286481#L456-2 assume !(0 == ~t1_st~0); 286479#L460-2 assume !(0 == ~t2_st~0); 286477#L464-2 assume !(0 == ~t3_st~0); 286475#L468-2 assume !(0 == ~t4_st~0); 286472#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 286470#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 286468#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 286466#L499 assume !(0 != eval_~tmp~0#1); 286465#L502 assume true; 286464#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 286459#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 286457#L599 assume !(0 == ~M_E~0); 286455#L604 assume !(0 == ~T1_E~0); 286452#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 286450#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 286448#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 286447#L624 assume !(0 == ~T5_E~0); 286446#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 286445#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 286440#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 286438#L644 assume !(0 == ~E_3~0); 286436#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 286434#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 286432#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286430#L292-1 assume 1 == ~m_pc~0; 286427#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 286425#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 286423#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 286421#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 286418#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 286416#L311-1 assume !(1 == ~t1_pc~0); 286414#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 286411#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 286409#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 286407#L751-1 assume !(0 != activate_threads_~tmp___0~0#1); 286406#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 286405#L330-1 assume !(1 == ~t2_pc~0); 286403#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 286401#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 286400#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 286399#L759-1 assume !(0 != activate_threads_~tmp___1~0#1); 286398#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 286397#L349-1 assume !(1 == ~t3_pc~0); 286395#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 286393#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 286391#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 286390#L767-1 assume !(0 != activate_threads_~tmp___2~0#1); 286388#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 286386#L368-1 assume !(1 == ~t4_pc~0); 286382#L378-1 is_transmit4_triggered_~__retres1~4#1 := 0; 286380#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 286378#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 286376#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 286374#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 286372#L387-1 assume !(1 == ~t5_pc~0); 286370#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 286368#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 286366#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 286364#L783-1 assume !(0 != activate_threads_~tmp___4~0#1); 286362#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 286360#L667 assume !(1 == ~M_E~0); 286177#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 286357#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 286355#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 286353#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 286350#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 286348#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 286346#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 286344#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 286342#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 286340#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 286338#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 286336#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 286333#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 286331#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 286329#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 286326#L947 assume !(0 == start_simulation_~tmp~3#1); 286327#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 293331#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 293329#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 293327#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 293325#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 293323#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 293321#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 293319#L960 assume !(0 != start_simulation_~tmp___0~1#1); 280418#L928 [2024-11-17 08:52:09,066 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,066 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 8 times [2024-11-17 08:52:09,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430044645] [2024-11-17 08:52:09,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:09,073 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:09,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:09,083 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:09,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,085 INFO L85 PathProgramCache]: Analyzing trace with hash -589045444, now seen corresponding path program 1 times [2024-11-17 08:52:09,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [419116029] [2024-11-17 08:52:09,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,138 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [419116029] [2024-11-17 08:52:09,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [419116029] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:09,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563193156] [2024-11-17 08:52:09,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,139 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:09,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:09,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:09,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:09,140 INFO L87 Difference]: Start difference. First operand 23534 states and 31322 transitions. cyclomatic complexity: 7804 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:09,297 INFO L93 Difference]: Finished difference Result 24497 states and 32285 transitions. [2024-11-17 08:52:09,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24497 states and 32285 transitions. [2024-11-17 08:52:09,364 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24160 [2024-11-17 08:52:09,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24497 states to 24497 states and 32285 transitions. [2024-11-17 08:52:09,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24497 [2024-11-17 08:52:09,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24497 [2024-11-17 08:52:09,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24497 states and 32285 transitions. [2024-11-17 08:52:09,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:09,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24497 states and 32285 transitions. [2024-11-17 08:52:09,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24497 states and 32285 transitions. [2024-11-17 08:52:09,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24497 to 24497. [2024-11-17 08:52:09,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24497 states, 24497 states have (on average 1.3179164795689269) internal successors, (32285), 24496 states have internal predecessors, (32285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24497 states to 24497 states and 32285 transitions. [2024-11-17 08:52:09,763 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24497 states and 32285 transitions. [2024-11-17 08:52:09,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:09,764 INFO L425 stractBuchiCegarLoop]: Abstraction has 24497 states and 32285 transitions. [2024-11-17 08:52:09,764 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:52:09,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24497 states and 32285 transitions. [2024-11-17 08:52:09,814 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24160 [2024-11-17 08:52:09,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:09,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:09,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,817 INFO L745 eck$LassoCheckResult]: Stem: 328483#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 327856#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 327857#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 327990#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 327991#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 327802#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 327803#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 328232#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 328233#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 328184#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 328185#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 328148#L599-1 assume !(0 == ~M_E~0); 327832#L604-1 assume !(0 == ~T1_E~0); 327823#L609-1 assume !(0 == ~T2_E~0); 327824#L614-1 assume !(0 == ~T3_E~0); 327973#L619-1 assume !(0 == ~T4_E~0); 328094#L624-1 assume !(0 == ~T5_E~0); 328234#L629-1 assume !(0 == ~E_M~0); 327922#L634-1 assume !(0 == ~E_1~0); 327923#L639-1 assume !(0 == ~E_2~0); 328339#L644-1 assume !(0 == ~E_3~0); 328350#L649-1 assume !(0 == ~E_4~0); 327883#L654-1 assume !(0 == ~E_5~0); 327884#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 328278#L292-8 assume !(1 == ~m_pc~0); 328042#L302-8 is_master_triggered_~__retres1~0#1 := 0; 328043#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 328131#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 327982#L743-8 assume !(0 != activate_threads_~tmp~1#1); 327983#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 327998#L311-8 assume !(1 == ~t1_pc~0); 328422#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 328478#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 328066#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 328067#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 328121#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 328283#L330-8 assume !(1 == ~t2_pc~0); 327806#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 327807#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328165#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 328166#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 328445#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 327948#L349-8 assume !(1 == ~t3_pc~0); 327949#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 327984#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 327985#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 328281#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 328269#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 328028#L368-8 assume !(1 == ~t4_pc~0); 327880#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 328417#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 328418#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 328318#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 328319#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 327814#L387-8 assume !(1 == ~t5_pc~0); 327815#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 328107#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 328108#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 327969#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 327970#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 328259#L667-1 assume !(1 == ~M_E~0); 328260#L672-1 assume !(1 == ~T1_E~0); 328078#L677-1 assume !(1 == ~T2_E~0); 328079#L682-1 assume !(1 == ~T3_E~0); 328313#L687-1 assume !(1 == ~T4_E~0); 328386#L692-1 assume !(1 == ~T5_E~0); 328300#L697-1 assume !(1 == ~E_M~0); 328301#L702-1 assume !(1 == ~E_1~0); 328346#L707-1 assume !(1 == ~E_2~0); 328210#L712-1 assume !(1 == ~E_3~0); 328211#L717-1 assume !(1 == ~E_4~0); 328323#L722-1 assume !(1 == ~E_5~0); 328324#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 328438#L928 [2024-11-17 08:52:09,817 INFO L747 eck$LassoCheckResult]: Loop: 328438#L928 assume true; 333191#L928-1 assume !false; 333137#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 333134#L494 assume true; 333132#L494-1 assume !false; 333128#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 333125#L452-2 assume !(0 == ~m_st~0); 333126#L456-2 assume !(0 == ~t1_st~0); 333376#L460-2 assume !(0 == ~t2_st~0); 333373#L464-2 assume !(0 == ~t3_st~0); 333371#L468-2 assume !(0 == ~t4_st~0); 333368#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 333366#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 333364#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 333362#L499 assume !(0 != eval_~tmp~0#1); 333360#L502 assume true; 333358#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 333356#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 333354#L599 assume !(0 == ~M_E~0); 333352#L604 assume !(0 == ~T1_E~0); 333350#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 333348#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 333346#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 333344#L624 assume !(0 == ~T5_E~0); 333342#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 333340#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 333338#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 333336#L644 assume !(0 == ~E_3~0); 333334#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 333330#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 333328#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 333326#L292-1 assume 1 == ~m_pc~0; 333323#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 333320#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 333318#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 333315#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 333313#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 333311#L311-1 assume !(1 == ~t1_pc~0); 333309#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 333307#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 333305#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 333304#L751-1 assume !(0 != activate_threads_~tmp___0~0#1); 333303#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 333301#L330-1 assume !(1 == ~t2_pc~0); 333299#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 333298#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 333297#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 333295#L759-1 assume !(0 != activate_threads_~tmp___1~0#1); 333292#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 333290#L349-1 assume !(1 == ~t3_pc~0); 333288#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 333287#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 333286#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 333284#L767-1 assume !(0 != activate_threads_~tmp___2~0#1); 333283#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 333282#L368-1 assume 1 == ~t4_pc~0; 333280#L369-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 333281#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 333285#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 333271#L775-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 333268#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 333266#L387-1 assume !(1 == ~t5_pc~0); 333264#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 333261#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 333259#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 333257#L783-1 assume !(0 != activate_threads_~tmp___4~0#1); 333252#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 333250#L667 assume !(1 == ~M_E~0); 333246#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 333244#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 333242#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 333240#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 333238#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 333236#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 333234#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 333232#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 333230#L712 assume 1 == ~E_3~0;~E_3~0 := 2; 333228#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 333226#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 333224#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 333221#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 333219#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 333217#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 333214#L947 assume !(0 == start_simulation_~tmp~3#1); 333211#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 333208#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 333206#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 333203#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 333201#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 333199#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 333196#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 333194#L960 assume !(0 != start_simulation_~tmp___0~1#1); 328438#L928 [2024-11-17 08:52:09,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,817 INFO L85 PathProgramCache]: Analyzing trace with hash -868621129, now seen corresponding path program 9 times [2024-11-17 08:52:09,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457717906] [2024-11-17 08:52:09,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:09,824 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:09,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:09,834 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:09,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,835 INFO L85 PathProgramCache]: Analyzing trace with hash -1313177991, now seen corresponding path program 1 times [2024-11-17 08:52:09,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978768625] [2024-11-17 08:52:09,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:09,843 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:09,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:09,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:09,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,853 INFO L85 PathProgramCache]: Analyzing trace with hash -55957969, now seen corresponding path program 1 times [2024-11-17 08:52:09,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765895604] [2024-11-17 08:52:09,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765895604] [2024-11-17 08:52:09,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765895604] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:09,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1472696452] [2024-11-17 08:52:09,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:10,942 INFO L204 LassoAnalysis]: Preferences: [2024-11-17 08:52:10,943 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-17 08:52:10,943 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-17 08:52:10,943 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-17 08:52:10,943 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-17 08:52:10,943 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:10,943 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-17 08:52:10,943 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-17 08:52:10,943 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-1.c_Iteration20_Loop [2024-11-17 08:52:10,944 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-17 08:52:10,944 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-17 08:52:10,966 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,971 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,979 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,981 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,992 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,995 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:10,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,000 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,002 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,006 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,009 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,011 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,014 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,019 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,021 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,022 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,027 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,031 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,036 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,038 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,042 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,044 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,048 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,050 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,051 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,053 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,055 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,056 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,062 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,064 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,067 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,073 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,075 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,077 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,082 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,084 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,086 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,089 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,091 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,092 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,094 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,095 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,097 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,098 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,100 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,102 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,103 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,105 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,109 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,112 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,114 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,115 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,117 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,119 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,440 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-17 08:52:11,440 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-17 08:52:11,442 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:11,442 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:11,444 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:11,446 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-17 08:52:11,447 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-17 08:52:11,447 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-17 08:52:11,461 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-17 08:52:11,462 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-17 08:52:11,472 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2024-11-17 08:52:11,472 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:11,473 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:11,474 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:11,475 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-17 08:52:11,505 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-17 08:52:11,505 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-17 08:52:11,516 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-17 08:52:11,516 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-17 08:52:11,528 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-17 08:52:11,529 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:11,529 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:11,530 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:11,531 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-17 08:52:11,532 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-17 08:52:11,532 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-17 08:52:11,547 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-17 08:52:11,547 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-17 08:52:11,560 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-17 08:52:11,560 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:11,560 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:11,561 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:11,562 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-17 08:52:11,563 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-17 08:52:11,564 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-17 08:52:11,598 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-17 08:52:11,599 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:11,599 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:11,600 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:11,601 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-17 08:52:11,603 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-17 08:52:11,604 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-17 08:52:11,616 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-17 08:52:11,626 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-11-17 08:52:11,627 INFO L204 LassoAnalysis]: Preferences: [2024-11-17 08:52:11,627 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-17 08:52:11,627 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-17 08:52:11,627 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-17 08:52:11,627 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-17 08:52:11,627 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:11,627 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-17 08:52:11,627 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-17 08:52:11,627 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-1.c_Iteration20_Loop [2024-11-17 08:52:11,627 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-17 08:52:11,627 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-17 08:52:11,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,633 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,642 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,651 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,658 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,660 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,664 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,666 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,682 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,737 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,751 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,754 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,759 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,770 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,772 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:11,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-17 08:52:12,075 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-17 08:52:12,078 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-17 08:52:12,079 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:12,079 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:12,080 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:12,081 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-17 08:52:12,083 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-17 08:52:12,093 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-17 08:52:12,093 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-17 08:52:12,093 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-17 08:52:12,094 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-17 08:52:12,094 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-17 08:52:12,095 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-17 08:52:12,095 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-17 08:52:12,096 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-17 08:52:12,106 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-17 08:52:12,107 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:12,107 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:12,108 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:12,108 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-17 08:52:12,109 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-17 08:52:12,118 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-17 08:52:12,118 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-17 08:52:12,119 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-17 08:52:12,119 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-17 08:52:12,119 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-17 08:52:12,119 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-17 08:52:12,119 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-17 08:52:12,120 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-17 08:52:12,130 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2024-11-17 08:52:12,130 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:12,130 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:12,131 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:12,132 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-17 08:52:12,133 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-17 08:52:12,142 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-17 08:52:12,142 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-17 08:52:12,142 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-17 08:52:12,142 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-17 08:52:12,142 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-17 08:52:12,143 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-17 08:52:12,143 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-17 08:52:12,144 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-17 08:52:12,153 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-11-17 08:52:12,154 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:12,154 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:12,155 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:12,156 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-17 08:52:12,157 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-17 08:52:12,166 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-17 08:52:12,167 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-17 08:52:12,167 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-17 08:52:12,167 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-17 08:52:12,167 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-17 08:52:12,167 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-17 08:52:12,167 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-17 08:52:12,169 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-17 08:52:12,171 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-17 08:52:12,171 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-17 08:52:12,172 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:12,172 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:12,195 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:12,197 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-17 08:52:12,197 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-17 08:52:12,198 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-17 08:52:12,198 INFO L474 LassoAnalysis]: Proved termination. [2024-11-17 08:52:12,198 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -2*~E_3~0 + 3 Supporting invariants [] [2024-11-17 08:52:12,208 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-11-17 08:52:12,210 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-17 08:52:12,235 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:12,276 INFO L255 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-17 08:52:12,277 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-17 08:52:12,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:12,385 INFO L255 TraceCheckSpWp]: Trace formula consists of 206 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-17 08:52:12,386 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-17 08:52:12,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:12,568 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-17 08:52:12,570 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 24497 states and 32285 transitions. cyclomatic complexity: 7804 Second operand has 4 states, 4 states have (on average 41.25) internal successors, (165), 4 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,878 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 24497 states and 32285 transitions. cyclomatic complexity: 7804. Second operand has 4 states, 4 states have (on average 41.25) internal successors, (165), 4 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 59203 states and 78664 transitions. Complement of second has 5 states. [2024-11-17 08:52:12,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-17 08:52:12,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 41.25) internal successors, (165), 4 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 767 transitions. [2024-11-17 08:52:12,882 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 767 transitions. Stem has 73 letters. Loop has 92 letters. [2024-11-17 08:52:12,888 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-17 08:52:12,888 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 767 transitions. Stem has 165 letters. Loop has 92 letters. [2024-11-17 08:52:12,889 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-17 08:52:12,889 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 767 transitions. Stem has 73 letters. Loop has 184 letters. [2024-11-17 08:52:12,894 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-17 08:52:12,895 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59203 states and 78664 transitions. [2024-11-17 08:52:13,153 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-17 08:52:13,260 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 35760 [2024-11-17 08:52:13,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59203 states to 59171 states and 78632 transitions. [2024-11-17 08:52:13,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36226 [2024-11-17 08:52:13,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36387 [2024-11-17 08:52:13,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59171 states and 78632 transitions. [2024-11-17 08:52:13,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-17 08:52:13,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59171 states and 78632 transitions. [2024-11-17 08:52:13,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59171 states and 78632 transitions. [2024-11-17 08:52:13,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59171 to 58914. [2024-11-17 08:52:13,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58914 states, 58914 states have (on average 1.3270699663916896) internal successors, (78183), 58913 states have internal predecessors, (78183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:14,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58914 states to 58914 states and 78183 transitions. [2024-11-17 08:52:14,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58914 states and 78183 transitions. [2024-11-17 08:52:14,040 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:14,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:14,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:14,041 INFO L87 Difference]: Start difference. First operand 58914 states and 78183 transitions. Second operand has 3 states, 3 states have (on average 55.0) internal successors, (165), 3 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:14,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:14,432 INFO L93 Difference]: Finished difference Result 62466 states and 82159 transitions. [2024-11-17 08:52:14,432 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62466 states and 82159 transitions. [2024-11-17 08:52:14,617 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 37904 [2024-11-17 08:52:14,913 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62466 states to 62466 states and 82159 transitions. [2024-11-17 08:52:14,916 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38338 [2024-11-17 08:52:14,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38338 [2024-11-17 08:52:14,934 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62466 states and 82159 transitions. [2024-11-17 08:52:14,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-17 08:52:14,938 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62466 states and 82159 transitions. [2024-11-17 08:52:14,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62466 states and 82159 transitions. [2024-11-17 08:52:15,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62466 to 58914. [2024-11-17 08:52:15,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58914 states, 58914 states have (on average 1.3216383202634348) internal successors, (77863), 58913 states have internal predecessors, (77863), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:15,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58914 states to 58914 states and 77863 transitions. [2024-11-17 08:52:15,540 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58914 states and 77863 transitions. [2024-11-17 08:52:15,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:15,541 INFO L425 stractBuchiCegarLoop]: Abstraction has 58914 states and 77863 transitions. [2024-11-17 08:52:15,541 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:52:15,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58914 states and 77863 transitions. [2024-11-17 08:52:15,810 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 35760 [2024-11-17 08:52:15,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:15,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:15,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:15,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:15,816 INFO L745 eck$LassoCheckResult]: Stem: 534712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 533494#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 533495#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 533733#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 533734#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 533398#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 533399#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 534186#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 534187#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 534097#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 534098#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 534033#L599-1 assume !(0 == ~M_E~0); 533450#L604-1 assume !(0 == ~T1_E~0); 533433#L609-1 assume !(0 == ~T2_E~0); 533434#L614-1 assume !(0 == ~T3_E~0); 533706#L619-1 assume !(0 == ~T4_E~0); 533926#L624-1 assume !(0 == ~T5_E~0); 534189#L629-1 assume !(0 == ~E_M~0); 533622#L634-1 assume !(0 == ~E_1~0); 533623#L639-1 assume !(0 == ~E_2~0); 534395#L644-1 assume !(0 == ~E_3~0); 534417#L649-1 assume !(0 == ~E_4~0); 533541#L654-1 assume !(0 == ~E_5~0); 533542#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 534271#L292-8 assume !(1 == ~m_pc~0); 533840#L302-8 is_master_triggered_~__retres1~0#1 := 0; 533841#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 534188#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 533721#L743-8 assume !(0 != activate_threads_~tmp~1#1); 533722#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 533750#L311-8 assume !(1 == ~t1_pc~0); 534572#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 534708#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 533883#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 533884#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 533977#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 534281#L330-8 assume !(1 == ~t2_pc~0); 533404#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 533405#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 534071#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 534072#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 534625#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 533663#L349-8 assume !(1 == ~t3_pc~0); 533664#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 533723#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 533724#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 534278#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 534254#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 533813#L368-8 assume !(1 == ~t4_pc~0); 533536#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 534571#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 534722#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 534354#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 534355#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 533427#L387-8 assume !(1 == ~t5_pc~0); 533428#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 533949#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 533950#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 533700#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 533701#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 534235#L667-1 assume !(1 == ~M_E~0); 534236#L672-1 assume !(1 == ~T1_E~0); 533899#L677-1 assume !(1 == ~T2_E~0); 533900#L682-1 assume !(1 == ~T3_E~0); 534346#L687-1 assume !(1 == ~T4_E~0); 534501#L692-1 assume !(1 == ~T5_E~0); 534323#L697-1 assume !(1 == ~E_M~0); 534324#L702-1 assume !(1 == ~E_1~0); 534410#L707-1 assume !(1 == ~E_2~0); 534141#L712-1 assume !(1 == ~E_3~0); 534142#L717-1 assume !(1 == ~E_4~0); 534361#L722-1 assume !(1 == ~E_5~0); 534362#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 534610#L928 assume true; 538644#L928-1 [2024-11-17 08:52:15,820 INFO L747 eck$LassoCheckResult]: Loop: 538644#L928-1 assume !false; 559530#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 557273#L494 assume true; 559410#L494-1 assume !false; 559408#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 559406#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 557307#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 557303#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 557301#L499 assume 0 != eval_~tmp~0#1; 557299#L504-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 557296#L507 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 557297#L68 assume 0 == ~m_pc~0; 567773#L69 assume true; 568944#L79 assume true; 568943#L79-1 assume !false; 568942#master_while_0_continue#1 assume true;havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 568941#L292-7 assume 1 == ~m_pc~0; 568937#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 567643#L295-7 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567644#L304-7 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 568936#L743-7 assume !(0 != activate_threads_~tmp~1#1); 568934#L749-7 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 568933#L311-7 assume !(1 == ~t1_pc~0); 568932#L321-7 is_transmit1_triggered_~__retres1~1#1 := 0; 568931#L314-7 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 568930#L323-7 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 568929#L751-7 assume !(0 != activate_threads_~tmp___0~0#1); 568928#L757-7 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 568927#L330-7 assume !(1 == ~t2_pc~0); 568926#L340-7 is_transmit2_triggered_~__retres1~2#1 := 0; 568925#L333-7 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 568924#L342-7 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 568923#L759-7 assume !(0 != activate_threads_~tmp___1~0#1); 568922#L765-7 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 568921#L349-7 assume !(1 == ~t3_pc~0); 568920#L359-7 is_transmit3_triggered_~__retres1~3#1 := 0; 568919#L352-7 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 568918#L361-7 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 568917#L767-7 assume !(0 != activate_threads_~tmp___2~0#1); 568916#L773-7 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 568915#L368-7 assume 1 == ~t4_pc~0; 568913#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 568912#L371-7 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 568911#L380-7 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 568910#L775-7 assume !(0 != activate_threads_~tmp___3~0#1); 568908#L781-7 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 568907#L387-7 assume !(1 == ~t5_pc~0); 568906#L397-7 is_transmit5_triggered_~__retres1~5#1 := 0; 568905#L390-7 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 568904#L399-7 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 568903#L783-7 assume !(0 != activate_threads_~tmp___4~0#1); 568901#L789-7 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 559269#L800-5 assume true;assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 559266#L91 assume true; 559263#L105 assume true;havoc master_#t~nondet4#1;assume { :end_inline_master } true; 559260#L504 havoc eval_~tmp_ndt_1~0#1; 559257#L518-1 assume !(0 == ~t1_st~0); 559254#L532-1 assume !(0 == ~t2_st~0); 559250#L546-1 assume !(0 == ~t3_st~0); 559247#L560-1 assume !(0 == ~t4_st~0); 559248#L574-1 assume !(0 == ~t5_st~0); 560860#L494 assume true; 560858#L494-1 assume !false; 560856#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 560854#L452-2 assume !(0 == ~m_st~0); 560852#L456-2 assume !(0 == ~t1_st~0); 560849#L460-2 assume !(0 == ~t2_st~0); 560847#L464-2 assume !(0 == ~t3_st~0); 560845#L468-2 assume !(0 == ~t4_st~0); 560843#L472-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 560842#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 560841#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 560839#L499 assume !(0 != eval_~tmp~0#1); 560838#L502 assume true; 560837#L592 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 560836#L407 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 560835#L599 assume !(0 == ~M_E~0); 560833#L604 assume !(0 == ~T1_E~0); 560830#L609 assume 0 == ~T2_E~0;~T2_E~0 := 1; 560828#L614 assume 0 == ~T3_E~0;~T3_E~0 := 1; 560826#L619 assume 0 == ~T4_E~0;~T4_E~0 := 1; 560825#L624 assume !(0 == ~T5_E~0); 560824#L629 assume 0 == ~E_M~0;~E_M~0 := 1; 560822#L634 assume 0 == ~E_1~0;~E_1~0 := 1; 560820#L639 assume 0 == ~E_2~0;~E_2~0 := 1; 560819#L644 assume !(0 == ~E_3~0); 560815#L649 assume 0 == ~E_4~0;~E_4~0 := 1; 560813#L654 assume 0 == ~E_5~0;~E_5~0 := 1; 560811#L660 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 560806#L292-1 assume 1 == ~m_pc~0; 560803#L293-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 560801#L295-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 560799#L304-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 560796#L743-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 560794#L749-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 560792#L311-1 assume !(1 == ~t1_pc~0); 560790#L321-1 is_transmit1_triggered_~__retres1~1#1 := 0; 560788#L314-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 560786#L323-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 560784#L751-1 assume !(0 != activate_threads_~tmp___0~0#1); 560782#L757-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560780#L330-1 assume !(1 == ~t2_pc~0); 560778#L340-1 is_transmit2_triggered_~__retres1~2#1 := 0; 560776#L333-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 560774#L342-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 560772#L759-1 assume !(0 != activate_threads_~tmp___1~0#1); 560770#L765-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 560768#L349-1 assume !(1 == ~t3_pc~0); 560766#L359-1 is_transmit3_triggered_~__retres1~3#1 := 0; 560762#L352-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 560760#L361-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 560758#L767-1 assume !(0 != activate_threads_~tmp___2~0#1); 560756#L773-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560753#L368-1 assume !(1 == ~t4_pc~0); 560749#L378-1 is_transmit4_triggered_~__retres1~4#1 := 0; 560747#L371-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 560745#L380-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 560743#L775-1 assume !(0 != activate_threads_~tmp___3~0#1); 560740#L781-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 560738#L387-1 assume !(1 == ~t5_pc~0); 560736#L397-1 is_transmit5_triggered_~__retres1~5#1 := 0; 560733#L390-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 560731#L399-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 560729#L783-1 assume !(0 != activate_threads_~tmp___4~0#1); 560727#L789-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 560725#L667 assume !(1 == ~M_E~0); 560721#L672 assume 1 == ~T1_E~0;~T1_E~0 := 2; 560719#L677 assume 1 == ~T2_E~0;~T2_E~0 := 2; 560717#L682 assume 1 == ~T3_E~0;~T3_E~0 := 2; 560715#L687 assume 1 == ~T4_E~0;~T4_E~0 := 2; 560713#L692 assume 1 == ~T5_E~0;~T5_E~0 := 2; 560712#L697 assume 1 == ~E_M~0;~E_M~0 := 2; 560711#L702 assume 1 == ~E_1~0;~E_1~0 := 2; 560709#L707 assume 1 == ~E_2~0;~E_2~0 := 2; 560707#L712 assume !(1 == ~E_3~0); 560706#L717 assume 1 == ~E_4~0;~E_4~0 := 2; 559573#L722 assume 1 == ~E_5~0;~E_5~0 := 2; 560705#L728 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 560704#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 560703#L474-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 560702#L485-1 assume true;start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 560701#L947 assume !(0 == start_simulation_~tmp~3#1); 560699#L958 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 560698#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 560697#L474 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 560696#L485 assume true;stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 560695#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 560694#L904 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 560693#L910 assume true;start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 560692#L960 assume !(0 != start_simulation_~tmp___0~1#1); 560691#L928 assume true; 538644#L928-1 [2024-11-17 08:52:15,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:15,822 INFO L85 PathProgramCache]: Analyzing trace with hash -1157450299, now seen corresponding path program 1 times [2024-11-17 08:52:15,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:15,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143061526] [2024-11-17 08:52:15,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:15,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:15,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:15,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:15,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:15,844 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:15,844 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:15,844 INFO L85 PathProgramCache]: Analyzing trace with hash -121861553, now seen corresponding path program 1 times [2024-11-17 08:52:15,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:15,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348362369] [2024-11-17 08:52:15,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:15,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:15,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:15,872 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:15,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:15,873 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348362369] [2024-11-17 08:52:15,873 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348362369] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:15,873 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:15,873 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:15,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366607776] [2024-11-17 08:52:15,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:15,873 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:15,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:15,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:15,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:15,874 INFO L87 Difference]: Start difference. First operand 58914 states and 77863 transitions. cyclomatic complexity: 18989 Second operand has 3 states, 3 states have (on average 50.333333333333336) internal successors, (151), 3 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:16,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:16,034 INFO L93 Difference]: Finished difference Result 70970 states and 92552 transitions. [2024-11-17 08:52:16,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70970 states and 92552 transitions. [2024-11-17 08:52:16,251 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 43072 [2024-11-17 08:52:16,401 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70970 states to 70970 states and 92552 transitions. [2024-11-17 08:52:16,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43640 [2024-11-17 08:52:16,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43640 [2024-11-17 08:52:16,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70970 states and 92552 transitions. [2024-11-17 08:52:16,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-17 08:52:16,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70970 states and 92552 transitions. [2024-11-17 08:52:16,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70970 states and 92552 transitions. [2024-11-17 08:52:17,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70970 to 67098. [2024-11-17 08:52:17,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67098 states, 67098 states have (on average 1.3105606724492533) internal successors, (87936), 67097 states have internal predecessors, (87936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:17,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67098 states to 67098 states and 87936 transitions. [2024-11-17 08:52:17,485 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67098 states and 87936 transitions. [2024-11-17 08:52:17,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:17,494 INFO L425 stractBuchiCegarLoop]: Abstraction has 67098 states and 87936 transitions. [2024-11-17 08:52:17,494 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:52:17,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67098 states and 87936 transitions. [2024-11-17 08:52:17,630 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 40736 [2024-11-17 08:52:17,630 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:17,630 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:17,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:17,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:17,631 INFO L745 eck$LassoCheckResult]: Stem: 664631#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 663382#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 663383#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 663620#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 663621#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 663288#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 663289#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 664084#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 664085#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 663988#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 663989#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 663921#L599-1 assume !(0 == ~M_E~0); 663340#L604-1 assume !(0 == ~T1_E~0); 663323#L609-1 assume !(0 == ~T2_E~0); 663324#L614-1 assume !(0 == ~T3_E~0); 663593#L619-1 assume !(0 == ~T4_E~0); 663817#L624-1 assume !(0 == ~T5_E~0); 664086#L629-1 assume !(0 == ~E_M~0); 663509#L634-1 assume !(0 == ~E_1~0); 663510#L639-1 assume !(0 == ~E_2~0); 664308#L644-1 assume !(0 == ~E_3~0); 664330#L649-1 assume !(0 == ~E_4~0); 663429#L654-1 assume !(0 == ~E_5~0); 663430#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 664176#L292-8 assume !(1 == ~m_pc~0); 663724#L302-8 is_master_triggered_~__retres1~0#1 := 0; 663725#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 663890#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 663608#L743-8 assume !(0 != activate_threads_~tmp~1#1); 663609#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 663638#L311-8 assume !(1 == ~t1_pc~0); 664483#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 664625#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 663772#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 663773#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 663867#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 664184#L330-8 assume !(1 == ~t2_pc~0); 663294#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 663295#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 663957#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 663958#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 664539#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 663550#L349-8 assume !(1 == ~t3_pc~0); 663551#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 663610#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 663611#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 664182#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 664153#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 663698#L368-8 assume !(1 == ~t4_pc~0); 663424#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 664482#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 664642#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 664262#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 664263#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 663317#L387-8 assume !(1 == ~t5_pc~0); 663318#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 663840#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 663841#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 663587#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 663588#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 664131#L667-1 assume !(1 == ~M_E~0); 664132#L672-1 assume !(1 == ~T1_E~0); 663788#L677-1 assume !(1 == ~T2_E~0); 663789#L682-1 assume !(1 == ~T3_E~0); 664254#L687-1 assume !(1 == ~T4_E~0); 664406#L692-1 assume !(1 == ~T5_E~0); 664227#L697-1 assume !(1 == ~E_M~0); 664228#L702-1 assume !(1 == ~E_1~0); 664323#L707-1 assume !(1 == ~E_2~0); 664035#L712-1 assume !(1 == ~E_3~0); 664036#L717-1 assume !(1 == ~E_4~0); 664273#L722-1 assume !(1 == ~E_5~0); 664274#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 664523#L928 assume true; 670484#L928-1 assume !false; 691514#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 691511#L494 [2024-11-17 08:52:17,631 INFO L747 eck$LassoCheckResult]: Loop: 691511#L494 assume true; 691509#L494-1 assume !false; 691506#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 691505#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 691470#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 691437#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 691417#L499 assume 0 != eval_~tmp~0#1; 691406#L504-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 691396#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 691389#L504 havoc eval_~tmp_ndt_1~0#1; 691381#L518-1 assume !(0 == ~t1_st~0); 691372#L532-1 assume !(0 == ~t2_st~0); 691357#L546-1 assume !(0 == ~t3_st~0); 691358#L560-1 assume !(0 == ~t4_st~0); 691515#L574-1 assume !(0 == ~t5_st~0); 691511#L494 [2024-11-17 08:52:17,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:17,632 INFO L85 PathProgramCache]: Analyzing trace with hash 86821859, now seen corresponding path program 1 times [2024-11-17 08:52:17,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:17,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358090814] [2024-11-17 08:52:17,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:17,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:17,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,637 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:17,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,646 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:17,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:17,647 INFO L85 PathProgramCache]: Analyzing trace with hash -1846225399, now seen corresponding path program 1 times [2024-11-17 08:52:17,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:17,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17570319] [2024-11-17 08:52:17,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:17,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:17,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,649 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:17,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:17,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:17,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:17,651 INFO L85 PathProgramCache]: Analyzing trace with hash -587298329, now seen corresponding path program 1 times [2024-11-17 08:52:17,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:17,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1447463154] [2024-11-17 08:52:17,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:17,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:17,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:17,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:17,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:17,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1447463154] [2024-11-17 08:52:17,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1447463154] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:17,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:17,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:17,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257271979] [2024-11-17 08:52:17,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:17,714 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:17,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:17,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:17,715 INFO L87 Difference]: Start difference. First operand 67098 states and 87936 transitions. cyclomatic complexity: 20918 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:17,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:17,864 INFO L93 Difference]: Finished difference Result 81102 states and 104794 transitions. [2024-11-17 08:52:17,864 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81102 states and 104794 transitions. [2024-11-17 08:52:18,339 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 49428 [2024-11-17 08:52:18,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81102 states to 81102 states and 104794 transitions. [2024-11-17 08:52:18,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50068 [2024-11-17 08:52:18,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50068 [2024-11-17 08:52:18,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81102 states and 104794 transitions. [2024-11-17 08:52:18,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-17 08:52:18,553 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81102 states and 104794 transitions. [2024-11-17 08:52:18,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81102 states and 104794 transitions. [2024-11-17 08:52:19,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81102 to 77162. [2024-11-17 08:52:19,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77162 states, 77162 states have (on average 1.2969337238537104) internal successors, (100074), 77161 states have internal predecessors, (100074), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:19,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77162 states to 77162 states and 100074 transitions. [2024-11-17 08:52:19,296 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77162 states and 100074 transitions. [2024-11-17 08:52:19,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:19,296 INFO L425 stractBuchiCegarLoop]: Abstraction has 77162 states and 100074 transitions. [2024-11-17 08:52:19,296 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-17 08:52:19,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77162 states and 100074 transitions. [2024-11-17 08:52:19,673 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 47048 [2024-11-17 08:52:19,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:19,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:19,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:19,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:19,674 INFO L745 eck$LassoCheckResult]: Stem: 812883#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 811590#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 811591#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 811830#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 811831#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 811500#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 811501#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 812305#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 812306#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 812209#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 812210#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 812139#L599-1 assume !(0 == ~M_E~0); 811547#L604-1 assume !(0 == ~T1_E~0); 811530#L609-1 assume !(0 == ~T2_E~0); 811531#L614-1 assume !(0 == ~T3_E~0); 811801#L619-1 assume !(0 == ~T4_E~0); 812032#L624-1 assume !(0 == ~T5_E~0); 812310#L629-1 assume !(0 == ~E_M~0); 811720#L634-1 assume !(0 == ~E_1~0); 811721#L639-1 assume !(0 == ~E_2~0); 812528#L644-1 assume !(0 == ~E_3~0); 812556#L649-1 assume !(0 == ~E_4~0); 811637#L654-1 assume !(0 == ~E_5~0); 811638#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 812396#L292-8 assume !(1 == ~m_pc~0); 811936#L302-8 is_master_triggered_~__retres1~0#1 := 0; 811937#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 812110#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 811817#L743-8 assume !(0 != activate_threads_~tmp~1#1); 811818#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 811849#L311-8 assume !(1 == ~t1_pc~0); 812720#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 812873#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 811983#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 811984#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 812086#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 812409#L330-8 assume !(1 == ~t2_pc~0); 811502#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 811503#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 812179#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 812180#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 812788#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 811761#L349-8 assume !(1 == ~t3_pc~0); 811762#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 811819#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 811820#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 812406#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 812375#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 811910#L368-8 assume !(1 == ~t4_pc~0); 811632#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 812719#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 812892#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 812484#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 812485#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 811524#L387-8 assume !(1 == ~t5_pc~0); 811525#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 812057#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 812058#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 811795#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 811796#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 812354#L667-1 assume !(1 == ~M_E~0); 812355#L672-1 assume !(1 == ~T1_E~0); 812004#L677-1 assume !(1 == ~T2_E~0); 812005#L682-1 assume !(1 == ~T3_E~0); 812473#L687-1 assume !(1 == ~T4_E~0); 812643#L692-1 assume !(1 == ~T5_E~0); 812449#L697-1 assume !(1 == ~E_M~0); 812450#L702-1 assume !(1 == ~E_1~0); 812546#L707-1 assume !(1 == ~E_2~0); 812256#L712-1 assume !(1 == ~E_3~0); 812257#L717-1 assume !(1 == ~E_4~0); 812493#L722-1 assume !(1 == ~E_5~0); 812494#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 812763#L928 assume true; 817843#L928-1 assume !false; 862168#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 862165#L494 [2024-11-17 08:52:19,674 INFO L747 eck$LassoCheckResult]: Loop: 862165#L494 assume true; 862163#L494-1 assume !false; 862161#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 862159#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 862157#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 862155#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 862153#L499 assume 0 != eval_~tmp~0#1; 862151#L504-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 862148#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 862146#L504 havoc eval_~tmp_ndt_1~0#1; 862143#L518-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 862140#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 862138#L518 havoc eval_~tmp_ndt_2~0#1; 862134#L532-1 assume !(0 == ~t2_st~0); 862135#L546-1 assume !(0 == ~t3_st~0); 862173#L560-1 assume !(0 == ~t4_st~0); 862169#L574-1 assume !(0 == ~t5_st~0); 862165#L494 [2024-11-17 08:52:19,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:19,675 INFO L85 PathProgramCache]: Analyzing trace with hash 86821859, now seen corresponding path program 2 times [2024-11-17 08:52:19,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:19,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091693929] [2024-11-17 08:52:19,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:19,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:19,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,680 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:19,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,689 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:19,689 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:19,689 INFO L85 PathProgramCache]: Analyzing trace with hash 1557251209, now seen corresponding path program 1 times [2024-11-17 08:52:19,690 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:19,690 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497183120] [2024-11-17 08:52:19,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:19,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:19,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,692 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:19,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:19,694 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:19,694 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:19,694 INFO L85 PathProgramCache]: Analyzing trace with hash 205388007, now seen corresponding path program 1 times [2024-11-17 08:52:19,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:19,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096422668] [2024-11-17 08:52:19,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:19,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:19,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:19,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:19,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:19,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096422668] [2024-11-17 08:52:19,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1096422668] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:19,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:19,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:19,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986776151] [2024-11-17 08:52:19,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:19,754 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:19,754 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:19,754 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:19,755 INFO L87 Difference]: Start difference. First operand 77162 states and 100074 transitions. cyclomatic complexity: 22992 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:19,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:19,948 INFO L93 Difference]: Finished difference Result 106394 states and 137116 transitions. [2024-11-17 08:52:19,948 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106394 states and 137116 transitions. [2024-11-17 08:52:20,277 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 69224 [2024-11-17 08:52:20,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106394 states to 106394 states and 137116 transitions. [2024-11-17 08:52:20,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70104 [2024-11-17 08:52:20,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70104 [2024-11-17 08:52:20,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106394 states and 137116 transitions. [2024-11-17 08:52:20,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-17 08:52:20,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 106394 states and 137116 transitions. [2024-11-17 08:52:20,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106394 states and 137116 transitions. [2024-11-17 08:52:21,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106394 to 104782. [2024-11-17 08:52:21,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104782 states, 104782 states have (on average 1.290221602947071) internal successors, (135192), 104781 states have internal predecessors, (135192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:21,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104782 states to 104782 states and 135192 transitions. [2024-11-17 08:52:21,921 INFO L240 hiAutomatonCegarLoop]: Abstraction has 104782 states and 135192 transitions. [2024-11-17 08:52:21,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:21,921 INFO L425 stractBuchiCegarLoop]: Abstraction has 104782 states and 135192 transitions. [2024-11-17 08:52:21,922 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-17 08:52:21,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104782 states and 135192 transitions. [2024-11-17 08:52:22,116 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 67612 [2024-11-17 08:52:22,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:22,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:22,117 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:22,117 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:22,117 INFO L745 eck$LassoCheckResult]: Stem: 996452#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 995155#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 995156#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 995398#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 995399#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 995060#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 995061#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 995861#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 995862#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 995771#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 995772#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 995700#L599-1 assume !(0 == ~M_E~0); 995109#L604-1 assume !(0 == ~T1_E~0); 995096#L609-1 assume !(0 == ~T2_E~0); 995097#L614-1 assume !(0 == ~T3_E~0); 995368#L619-1 assume !(0 == ~T4_E~0); 995592#L624-1 assume !(0 == ~T5_E~0); 995863#L629-1 assume !(0 == ~E_M~0); 995282#L634-1 assume !(0 == ~E_1~0); 995283#L639-1 assume !(0 == ~E_2~0); 996081#L644-1 assume !(0 == ~E_3~0); 996108#L649-1 assume !(0 == ~E_4~0); 995205#L654-1 assume !(0 == ~E_5~0); 995206#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 995947#L292-8 assume !(1 == ~m_pc~0); 995493#L302-8 is_master_triggered_~__retres1~0#1 := 0; 995494#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 995667#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 995385#L743-8 assume !(0 != activate_threads_~tmp~1#1); 995386#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 995411#L311-8 assume !(1 == ~t1_pc~0); 996281#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 996445#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 995541#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 995542#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 995645#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 995959#L330-8 assume !(1 == ~t2_pc~0); 995066#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 995067#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995736#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 995737#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 996349#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 995327#L349-8 assume !(1 == ~t3_pc~0); 995328#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 995387#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 995388#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 995956#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 995928#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 995469#L368-8 assume !(1 == ~t4_pc~0); 995200#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 996280#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 996460#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 996037#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 996038#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 995080#L387-8 assume !(1 == ~t5_pc~0); 995081#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 995616#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 995617#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 995361#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 995362#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 995909#L667-1 assume !(1 == ~M_E~0); 995910#L672-1 assume !(1 == ~T1_E~0); 995562#L677-1 assume !(1 == ~T2_E~0); 995563#L682-1 assume !(1 == ~T3_E~0); 996029#L687-1 assume !(1 == ~T4_E~0); 996194#L692-1 assume !(1 == ~T5_E~0); 996003#L697-1 assume !(1 == ~E_M~0); 996004#L702-1 assume !(1 == ~E_1~0); 996101#L707-1 assume !(1 == ~E_2~0); 995817#L712-1 assume !(1 == ~E_3~0); 995818#L717-1 assume !(1 == ~E_4~0); 996046#L722-1 assume !(1 == ~E_5~0); 996047#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 996322#L928 assume true; 1005776#L928-1 assume !false; 1069691#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1069688#L494 [2024-11-17 08:52:22,118 INFO L747 eck$LassoCheckResult]: Loop: 1069688#L494 assume true; 1069686#L494-1 assume !false; 1069684#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1069681#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1069679#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1069677#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1069674#L499 assume 0 != eval_~tmp~0#1; 1069672#L504-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1069669#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 1069666#L504 havoc eval_~tmp_ndt_1~0#1; 1069664#L518-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1069661#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 1069659#L518 havoc eval_~tmp_ndt_2~0#1; 1069657#L532-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1069655#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 1069653#L532 havoc eval_~tmp_ndt_3~0#1; 1069650#L546-1 assume !(0 == ~t3_st~0); 1069651#L560-1 assume !(0 == ~t4_st~0); 1069692#L574-1 assume !(0 == ~t5_st~0); 1069688#L494 [2024-11-17 08:52:22,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:22,118 INFO L85 PathProgramCache]: Analyzing trace with hash 86821859, now seen corresponding path program 3 times [2024-11-17 08:52:22,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:22,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857294173] [2024-11-17 08:52:22,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:22,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:22,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:22,125 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:22,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:22,136 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:22,136 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:22,136 INFO L85 PathProgramCache]: Analyzing trace with hash 1932974985, now seen corresponding path program 1 times [2024-11-17 08:52:22,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:22,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364159384] [2024-11-17 08:52:22,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:22,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:22,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:22,141 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:22,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:22,143 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:22,143 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:22,143 INFO L85 PathProgramCache]: Analyzing trace with hash -127438745, now seen corresponding path program 1 times [2024-11-17 08:52:22,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:22,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521709126] [2024-11-17 08:52:22,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:22,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:22,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:22,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:22,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:22,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521709126] [2024-11-17 08:52:22,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521709126] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:22,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:22,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:22,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893832954] [2024-11-17 08:52:22,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:22,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:22,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:22,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:22,213 INFO L87 Difference]: Start difference. First operand 104782 states and 135192 transitions. cyclomatic complexity: 30490 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:22,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:22,812 INFO L93 Difference]: Finished difference Result 133894 states and 171539 transitions. [2024-11-17 08:52:22,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133894 states and 171539 transitions. [2024-11-17 08:52:23,321 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 86092 [2024-11-17 08:52:23,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133894 states to 133894 states and 171539 transitions. [2024-11-17 08:52:23,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87154 [2024-11-17 08:52:23,703 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87154 [2024-11-17 08:52:23,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133894 states and 171539 transitions. [2024-11-17 08:52:23,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-17 08:52:23,704 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133894 states and 171539 transitions. [2024-11-17 08:52:23,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133894 states and 171539 transitions. [2024-11-17 08:52:24,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133894 to 129478. [2024-11-17 08:52:24,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129478 states, 129478 states have (on average 1.2840714252614345) internal successors, (166259), 129477 states have internal predecessors, (166259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:25,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129478 states to 129478 states and 166259 transitions. [2024-11-17 08:52:25,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129478 states and 166259 transitions. [2024-11-17 08:52:25,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:25,066 INFO L425 stractBuchiCegarLoop]: Abstraction has 129478 states and 166259 transitions. [2024-11-17 08:52:25,066 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-17 08:52:25,066 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129478 states and 166259 transitions. [2024-11-17 08:52:25,781 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 83286 [2024-11-17 08:52:25,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:25,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:25,782 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:25,782 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:25,782 INFO L745 eck$LassoCheckResult]: Stem: 1235192#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1233837#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1233838#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1234079#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1234080#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1233744#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1233745#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1234550#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1234551#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1234454#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1234455#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1234387#L599-1 assume !(0 == ~M_E~0); 1233793#L604-1 assume !(0 == ~T1_E~0); 1233780#L609-1 assume !(0 == ~T2_E~0); 1233781#L614-1 assume !(0 == ~T3_E~0); 1234049#L619-1 assume !(0 == ~T4_E~0); 1234280#L624-1 assume !(0 == ~T5_E~0); 1234552#L629-1 assume !(0 == ~E_M~0); 1233963#L634-1 assume !(0 == ~E_1~0); 1233964#L639-1 assume !(0 == ~E_2~0); 1234777#L644-1 assume !(0 == ~E_3~0); 1234806#L649-1 assume !(0 == ~E_4~0); 1233884#L654-1 assume !(0 == ~E_5~0); 1233885#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1234641#L292-8 assume !(1 == ~m_pc~0); 1234182#L302-8 is_master_triggered_~__retres1~0#1 := 0; 1234183#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1234352#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1234068#L743-8 assume !(0 != activate_threads_~tmp~1#1); 1234069#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1234094#L311-8 assume !(1 == ~t1_pc~0); 1235004#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1235182#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1234229#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1234230#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 1234332#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1234659#L330-8 assume !(1 == ~t2_pc~0); 1233750#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1233751#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1234422#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1234423#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 1235071#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1234008#L349-8 assume !(1 == ~t3_pc~0); 1234009#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 1234066#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1234067#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1234656#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 1234620#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1234159#L368-8 assume !(1 == ~t4_pc~0); 1233879#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1235003#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1235201#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1234741#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 1234742#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1233764#L387-8 assume !(1 == ~t5_pc~0); 1233765#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 1234303#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1234304#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1234043#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 1234044#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1234598#L667-1 assume !(1 == ~M_E~0); 1234599#L672-1 assume !(1 == ~T1_E~0); 1234250#L677-1 assume !(1 == ~T2_E~0); 1234251#L682-1 assume !(1 == ~T3_E~0); 1234733#L687-1 assume !(1 == ~T4_E~0); 1234899#L692-1 assume !(1 == ~T5_E~0); 1234706#L697-1 assume !(1 == ~E_M~0); 1234707#L702-1 assume !(1 == ~E_1~0); 1234798#L707-1 assume !(1 == ~E_2~0); 1234505#L712-1 assume !(1 == ~E_3~0); 1234506#L717-1 assume !(1 == ~E_4~0); 1234748#L722-1 assume !(1 == ~E_5~0); 1234749#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 1235046#L928 assume true; 1252321#L928-1 assume !false; 1297639#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1297636#L494 [2024-11-17 08:52:25,785 INFO L747 eck$LassoCheckResult]: Loop: 1297636#L494 assume true; 1297634#L494-1 assume !false; 1297632#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1297630#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1297628#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1297626#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1297624#L499 assume 0 != eval_~tmp~0#1; 1297623#L504-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1297621#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 1297620#L504 havoc eval_~tmp_ndt_1~0#1; 1297618#L518-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1297614#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 1297616#L518 havoc eval_~tmp_ndt_2~0#1; 1297662#L532-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1297659#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 1297657#L532 havoc eval_~tmp_ndt_3~0#1; 1297653#L546-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1297650#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 1297648#L546 havoc eval_~tmp_ndt_4~0#1; 1297645#L560-1 assume !(0 == ~t4_st~0); 1297640#L574-1 assume !(0 == ~t5_st~0); 1297636#L494 [2024-11-17 08:52:25,785 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:25,785 INFO L85 PathProgramCache]: Analyzing trace with hash 86821859, now seen corresponding path program 4 times [2024-11-17 08:52:25,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:25,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735219077] [2024-11-17 08:52:25,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:25,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:25,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:25,802 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:25,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:25,831 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:25,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:25,831 INFO L85 PathProgramCache]: Analyzing trace with hash -2129831415, now seen corresponding path program 1 times [2024-11-17 08:52:25,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:25,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065711646] [2024-11-17 08:52:25,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:25,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:25,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:25,837 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:25,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:25,839 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:25,840 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:25,840 INFO L85 PathProgramCache]: Analyzing trace with hash 2087464807, now seen corresponding path program 1 times [2024-11-17 08:52:25,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:25,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074567110] [2024-11-17 08:52:25,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:25,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:25,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:25,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:25,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:25,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074567110] [2024-11-17 08:52:25,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074567110] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:25,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:25,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:25,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820488203] [2024-11-17 08:52:25,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:25,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:25,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:25,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:25,916 INFO L87 Difference]: Start difference. First operand 129478 states and 166259 transitions. cyclomatic complexity: 36861 Second operand has 3 states, 3 states have (on average 32.333333333333336) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:26,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:26,295 INFO L93 Difference]: Finished difference Result 227563 states and 291378 transitions. [2024-11-17 08:52:26,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 227563 states and 291378 transitions. [2024-11-17 08:52:27,534 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 146516 [2024-11-17 08:52:27,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 227563 states to 227563 states and 291378 transitions. [2024-11-17 08:52:27,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 148631 [2024-11-17 08:52:27,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 148631 [2024-11-17 08:52:27,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 227563 states and 291378 transitions. [2024-11-17 08:52:27,995 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-17 08:52:27,995 INFO L218 hiAutomatonCegarLoop]: Abstraction has 227563 states and 291378 transitions. [2024-11-17 08:52:28,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227563 states and 291378 transitions. [2024-11-17 08:52:30,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227563 to 220699. [2024-11-17 08:52:30,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220699 states, 220699 states have (on average 1.2855608770316131) internal successors, (283722), 220698 states have internal predecessors, (283722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:30,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220699 states to 220699 states and 283722 transitions. [2024-11-17 08:52:30,714 INFO L240 hiAutomatonCegarLoop]: Abstraction has 220699 states and 283722 transitions. [2024-11-17 08:52:30,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:30,715 INFO L425 stractBuchiCegarLoop]: Abstraction has 220699 states and 283722 transitions. [2024-11-17 08:52:30,715 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-17 08:52:30,715 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 220699 states and 283722 transitions. [2024-11-17 08:52:31,176 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 142174 [2024-11-17 08:52:31,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:31,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:31,177 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:31,177 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:31,177 INFO L745 eck$LassoCheckResult]: Stem: 1592262#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1590892#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1590893#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1591138#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1591139#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1590793#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1590794#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1591620#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1591621#L434 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1591767#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1615894#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1615893#L599-1 assume !(0 == ~M_E~0); 1615892#L604-1 assume !(0 == ~T1_E~0); 1615891#L609-1 assume !(0 == ~T2_E~0); 1615890#L614-1 assume !(0 == ~T3_E~0); 1615889#L619-1 assume !(0 == ~T4_E~0); 1615888#L624-1 assume !(0 == ~T5_E~0); 1615887#L629-1 assume !(0 == ~E_M~0); 1615886#L634-1 assume !(0 == ~E_1~0); 1615885#L639-1 assume !(0 == ~E_2~0); 1615884#L644-1 assume !(0 == ~E_3~0); 1615883#L649-1 assume !(0 == ~E_4~0); 1615882#L654-1 assume !(0 == ~E_5~0); 1615881#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1615880#L292-8 assume !(1 == ~m_pc~0); 1615879#L302-8 is_master_triggered_~__retres1~0#1 := 0; 1615878#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1615877#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1615876#L743-8 assume !(0 != activate_threads_~tmp~1#1); 1615875#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1615874#L311-8 assume !(1 == ~t1_pc~0); 1615873#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1615872#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1615871#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1615870#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 1615869#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1615868#L330-8 assume !(1 == ~t2_pc~0); 1615867#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1615866#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1615865#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1615864#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 1615863#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1591062#L349-8 assume !(1 == ~t3_pc~0); 1591063#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 1591126#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1591127#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1591725#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 1591691#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1591218#L368-8 assume !(1 == ~t4_pc~0); 1590932#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1592044#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1591035#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1591036#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 1591800#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1590823#L387-8 assume !(1 == ~t5_pc~0); 1590824#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 1591363#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1591364#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1591101#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 1591102#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1591667#L667-1 assume !(1 == ~M_E~0); 1591668#L672-1 assume !(1 == ~T1_E~0); 1591310#L677-1 assume !(1 == ~T2_E~0); 1591311#L682-1 assume !(1 == ~T3_E~0); 1591794#L687-1 assume !(1 == ~T4_E~0); 1591957#L692-1 assume !(1 == ~T5_E~0); 1591768#L697-1 assume !(1 == ~E_M~0); 1591769#L702-1 assume !(1 == ~E_1~0); 1591863#L707-1 assume !(1 == ~E_2~0); 1591568#L712-1 assume !(1 == ~E_3~0); 1591569#L717-1 assume !(1 == ~E_4~0); 1591811#L722-1 assume !(1 == ~E_5~0); 1591812#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 1592113#L928 assume true; 1620990#L928-1 assume !false; 1699767#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1699768#L494 [2024-11-17 08:52:31,177 INFO L747 eck$LassoCheckResult]: Loop: 1699768#L494 assume true; 1705909#L494-1 assume !false; 1705908#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1705907#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1705906#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1705905#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1705904#L499 assume 0 != eval_~tmp~0#1; 1705903#L504-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1705901#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 1705902#L504 havoc eval_~tmp_ndt_1~0#1; 1715541#L518-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1699734#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 1699735#L518 havoc eval_~tmp_ndt_2~0#1; 1702789#L532-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1702786#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 1702787#L532 havoc eval_~tmp_ndt_3~0#1; 1705882#L546-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1705879#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 1705880#L546 havoc eval_~tmp_ndt_4~0#1; 1705914#L560-1 assume !(0 == ~t4_st~0); 1705911#L574-1 assume !(0 == ~t5_st~0); 1699768#L494 [2024-11-17 08:52:31,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:31,177 INFO L85 PathProgramCache]: Analyzing trace with hash -1583691710, now seen corresponding path program 1 times [2024-11-17 08:52:31,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:31,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431009709] [2024-11-17 08:52:31,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:31,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:31,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:31,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:31,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:31,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431009709] [2024-11-17 08:52:31,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431009709] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:31,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:31,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:31,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751711945] [2024-11-17 08:52:31,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:31,193 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:31,193 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:31,193 INFO L85 PathProgramCache]: Analyzing trace with hash -2129831415, now seen corresponding path program 2 times [2024-11-17 08:52:31,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:31,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878984283] [2024-11-17 08:52:31,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:31,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:31,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:31,195 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:31,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:31,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:31,245 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:31,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:31,245 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:31,245 INFO L87 Difference]: Start difference. First operand 220699 states and 283722 transitions. cyclomatic complexity: 63103 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:32,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:32,236 INFO L93 Difference]: Finished difference Result 220626 states and 283623 transitions. [2024-11-17 08:52:32,236 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 220626 states and 283623 transitions. [2024-11-17 08:52:32,907 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 142174 [2024-11-17 08:52:33,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 220626 states to 220626 states and 283623 transitions. [2024-11-17 08:52:33,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144218 [2024-11-17 08:52:33,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144218 [2024-11-17 08:52:33,971 INFO L73 IsDeterministic]: Start isDeterministic. Operand 220626 states and 283623 transitions. [2024-11-17 08:52:33,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-17 08:52:33,971 INFO L218 hiAutomatonCegarLoop]: Abstraction has 220626 states and 283623 transitions. [2024-11-17 08:52:34,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220626 states and 283623 transitions. [2024-11-17 08:52:35,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220626 to 220626. [2024-11-17 08:52:35,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220626 states, 220626 states have (on average 1.2855375159772646) internal successors, (283623), 220625 states have internal predecessors, (283623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:36,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220626 states to 220626 states and 283623 transitions. [2024-11-17 08:52:36,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 220626 states and 283623 transitions. [2024-11-17 08:52:36,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:36,095 INFO L425 stractBuchiCegarLoop]: Abstraction has 220626 states and 283623 transitions. [2024-11-17 08:52:36,095 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-17 08:52:36,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 220626 states and 283623 transitions. [2024-11-17 08:52:37,225 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 142174 [2024-11-17 08:52:37,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:37,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:37,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:37,226 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:37,226 INFO L745 eck$LassoCheckResult]: Stem: 2033557#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2032219#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2032220#L891 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2032460#L407-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2032461#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 2032124#L419 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2032125#L424 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2032937#L429 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2032938#L434 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2032835#L439 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2032836#L445 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2032764#L599-1 assume !(0 == ~M_E~0); 2032173#L604-1 assume !(0 == ~T1_E~0); 2032160#L609-1 assume !(0 == ~T2_E~0); 2032161#L614-1 assume !(0 == ~T3_E~0); 2032429#L619-1 assume !(0 == ~T4_E~0); 2032657#L624-1 assume !(0 == ~T5_E~0); 2032939#L629-1 assume !(0 == ~E_M~0); 2032343#L634-1 assume !(0 == ~E_1~0); 2032344#L639-1 assume !(0 == ~E_2~0); 2033162#L644-1 assume !(0 == ~E_3~0); 2033190#L649-1 assume !(0 == ~E_4~0); 2032266#L654-1 assume !(0 == ~E_5~0); 2032267#L660-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2033030#L292-8 assume !(1 == ~m_pc~0); 2032559#L302-8 is_master_triggered_~__retres1~0#1 := 0; 2032560#L295-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2032728#L304-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2032448#L743-8 assume !(0 != activate_threads_~tmp~1#1); 2032449#L749-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2032473#L311-8 assume !(1 == ~t1_pc~0); 2033371#L321-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2033547#L314-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2032612#L323-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2032613#L751-8 assume !(0 != activate_threads_~tmp___0~0#1); 2032709#L757-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2033043#L330-8 assume !(1 == ~t2_pc~0); 2032130#L340-8 is_transmit2_triggered_~__retres1~2#1 := 0; 2032131#L333-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2032800#L342-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2032801#L759-8 assume !(0 != activate_threads_~tmp___1~0#1); 2033441#L765-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2032388#L349-8 assume !(1 == ~t3_pc~0); 2032389#L359-8 is_transmit3_triggered_~__retres1~3#1 := 0; 2032446#L352-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2032447#L361-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2033040#L767-8 assume !(0 != activate_threads_~tmp___2~0#1); 2033009#L773-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2032534#L368-8 assume !(1 == ~t4_pc~0); 2032261#L378-8 is_transmit4_triggered_~__retres1~4#1 := 0; 2033370#L371-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2033564#L380-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2033121#L775-8 assume !(0 != activate_threads_~tmp___3~0#1); 2033122#L781-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2032144#L387-8 assume !(1 == ~t5_pc~0); 2032145#L397-8 is_transmit5_triggered_~__retres1~5#1 := 0; 2032681#L390-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2032682#L399-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2032423#L783-8 assume !(0 != activate_threads_~tmp___4~0#1); 2032424#L789-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2032986#L667-1 assume !(1 == ~M_E~0); 2032987#L672-1 assume !(1 == ~T1_E~0); 2032631#L677-1 assume !(1 == ~T2_E~0); 2032632#L682-1 assume !(1 == ~T3_E~0); 2033111#L687-1 assume !(1 == ~T4_E~0); 2033280#L692-1 assume !(1 == ~T5_E~0); 2033086#L697-1 assume !(1 == ~E_M~0); 2033087#L702-1 assume !(1 == ~E_1~0); 2033183#L707-1 assume !(1 == ~E_2~0); 2032886#L712-1 assume !(1 == ~E_3~0); 2032887#L717-1 assume !(1 == ~E_4~0); 2033130#L722-1 assume !(1 == ~E_5~0); 2033131#L728-1 assume true;assume { :end_inline_reset_delta_events } true; 2033418#L928 assume true; 2064964#L928-1 assume !false; 2181113#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2181073#L494 [2024-11-17 08:52:37,226 INFO L747 eck$LassoCheckResult]: Loop: 2181073#L494 assume true; 2181062#L494-1 assume !false; 2181051#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2181040#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2181028#L474-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2181018#L485-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2181010#L499 assume 0 != eval_~tmp~0#1; 2180991#L504-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2180980#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 2180981#L504 havoc eval_~tmp_ndt_1~0#1; 2181228#L518-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2181225#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 2181223#L518 havoc eval_~tmp_ndt_2~0#1; 2181221#L532-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2181217#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 2181215#L532 havoc eval_~tmp_ndt_3~0#1; 2181213#L546-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2181210#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 2181208#L546 havoc eval_~tmp_ndt_4~0#1; 2181206#L560-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 2181132#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 2181204#L560 havoc eval_~tmp_ndt_5~0#1; 2181114#L574-1 assume !(0 == ~t5_st~0); 2181073#L494 [2024-11-17 08:52:37,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:37,227 INFO L85 PathProgramCache]: Analyzing trace with hash 86821859, now seen corresponding path program 5 times [2024-11-17 08:52:37,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:37,227 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535181497] [2024-11-17 08:52:37,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:37,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:37,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:37,233 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:37,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:37,244 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:37,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:37,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1931485449, now seen corresponding path program 1 times [2024-11-17 08:52:37,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:37,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504194123] [2024-11-17 08:52:37,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:37,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:37,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:37,247 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:37,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:37,250 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:37,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:37,250 INFO L85 PathProgramCache]: Analyzing trace with hash 304027367, now seen corresponding path program 1 times [2024-11-17 08:52:37,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:37,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347804822] [2024-11-17 08:52:37,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:37,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:37,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:37,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:37,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:37,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347804822] [2024-11-17 08:52:37,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347804822] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:37,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:37,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:37,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783668728] [2024-11-17 08:52:37,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:37,317 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:37,318 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:37,318 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:37,318 INFO L87 Difference]: Start difference. First operand 220626 states and 283623 transitions. cyclomatic complexity: 63077 Second operand has 3 states, 2 states have (on average 49.5) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:37,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:37,786 INFO L93 Difference]: Finished difference Result 279791 states and 356950 transitions. [2024-11-17 08:52:37,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 279791 states and 356950 transitions.