./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:52:01,061 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:52:01,127 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:52:01,132 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:52:01,133 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:52:01,133 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:52:01,162 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:52:01,163 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:52:01,163 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:52:01,164 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:52:01,164 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:52:01,165 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:52:01,165 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:52:01,165 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:52:01,166 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:52:01,166 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:52:01,167 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:52:01,167 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:52:01,167 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:52:01,167 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:52:01,168 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:52:01,168 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:52:01,168 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:52:01,169 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:52:01,169 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:52:01,169 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:52:01,170 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:52:01,170 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:52:01,170 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:52:01,171 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:52:01,171 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:52:01,171 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:52:01,171 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:52:01,172 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:52:01,172 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:52:01,172 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:52:01,173 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:52:01,173 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:52:01,173 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:52:01,174 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:52:01,174 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2024-11-17 08:52:01,394 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:52:01,418 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:52:01,421 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:52:01,422 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:52:01,422 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:52:01,423 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2024-11-17 08:52:02,851 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:52:03,064 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:52:03,065 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2024-11-17 08:52:03,076 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4de8fa944/d38484b3c6c842caa6eb45d91e98b3c8/FLAGe2e186bf4 [2024-11-17 08:52:03,088 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4de8fa944/d38484b3c6c842caa6eb45d91e98b3c8 [2024-11-17 08:52:03,091 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:52:03,092 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:52:03,094 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:03,094 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:52:03,099 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:52:03,099 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,100 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@35d185a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03, skipping insertion in model container [2024-11-17 08:52:03,100 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,138 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:52:03,433 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:03,447 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:52:03,504 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:03,522 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:52:03,523 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03 WrapperNode [2024-11-17 08:52:03,523 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:03,524 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:03,524 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:52:03,524 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:52:03,529 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,537 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,604 INFO L138 Inliner]: procedures = 38, calls = 48, calls flagged for inlining = 43, calls inlined = 97, statements flattened = 1360 [2024-11-17 08:52:03,604 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:03,605 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:52:03,605 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:52:03,607 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:52:03,628 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,628 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,641 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,668 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:52:03,673 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,674 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,693 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,694 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,696 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,699 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,703 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:52:03,704 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:52:03,704 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:52:03,704 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:52:03,705 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (1/1) ... [2024-11-17 08:52:03,710 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:03,720 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:03,746 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:03,749 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:52:03,799 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:52:03,799 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:52:03,799 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:52:03,800 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:52:03,915 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:52:03,917 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:05,145 INFO L? ?]: Removed 256 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:05,146 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:05,176 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:05,176 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:05,176 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:05 BoogieIcfgContainer [2024-11-17 08:52:05,177 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:05,178 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:05,178 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:05,185 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:05,186 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:05,187 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:52:03" (1/3) ... [2024-11-17 08:52:05,188 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6bf2c4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:05, skipping insertion in model container [2024-11-17 08:52:05,188 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:05,188 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:03" (2/3) ... [2024-11-17 08:52:05,189 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6bf2c4b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:05, skipping insertion in model container [2024-11-17 08:52:05,189 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:05,190 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:05" (3/3) ... [2024-11-17 08:52:05,191 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2024-11-17 08:52:05,254 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:05,254 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:05,254 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:05,254 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:05,254 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:05,254 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:05,254 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:05,254 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:05,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 596 states, 595 states have (on average 1.4974789915966387) internal successors, (891), 595 states have internal predecessors, (891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 512 [2024-11-17 08:52:05,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:05,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:05,315 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,315 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:05,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 596 states, 595 states have (on average 1.4974789915966387) internal successors, (891), 595 states have internal predecessors, (891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,332 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 512 [2024-11-17 08:52:05,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:05,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:05,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,343 INFO L745 eck$LassoCheckResult]: Stem: 582#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 35#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 254#L903true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 437#L419-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 264#L426true assume !(1 == ~m_i~0);~m_st~0 := 2; 280#L431true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 496#L436true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 28#L441true assume 1 == ~t3_i~0;~t3_st~0 := 0; 567#L446true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 146#L451true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 169#L457true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 558#L611-1true assume !(0 == ~M_E~0); 386#L616-1true assume !(0 == ~T1_E~0); 397#L621-1true assume !(0 == ~T2_E~0); 65#L626-1true assume !(0 == ~T3_E~0); 344#L631-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 173#L636-1true assume !(0 == ~T5_E~0); 93#L641-1true assume !(0 == ~E_M~0); 183#L646-1true assume !(0 == ~E_1~0); 527#L651-1true assume !(0 == ~E_2~0); 469#L656-1true assume !(0 == ~E_3~0); 356#L661-1true assume !(0 == ~E_4~0); 413#L666-1true assume !(0 == ~E_5~0); 346#L672-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 181#L304-8true assume 1 == ~m_pc~0; 104#L305-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 550#L307-8true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36#L316-8true assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23#L755-8true assume !(0 != activate_threads_~tmp~1#1); 87#L761-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140#L323-8true assume 1 == ~t1_pc~0; 591#L324-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 585#L326-8true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 263#L335-8true assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 261#L763-8true assume !(0 != activate_threads_~tmp___0~0#1); 403#L769-8true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209#L342-8true assume 1 == ~t2_pc~0; 127#L343-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 288#L345-8true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 320#L354-8true assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 450#L771-8true assume !(0 != activate_threads_~tmp___1~0#1); 249#L777-8true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 290#L361-8true assume 1 == ~t3_pc~0; 152#L362-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 478#L364-8true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19#L373-8true assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 577#L779-8true assume !(0 != activate_threads_~tmp___2~0#1); 442#L785-8true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72#L380-8true assume 1 == ~t4_pc~0; 293#L381-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 195#L383-8true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 387#L392-8true assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53#L787-8true assume !(0 != activate_threads_~tmp___3~0#1); 509#L793-8true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 594#L399-8true assume 1 == ~t5_pc~0; 544#L400-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 339#L402-8true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95#L411-8true assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45#L795-8true assume !(0 != activate_threads_~tmp___4~0#1); 231#L801-8true assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 377#L679-1true assume !(1 == ~M_E~0); 113#L684-1true assume !(1 == ~T1_E~0); 247#L689-1true assume !(1 == ~T2_E~0); 574#L694-1true assume !(1 == ~T3_E~0); 245#L699-1true assume !(1 == ~T4_E~0); 357#L704-1true assume !(1 == ~T5_E~0); 219#L709-1true assume !(1 == ~E_M~0); 175#L714-1true assume !(1 == ~E_1~0); 337#L719-1true assume !(1 == ~E_2~0); 513#L724-1true assume !(1 == ~E_3~0); 60#L729-1true assume !(1 == ~E_4~0); 492#L734-1true assume !(1 == ~E_5~0); 129#L740-1true assume true;assume { :end_inline_reset_delta_events } true; 551#L940true [2024-11-17 08:52:05,345 INFO L747 eck$LassoCheckResult]: Loop: 551#L940true assume true; 54#L940-1true assume !false; 548#start_simulation_while_7_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 422#L506true assume !true; 90#L514true assume true; 205#L604true assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3#L419true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 203#L611true assume 0 == ~M_E~0;~M_E~0 := 1; 566#L616true assume !(0 == ~T1_E~0); 69#L621true assume 0 == ~T2_E~0;~T2_E~0 := 1; 227#L626true assume 0 == ~T3_E~0;~T3_E~0 := 1; 532#L631true assume 0 == ~T4_E~0;~T4_E~0 := 1; 557#L636true assume 0 == ~T5_E~0;~T5_E~0 := 1; 197#L641true assume 0 == ~E_M~0;~E_M~0 := 1; 244#L646true assume 0 == ~E_1~0;~E_1~0 := 1; 268#L651true assume 0 == ~E_2~0;~E_2~0 := 1; 392#L656true assume !(0 == ~E_3~0); 416#L661true assume 0 == ~E_4~0;~E_4~0 := 1; 470#L666true assume 0 == ~E_5~0;~E_5~0 := 1; 415#L672true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 395#L304-1true assume 1 == ~m_pc~0; 31#L305-1true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 483#L307-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 374#L316-1true assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 354#L755-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 130#L761-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 388#L323-1true assume !(1 == ~t1_pc~0); 260#L333-1true is_transmit1_triggered_~__retres1~1#1 := 0; 311#L326-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 419#L335-1true assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 444#L763-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 517#L769-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9#L342-1true assume !(1 == ~t2_pc~0); 383#L352-1true is_transmit2_triggered_~__retres1~2#1 := 0; 91#L345-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52#L354-1true assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 279#L771-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 309#L777-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 170#L361-1true assume 1 == ~t3_pc~0; 182#L362-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49#L364-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171#L373-1true assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 359#L779-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 307#L785-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 458#L380-1true assume 1 == ~t4_pc~0; 399#L381-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 295#L383-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 547#L392-1true assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76#L787-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 312#L793-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 433#L399-1true assume !(1 == ~t5_pc~0); 338#L409-1true is_transmit5_triggered_~__retres1~5#1 := 0; 151#L402-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 490#L411-1true assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 303#L795-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 501#L801-1true assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 562#L679true assume 1 == ~M_E~0;~M_E~0 := 2; 453#L684true assume 1 == ~T1_E~0;~T1_E~0 := 2; 240#L689true assume 1 == ~T2_E~0;~T2_E~0 := 2; 384#L694true assume 1 == ~T3_E~0;~T3_E~0 := 2; 201#L699true assume 1 == ~T4_E~0;~T4_E~0 := 2; 518#L704true assume 1 == ~T5_E~0;~T5_E~0 := 2; 128#L709true assume 1 == ~E_M~0;~E_M~0 := 2; 461#L714true assume 1 == ~E_1~0;~E_1~0 := 2; 530#L719true assume 1 == ~E_2~0;~E_2~0 := 2; 26#L724true assume 1 == ~E_3~0;~E_3~0 := 2; 189#L729true assume 1 == ~E_4~0;~E_4~0 := 2; 107#L734true assume 1 == ~E_5~0;~E_5~0 := 2; 507#L740true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 39#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 137#L486-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 44#L497-1true assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 253#L959true assume !(0 == start_simulation_~tmp~3#1); 27#L970true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 570#L464true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 108#L486true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 588#L497true assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 371#L914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 270#L916true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 587#L922true assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 299#L972true assume !(0 != start_simulation_~tmp___0~1#1); 551#L940true [2024-11-17 08:52:05,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,351 INFO L85 PathProgramCache]: Analyzing trace with hash 1976800981, now seen corresponding path program 1 times [2024-11-17 08:52:05,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,360 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606262280] [2024-11-17 08:52:05,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1606262280] [2024-11-17 08:52:05,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1606262280] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:05,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658521585] [2024-11-17 08:52:05,626 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,630 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:05,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,633 INFO L85 PathProgramCache]: Analyzing trace with hash 614871505, now seen corresponding path program 1 times [2024-11-17 08:52:05,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979000204] [2024-11-17 08:52:05,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:05,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:05,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:05,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979000204] [2024-11-17 08:52:05,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979000204] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:05,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:05,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:05,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800051567] [2024-11-17 08:52:05,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:05,680 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:05,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:05,737 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:05,737 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:05,740 INFO L87 Difference]: Start difference. First operand has 596 states, 595 states have (on average 1.4974789915966387) internal successors, (891), 595 states have internal predecessors, (891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:05,796 INFO L93 Difference]: Finished difference Result 586 states and 862 transitions. [2024-11-17 08:52:05,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 586 states and 862 transitions. [2024-11-17 08:52:05,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:05,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 586 states to 579 states and 855 transitions. [2024-11-17 08:52:05,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 579 [2024-11-17 08:52:05,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 579 [2024-11-17 08:52:05,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 579 states and 855 transitions. [2024-11-17 08:52:05,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:05,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 579 states and 855 transitions. [2024-11-17 08:52:05,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 579 states and 855 transitions. [2024-11-17 08:52:05,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 579 to 579. [2024-11-17 08:52:05,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 579 states, 579 states have (on average 1.4766839378238341) internal successors, (855), 578 states have internal predecessors, (855), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:05,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 855 transitions. [2024-11-17 08:52:05,893 INFO L240 hiAutomatonCegarLoop]: Abstraction has 579 states and 855 transitions. [2024-11-17 08:52:05,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:05,898 INFO L425 stractBuchiCegarLoop]: Abstraction has 579 states and 855 transitions. [2024-11-17 08:52:05,899 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:05,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 579 states and 855 transitions. [2024-11-17 08:52:05,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:05,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:05,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:05,906 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:05,910 INFO L745 eck$LassoCheckResult]: Stem: 1769#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1263#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1264#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1604#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1617#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1618#L431 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1632#L436 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1247#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1248#L446 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1467#L451 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1468#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1499#L611-1 assume !(0 == ~M_E~0); 1711#L616-1 assume !(0 == ~T1_E~0); 1712#L621-1 assume !(0 == ~T2_E~0); 1323#L626-1 assume !(0 == ~T3_E~0); 1324#L631-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1504#L636-1 assume !(0 == ~T5_E~0); 1374#L641-1 assume !(0 == ~E_M~0); 1375#L646-1 assume !(0 == ~E_1~0); 1517#L651-1 assume !(0 == ~E_2~0); 1748#L656-1 assume !(0 == ~E_3~0); 1691#L661-1 assume !(0 == ~E_4~0); 1692#L666-1 assume !(0 == ~E_5~0); 1686#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1516#L304-8 assume 1 == ~m_pc~0; 1395#L305-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1396#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1265#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1237#L755-8 assume !(0 != activate_threads_~tmp~1#1); 1238#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1366#L323-8 assume 1 == ~t1_pc~0; 1460#L324-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1620#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1616#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1613#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 1614#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1552#L342-8 assume 1 == ~t2_pc~0; 1436#L343-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1389#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1639#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1669#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 1600#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1601#L361-8 assume 1 == ~t3_pc~0; 1479#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1480#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1229#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1230#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 1738#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1335#L380-8 assume 1 == ~t4_pc~0; 1336#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1494#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1534#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1301#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 1302#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1759#L399-8 assume 1 == ~t5_pc~0; 1767#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1394#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1379#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1283#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 1284#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1579#L679-1 assume !(1 == ~M_E~0); 1410#L684-1 assume !(1 == ~T1_E~0); 1411#L689-1 assume !(1 == ~T2_E~0); 1597#L694-1 assume !(1 == ~T3_E~0); 1594#L699-1 assume !(1 == ~T4_E~0); 1595#L704-1 assume !(1 == ~T5_E~0); 1564#L709-1 assume !(1 == ~E_M~0); 1507#L714-1 assume !(1 == ~E_1~0); 1508#L719-1 assume !(1 == ~E_2~0); 1684#L724-1 assume !(1 == ~E_3~0); 1315#L729-1 assume !(1 == ~E_4~0); 1316#L734-1 assume !(1 == ~E_5~0); 1439#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 1440#L940 [2024-11-17 08:52:05,911 INFO L747 eck$LassoCheckResult]: Loop: 1440#L940 assume true; 1303#L940-1 assume !false; 1304#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1408#L506 assume true; 1730#L506-1 assume !false; 1590#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1509#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1510#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1732#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1574#L511 assume !(0 != eval_~tmp~0#1); 1369#L514 assume true; 1370#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1196#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1197#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 1547#L616 assume !(0 == ~T1_E~0); 1329#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1330#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1573#L631 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1763#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1538#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 1539#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 1593#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 1621#L656 assume !(0 == ~E_3~0); 1714#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 1727#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 1726#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1718#L304-1 assume 1 == ~m_pc~0; 1256#L305-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1257#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1701#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1689#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1441#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1442#L323-1 assume 1 == ~t1_pc~0; 1713#L324-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1612#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1662#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1728#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1739#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1206#L342-1 assume !(1 == ~t2_pc~0); 1207#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1371#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1299#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1300#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1630#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1500#L361-1 assume !(1 == ~t3_pc~0); 1490#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1291#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1292#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1502#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1657#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1658#L380-1 assume !(1 == ~t4_pc~0); 1602#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1603#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1644#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1342#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1343#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1663#L399-1 assume 1 == ~t5_pc~0; 1571#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1477#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1478#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1653#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1654#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1756#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 1743#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1588#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1589#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1543#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1544#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1437#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 1438#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 1747#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 1243#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 1244#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 1401#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 1402#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1268#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1269#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1281#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1282#L959 assume !(0 == start_simulation_~tmp~3#1); 1245#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1246#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1403#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1404#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1700#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1622#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1623#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1646#L972 assume !(0 != start_simulation_~tmp___0~1#1); 1440#L940 [2024-11-17 08:52:05,912 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:05,912 INFO L85 PathProgramCache]: Analyzing trace with hash -2071853228, now seen corresponding path program 1 times [2024-11-17 08:52:05,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:05,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760348377] [2024-11-17 08:52:05,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:05,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:05,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760348377] [2024-11-17 08:52:06,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760348377] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:06,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900827048] [2024-11-17 08:52:06,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,021 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:06,022 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,023 INFO L85 PathProgramCache]: Analyzing trace with hash 359999896, now seen corresponding path program 1 times [2024-11-17 08:52:06,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049513185] [2024-11-17 08:52:06,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049513185] [2024-11-17 08:52:06,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049513185] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425874874] [2024-11-17 08:52:06,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,190 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:06,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:06,191 INFO L87 Difference]: Start difference. First operand 579 states and 855 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,219 INFO L93 Difference]: Finished difference Result 579 states and 854 transitions. [2024-11-17 08:52:06,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 579 states and 854 transitions. [2024-11-17 08:52:06,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:06,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 579 states to 579 states and 854 transitions. [2024-11-17 08:52:06,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 579 [2024-11-17 08:52:06,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 579 [2024-11-17 08:52:06,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 579 states and 854 transitions. [2024-11-17 08:52:06,231 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,232 INFO L218 hiAutomatonCegarLoop]: Abstraction has 579 states and 854 transitions. [2024-11-17 08:52:06,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 579 states and 854 transitions. [2024-11-17 08:52:06,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 579 to 579. [2024-11-17 08:52:06,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 579 states, 579 states have (on average 1.4749568221070812) internal successors, (854), 578 states have internal predecessors, (854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 854 transitions. [2024-11-17 08:52:06,257 INFO L240 hiAutomatonCegarLoop]: Abstraction has 579 states and 854 transitions. [2024-11-17 08:52:06,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:06,259 INFO L425 stractBuchiCegarLoop]: Abstraction has 579 states and 854 transitions. [2024-11-17 08:52:06,261 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:06,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 579 states and 854 transitions. [2024-11-17 08:52:06,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:06,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:06,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:06,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,269 INFO L745 eck$LassoCheckResult]: Stem: 2936#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2432#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2433#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2771#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2784#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 2785#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2799#L436 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2414#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2415#L446 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2634#L451 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2635#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2666#L611-1 assume !(0 == ~M_E~0); 2879#L616-1 assume !(0 == ~T1_E~0); 2880#L621-1 assume !(0 == ~T2_E~0); 2490#L626-1 assume !(0 == ~T3_E~0); 2491#L631-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2672#L636-1 assume !(0 == ~T5_E~0); 2541#L641-1 assume !(0 == ~E_M~0); 2542#L646-1 assume !(0 == ~E_1~0); 2684#L651-1 assume !(0 == ~E_2~0); 2915#L656-1 assume !(0 == ~E_3~0); 2858#L661-1 assume !(0 == ~E_4~0); 2859#L666-1 assume !(0 == ~E_5~0); 2853#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2683#L304-8 assume 1 == ~m_pc~0; 2562#L305-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2563#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2434#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2406#L755-8 assume !(0 != activate_threads_~tmp~1#1); 2407#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2533#L323-8 assume 1 == ~t1_pc~0; 2627#L324-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2787#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2783#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2780#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 2781#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2719#L342-8 assume 1 == ~t2_pc~0; 2603#L343-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2558#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2806#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2836#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 2767#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2768#L361-8 assume 1 == ~t3_pc~0; 2646#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2647#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2396#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2397#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 2905#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2502#L380-8 assume 1 == ~t4_pc~0; 2503#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2661#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2701#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2468#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 2469#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2926#L399-8 assume 1 == ~t5_pc~0; 2934#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2561#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2546#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2450#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 2451#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2746#L679-1 assume !(1 == ~M_E~0); 2577#L684-1 assume !(1 == ~T1_E~0); 2578#L689-1 assume !(1 == ~T2_E~0); 2764#L694-1 assume !(1 == ~T3_E~0); 2761#L699-1 assume !(1 == ~T4_E~0); 2762#L704-1 assume !(1 == ~T5_E~0); 2731#L709-1 assume !(1 == ~E_M~0); 2674#L714-1 assume !(1 == ~E_1~0); 2675#L719-1 assume !(1 == ~E_2~0); 2851#L724-1 assume !(1 == ~E_3~0); 2482#L729-1 assume !(1 == ~E_4~0); 2483#L734-1 assume !(1 == ~E_5~0); 2608#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 2609#L940 [2024-11-17 08:52:06,269 INFO L747 eck$LassoCheckResult]: Loop: 2609#L940 assume true; 2470#L940-1 assume !false; 2471#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2575#L506 assume true; 2897#L506-1 assume !false; 2757#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2676#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2677#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2899#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2741#L511 assume !(0 != eval_~tmp~0#1); 2537#L514 assume true; 2538#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2363#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2364#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 2714#L616 assume !(0 == ~T1_E~0); 2496#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2497#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2740#L631 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2930#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2708#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 2709#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 2760#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 2788#L656 assume !(0 == ~E_3~0); 2881#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 2894#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 2893#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2885#L304-1 assume 1 == ~m_pc~0; 2425#L305-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2426#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2868#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2856#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2606#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2607#L323-1 assume !(1 == ~t1_pc~0); 2778#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 2779#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2829#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2895#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2906#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2371#L342-1 assume !(1 == ~t2_pc~0); 2372#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 2536#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2466#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2467#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2797#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2667#L361-1 assume !(1 == ~t3_pc~0); 2657#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 2458#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2459#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2669#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2824#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2825#L380-1 assume !(1 == ~t4_pc~0); 2769#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 2770#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2811#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2509#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2510#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2830#L399-1 assume 1 == ~t5_pc~0; 2738#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2644#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2645#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2820#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2821#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2923#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 2910#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2755#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2756#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2710#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2711#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2604#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 2605#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 2914#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 2410#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 2411#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 2568#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 2569#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2436#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2437#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2448#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2449#L959 assume !(0 == start_simulation_~tmp~3#1); 2412#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2413#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2570#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2571#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2867#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2789#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2790#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2813#L972 assume !(0 != start_simulation_~tmp___0~1#1); 2609#L940 [2024-11-17 08:52:06,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,271 INFO L85 PathProgramCache]: Analyzing trace with hash -401339659, now seen corresponding path program 1 times [2024-11-17 08:52:06,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932052101] [2024-11-17 08:52:06,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [932052101] [2024-11-17 08:52:06,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [932052101] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,326 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:06,326 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670593911] [2024-11-17 08:52:06,326 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,326 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:06,326 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,327 INFO L85 PathProgramCache]: Analyzing trace with hash 177373595, now seen corresponding path program 1 times [2024-11-17 08:52:06,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845801226] [2024-11-17 08:52:06,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,401 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845801226] [2024-11-17 08:52:06,402 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1845801226] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,402 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,402 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,402 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371268035] [2024-11-17 08:52:06,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,402 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,403 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:06,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:06,403 INFO L87 Difference]: Start difference. First operand 579 states and 854 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,419 INFO L93 Difference]: Finished difference Result 579 states and 853 transitions. [2024-11-17 08:52:06,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 579 states and 853 transitions. [2024-11-17 08:52:06,422 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:06,425 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 579 states to 579 states and 853 transitions. [2024-11-17 08:52:06,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 579 [2024-11-17 08:52:06,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 579 [2024-11-17 08:52:06,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 579 states and 853 transitions. [2024-11-17 08:52:06,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 579 states and 853 transitions. [2024-11-17 08:52:06,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 579 states and 853 transitions. [2024-11-17 08:52:06,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 579 to 579. [2024-11-17 08:52:06,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 579 states, 579 states have (on average 1.4732297063903281) internal successors, (853), 578 states have internal predecessors, (853), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 853 transitions. [2024-11-17 08:52:06,436 INFO L240 hiAutomatonCegarLoop]: Abstraction has 579 states and 853 transitions. [2024-11-17 08:52:06,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:06,437 INFO L425 stractBuchiCegarLoop]: Abstraction has 579 states and 853 transitions. [2024-11-17 08:52:06,437 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:06,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 579 states and 853 transitions. [2024-11-17 08:52:06,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:06,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:06,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:06,441 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,441 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,442 INFO L745 eck$LassoCheckResult]: Stem: 4103#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3599#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3600#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3938#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3951#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 3952#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3966#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3581#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3582#L446 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3801#L451 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3802#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3833#L611-1 assume !(0 == ~M_E~0); 4046#L616-1 assume !(0 == ~T1_E~0); 4047#L621-1 assume !(0 == ~T2_E~0); 3660#L626-1 assume !(0 == ~T3_E~0); 3661#L631-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3839#L636-1 assume !(0 == ~T5_E~0); 3708#L641-1 assume !(0 == ~E_M~0); 3709#L646-1 assume !(0 == ~E_1~0); 3851#L651-1 assume !(0 == ~E_2~0); 4082#L656-1 assume !(0 == ~E_3~0); 4025#L661-1 assume !(0 == ~E_4~0); 4026#L666-1 assume !(0 == ~E_5~0); 4020#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3850#L304-8 assume 1 == ~m_pc~0; 3729#L305-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3730#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3601#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3575#L755-8 assume !(0 != activate_threads_~tmp~1#1); 3576#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3700#L323-8 assume 1 == ~t1_pc~0; 3794#L324-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3954#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3950#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3947#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 3948#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3886#L342-8 assume 1 == ~t2_pc~0; 3770#L343-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3725#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3973#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4005#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 3934#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3935#L361-8 assume 1 == ~t3_pc~0; 3813#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3814#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3563#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3564#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 4072#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3669#L380-8 assume 1 == ~t4_pc~0; 3670#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3828#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3868#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3635#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 3636#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4093#L399-8 assume 1 == ~t5_pc~0; 4101#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3728#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3713#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3617#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 3618#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3913#L679-1 assume !(1 == ~M_E~0); 3744#L684-1 assume !(1 == ~T1_E~0); 3745#L689-1 assume !(1 == ~T2_E~0); 3931#L694-1 assume !(1 == ~T3_E~0); 3928#L699-1 assume !(1 == ~T4_E~0); 3929#L704-1 assume !(1 == ~T5_E~0); 3898#L709-1 assume !(1 == ~E_M~0); 3844#L714-1 assume !(1 == ~E_1~0); 3845#L719-1 assume !(1 == ~E_2~0); 4018#L724-1 assume !(1 == ~E_3~0); 3649#L729-1 assume !(1 == ~E_4~0); 3650#L734-1 assume !(1 == ~E_5~0); 3775#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 3776#L940 [2024-11-17 08:52:06,442 INFO L747 eck$LassoCheckResult]: Loop: 3776#L940 assume true; 3637#L940-1 assume !false; 3638#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3742#L506 assume true; 4064#L506-1 assume !false; 3924#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3846#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3847#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4066#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3910#L511 assume !(0 != eval_~tmp~0#1); 3704#L514 assume true; 3705#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3530#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3531#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 3881#L616 assume !(0 == ~T1_E~0); 3663#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3664#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3907#L631 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4097#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3872#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 3873#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 3927#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 3955#L656 assume !(0 == ~E_3~0); 4048#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 4061#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 4060#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4052#L304-1 assume 1 == ~m_pc~0; 3588#L305-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3589#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4035#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4023#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3773#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3774#L323-1 assume !(1 == ~t1_pc~0); 3945#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 3946#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3996#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4062#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4073#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3538#L342-1 assume !(1 == ~t2_pc~0); 3539#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 3703#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3633#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3634#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3964#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3834#L361-1 assume !(1 == ~t3_pc~0); 3824#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 3625#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3626#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3836#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3991#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3992#L380-1 assume !(1 == ~t4_pc~0); 3936#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 3937#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3978#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3676#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3677#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3997#L399-1 assume 1 == ~t5_pc~0; 3905#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3811#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3812#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3987#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3988#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4091#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 4077#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3922#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3923#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3879#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3880#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3771#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 3772#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 4081#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 3577#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 3578#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 3735#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 3736#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3603#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3604#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3615#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3616#L959 assume !(0 == start_simulation_~tmp~3#1); 3579#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3580#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3737#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3738#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4034#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3956#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3957#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3983#L972 assume !(0 != start_simulation_~tmp___0~1#1); 3776#L940 [2024-11-17 08:52:06,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,443 INFO L85 PathProgramCache]: Analyzing trace with hash 206737204, now seen corresponding path program 1 times [2024-11-17 08:52:06,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929525678] [2024-11-17 08:52:06,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929525678] [2024-11-17 08:52:06,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929525678] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:06,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055464989] [2024-11-17 08:52:06,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,481 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:06,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,481 INFO L85 PathProgramCache]: Analyzing trace with hash 177373595, now seen corresponding path program 2 times [2024-11-17 08:52:06,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596295396] [2024-11-17 08:52:06,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596295396] [2024-11-17 08:52:06,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596295396] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1403159803] [2024-11-17 08:52:06,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,561 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:06,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:06,562 INFO L87 Difference]: Start difference. First operand 579 states and 853 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,573 INFO L93 Difference]: Finished difference Result 579 states and 852 transitions. [2024-11-17 08:52:06,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 579 states and 852 transitions. [2024-11-17 08:52:06,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:06,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 579 states to 579 states and 852 transitions. [2024-11-17 08:52:06,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 579 [2024-11-17 08:52:06,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 579 [2024-11-17 08:52:06,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 579 states and 852 transitions. [2024-11-17 08:52:06,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 579 states and 852 transitions. [2024-11-17 08:52:06,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 579 states and 852 transitions. [2024-11-17 08:52:06,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 579 to 579. [2024-11-17 08:52:06,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 579 states, 579 states have (on average 1.471502590673575) internal successors, (852), 578 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 852 transitions. [2024-11-17 08:52:06,593 INFO L240 hiAutomatonCegarLoop]: Abstraction has 579 states and 852 transitions. [2024-11-17 08:52:06,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:06,595 INFO L425 stractBuchiCegarLoop]: Abstraction has 579 states and 852 transitions. [2024-11-17 08:52:06,595 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:06,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 579 states and 852 transitions. [2024-11-17 08:52:06,598 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:06,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:06,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:06,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,601 INFO L745 eck$LassoCheckResult]: Stem: 5270#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4764#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4765#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5105#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5118#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 5119#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5132#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4748#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4749#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4968#L451 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4969#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5000#L611-1 assume !(0 == ~M_E~0); 5212#L616-1 assume !(0 == ~T1_E~0); 5213#L621-1 assume !(0 == ~T2_E~0); 4824#L626-1 assume !(0 == ~T3_E~0); 4825#L631-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5005#L636-1 assume !(0 == ~T5_E~0); 4875#L641-1 assume !(0 == ~E_M~0); 4876#L646-1 assume !(0 == ~E_1~0); 5018#L651-1 assume !(0 == ~E_2~0); 5249#L656-1 assume !(0 == ~E_3~0); 5192#L661-1 assume !(0 == ~E_4~0); 5193#L666-1 assume !(0 == ~E_5~0); 5187#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5017#L304-8 assume 1 == ~m_pc~0; 4896#L305-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4897#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4766#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4738#L755-8 assume !(0 != activate_threads_~tmp~1#1); 4739#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4867#L323-8 assume 1 == ~t1_pc~0; 4961#L324-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5121#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5117#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5114#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 5115#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5053#L342-8 assume 1 == ~t2_pc~0; 4937#L343-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4890#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5140#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5170#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 5101#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5102#L361-8 assume 1 == ~t3_pc~0; 4980#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4981#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4730#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4731#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 5239#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4836#L380-8 assume 1 == ~t4_pc~0; 4837#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4994#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5035#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4802#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 4803#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5260#L399-8 assume 1 == ~t5_pc~0; 5268#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4895#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4880#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4784#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 4785#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5079#L679-1 assume !(1 == ~M_E~0); 4911#L684-1 assume !(1 == ~T1_E~0); 4912#L689-1 assume !(1 == ~T2_E~0); 5098#L694-1 assume !(1 == ~T3_E~0); 5095#L699-1 assume !(1 == ~T4_E~0); 5096#L704-1 assume !(1 == ~T5_E~0); 5065#L709-1 assume !(1 == ~E_M~0); 5007#L714-1 assume !(1 == ~E_1~0); 5008#L719-1 assume !(1 == ~E_2~0); 5185#L724-1 assume !(1 == ~E_3~0); 4816#L729-1 assume !(1 == ~E_4~0); 4817#L734-1 assume !(1 == ~E_5~0); 4940#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 4941#L940 [2024-11-17 08:52:06,602 INFO L747 eck$LassoCheckResult]: Loop: 4941#L940 assume true; 4804#L940-1 assume !false; 4805#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4909#L506 assume true; 5231#L506-1 assume !false; 5091#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5009#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5010#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5232#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5075#L511 assume !(0 != eval_~tmp~0#1); 4870#L514 assume true; 4871#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4694#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4695#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 5048#L616 assume !(0 == ~T1_E~0); 4830#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4831#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5074#L631 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5264#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5039#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 5040#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 5094#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 5122#L656 assume !(0 == ~E_3~0); 5215#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 5228#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 5227#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5219#L304-1 assume 1 == ~m_pc~0; 4755#L305-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4756#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5202#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5190#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4942#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4943#L323-1 assume !(1 == ~t1_pc~0); 5112#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 5113#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5163#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5229#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5240#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4705#L342-1 assume !(1 == ~t2_pc~0); 4706#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 4872#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4800#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4801#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5131#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5001#L361-1 assume 1 == ~t3_pc~0; 5002#L362-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4792#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4793#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5003#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5158#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5159#L380-1 assume 1 == ~t4_pc~0; 5221#L381-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5104#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5145#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4843#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4844#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5164#L399-1 assume 1 == ~t5_pc~0; 5072#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4978#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4979#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5154#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5155#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5258#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 5244#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5089#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5090#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5046#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5047#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4938#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 4939#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 5248#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 4744#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 4745#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 4902#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 4903#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4770#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4771#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4782#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4783#L959 assume !(0 == start_simulation_~tmp~3#1); 4746#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4747#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4904#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4905#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5201#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5123#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5124#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5150#L972 assume !(0 != start_simulation_~tmp___0~1#1); 4941#L940 [2024-11-17 08:52:06,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,602 INFO L85 PathProgramCache]: Analyzing trace with hash -1097656525, now seen corresponding path program 1 times [2024-11-17 08:52:06,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965807251] [2024-11-17 08:52:06,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965807251] [2024-11-17 08:52:06,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965807251] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:06,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404903087] [2024-11-17 08:52:06,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,640 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:06,641 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,641 INFO L85 PathProgramCache]: Analyzing trace with hash 150084181, now seen corresponding path program 1 times [2024-11-17 08:52:06,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,641 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846595643] [2024-11-17 08:52:06,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,714 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846595643] [2024-11-17 08:52:06,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [846595643] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,715 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31246150] [2024-11-17 08:52:06,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,715 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,715 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:06,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:06,716 INFO L87 Difference]: Start difference. First operand 579 states and 852 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,730 INFO L93 Difference]: Finished difference Result 579 states and 851 transitions. [2024-11-17 08:52:06,730 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 579 states and 851 transitions. [2024-11-17 08:52:06,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:06,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 579 states to 579 states and 851 transitions. [2024-11-17 08:52:06,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 579 [2024-11-17 08:52:06,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 579 [2024-11-17 08:52:06,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 579 states and 851 transitions. [2024-11-17 08:52:06,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:06,738 INFO L218 hiAutomatonCegarLoop]: Abstraction has 579 states and 851 transitions. [2024-11-17 08:52:06,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 579 states and 851 transitions. [2024-11-17 08:52:06,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 579 to 579. [2024-11-17 08:52:06,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 579 states, 579 states have (on average 1.4697754749568221) internal successors, (851), 578 states have internal predecessors, (851), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 851 transitions. [2024-11-17 08:52:06,746 INFO L240 hiAutomatonCegarLoop]: Abstraction has 579 states and 851 transitions. [2024-11-17 08:52:06,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:06,748 INFO L425 stractBuchiCegarLoop]: Abstraction has 579 states and 851 transitions. [2024-11-17 08:52:06,749 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:06,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 579 states and 851 transitions. [2024-11-17 08:52:06,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 500 [2024-11-17 08:52:06,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:06,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:06,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:06,754 INFO L745 eck$LassoCheckResult]: Stem: 6437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5931#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5932#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6272#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6285#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 6286#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6299#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5915#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5916#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6135#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6136#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6167#L611-1 assume !(0 == ~M_E~0); 6379#L616-1 assume !(0 == ~T1_E~0); 6380#L621-1 assume !(0 == ~T2_E~0); 5991#L626-1 assume !(0 == ~T3_E~0); 5992#L631-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6172#L636-1 assume !(0 == ~T5_E~0); 6042#L641-1 assume !(0 == ~E_M~0); 6043#L646-1 assume !(0 == ~E_1~0); 6185#L651-1 assume !(0 == ~E_2~0); 6416#L656-1 assume !(0 == ~E_3~0); 6359#L661-1 assume !(0 == ~E_4~0); 6360#L666-1 assume !(0 == ~E_5~0); 6354#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6184#L304-8 assume 1 == ~m_pc~0; 6063#L305-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6064#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5933#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5905#L755-8 assume !(0 != activate_threads_~tmp~1#1); 5906#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6034#L323-8 assume 1 == ~t1_pc~0; 6128#L324-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6288#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6284#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6281#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 6282#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6220#L342-8 assume 1 == ~t2_pc~0; 6104#L343-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6057#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6307#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6337#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 6268#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6269#L361-8 assume 1 == ~t3_pc~0; 6147#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6148#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5897#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5898#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 6406#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6003#L380-8 assume 1 == ~t4_pc~0; 6004#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6161#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6202#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5969#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 5970#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6427#L399-8 assume 1 == ~t5_pc~0; 6435#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6062#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6047#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5951#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 5952#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6246#L679-1 assume !(1 == ~M_E~0); 6078#L684-1 assume !(1 == ~T1_E~0); 6079#L689-1 assume !(1 == ~T2_E~0); 6265#L694-1 assume !(1 == ~T3_E~0); 6262#L699-1 assume !(1 == ~T4_E~0); 6263#L704-1 assume !(1 == ~T5_E~0); 6232#L709-1 assume !(1 == ~E_M~0); 6174#L714-1 assume !(1 == ~E_1~0); 6175#L719-1 assume !(1 == ~E_2~0); 6352#L724-1 assume !(1 == ~E_3~0); 5983#L729-1 assume !(1 == ~E_4~0); 5984#L734-1 assume !(1 == ~E_5~0); 6107#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 6108#L940 [2024-11-17 08:52:06,754 INFO L747 eck$LassoCheckResult]: Loop: 6108#L940 assume true; 5971#L940-1 assume !false; 5972#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6076#L506 assume true; 6398#L506-1 assume !false; 6258#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6176#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6177#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6399#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6242#L511 assume !(0 != eval_~tmp~0#1); 6037#L514 assume true; 6038#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5861#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5862#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 6215#L616 assume !(0 == ~T1_E~0); 5997#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5998#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6241#L631 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6431#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6206#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 6207#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 6261#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 6289#L656 assume !(0 == ~E_3~0); 6382#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 6395#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 6394#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6386#L304-1 assume 1 == ~m_pc~0; 5922#L305-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5923#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6369#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6357#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6109#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6110#L323-1 assume !(1 == ~t1_pc~0); 6279#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 6280#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6330#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6396#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6407#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5872#L342-1 assume !(1 == ~t2_pc~0); 5873#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 6039#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5967#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5968#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6298#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6168#L361-1 assume 1 == ~t3_pc~0; 6169#L362-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5959#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5960#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6170#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6325#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6326#L380-1 assume 1 == ~t4_pc~0; 6388#L381-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6271#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6312#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6010#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6011#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6331#L399-1 assume !(1 == ~t5_pc~0); 6240#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 6145#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6146#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6321#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6322#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6425#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 6411#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6256#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6257#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6213#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6214#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6105#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 6106#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 6415#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 5911#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 5912#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 6069#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 6070#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5937#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5938#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5949#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5950#L959 assume !(0 == start_simulation_~tmp~3#1); 5913#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5914#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6071#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6072#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6368#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6290#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6291#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6317#L972 assume !(0 != start_simulation_~tmp___0~1#1); 6108#L940 [2024-11-17 08:52:06,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1077023572, now seen corresponding path program 1 times [2024-11-17 08:52:06,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054594697] [2024-11-17 08:52:06,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054594697] [2024-11-17 08:52:06,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054594697] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:06,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638544382] [2024-11-17 08:52:06,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,825 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:06,825 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:06,825 INFO L85 PathProgramCache]: Analyzing trace with hash 478251864, now seen corresponding path program 1 times [2024-11-17 08:52:06,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:06,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1423207678] [2024-11-17 08:52:06,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:06,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:06,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:06,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:06,887 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:06,887 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1423207678] [2024-11-17 08:52:06,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1423207678] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:06,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:06,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:06,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1474876700] [2024-11-17 08:52:06,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:06,888 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:06,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:06,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:06,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:06,890 INFO L87 Difference]: Start difference. First operand 579 states and 851 transitions. cyclomatic complexity: 273 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:06,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:06,991 INFO L93 Difference]: Finished difference Result 1035 states and 1512 transitions. [2024-11-17 08:52:06,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1035 states and 1512 transitions. [2024-11-17 08:52:06,997 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 944 [2024-11-17 08:52:07,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1035 states to 1035 states and 1512 transitions. [2024-11-17 08:52:07,002 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1035 [2024-11-17 08:52:07,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1035 [2024-11-17 08:52:07,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1035 states and 1512 transitions. [2024-11-17 08:52:07,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,005 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1035 states and 1512 transitions. [2024-11-17 08:52:07,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1035 states and 1512 transitions. [2024-11-17 08:52:07,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1035 to 1035. [2024-11-17 08:52:07,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1035 states, 1035 states have (on average 1.4608695652173913) internal successors, (1512), 1034 states have internal predecessors, (1512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1035 states to 1035 states and 1512 transitions. [2024-11-17 08:52:07,027 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1035 states and 1512 transitions. [2024-11-17 08:52:07,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:07,029 INFO L425 stractBuchiCegarLoop]: Abstraction has 1035 states and 1512 transitions. [2024-11-17 08:52:07,030 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:52:07,030 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1035 states and 1512 transitions. [2024-11-17 08:52:07,034 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 944 [2024-11-17 08:52:07,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,037 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,037 INFO L745 eck$LassoCheckResult]: Stem: 8143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7557#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7558#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7920#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7933#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 7934#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7948#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7541#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7542#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7766#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7767#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7800#L611-1 assume !(0 == ~M_E~0); 8046#L616-1 assume !(0 == ~T1_E~0); 8047#L621-1 assume !(0 == ~T2_E~0); 7617#L626-1 assume !(0 == ~T3_E~0); 7618#L631-1 assume !(0 == ~T4_E~0); 7806#L636-1 assume !(0 == ~T5_E~0); 7668#L641-1 assume !(0 == ~E_M~0); 7669#L646-1 assume !(0 == ~E_1~0); 7823#L651-1 assume !(0 == ~E_2~0); 8102#L656-1 assume !(0 == ~E_3~0); 8018#L661-1 assume !(0 == ~E_4~0); 8019#L666-1 assume !(0 == ~E_5~0); 8013#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7822#L304-8 assume 1 == ~m_pc~0; 7689#L305-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7690#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7559#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7531#L755-8 assume !(0 != activate_threads_~tmp~1#1); 7532#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7660#L323-8 assume 1 == ~t1_pc~0; 7759#L324-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7936#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7932#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7929#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 7930#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7862#L342-8 assume 1 == ~t2_pc~0; 7735#L343-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7683#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7958#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7991#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 7916#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7917#L361-8 assume 1 == ~t3_pc~0; 7778#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7779#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7523#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7524#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 8085#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7629#L380-8 assume 1 == ~t4_pc~0; 7630#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7794#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7840#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7595#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 7596#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8119#L399-8 assume 1 == ~t5_pc~0; 8133#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7688#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7673#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7577#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 7578#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7890#L679-1 assume 1 == ~M_E~0;~M_E~0 := 2; 8037#L684-1 assume !(1 == ~T1_E~0); 8350#L689-1 assume !(1 == ~T2_E~0); 8349#L694-1 assume !(1 == ~T3_E~0); 8348#L699-1 assume !(1 == ~T4_E~0); 7909#L704-1 assume !(1 == ~T5_E~0); 8308#L709-1 assume !(1 == ~E_M~0); 8306#L714-1 assume !(1 == ~E_1~0); 8304#L719-1 assume !(1 == ~E_2~0); 8302#L724-1 assume !(1 == ~E_3~0); 8300#L729-1 assume !(1 == ~E_4~0); 8299#L734-1 assume !(1 == ~E_5~0); 7738#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 7739#L940 [2024-11-17 08:52:07,040 INFO L747 eck$LassoCheckResult]: Loop: 7739#L940 assume true; 7597#L940-1 assume !false; 7598#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8154#L506 assume true; 8153#L506-1 assume !false; 8152#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7812#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7813#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 8109#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8110#L511 assume !(0 != eval_~tmp~0#1); 7663#L514 assume true; 7664#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7487#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7488#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 8138#L616 assume !(0 == ~T1_E~0); 7623#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7624#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7884#L631 assume !(0 == ~T4_E~0); 8127#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7844#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 7845#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 7907#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 7937#L656 assume !(0 == ~E_3~0); 8049#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 8064#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 8063#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8053#L304-1 assume 1 == ~m_pc~0; 7548#L305-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7549#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8032#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8016#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7740#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7741#L323-1 assume 1 == ~t1_pc~0; 8048#L324-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7928#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7981#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8066#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8088#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7498#L342-1 assume !(1 == ~t2_pc~0); 7499#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 7665#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7593#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7594#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7947#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7801#L361-1 assume 1 == ~t3_pc~0; 7802#L362-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7585#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7586#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7803#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7976#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7977#L380-1 assume 1 == ~t4_pc~0; 8056#L381-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7919#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7963#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7636#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7637#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7982#L399-1 assume 1 == ~t5_pc~0; 7882#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7776#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7777#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7972#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7973#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8116#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 8092#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7901#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7902#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7851#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7852#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7736#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 7737#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 8097#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 7537#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 7538#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 7695#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 7696#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7563#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7564#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7575#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7576#L959 assume !(0 == start_simulation_~tmp~3#1); 7539#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7540#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8309#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 8307#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 8305#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8303#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8301#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7968#L972 assume !(0 != start_simulation_~tmp___0~1#1); 7739#L940 [2024-11-17 08:52:07,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,040 INFO L85 PathProgramCache]: Analyzing trace with hash -560192526, now seen corresponding path program 1 times [2024-11-17 08:52:07,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889282859] [2024-11-17 08:52:07,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889282859] [2024-11-17 08:52:07,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889282859] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,083 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:07,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192407577] [2024-11-17 08:52:07,084 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,084 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:07,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1286939377, now seen corresponding path program 1 times [2024-11-17 08:52:07,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724787637] [2024-11-17 08:52:07,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,163 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,163 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724787637] [2024-11-17 08:52:07,163 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724787637] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,163 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:07,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237151016] [2024-11-17 08:52:07,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,164 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:07,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:07,164 INFO L87 Difference]: Start difference. First operand 1035 states and 1512 transitions. cyclomatic complexity: 479 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,234 INFO L93 Difference]: Finished difference Result 1945 states and 2805 transitions. [2024-11-17 08:52:07,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1945 states and 2805 transitions. [2024-11-17 08:52:07,245 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1851 [2024-11-17 08:52:07,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1945 states to 1945 states and 2805 transitions. [2024-11-17 08:52:07,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1945 [2024-11-17 08:52:07,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1945 [2024-11-17 08:52:07,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1945 states and 2805 transitions. [2024-11-17 08:52:07,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1945 states and 2805 transitions. [2024-11-17 08:52:07,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1945 states and 2805 transitions. [2024-11-17 08:52:07,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1945 to 1863. [2024-11-17 08:52:07,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1863 states, 1863 states have (on average 1.4444444444444444) internal successors, (2691), 1862 states have internal predecessors, (2691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1863 states to 1863 states and 2691 transitions. [2024-11-17 08:52:07,291 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1863 states and 2691 transitions. [2024-11-17 08:52:07,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:07,293 INFO L425 stractBuchiCegarLoop]: Abstraction has 1863 states and 2691 transitions. [2024-11-17 08:52:07,293 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:52:07,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1863 states and 2691 transitions. [2024-11-17 08:52:07,302 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1769 [2024-11-17 08:52:07,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,303 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,303 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,304 INFO L745 eck$LassoCheckResult]: Stem: 11171#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 10546#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 10547#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10902#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10916#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 10917#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10933#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10530#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10531#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10749#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10750#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10783#L611-1 assume !(0 == ~M_E~0); 11046#L616-1 assume !(0 == ~T1_E~0); 11047#L621-1 assume !(0 == ~T2_E~0); 10606#L626-1 assume !(0 == ~T3_E~0); 10607#L631-1 assume !(0 == ~T4_E~0); 10788#L636-1 assume !(0 == ~T5_E~0); 10657#L641-1 assume !(0 == ~E_M~0); 10658#L646-1 assume !(0 == ~E_1~0); 10805#L651-1 assume !(0 == ~E_2~0); 11111#L656-1 assume !(0 == ~E_3~0); 11019#L661-1 assume !(0 == ~E_4~0); 11020#L666-1 assume !(0 == ~E_5~0); 11011#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10803#L304-8 assume !(1 == ~m_pc~0); 10804#L314-8 is_master_triggered_~__retres1~0#1 := 0; 11160#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10548#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10520#L755-8 assume !(0 != activate_threads_~tmp~1#1); 10521#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10649#L323-8 assume 1 == ~t1_pc~0; 10741#L324-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10919#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10915#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10912#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 10913#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10845#L342-8 assume 1 == ~t2_pc~0; 10716#L343-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10672#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10942#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10984#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 10898#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10899#L361-8 assume 1 == ~t3_pc~0; 10761#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10762#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10512#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10513#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 11094#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10618#L380-8 assume 1 == ~t4_pc~0; 10619#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10777#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10826#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10584#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 10585#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11140#L399-8 assume 1 == ~t5_pc~0; 11158#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10677#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10662#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10566#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 10567#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10874#L679-1 assume 1 == ~M_E~0;~M_E~0 := 2; 11037#L684-1 assume !(1 == ~T1_E~0); 12243#L689-1 assume !(1 == ~T2_E~0); 12242#L694-1 assume !(1 == ~T3_E~0); 12241#L699-1 assume !(1 == ~T4_E~0); 10893#L704-1 assume !(1 == ~T5_E~0); 12240#L709-1 assume !(1 == ~E_M~0); 12239#L714-1 assume !(1 == ~E_1~0); 12238#L719-1 assume !(1 == ~E_2~0); 12235#L724-1 assume !(1 == ~E_3~0); 12233#L729-1 assume !(1 == ~E_4~0); 12231#L734-1 assume !(1 == ~E_5~0); 12229#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 12226#L940 [2024-11-17 08:52:07,304 INFO L747 eck$LassoCheckResult]: Loop: 12226#L940 assume true; 12224#L940-1 assume !false; 12036#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12035#L506 assume true; 12034#L506-1 assume !false; 12033#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12027#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12026#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12025#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12023#L511 assume !(0 != eval_~tmp~0#1); 12024#L514 assume true; 12336#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12335#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12334#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 12333#L616 assume !(0 == ~T1_E~0); 12332#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12331#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12330#L631 assume !(0 == ~T4_E~0); 12329#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12328#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 12327#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 12326#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 12325#L656 assume !(0 == ~E_3~0); 12324#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 12323#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 12322#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12321#L304-1 assume !(1 == ~m_pc~0); 12320#L314-1 is_master_triggered_~__retres1~0#1 := 0; 12319#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12318#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12317#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12316#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12315#L323-1 assume !(1 == ~t1_pc~0); 12313#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 12312#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12311#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12310#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12309#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12308#L342-1 assume !(1 == ~t2_pc~0); 12306#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 12305#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12304#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12303#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12302#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12301#L361-1 assume 1 == ~t3_pc~0; 12299#L362-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12298#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12297#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12296#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12295#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12294#L380-1 assume !(1 == ~t4_pc~0); 12292#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 12291#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12290#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12289#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12288#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12287#L399-1 assume !(1 == ~t5_pc~0); 12285#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 12284#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12283#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12282#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12281#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12280#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 11968#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12279#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12278#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12277#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11961#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12276#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 12275#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 12274#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 12273#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 12272#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 12271#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 12270#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12264#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12263#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12262#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 12261#L959 assume !(0 == start_simulation_~tmp~3#1); 10949#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12255#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12254#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12253#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12252#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12251#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12250#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12228#L972 assume !(0 != start_simulation_~tmp___0~1#1); 12226#L940 [2024-11-17 08:52:07,304 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,304 INFO L85 PathProgramCache]: Analyzing trace with hash 1787853365, now seen corresponding path program 1 times [2024-11-17 08:52:07,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992739947] [2024-11-17 08:52:07,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1992739947] [2024-11-17 08:52:07,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1992739947] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,349 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,349 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:07,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499927488] [2024-11-17 08:52:07,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,351 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:07,352 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,352 INFO L85 PathProgramCache]: Analyzing trace with hash 788093053, now seen corresponding path program 1 times [2024-11-17 08:52:07,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310487937] [2024-11-17 08:52:07,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310487937] [2024-11-17 08:52:07,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310487937] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,408 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:07,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615115999] [2024-11-17 08:52:07,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,409 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:07,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:07,410 INFO L87 Difference]: Start difference. First operand 1863 states and 2691 transitions. cyclomatic complexity: 832 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,489 INFO L93 Difference]: Finished difference Result 3429 states and 4913 transitions. [2024-11-17 08:52:07,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3429 states and 4913 transitions. [2024-11-17 08:52:07,515 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3324 [2024-11-17 08:52:07,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3429 states to 3429 states and 4913 transitions. [2024-11-17 08:52:07,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3429 [2024-11-17 08:52:07,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3429 [2024-11-17 08:52:07,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3429 states and 4913 transitions. [2024-11-17 08:52:07,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3429 states and 4913 transitions. [2024-11-17 08:52:07,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3429 states and 4913 transitions. [2024-11-17 08:52:07,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3429 to 3413. [2024-11-17 08:52:07,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3413 states, 3413 states have (on average 1.4348080867272195) internal successors, (4897), 3412 states have internal predecessors, (4897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3413 states to 3413 states and 4897 transitions. [2024-11-17 08:52:07,594 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3413 states and 4897 transitions. [2024-11-17 08:52:07,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:07,595 INFO L425 stractBuchiCegarLoop]: Abstraction has 3413 states and 4897 transitions. [2024-11-17 08:52:07,595 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:52:07,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3413 states and 4897 transitions. [2024-11-17 08:52:07,608 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3308 [2024-11-17 08:52:07,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,610 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,610 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,610 INFO L745 eck$LassoCheckResult]: Stem: 16428#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 15846#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15847#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16201#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16214#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 16215#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16231#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15830#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15831#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16053#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16054#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16086#L611-1 assume !(0 == ~M_E~0); 16329#L616-1 assume !(0 == ~T1_E~0); 16330#L621-1 assume !(0 == ~T2_E~0); 15906#L626-1 assume !(0 == ~T3_E~0); 15907#L631-1 assume !(0 == ~T4_E~0); 16092#L636-1 assume !(0 == ~T5_E~0); 15958#L641-1 assume !(0 == ~E_M~0); 15959#L646-1 assume !(0 == ~E_1~0); 16106#L651-1 assume !(0 == ~E_2~0); 16378#L656-1 assume !(0 == ~E_3~0); 16303#L661-1 assume !(0 == ~E_4~0); 16304#L666-1 assume !(0 == ~E_5~0); 16298#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16104#L304-8 assume !(1 == ~m_pc~0); 16105#L314-8 is_master_triggered_~__retres1~0#1 := 0; 16415#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15848#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15820#L755-8 assume !(0 != activate_threads_~tmp~1#1); 15821#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15950#L323-8 assume !(1 == ~t1_pc~0); 16046#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 16217#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16213#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16210#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 16211#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16143#L342-8 assume 1 == ~t2_pc~0; 16020#L343-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15973#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16239#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16277#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 16196#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16197#L361-8 assume 1 == ~t3_pc~0; 16065#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16066#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15812#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15813#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 16363#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15918#L380-8 assume 1 == ~t4_pc~0; 15919#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16080#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16124#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15884#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 15885#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16396#L399-8 assume 1 == ~t5_pc~0; 16412#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15978#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15963#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15866#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 15867#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16173#L679-1 assume 1 == ~M_E~0;~M_E~0 := 2; 16323#L684-1 assume !(1 == ~T1_E~0); 16193#L689-1 assume !(1 == ~T2_E~0); 16194#L694-1 assume !(1 == ~T3_E~0); 16190#L699-1 assume !(1 == ~T4_E~0); 16191#L704-1 assume !(1 == ~T5_E~0); 16157#L709-1 assume !(1 == ~E_M~0); 16158#L714-1 assume !(1 == ~E_1~0); 16295#L719-1 assume !(1 == ~E_2~0); 16296#L724-1 assume !(1 == ~E_3~0); 15898#L729-1 assume !(1 == ~E_4~0); 15899#L734-1 assume !(1 == ~E_5~0); 16023#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 16024#L940 [2024-11-17 08:52:07,610 INFO L747 eck$LassoCheckResult]: Loop: 16024#L940 assume true; 17831#L940-1 assume !false; 17826#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17824#L506 assume true; 17822#L506-1 assume !false; 17820#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 17812#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 17810#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 17808#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17805#L511 assume !(0 != eval_~tmp~0#1); 17803#L514 assume true; 17801#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17799#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17797#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 17795#L616 assume !(0 == ~T1_E~0); 17793#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17791#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17788#L631 assume !(0 == ~T4_E~0); 17785#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17781#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 17778#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 17775#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 17772#L656 assume !(0 == ~E_3~0); 17769#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 17766#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 17762#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17759#L304-1 assume !(1 == ~m_pc~0); 17756#L314-1 is_master_triggered_~__retres1~0#1 := 0; 17753#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17750#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17746#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17742#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17739#L323-1 assume !(1 == ~t1_pc~0); 17736#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 17733#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17730#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17726#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17725#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17724#L342-1 assume !(1 == ~t2_pc~0); 17721#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 17719#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17717#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17715#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17713#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17711#L361-1 assume 1 == ~t3_pc~0; 17708#L362-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17706#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17704#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17702#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17700#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17698#L380-1 assume 1 == ~t4_pc~0; 17696#L381-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17692#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17690#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17688#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17686#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17684#L399-1 assume !(1 == ~t5_pc~0); 17681#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 17675#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17671#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17667#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17663#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17659#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 17654#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17649#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17645#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17641#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17636#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17632#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 17627#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 17622#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 17618#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 17614#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 17610#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 17609#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 17603#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16040#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 15864#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 15865#L959 assume !(0 == start_simulation_~tmp~3#1); 16200#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 17894#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 17892#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 17890#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 17888#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17886#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17884#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 17877#L972 assume !(0 != start_simulation_~tmp___0~1#1); 16024#L940 [2024-11-17 08:52:07,611 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,611 INFO L85 PathProgramCache]: Analyzing trace with hash 1091010232, now seen corresponding path program 1 times [2024-11-17 08:52:07,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,611 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113946071] [2024-11-17 08:52:07,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,612 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113946071] [2024-11-17 08:52:07,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113946071] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:07,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562225859] [2024-11-17 08:52:07,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,671 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:07,672 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,672 INFO L85 PathProgramCache]: Analyzing trace with hash 63960506, now seen corresponding path program 1 times [2024-11-17 08:52:07,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309017820] [2024-11-17 08:52:07,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309017820] [2024-11-17 08:52:07,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309017820] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,724 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:07,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581882566] [2024-11-17 08:52:07,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,725 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,725 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:07,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:07,725 INFO L87 Difference]: Start difference. First operand 3413 states and 4897 transitions. cyclomatic complexity: 1492 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,802 INFO L93 Difference]: Finished difference Result 6332 states and 9026 transitions. [2024-11-17 08:52:07,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6332 states and 9026 transitions. [2024-11-17 08:52:07,832 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6196 [2024-11-17 08:52:07,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6332 states to 6332 states and 9026 transitions. [2024-11-17 08:52:07,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6332 [2024-11-17 08:52:07,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6332 [2024-11-17 08:52:07,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6332 states and 9026 transitions. [2024-11-17 08:52:07,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6332 states and 9026 transitions. [2024-11-17 08:52:07,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6332 states and 9026 transitions. [2024-11-17 08:52:07,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6332 to 6300. [2024-11-17 08:52:07,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6300 states, 6300 states have (on average 1.4276190476190476) internal successors, (8994), 6299 states have internal predecessors, (8994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6300 states to 6300 states and 8994 transitions. [2024-11-17 08:52:07,990 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6300 states and 8994 transitions. [2024-11-17 08:52:07,990 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:07,991 INFO L425 stractBuchiCegarLoop]: Abstraction has 6300 states and 8994 transitions. [2024-11-17 08:52:07,991 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:52:07,991 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6300 states and 8994 transitions. [2024-11-17 08:52:08,017 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6164 [2024-11-17 08:52:08,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,018 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,018 INFO L745 eck$LassoCheckResult]: Stem: 26198#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 25599#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 25600#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25961#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25975#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 25976#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25993#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25583#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25584#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25808#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25809#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25844#L611-1 assume !(0 == ~M_E~0); 26093#L616-1 assume !(0 == ~T1_E~0); 26094#L621-1 assume !(0 == ~T2_E~0); 25660#L626-1 assume !(0 == ~T3_E~0); 25661#L631-1 assume !(0 == ~T4_E~0); 25849#L636-1 assume !(0 == ~T5_E~0); 25715#L641-1 assume !(0 == ~E_M~0); 25716#L646-1 assume !(0 == ~E_1~0); 25862#L651-1 assume !(0 == ~E_2~0); 26145#L656-1 assume !(0 == ~E_3~0); 26071#L661-1 assume !(0 == ~E_4~0); 26072#L666-1 assume !(0 == ~E_5~0); 26065#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25860#L304-8 assume !(1 == ~m_pc~0); 25861#L314-8 is_master_triggered_~__retres1~0#1 := 0; 26181#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25601#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25573#L755-8 assume !(0 != activate_threads_~tmp~1#1); 25574#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25705#L323-8 assume !(1 == ~t1_pc~0); 25798#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 25978#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25974#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25971#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 25972#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25901#L342-8 assume !(1 == ~t2_pc~0); 25729#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 25730#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26001#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26041#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 25956#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25957#L361-8 assume 1 == ~t3_pc~0; 25821#L362-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25822#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25565#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25566#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 26132#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25674#L380-8 assume 1 == ~t4_pc~0; 25675#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25838#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25882#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25637#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 25638#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26164#L399-8 assume 1 == ~t5_pc~0; 26179#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25735#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25720#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25619#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 25620#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25931#L679-1 assume 1 == ~M_E~0;~M_E~0 := 2; 25748#L684-1 assume !(1 == ~T1_E~0); 25749#L689-1 assume !(1 == ~T2_E~0); 25954#L694-1 assume !(1 == ~T3_E~0); 25951#L699-1 assume !(1 == ~T4_E~0); 25952#L704-1 assume !(1 == ~T5_E~0); 25914#L709-1 assume !(1 == ~E_M~0); 25851#L714-1 assume !(1 == ~E_1~0); 25852#L719-1 assume !(1 == ~E_2~0); 30019#L724-1 assume !(1 == ~E_3~0); 30017#L729-1 assume !(1 == ~E_4~0); 30015#L734-1 assume !(1 == ~E_5~0); 25776#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 25777#L940 [2024-11-17 08:52:08,019 INFO L747 eck$LassoCheckResult]: Loop: 25777#L940 assume true; 25639#L940-1 assume !false; 25640#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25745#L506 assume true; 26122#L506-1 assume !false; 25946#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25853#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25854#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 26124#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25926#L511 assume !(0 != eval_~tmp~0#1); 25928#L514 assume true; 31329#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31327#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31325#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 31323#L616 assume !(0 == ~T1_E~0); 31321#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31319#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31317#L631 assume !(0 == ~T4_E~0); 31315#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31313#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 31311#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 31309#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 31307#L656 assume !(0 == ~E_3~0); 31305#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 31303#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 26115#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26097#L304-1 assume !(1 == ~m_pc~0); 26098#L314-1 is_master_triggered_~__retres1~0#1 := 0; 26150#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26081#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26069#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25778#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25779#L323-1 assume !(1 == ~t1_pc~0); 25969#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 25970#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26031#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26118#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26133#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25541#L342-1 assume !(1 == ~t2_pc~0); 25542#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 26089#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31286#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25991#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25992#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25845#L361-1 assume 1 == ~t3_pc~0; 25846#L362-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25834#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31629#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31628#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31626#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31625#L380-1 assume !(1 == ~t4_pc~0); 31623#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 31621#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31620#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31619#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31618#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31617#L399-1 assume !(1 == ~t5_pc~0); 31388#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 31386#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31384#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31382#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31380#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31379#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 30229#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31378#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31377#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31374#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30220#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31370#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 31369#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 31368#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 31367#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 31366#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 31365#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 31364#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31352#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31351#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31350#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 31349#L959 assume !(0 == start_simulation_~tmp~3#1); 31346#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31347#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31337#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31338#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 31334#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31333#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31331#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 26014#L972 assume !(0 != start_simulation_~tmp___0~1#1); 25777#L940 [2024-11-17 08:52:08,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,019 INFO L85 PathProgramCache]: Analyzing trace with hash 1815142779, now seen corresponding path program 1 times [2024-11-17 08:52:08,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [95798153] [2024-11-17 08:52:08,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,120 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [95798153] [2024-11-17 08:52:08,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [95798153] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,121 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,121 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:08,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1976397187] [2024-11-17 08:52:08,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,122 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,122 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,122 INFO L85 PathProgramCache]: Analyzing trace with hash 788093053, now seen corresponding path program 2 times [2024-11-17 08:52:08,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [802661745] [2024-11-17 08:52:08,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [802661745] [2024-11-17 08:52:08,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [802661745] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508422777] [2024-11-17 08:52:08,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,187 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:08,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:08,188 INFO L87 Difference]: Start difference. First operand 6300 states and 8994 transitions. cyclomatic complexity: 2710 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,293 INFO L93 Difference]: Finished difference Result 11719 states and 16643 transitions. [2024-11-17 08:52:08,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11719 states and 16643 transitions. [2024-11-17 08:52:08,345 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 11504 [2024-11-17 08:52:08,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11719 states to 11719 states and 16643 transitions. [2024-11-17 08:52:08,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11719 [2024-11-17 08:52:08,415 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11719 [2024-11-17 08:52:08,415 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11719 states and 16643 transitions. [2024-11-17 08:52:08,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11719 states and 16643 transitions. [2024-11-17 08:52:08,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11719 states and 16643 transitions. [2024-11-17 08:52:08,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11719 to 11655. [2024-11-17 08:52:08,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11655 states, 11655 states have (on average 1.4224796224796226) internal successors, (16579), 11654 states have internal predecessors, (16579), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11655 states to 11655 states and 16579 transitions. [2024-11-17 08:52:08,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11655 states and 16579 transitions. [2024-11-17 08:52:08,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,779 INFO L425 stractBuchiCegarLoop]: Abstraction has 11655 states and 16579 transitions. [2024-11-17 08:52:08,779 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:52:08,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11655 states and 16579 transitions. [2024-11-17 08:52:08,821 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 11440 [2024-11-17 08:52:08,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,823 INFO L745 eck$LassoCheckResult]: Stem: 44217#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 43629#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 43630#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43974#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43989#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 43990#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44006#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43611#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43612#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43828#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43829#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43860#L611-1 assume !(0 == ~M_E~0); 44109#L616-1 assume !(0 == ~T1_E~0); 44110#L621-1 assume !(0 == ~T2_E~0); 43689#L626-1 assume !(0 == ~T3_E~0); 43690#L631-1 assume !(0 == ~T4_E~0); 43866#L636-1 assume !(0 == ~T5_E~0); 43738#L641-1 assume !(0 == ~E_M~0); 43739#L646-1 assume !(0 == ~E_1~0); 43878#L651-1 assume !(0 == ~E_2~0); 44165#L656-1 assume !(0 == ~E_3~0); 44082#L661-1 assume !(0 == ~E_4~0); 44083#L666-1 assume !(0 == ~E_5~0); 44075#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43876#L304-8 assume !(1 == ~m_pc~0); 43877#L314-8 is_master_triggered_~__retres1~0#1 := 0; 44202#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43631#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43605#L755-8 assume !(0 != activate_threads_~tmp~1#1); 43606#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43730#L323-8 assume !(1 == ~t1_pc~0); 43821#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 43992#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43988#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43985#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 43986#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43913#L342-8 assume !(1 == ~t2_pc~0); 43754#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 43755#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44013#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44056#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 43968#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43969#L361-8 assume !(1 == ~t3_pc~0); 44014#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 44166#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43593#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43594#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 44148#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43700#L380-8 assume 1 == ~t4_pc~0; 43701#L381-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43855#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43895#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43666#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 43667#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44184#L399-8 assume 1 == ~t5_pc~0; 44200#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43758#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43743#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43646#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 43647#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43947#L679-1 assume 1 == ~M_E~0;~M_E~0 := 2; 43771#L684-1 assume !(1 == ~T1_E~0); 43772#L689-1 assume !(1 == ~T2_E~0); 43966#L694-1 assume !(1 == ~T3_E~0); 43964#L699-1 assume !(1 == ~T4_E~0); 43965#L704-1 assume !(1 == ~T5_E~0); 43930#L709-1 assume !(1 == ~E_M~0); 43873#L714-1 assume !(1 == ~E_1~0); 43874#L719-1 assume !(1 == ~E_2~0); 44073#L724-1 assume !(1 == ~E_3~0); 43678#L729-1 assume !(1 == ~E_4~0); 43679#L734-1 assume !(1 == ~E_5~0); 43800#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 43801#L940 [2024-11-17 08:52:08,823 INFO L747 eck$LassoCheckResult]: Loop: 43801#L940 assume true; 49691#L940-1 assume !false; 48921#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48919#L506 assume true; 48917#L506-1 assume !false; 48916#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 48910#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 48909#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 48908#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48906#L511 assume !(0 != eval_~tmp~0#1); 48907#L514 assume true; 49879#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49876#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49874#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 49872#L616 assume !(0 == ~T1_E~0); 49870#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49868#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49866#L631 assume !(0 == ~T4_E~0); 49863#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49861#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 49859#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 49857#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 49855#L656 assume !(0 == ~E_3~0); 49854#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 49853#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 49852#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49851#L304-1 assume !(1 == ~m_pc~0); 49850#L314-1 is_master_triggered_~__retres1~0#1 := 0; 49849#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49848#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49847#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49846#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49845#L323-1 assume !(1 == ~t1_pc~0); 49844#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 49843#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49841#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49839#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49837#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49835#L342-1 assume !(1 == ~t2_pc~0); 49833#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 49831#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49829#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49827#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49825#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49823#L361-1 assume !(1 == ~t3_pc~0); 49821#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 49819#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49817#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49815#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49813#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49811#L380-1 assume !(1 == ~t4_pc~0); 49808#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 49806#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49804#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49802#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49800#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49798#L399-1 assume !(1 == ~t5_pc~0); 49795#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 49793#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49791#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49788#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49786#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49784#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 49294#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49781#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49779#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49776#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49285#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49773#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 49771#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 49769#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 49767#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 49765#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 49763#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 49761#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 49749#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 49747#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 49745#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 49744#L959 assume !(0 == start_simulation_~tmp~3#1); 49742#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 49704#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 49702#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 49700#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 49697#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49695#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49693#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 49692#L972 assume !(0 != start_simulation_~tmp___0~1#1); 43801#L940 [2024-11-17 08:52:08,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,824 INFO L85 PathProgramCache]: Analyzing trace with hash 2143310462, now seen corresponding path program 1 times [2024-11-17 08:52:08,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175921848] [2024-11-17 08:52:08,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,873 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175921848] [2024-11-17 08:52:08,873 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175921848] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,874 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,874 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:08,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241798921] [2024-11-17 08:52:08,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,874 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,875 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,875 INFO L85 PathProgramCache]: Analyzing trace with hash 91249920, now seen corresponding path program 1 times [2024-11-17 08:52:08,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,876 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071870410] [2024-11-17 08:52:08,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,929 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,929 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071870410] [2024-11-17 08:52:08,929 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071870410] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,929 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153567045] [2024-11-17 08:52:08,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,930 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,932 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:08,932 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:08,933 INFO L87 Difference]: Start difference. First operand 11655 states and 16579 transitions. cyclomatic complexity: 4956 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:09,103 INFO L93 Difference]: Finished difference Result 21638 states and 30640 transitions. [2024-11-17 08:52:09,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21638 states and 30640 transitions. [2024-11-17 08:52:09,205 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 21264 [2024-11-17 08:52:09,382 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21638 states to 21638 states and 30640 transitions. [2024-11-17 08:52:09,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21638 [2024-11-17 08:52:09,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21638 [2024-11-17 08:52:09,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21638 states and 30640 transitions. [2024-11-17 08:52:09,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:09,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21638 states and 30640 transitions. [2024-11-17 08:52:09,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21638 states and 30640 transitions. [2024-11-17 08:52:09,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21638 to 21510. [2024-11-17 08:52:09,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21510 states, 21510 states have (on average 1.418503021850302) internal successors, (30512), 21509 states have internal predecessors, (30512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21510 states to 21510 states and 30512 transitions. [2024-11-17 08:52:09,787 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21510 states and 30512 transitions. [2024-11-17 08:52:09,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:09,788 INFO L425 stractBuchiCegarLoop]: Abstraction has 21510 states and 30512 transitions. [2024-11-17 08:52:09,788 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:52:09,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21510 states and 30512 transitions. [2024-11-17 08:52:09,854 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 21136 [2024-11-17 08:52:09,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:09,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:09,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,856 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,856 INFO L745 eck$LassoCheckResult]: Stem: 77567#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 76930#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 76931#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77292#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77310#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 77311#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77332#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76912#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76913#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77132#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77133#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77165#L611-1 assume !(0 == ~M_E~0); 77442#L616-1 assume !(0 == ~T1_E~0); 77443#L621-1 assume !(0 == ~T2_E~0); 76990#L626-1 assume !(0 == ~T3_E~0); 76991#L631-1 assume !(0 == ~T4_E~0); 77175#L636-1 assume !(0 == ~T5_E~0); 77040#L641-1 assume !(0 == ~E_M~0); 77041#L646-1 assume !(0 == ~E_1~0); 77190#L651-1 assume !(0 == ~E_2~0); 77503#L656-1 assume !(0 == ~E_3~0); 77411#L661-1 assume !(0 == ~E_4~0); 77412#L666-1 assume !(0 == ~E_5~0); 77402#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77188#L304-8 assume !(1 == ~m_pc~0); 77189#L314-8 is_master_triggered_~__retres1~0#1 := 0; 77549#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76932#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76906#L755-8 assume !(0 != activate_threads_~tmp~1#1); 76907#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77030#L323-8 assume !(1 == ~t1_pc~0); 77124#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 77313#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77309#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77306#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 77307#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77227#L342-8 assume !(1 == ~t2_pc~0); 77056#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 77057#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77339#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77383#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 77286#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77287#L361-8 assume !(1 == ~t3_pc~0); 77340#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 77505#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76894#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76895#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 77484#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77001#L380-8 assume !(1 == ~t4_pc~0); 77002#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 77160#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77209#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76967#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 76968#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77525#L399-8 assume 1 == ~t5_pc~0; 77546#L400-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77062#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77045#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76947#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 76948#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77263#L679-1 assume 1 == ~M_E~0;~M_E~0 := 2; 77077#L684-1 assume !(1 == ~T1_E~0); 77078#L689-1 assume !(1 == ~T2_E~0); 77283#L694-1 assume !(1 == ~T3_E~0); 77281#L699-1 assume !(1 == ~T4_E~0); 77282#L704-1 assume !(1 == ~T5_E~0); 77241#L709-1 assume !(1 == ~E_M~0); 77182#L714-1 assume !(1 == ~E_1~0); 77183#L719-1 assume !(1 == ~E_2~0); 77399#L724-1 assume !(1 == ~E_3~0); 76979#L729-1 assume !(1 == ~E_4~0); 76980#L734-1 assume !(1 == ~E_5~0); 77106#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 77107#L940 [2024-11-17 08:52:09,857 INFO L747 eck$LassoCheckResult]: Loop: 77107#L940 assume true; 97479#L940-1 assume !false; 97470#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97468#L506 assume true; 97469#L506-1 assume !false; 98026#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 97446#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 97447#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 77512#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77255#L511 assume !(0 != eval_~tmp~0#1); 77035#L514 assume true; 77036#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76861#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76862#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 77222#L616 assume !(0 == ~T1_E~0); 76995#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76996#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77254#L631 assume !(0 == ~T4_E~0); 77535#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77213#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 77214#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 77279#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 77316#L656 assume !(0 == ~E_3~0); 77446#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 77465#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 77464#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77449#L304-1 assume !(1 == ~m_pc~0); 77450#L314-1 is_master_triggered_~__retres1~0#1 := 0; 77508#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77424#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77409#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77104#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77105#L323-1 assume !(1 == ~t1_pc~0); 97965#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 97963#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97964#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 97959#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 97960#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97947#L342-1 assume !(1 == ~t2_pc~0); 97948#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 77033#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77034#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77329#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77330#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77166#L361-1 assume !(1 == ~t3_pc~0); 77167#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 76955#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76956#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77414#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77415#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77499#L380-1 assume !(1 == ~t4_pc~0); 77500#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 77347#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77348#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 98123#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77372#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77373#L399-1 assume 1 == ~t5_pc~0; 77251#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77252#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77513#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77359#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77360#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77561#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 77562#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77273#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77274#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77218#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77219#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77102#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 77103#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 77501#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 97748#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 97747#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 97746#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 97744#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 97646#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 97644#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 97642#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 77290#L959 assume !(0 == start_simulation_~tmp~3#1); 77291#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 98148#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 98147#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 98146#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 97840#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97837#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97836#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 97835#L972 assume !(0 != start_simulation_~tmp___0~1#1); 77107#L940 [2024-11-17 08:52:09,857 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,858 INFO L85 PathProgramCache]: Analyzing trace with hash 200114625, now seen corresponding path program 1 times [2024-11-17 08:52:09,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,858 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179148884] [2024-11-17 08:52:09,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179148884] [2024-11-17 08:52:09,905 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1179148884] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,905 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,905 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:09,906 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097274281] [2024-11-17 08:52:09,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,906 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:09,906 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,907 INFO L85 PathProgramCache]: Analyzing trace with hash -236917763, now seen corresponding path program 1 times [2024-11-17 08:52:09,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203637794] [2024-11-17 08:52:09,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:10,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:10,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:10,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203637794] [2024-11-17 08:52:10,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203637794] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:10,076 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:10,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:10,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2010080697] [2024-11-17 08:52:10,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:10,077 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:10,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:10,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:10,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:10,077 INFO L87 Difference]: Start difference. First operand 21510 states and 30512 transitions. cyclomatic complexity: 9066 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:10,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:10,261 INFO L93 Difference]: Finished difference Result 39893 states and 56445 transitions. [2024-11-17 08:52:10,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39893 states and 56445 transitions. [2024-11-17 08:52:10,551 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 39104 [2024-11-17 08:52:10,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39893 states to 39893 states and 56445 transitions. [2024-11-17 08:52:10,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39893 [2024-11-17 08:52:10,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39893 [2024-11-17 08:52:10,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39893 states and 56445 transitions. [2024-11-17 08:52:10,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:10,988 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39893 states and 56445 transitions. [2024-11-17 08:52:11,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39893 states and 56445 transitions. [2024-11-17 08:52:11,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39893 to 39637. [2024-11-17 08:52:11,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39637 states, 39637 states have (on average 1.4175896258546308) internal successors, (56189), 39636 states have internal predecessors, (56189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39637 states to 39637 states and 56189 transitions. [2024-11-17 08:52:12,058 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39637 states and 56189 transitions. [2024-11-17 08:52:12,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:12,059 INFO L425 stractBuchiCegarLoop]: Abstraction has 39637 states and 56189 transitions. [2024-11-17 08:52:12,059 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:52:12,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39637 states and 56189 transitions. [2024-11-17 08:52:12,164 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 38848 [2024-11-17 08:52:12,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:12,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:12,165 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:12,165 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:12,166 INFO L745 eck$LassoCheckResult]: Stem: 138985#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 138342#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 138343#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 138706#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 138721#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 138722#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 138741#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 138324#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 138325#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 138552#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 138553#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 138584#L611-1 assume !(0 == ~M_E~0); 138855#L616-1 assume !(0 == ~T1_E~0); 138856#L621-1 assume !(0 == ~T2_E~0); 138401#L626-1 assume !(0 == ~T3_E~0); 138402#L631-1 assume !(0 == ~T4_E~0); 138591#L636-1 assume !(0 == ~T5_E~0); 138455#L641-1 assume !(0 == ~E_M~0); 138456#L646-1 assume !(0 == ~E_1~0); 138603#L651-1 assume !(0 == ~E_2~0); 138926#L656-1 assume !(0 == ~E_3~0); 138825#L661-1 assume !(0 == ~E_4~0); 138826#L666-1 assume !(0 == ~E_5~0); 138817#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138601#L304-8 assume !(1 == ~m_pc~0); 138602#L314-8 is_master_triggered_~__retres1~0#1 := 0; 138970#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138344#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 138316#L755-8 assume !(0 != activate_threads_~tmp~1#1); 138317#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138444#L323-8 assume !(1 == ~t1_pc~0); 138544#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 138725#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138720#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 138717#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 138718#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138640#L342-8 assume !(1 == ~t2_pc~0); 138471#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 138472#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138751#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 138789#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 138700#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138701#L361-8 assume !(1 == ~t3_pc~0); 138752#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 138928#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138306#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138307#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 138906#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138413#L380-8 assume !(1 == ~t4_pc~0); 138414#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 138579#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138621#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 138380#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 138381#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138945#L399-8 assume !(1 == ~t5_pc~0); 138476#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 138477#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138460#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 138360#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 138361#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138675#L679-1 assume 1 == ~M_E~0;~M_E~0 := 2; 138846#L684-1 assume !(1 == ~T1_E~0); 163459#L689-1 assume !(1 == ~T2_E~0); 163457#L694-1 assume !(1 == ~T3_E~0); 163455#L699-1 assume !(1 == ~T4_E~0); 138694#L704-1 assume !(1 == ~T5_E~0); 163452#L709-1 assume !(1 == ~E_M~0); 163450#L714-1 assume !(1 == ~E_1~0); 163448#L719-1 assume !(1 == ~E_2~0); 163446#L724-1 assume !(1 == ~E_3~0); 163444#L729-1 assume !(1 == ~E_4~0); 163442#L734-1 assume !(1 == ~E_5~0); 163440#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 163437#L940 [2024-11-17 08:52:12,166 INFO L747 eck$LassoCheckResult]: Loop: 163437#L940 assume true; 163434#L940-1 assume !false; 163395#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 163393#L506 assume true; 163391#L506-1 assume !false; 163389#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 163175#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 163173#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 163171#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 163145#L511 assume !(0 != eval_~tmp~0#1); 163146#L514 assume true; 163803#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 163801#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163799#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 163797#L616 assume !(0 == ~T1_E~0); 163795#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 163793#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 163791#L631 assume !(0 == ~T4_E~0); 163789#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 163787#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 163785#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 163783#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 163781#L656 assume !(0 == ~E_3~0); 163779#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 163777#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 163775#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163773#L304-1 assume !(1 == ~m_pc~0); 163771#L314-1 is_master_triggered_~__retres1~0#1 := 0; 163769#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163767#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 163765#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 163763#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163761#L323-1 assume !(1 == ~t1_pc~0); 163759#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 163757#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163755#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 163753#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 163751#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163749#L342-1 assume !(1 == ~t2_pc~0); 163747#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 163746#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163745#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163744#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 163742#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163740#L361-1 assume !(1 == ~t3_pc~0); 163738#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 163735#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163733#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 163731#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 163729#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163727#L380-1 assume !(1 == ~t4_pc~0); 163725#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 163723#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163721#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 163719#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 163717#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163715#L399-1 assume !(1 == ~t5_pc~0); 163713#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 163711#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163709#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163707#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 163705#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163703#L679 assume 1 == ~M_E~0;~M_E~0 := 2; 163699#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 163697#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 163695#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 163693#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 163689#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 163687#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 163685#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 163682#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 163680#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 163678#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 163676#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 163674#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 163662#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 163659#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 163657#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 163654#L959 assume !(0 == start_simulation_~tmp~3#1); 163651#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 163619#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 163613#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 163612#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 163611#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 163610#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 163609#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 163439#L972 assume !(0 != start_simulation_~tmp___0~1#1); 163437#L940 [2024-11-17 08:52:12,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,167 INFO L85 PathProgramCache]: Analyzing trace with hash 1349787460, now seen corresponding path program 1 times [2024-11-17 08:52:12,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308845832] [2024-11-17 08:52:12,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:12,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:12,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:12,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308845832] [2024-11-17 08:52:12,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308845832] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:12,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:12,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:12,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854729952] [2024-11-17 08:52:12,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:12,208 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:12,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,209 INFO L85 PathProgramCache]: Analyzing trace with hash 91249920, now seen corresponding path program 2 times [2024-11-17 08:52:12,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608717405] [2024-11-17 08:52:12,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:12,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:12,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:12,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608717405] [2024-11-17 08:52:12,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [608717405] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:12,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:12,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:12,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245994056] [2024-11-17 08:52:12,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:12,408 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:12,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:12,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:12,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:12,409 INFO L87 Difference]: Start difference. First operand 39637 states and 56189 transitions. cyclomatic complexity: 16680 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:12,595 INFO L93 Difference]: Finished difference Result 58481 states and 83060 transitions. [2024-11-17 08:52:12,595 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58481 states and 83060 transitions. [2024-11-17 08:52:13,032 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 57344 [2024-11-17 08:52:13,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58481 states to 58481 states and 83060 transitions. [2024-11-17 08:52:13,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58481 [2024-11-17 08:52:13,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58481 [2024-11-17 08:52:13,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58481 states and 83060 transitions. [2024-11-17 08:52:13,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:13,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 58481 states and 83060 transitions. [2024-11-17 08:52:13,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58481 states and 83060 transitions. [2024-11-17 08:52:13,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58481 to 40393. [2024-11-17 08:52:14,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40393 states, 40393 states have (on average 1.4253212190230982) internal successors, (57573), 40392 states have internal predecessors, (57573), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:14,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40393 states to 40393 states and 57573 transitions. [2024-11-17 08:52:14,092 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40393 states and 57573 transitions. [2024-11-17 08:52:14,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:14,094 INFO L425 stractBuchiCegarLoop]: Abstraction has 40393 states and 57573 transitions. [2024-11-17 08:52:14,094 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:52:14,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40393 states and 57573 transitions. [2024-11-17 08:52:14,209 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 39616 [2024-11-17 08:52:14,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:14,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:14,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:14,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:14,212 INFO L745 eck$LassoCheckResult]: Stem: 237048#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 236469#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 236470#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 236816#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 236833#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 236834#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 236848#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 236453#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 236454#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 236668#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 236669#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 236698#L611-1 assume !(0 == ~M_E~0); 236949#L616-1 assume !(0 == ~T1_E~0); 236950#L621-1 assume !(0 == ~T2_E~0); 236528#L626-1 assume !(0 == ~T3_E~0); 236529#L631-1 assume !(0 == ~T4_E~0); 236702#L636-1 assume !(0 == ~T5_E~0); 236576#L641-1 assume !(0 == ~E_M~0); 236577#L646-1 assume !(0 == ~E_1~0); 236718#L651-1 assume !(0 == ~E_2~0); 236997#L656-1 assume !(0 == ~E_3~0); 236923#L661-1 assume !(0 == ~E_4~0); 236924#L666-1 assume !(0 == ~E_5~0); 236916#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 236713#L304-8 assume !(1 == ~m_pc~0); 236714#L314-8 is_master_triggered_~__retres1~0#1 := 0; 237036#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 236471#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 236443#L755-8 assume !(0 != activate_threads_~tmp~1#1); 236444#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 236568#L323-8 assume !(1 == ~t1_pc~0); 236659#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 236836#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 236832#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 236829#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 236830#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 236755#L342-8 assume !(1 == ~t2_pc~0); 236590#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 236591#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 236857#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 236896#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 236810#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 236811#L361-8 assume !(1 == ~t3_pc~0); 236858#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 237000#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 236435#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 236436#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 236985#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 236540#L380-8 assume !(1 == ~t4_pc~0); 236541#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 236692#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 236736#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 236506#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 236507#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 237019#L399-8 assume !(1 == ~t5_pc~0); 236595#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 236596#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 236581#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 236488#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 236489#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 236788#L679-1 assume !(1 == ~M_E~0); 236611#L684-1 assume !(1 == ~T1_E~0); 236612#L689-1 assume !(1 == ~T2_E~0); 236807#L694-1 assume !(1 == ~T3_E~0); 236804#L699-1 assume !(1 == ~T4_E~0); 236805#L704-1 assume !(1 == ~T5_E~0); 236770#L709-1 assume !(1 == ~E_M~0); 236704#L714-1 assume !(1 == ~E_1~0); 236705#L719-1 assume !(1 == ~E_2~0); 236914#L724-1 assume !(1 == ~E_3~0); 236520#L729-1 assume !(1 == ~E_4~0); 236521#L734-1 assume !(1 == ~E_5~0); 236638#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 236639#L940 [2024-11-17 08:52:14,212 INFO L747 eck$LassoCheckResult]: Loop: 236639#L940 assume true; 248132#L940-1 assume !false; 248094#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 248092#L506 assume true; 248089#L506-1 assume !false; 248087#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 248073#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 248071#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 248069#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 248066#L511 assume !(0 != eval_~tmp~0#1); 248063#L514 assume true; 248061#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 248059#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 248057#L611 assume !(0 == ~M_E~0); 248055#L616 assume !(0 == ~T1_E~0); 248053#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 248051#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 248049#L631 assume !(0 == ~T4_E~0); 248047#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 248045#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 248043#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 248042#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 248041#L656 assume !(0 == ~E_3~0); 248040#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 248038#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 248037#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 248035#L304-1 assume !(1 == ~m_pc~0); 248033#L314-1 is_master_triggered_~__retres1~0#1 := 0; 248031#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 248029#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 248028#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 248027#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 248026#L323-1 assume !(1 == ~t1_pc~0); 248025#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 248024#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 248023#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 248021#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 248019#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 248017#L342-1 assume !(1 == ~t2_pc~0); 248014#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 248012#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 248010#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 248008#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 248006#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 248004#L361-1 assume !(1 == ~t3_pc~0); 248002#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 248000#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247998#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 247996#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247994#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247992#L380-1 assume !(1 == ~t4_pc~0); 247989#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 247987#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247985#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 247983#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 247981#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247979#L399-1 assume !(1 == ~t5_pc~0); 247976#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 247974#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247972#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 247970#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 247968#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247966#L679 assume !(1 == ~M_E~0); 240515#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 247962#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 247960#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 247958#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 247956#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 247954#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 247952#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 247950#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 247948#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 247946#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 247944#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 247943#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 247937#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 247936#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 247935#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 240594#L959 assume !(0 == start_simulation_~tmp~3#1); 240595#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 248144#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 248142#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 248140#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 248138#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 248136#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 248134#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 248133#L972 assume !(0 != start_simulation_~tmp___0~1#1); 236639#L940 [2024-11-17 08:52:14,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:14,213 INFO L85 PathProgramCache]: Analyzing trace with hash 1056384453, now seen corresponding path program 1 times [2024-11-17 08:52:14,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:14,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664112995] [2024-11-17 08:52:14,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:14,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:14,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,410 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:14,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:14,536 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:14,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:14,537 INFO L85 PathProgramCache]: Analyzing trace with hash -1542348000, now seen corresponding path program 1 times [2024-11-17 08:52:14,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:14,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487953204] [2024-11-17 08:52:14,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:14,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:14,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:14,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:14,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:14,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487953204] [2024-11-17 08:52:14,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487953204] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:14,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:14,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:14,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1734930927] [2024-11-17 08:52:14,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:14,604 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:14,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:14,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:14,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:14,605 INFO L87 Difference]: Start difference. First operand 40393 states and 57573 transitions. cyclomatic complexity: 17244 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:14,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:14,794 INFO L93 Difference]: Finished difference Result 41289 states and 58469 transitions. [2024-11-17 08:52:14,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41289 states and 58469 transitions. [2024-11-17 08:52:15,270 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 40512 [2024-11-17 08:52:15,444 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41289 states to 41289 states and 58469 transitions. [2024-11-17 08:52:15,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41289 [2024-11-17 08:52:15,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41289 [2024-11-17 08:52:15,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41289 states and 58469 transitions. [2024-11-17 08:52:15,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:15,532 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41289 states and 58469 transitions. [2024-11-17 08:52:15,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41289 states and 58469 transitions. [2024-11-17 08:52:16,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41289 to 40777. [2024-11-17 08:52:16,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40777 states, 40777 states have (on average 1.4213159379061726) internal successors, (57957), 40776 states have internal predecessors, (57957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:16,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40777 states to 40777 states and 57957 transitions. [2024-11-17 08:52:16,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40777 states and 57957 transitions. [2024-11-17 08:52:16,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:16,162 INFO L425 stractBuchiCegarLoop]: Abstraction has 40777 states and 57957 transitions. [2024-11-17 08:52:16,162 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:52:16,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40777 states and 57957 transitions. [2024-11-17 08:52:16,303 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 40000 [2024-11-17 08:52:16,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:16,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:16,305 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:16,305 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:16,305 INFO L745 eck$LassoCheckResult]: Stem: 318791#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 318159#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 318160#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 318518#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 318532#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 318533#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 318548#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 318143#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 318144#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 318366#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 318367#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 318400#L611-1 assume !(0 == ~M_E~0); 318662#L616-1 assume !(0 == ~T1_E~0); 318663#L621-1 assume !(0 == ~T2_E~0); 318218#L626-1 assume !(0 == ~T3_E~0); 318219#L631-1 assume !(0 == ~T4_E~0); 318407#L636-1 assume !(0 == ~T5_E~0); 318267#L641-1 assume !(0 == ~E_M~0); 318268#L646-1 assume !(0 == ~E_1~0); 318423#L651-1 assume !(0 == ~E_2~0); 318721#L656-1 assume !(0 == ~E_3~0); 318631#L661-1 assume !(0 == ~E_4~0); 318632#L666-1 assume !(0 == ~E_5~0); 318622#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 318421#L304-8 assume !(1 == ~m_pc~0); 318422#L314-8 is_master_triggered_~__retres1~0#1 := 0; 318775#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 318161#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 318133#L755-8 assume !(0 != activate_threads_~tmp~1#1); 318134#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 318259#L323-8 assume !(1 == ~t1_pc~0); 318356#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 318535#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318531#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 318528#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 318529#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 318458#L342-8 assume !(1 == ~t2_pc~0); 318281#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 318282#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 318556#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 318595#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 318513#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 318514#L361-8 assume !(1 == ~t3_pc~0); 318557#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 318727#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 318125#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 318126#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 318706#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 318230#L380-8 assume !(1 == ~t4_pc~0); 318231#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 318394#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 318440#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 318196#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 318197#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 318749#L399-8 assume !(1 == ~t5_pc~0); 318288#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 318289#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 318272#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 318178#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 318179#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 318486#L679-1 assume !(1 == ~M_E~0); 318303#L684-1 assume !(1 == ~T1_E~0); 318304#L689-1 assume !(1 == ~T2_E~0); 318511#L694-1 assume !(1 == ~T3_E~0); 318508#L699-1 assume !(1 == ~T4_E~0); 318509#L704-1 assume !(1 == ~T5_E~0); 318471#L709-1 assume !(1 == ~E_M~0); 318411#L714-1 assume !(1 == ~E_1~0); 318412#L719-1 assume !(1 == ~E_2~0); 318618#L724-1 assume !(1 == ~E_3~0); 318210#L729-1 assume !(1 == ~E_4~0); 318211#L734-1 assume !(1 == ~E_5~0); 318333#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 318334#L940 [2024-11-17 08:52:16,306 INFO L747 eck$LassoCheckResult]: Loop: 318334#L940 assume true; 326751#L940-1 assume !false; 326748#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 326747#L506 assume true; 326746#L506-1 assume !false; 326745#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 326744#L464-2 assume !(0 == ~m_st~0); 326743#L468-2 assume !(0 == ~t1_st~0); 326742#L472-2 assume !(0 == ~t2_st~0); 326741#L476-2 assume !(0 == ~t3_st~0); 326740#L480-2 assume !(0 == ~t4_st~0); 326738#L484-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 326737#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 326736#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 326735#L511 assume !(0 != eval_~tmp~0#1); 326734#L514 assume true; 326733#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 326732#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 326731#L611 assume !(0 == ~M_E~0); 326730#L616 assume !(0 == ~T1_E~0); 326729#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 326728#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 326727#L631 assume !(0 == ~T4_E~0); 326726#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 326725#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 326724#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 326723#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 326722#L656 assume !(0 == ~E_3~0); 326721#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 326720#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 326719#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 326718#L304-1 assume !(1 == ~m_pc~0); 326717#L314-1 is_master_triggered_~__retres1~0#1 := 0; 326716#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 326715#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 326714#L755-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 326713#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 326712#L323-1 assume !(1 == ~t1_pc~0); 326711#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 326710#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 326709#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 326708#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 326707#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326706#L342-1 assume !(1 == ~t2_pc~0); 326705#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 326704#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 326703#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 326702#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 326701#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326700#L361-1 assume !(1 == ~t3_pc~0); 326699#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 326698#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 326697#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 326696#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 326695#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 326694#L380-1 assume !(1 == ~t4_pc~0); 326693#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 326692#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 326691#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 326690#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 326689#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 326688#L399-1 assume !(1 == ~t5_pc~0); 326687#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 326686#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 326685#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 326684#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 326683#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 326682#L679 assume !(1 == ~M_E~0); 326612#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 326681#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 326680#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 326679#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 326678#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 326677#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 326676#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 326675#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 326674#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 326673#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 326672#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 326671#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 326665#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 326591#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 326441#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 326439#L959 assume !(0 == start_simulation_~tmp~3#1); 326440#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 326819#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 326768#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 326757#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 326756#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 326755#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 326754#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 326753#L972 assume !(0 != start_simulation_~tmp___0~1#1); 318334#L940 [2024-11-17 08:52:16,307 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:16,307 INFO L85 PathProgramCache]: Analyzing trace with hash 1056384453, now seen corresponding path program 2 times [2024-11-17 08:52:16,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:16,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [295586792] [2024-11-17 08:52:16,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:16,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:16,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:16,319 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:16,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:16,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:16,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:16,346 INFO L85 PathProgramCache]: Analyzing trace with hash -1489324341, now seen corresponding path program 1 times [2024-11-17 08:52:16,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:16,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616217003] [2024-11-17 08:52:16,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:16,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:16,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:16,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:16,430 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:16,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616217003] [2024-11-17 08:52:16,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616217003] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:16,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:16,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:16,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824475362] [2024-11-17 08:52:16,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:16,431 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:16,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:16,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:16,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:16,432 INFO L87 Difference]: Start difference. First operand 40777 states and 57957 transitions. cyclomatic complexity: 17244 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:17,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:17,046 INFO L93 Difference]: Finished difference Result 41737 states and 58660 transitions. [2024-11-17 08:52:17,046 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41737 states and 58660 transitions. [2024-11-17 08:52:17,216 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 40960 [2024-11-17 08:52:17,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41737 states to 41737 states and 58660 transitions. [2024-11-17 08:52:17,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41737 [2024-11-17 08:52:17,392 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41737 [2024-11-17 08:52:17,392 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41737 states and 58660 transitions. [2024-11-17 08:52:17,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:17,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41737 states and 58660 transitions. [2024-11-17 08:52:17,461 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41737 states and 58660 transitions. [2024-11-17 08:52:18,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41737 to 41737. [2024-11-17 08:52:18,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41737 states, 41737 states have (on average 1.40546757074059) internal successors, (58660), 41736 states have internal predecessors, (58660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:18,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41737 states to 41737 states and 58660 transitions. [2024-11-17 08:52:18,379 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41737 states and 58660 transitions. [2024-11-17 08:52:18,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:18,384 INFO L425 stractBuchiCegarLoop]: Abstraction has 41737 states and 58660 transitions. [2024-11-17 08:52:18,384 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:52:18,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41737 states and 58660 transitions. [2024-11-17 08:52:18,510 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 40960 [2024-11-17 08:52:18,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:18,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:18,511 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:18,511 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:18,512 INFO L745 eck$LassoCheckResult]: Stem: 401304#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 400682#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 400683#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 401042#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 401055#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 401056#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 401074#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 400664#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 400665#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 400885#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 400886#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 400919#L611-1 assume !(0 == ~M_E~0); 401187#L616-1 assume !(0 == ~T1_E~0); 401188#L621-1 assume !(0 == ~T2_E~0); 400743#L626-1 assume !(0 == ~T3_E~0); 400744#L631-1 assume !(0 == ~T4_E~0); 400927#L636-1 assume !(0 == ~T5_E~0); 400793#L641-1 assume !(0 == ~E_M~0); 400794#L646-1 assume !(0 == ~E_1~0); 400943#L651-1 assume !(0 == ~E_2~0); 401245#L656-1 assume !(0 == ~E_3~0); 401157#L661-1 assume !(0 == ~E_4~0); 401158#L666-1 assume !(0 == ~E_5~0); 401149#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 400941#L304-8 assume !(1 == ~m_pc~0); 400942#L314-8 is_master_triggered_~__retres1~0#1 := 0; 401290#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 400684#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 400658#L755-8 assume !(0 != activate_threads_~tmp~1#1); 400659#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400782#L323-8 assume !(1 == ~t1_pc~0); 400877#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 401058#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 401054#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 401051#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 401052#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 400981#L342-8 assume !(1 == ~t2_pc~0); 400809#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 400810#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 401081#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 401128#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 401036#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 401037#L361-8 assume !(1 == ~t3_pc~0); 401082#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 401248#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 400646#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 400647#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 401226#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 400752#L380-8 assume !(1 == ~t4_pc~0); 400753#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 400914#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 400962#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 400719#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 400720#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 401267#L399-8 assume !(1 == ~t5_pc~0); 400814#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 400815#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 400798#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 400699#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 400700#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 401012#L679-1 assume !(1 == ~M_E~0); 400829#L684-1 assume !(1 == ~T1_E~0); 400830#L689-1 assume !(1 == ~T2_E~0); 401034#L694-1 assume !(1 == ~T3_E~0); 401032#L699-1 assume !(1 == ~T4_E~0); 401033#L704-1 assume !(1 == ~T5_E~0); 400995#L709-1 assume !(1 == ~E_M~0); 400934#L714-1 assume !(1 == ~E_1~0); 400935#L719-1 assume !(1 == ~E_2~0); 401147#L724-1 assume !(1 == ~E_3~0); 400731#L729-1 assume !(1 == ~E_4~0); 400732#L734-1 assume !(1 == ~E_5~0); 400859#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 400860#L940 [2024-11-17 08:52:18,512 INFO L747 eck$LassoCheckResult]: Loop: 400860#L940 assume true; 409462#L940-1 assume !false; 409460#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 406119#L506 assume true; 409457#L506-1 assume !false; 409455#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 409453#L464-2 assume !(0 == ~m_st~0); 409451#L468-2 assume !(0 == ~t1_st~0); 409449#L472-2 assume !(0 == ~t2_st~0); 409447#L476-2 assume !(0 == ~t3_st~0); 409445#L480-2 assume !(0 == ~t4_st~0); 409442#L484-2 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 409440#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 409438#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 409436#L511 assume !(0 != eval_~tmp~0#1); 409434#L514 assume true; 409432#L604 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 409430#L419 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 409427#L611 assume !(0 == ~M_E~0); 409425#L616 assume !(0 == ~T1_E~0); 409423#L621 assume 0 == ~T2_E~0;~T2_E~0 := 1; 409421#L626 assume 0 == ~T3_E~0;~T3_E~0 := 1; 409419#L631 assume !(0 == ~T4_E~0); 409417#L636 assume 0 == ~T5_E~0;~T5_E~0 := 1; 409415#L641 assume 0 == ~E_M~0;~E_M~0 := 1; 409413#L646 assume 0 == ~E_1~0;~E_1~0 := 1; 409411#L651 assume 0 == ~E_2~0;~E_2~0 := 1; 409409#L656 assume !(0 == ~E_3~0); 409407#L661 assume 0 == ~E_4~0;~E_4~0 := 1; 409405#L666 assume 0 == ~E_5~0;~E_5~0 := 1; 409403#L672 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 409401#L304-1 assume !(1 == ~m_pc~0); 409399#L314-1 is_master_triggered_~__retres1~0#1 := 0; 409397#L307-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 409395#L316-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 409393#L755-1 assume !(0 != activate_threads_~tmp~1#1); 409391#L761-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 409389#L323-1 assume !(1 == ~t1_pc~0); 409385#L333-1 is_transmit1_triggered_~__retres1~1#1 := 0; 409383#L326-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 409380#L335-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 409377#L763-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 409375#L769-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 409372#L342-1 assume !(1 == ~t2_pc~0); 409369#L352-1 is_transmit2_triggered_~__retres1~2#1 := 0; 409366#L345-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 409363#L354-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 409360#L771-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 409356#L777-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 409353#L361-1 assume !(1 == ~t3_pc~0); 409350#L371-1 is_transmit3_triggered_~__retres1~3#1 := 0; 409347#L364-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 409344#L373-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 409341#L779-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 409332#L785-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 409329#L380-1 assume !(1 == ~t4_pc~0); 409326#L390-1 is_transmit4_triggered_~__retres1~4#1 := 0; 409322#L383-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 409320#L392-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 409317#L787-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 409314#L793-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 409311#L399-1 assume !(1 == ~t5_pc~0); 409307#L409-1 is_transmit5_triggered_~__retres1~5#1 := 0; 409303#L402-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 409299#L411-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 409295#L795-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 409291#L801-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 409287#L679 assume !(1 == ~M_E~0); 409091#L684 assume 1 == ~T1_E~0;~T1_E~0 := 2; 409280#L689 assume 1 == ~T2_E~0;~T2_E~0 := 2; 409276#L694 assume 1 == ~T3_E~0;~T3_E~0 := 2; 409272#L699 assume 1 == ~T4_E~0;~T4_E~0 := 2; 409266#L704 assume 1 == ~T5_E~0;~T5_E~0 := 2; 409263#L709 assume 1 == ~E_M~0;~E_M~0 := 2; 409254#L714 assume 1 == ~E_1~0;~E_1~0 := 2; 409250#L719 assume 1 == ~E_2~0;~E_2~0 := 2; 409244#L724 assume 1 == ~E_3~0;~E_3~0 := 2; 409239#L729 assume 1 == ~E_4~0;~E_4~0 := 2; 409235#L734 assume 1 == ~E_5~0;~E_5~0 := 2; 409231#L740 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 409222#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 409218#L486-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 409213#L497-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 409207#L959 assume !(0 == start_simulation_~tmp~3#1); 409208#L970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 409477#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 409475#L486 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 409473#L497 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 409471#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 409469#L916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 409467#L922 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 409465#L972 assume !(0 != start_simulation_~tmp___0~1#1); 400860#L940 [2024-11-17 08:52:18,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:18,513 INFO L85 PathProgramCache]: Analyzing trace with hash 1056384453, now seen corresponding path program 3 times [2024-11-17 08:52:18,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:18,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386191161] [2024-11-17 08:52:18,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:18,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:18,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:18,527 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:18,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:18,544 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:18,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:18,545 INFO L85 PathProgramCache]: Analyzing trace with hash -858865716, now seen corresponding path program 1 times [2024-11-17 08:52:18,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:18,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160220053] [2024-11-17 08:52:18,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:18,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:18,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:18,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:18,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:18,578 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160220053] [2024-11-17 08:52:18,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160220053] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:18,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:18,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:18,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205060506] [2024-11-17 08:52:18,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:18,579 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:18,579 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:18,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:18,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:18,579 INFO L87 Difference]: Start difference. First operand 41737 states and 58660 transitions. cyclomatic complexity: 16987 Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:18,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:18,818 INFO L93 Difference]: Finished difference Result 65052 states and 89767 transitions. [2024-11-17 08:52:18,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65052 states and 89767 transitions. [2024-11-17 08:52:19,080 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 63904 [2024-11-17 08:52:19,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65052 states to 65052 states and 89767 transitions. [2024-11-17 08:52:19,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65052 [2024-11-17 08:52:19,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65052 [2024-11-17 08:52:19,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65052 states and 89767 transitions. [2024-11-17 08:52:19,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:19,692 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65052 states and 89767 transitions. [2024-11-17 08:52:19,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65052 states and 89767 transitions. [2024-11-17 08:52:20,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65052 to 62844. [2024-11-17 08:52:20,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62844 states, 62844 states have (on average 1.3830914645789574) internal successors, (86919), 62843 states have internal predecessors, (86919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:20,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62844 states to 62844 states and 86919 transitions. [2024-11-17 08:52:20,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62844 states and 86919 transitions. [2024-11-17 08:52:20,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:20,615 INFO L425 stractBuchiCegarLoop]: Abstraction has 62844 states and 86919 transitions. [2024-11-17 08:52:20,615 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:52:20,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62844 states and 86919 transitions. [2024-11-17 08:52:20,777 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 61696 [2024-11-17 08:52:20,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:20,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:20,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:20,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:20,778 INFO L745 eck$LassoCheckResult]: Stem: 508076#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 507475#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 507476#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 507830#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 507843#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 507844#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 507860#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 507459#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 507460#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 507680#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 507681#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 507712#L611-1 assume !(0 == ~M_E~0); 507962#L616-1 assume !(0 == ~T1_E~0); 507963#L621-1 assume !(0 == ~T2_E~0); 507535#L626-1 assume !(0 == ~T3_E~0); 507536#L631-1 assume !(0 == ~T4_E~0); 507719#L636-1 assume !(0 == ~T5_E~0); 507585#L641-1 assume !(0 == ~E_M~0); 507586#L646-1 assume !(0 == ~E_1~0); 507732#L651-1 assume !(0 == ~E_2~0); 508019#L656-1 assume !(0 == ~E_3~0); 507934#L661-1 assume !(0 == ~E_4~0); 507935#L666-1 assume !(0 == ~E_5~0); 507926#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 507730#L304-8 assume !(1 == ~m_pc~0); 507731#L314-8 is_master_triggered_~__retres1~0#1 := 0; 508060#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 507477#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 507449#L755-8 assume !(0 != activate_threads_~tmp~1#1); 507450#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 507576#L323-8 assume !(1 == ~t1_pc~0); 507673#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 507846#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 507842#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 507839#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 507840#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 507768#L342-8 assume !(1 == ~t2_pc~0); 507599#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 507600#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 507870#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 507908#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 507824#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 507825#L361-8 assume !(1 == ~t3_pc~0); 507871#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 508022#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 507441#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 507442#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 508000#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 507547#L380-8 assume !(1 == ~t4_pc~0); 507548#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 507706#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 507750#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 507513#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 507514#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 508039#L399-8 assume !(1 == ~t5_pc~0); 507606#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 507607#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 507590#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 507494#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 507495#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 507799#L679-1 assume !(1 == ~M_E~0); 507622#L684-1 assume !(1 == ~T1_E~0); 507623#L689-1 assume !(1 == ~T2_E~0); 507821#L694-1 assume !(1 == ~T3_E~0); 507818#L699-1 assume !(1 == ~T4_E~0); 507819#L704-1 assume !(1 == ~T5_E~0); 507784#L709-1 assume !(1 == ~E_M~0); 507721#L714-1 assume !(1 == ~E_1~0); 507722#L719-1 assume !(1 == ~E_2~0); 507924#L724-1 assume !(1 == ~E_3~0); 507527#L729-1 assume !(1 == ~E_4~0); 507528#L734-1 assume !(1 == ~E_5~0); 507650#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 507651#L940 assume true; 513765#L940-1 assume !false; 513753#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 513748#L506 [2024-11-17 08:52:20,778 INFO L747 eck$LassoCheckResult]: Loop: 513748#L506 assume true; 513743#L506-1 assume !false; 513737#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 513730#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 513725#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 513716#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 513711#L511 assume 0 != eval_~tmp~0#1; 513705#L516-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 513699#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 513693#L516 havoc eval_~tmp_ndt_1~0#1; 513663#L530-1 assume !(0 == ~t1_st~0); 513634#L544-1 assume !(0 == ~t2_st~0); 513630#L558-1 assume !(0 == ~t3_st~0); 513626#L572-1 assume !(0 == ~t4_st~0); 513627#L586-1 assume !(0 == ~t5_st~0); 513748#L506 [2024-11-17 08:52:20,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:20,779 INFO L85 PathProgramCache]: Analyzing trace with hash 1524792931, now seen corresponding path program 1 times [2024-11-17 08:52:20,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:20,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120644004] [2024-11-17 08:52:20,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:20,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:20,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:20,791 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:20,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:20,817 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:20,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:20,818 INFO L85 PathProgramCache]: Analyzing trace with hash 2082655383, now seen corresponding path program 1 times [2024-11-17 08:52:20,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:20,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989613492] [2024-11-17 08:52:20,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:20,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:20,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:20,823 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:20,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:20,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:20,826 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:20,826 INFO L85 PathProgramCache]: Analyzing trace with hash -435454475, now seen corresponding path program 1 times [2024-11-17 08:52:20,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:20,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511499798] [2024-11-17 08:52:20,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:20,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:20,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:20,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:20,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:20,873 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511499798] [2024-11-17 08:52:20,873 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511499798] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:20,873 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:20,874 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:20,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658034301] [2024-11-17 08:52:20,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:20,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:20,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:20,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:20,969 INFO L87 Difference]: Start difference. First operand 62844 states and 86919 transitions. cyclomatic complexity: 24171 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:21,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:21,210 INFO L93 Difference]: Finished difference Result 72664 states and 98858 transitions. [2024-11-17 08:52:21,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72664 states and 98858 transitions. [2024-11-17 08:52:21,496 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 71321 [2024-11-17 08:52:21,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72664 states to 72664 states and 98858 transitions. [2024-11-17 08:52:21,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72664 [2024-11-17 08:52:21,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72664 [2024-11-17 08:52:21,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72664 states and 98858 transitions. [2024-11-17 08:52:21,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:21,787 INFO L218 hiAutomatonCegarLoop]: Abstraction has 72664 states and 98858 transitions. [2024-11-17 08:52:21,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72664 states and 98858 transitions. [2024-11-17 08:52:22,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72664 to 69192. [2024-11-17 08:52:22,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69192 states, 69192 states have (on average 1.3656203029251937) internal successors, (94490), 69191 states have internal predecessors, (94490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:22,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69192 states to 69192 states and 94490 transitions. [2024-11-17 08:52:22,848 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69192 states and 94490 transitions. [2024-11-17 08:52:22,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:22,849 INFO L425 stractBuchiCegarLoop]: Abstraction has 69192 states and 94490 transitions. [2024-11-17 08:52:22,849 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:52:22,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69192 states and 94490 transitions. [2024-11-17 08:52:23,008 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 67849 [2024-11-17 08:52:23,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:23,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:23,009 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:23,009 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:23,010 INFO L745 eck$LassoCheckResult]: Stem: 643637#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 642990#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 642991#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 643347#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 643362#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 643363#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 643381#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 642974#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 642975#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 643197#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 643198#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 643229#L611-1 assume !(0 == ~M_E~0); 643493#L616-1 assume !(0 == ~T1_E~0); 643494#L621-1 assume !(0 == ~T2_E~0); 643050#L626-1 assume !(0 == ~T3_E~0); 643051#L631-1 assume !(0 == ~T4_E~0); 643235#L636-1 assume !(0 == ~T5_E~0); 643102#L641-1 assume !(0 == ~E_M~0); 643103#L646-1 assume !(0 == ~E_1~0); 643247#L651-1 assume !(0 == ~E_2~0); 643564#L656-1 assume !(0 == ~E_3~0); 643463#L661-1 assume !(0 == ~E_4~0); 643464#L666-1 assume !(0 == ~E_5~0); 643455#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 643245#L304-8 assume !(1 == ~m_pc~0); 643246#L314-8 is_master_triggered_~__retres1~0#1 := 0; 643617#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 642992#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 642964#L755-8 assume !(0 != activate_threads_~tmp~1#1); 642965#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 643092#L323-8 assume !(1 == ~t1_pc~0); 643190#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 643365#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 643361#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 643357#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 643358#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 643284#L342-8 assume !(1 == ~t2_pc~0); 643116#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 643117#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 643388#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 643430#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 643341#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 643342#L361-8 assume !(1 == ~t3_pc~0); 643391#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 643571#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 642956#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 642957#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 643543#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 643064#L380-8 assume !(1 == ~t4_pc~0); 643065#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 643222#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 643266#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 643027#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 643028#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 643593#L399-8 assume !(1 == ~t5_pc~0); 643121#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 643122#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 643107#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 643008#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 643009#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 643315#L679-1 assume !(1 == ~M_E~0); 643137#L684-1 assume !(1 == ~T1_E~0); 643138#L689-1 assume !(1 == ~T2_E~0); 643339#L694-1 assume !(1 == ~T3_E~0); 643336#L699-1 assume !(1 == ~T4_E~0); 643337#L704-1 assume !(1 == ~T5_E~0); 643299#L709-1 assume !(1 == ~E_M~0); 643237#L714-1 assume !(1 == ~E_1~0); 643238#L719-1 assume !(1 == ~E_2~0); 643452#L724-1 assume !(1 == ~E_3~0); 643041#L729-1 assume !(1 == ~E_4~0); 643042#L734-1 assume !(1 == ~E_5~0); 643167#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 643168#L940 assume true; 664859#L940-1 assume !false; 664821#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 664819#L506 [2024-11-17 08:52:23,010 INFO L747 eck$LassoCheckResult]: Loop: 664819#L506 assume true; 664817#L506-1 assume !false; 664814#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 664811#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 664809#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 664807#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 664805#L511 assume 0 != eval_~tmp~0#1; 664802#L516-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 664799#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 664800#L516 havoc eval_~tmp_ndt_1~0#1; 664842#L530-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 664840#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 664839#L530 havoc eval_~tmp_ndt_2~0#1; 664837#L544-1 assume !(0 == ~t2_st~0); 664833#L558-1 assume !(0 == ~t3_st~0); 664827#L572-1 assume !(0 == ~t4_st~0); 664823#L586-1 assume !(0 == ~t5_st~0); 664819#L506 [2024-11-17 08:52:23,010 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:23,011 INFO L85 PathProgramCache]: Analyzing trace with hash 1524792931, now seen corresponding path program 2 times [2024-11-17 08:52:23,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:23,011 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744753376] [2024-11-17 08:52:23,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:23,011 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:23,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:23,023 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:23,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:23,036 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:23,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:23,037 INFO L85 PathProgramCache]: Analyzing trace with hash 1935429527, now seen corresponding path program 1 times [2024-11-17 08:52:23,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:23,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573122771] [2024-11-17 08:52:23,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:23,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:23,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:23,040 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:23,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:23,043 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:23,043 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:23,043 INFO L85 PathProgramCache]: Analyzing trace with hash 98443637, now seen corresponding path program 1 times [2024-11-17 08:52:23,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:23,043 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686718171] [2024-11-17 08:52:23,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:23,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:23,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:23,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:23,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:23,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686718171] [2024-11-17 08:52:23,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686718171] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:23,076 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:23,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:23,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024036635] [2024-11-17 08:52:23,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:23,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:23,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:23,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:23,150 INFO L87 Difference]: Start difference. First operand 69192 states and 94490 transitions. cyclomatic complexity: 25394 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:23,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:23,401 INFO L93 Difference]: Finished difference Result 83948 states and 113399 transitions. [2024-11-17 08:52:23,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83948 states and 113399 transitions. [2024-11-17 08:52:24,193 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 82349 [2024-11-17 08:52:24,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83948 states to 83948 states and 113399 transitions. [2024-11-17 08:52:24,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83948 [2024-11-17 08:52:24,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83948 [2024-11-17 08:52:24,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83948 states and 113399 transitions. [2024-11-17 08:52:24,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:24,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 83948 states and 113399 transitions. [2024-11-17 08:52:24,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83948 states and 113399 transitions. [2024-11-17 08:52:25,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83948 to 80420. [2024-11-17 08:52:25,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80420 states, 80420 states have (on average 1.3554712758020393) internal successors, (109007), 80419 states have internal predecessors, (109007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:25,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80420 states to 80420 states and 109007 transitions. [2024-11-17 08:52:25,429 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80420 states and 109007 transitions. [2024-11-17 08:52:25,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:25,430 INFO L425 stractBuchiCegarLoop]: Abstraction has 80420 states and 109007 transitions. [2024-11-17 08:52:25,430 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:52:25,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80420 states and 109007 transitions. [2024-11-17 08:52:25,616 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 78821 [2024-11-17 08:52:25,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:25,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:25,617 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:25,617 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:25,618 INFO L745 eck$LassoCheckResult]: Stem: 796806#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 796143#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 796144#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 796513#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 796527#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 796528#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 796546#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 796125#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 796126#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 796354#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 796355#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 796386#L611-1 assume !(0 == ~M_E~0); 796665#L616-1 assume !(0 == ~T1_E~0); 796666#L621-1 assume !(0 == ~T2_E~0); 796205#L626-1 assume !(0 == ~T3_E~0); 796206#L631-1 assume !(0 == ~T4_E~0); 796393#L636-1 assume !(0 == ~T5_E~0); 796255#L641-1 assume !(0 == ~E_M~0); 796256#L646-1 assume !(0 == ~E_1~0); 796405#L651-1 assume !(0 == ~E_2~0); 796727#L656-1 assume !(0 == ~E_3~0); 796635#L661-1 assume !(0 == ~E_4~0); 796636#L666-1 assume !(0 == ~E_5~0); 796626#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 796403#L304-8 assume !(1 == ~m_pc~0); 796404#L314-8 is_master_triggered_~__retres1~0#1 := 0; 796782#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 796145#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 796117#L755-8 assume !(0 != activate_threads_~tmp~1#1); 796118#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 796246#L323-8 assume !(1 == ~t1_pc~0); 796346#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 796530#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 796526#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 796523#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 796524#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 796447#L342-8 assume !(1 == ~t2_pc~0); 796271#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 796272#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 796554#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 796598#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 796507#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 796508#L361-8 assume !(1 == ~t3_pc~0); 796556#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 796732#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 796107#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 796108#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 796705#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 796216#L380-8 assume !(1 == ~t4_pc~0); 796217#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 796381#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 796425#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 796179#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 796180#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 796754#L399-8 assume !(1 == ~t5_pc~0); 796276#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 796277#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 796260#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 796160#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 796161#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 796480#L679-1 assume !(1 == ~M_E~0); 796294#L684-1 assume !(1 == ~T1_E~0); 796295#L689-1 assume !(1 == ~T2_E~0); 796504#L694-1 assume !(1 == ~T3_E~0); 796501#L699-1 assume !(1 == ~T4_E~0); 796502#L704-1 assume !(1 == ~T5_E~0); 796462#L709-1 assume !(1 == ~E_M~0); 796398#L714-1 assume !(1 == ~E_1~0); 796399#L719-1 assume !(1 == ~E_2~0); 796623#L724-1 assume !(1 == ~E_3~0); 796193#L729-1 assume !(1 == ~E_4~0); 796194#L734-1 assume !(1 == ~E_5~0); 796324#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 796325#L940 assume true; 806549#L940-1 assume !false; 806546#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 806499#L506 [2024-11-17 08:52:25,618 INFO L747 eck$LassoCheckResult]: Loop: 806499#L506 assume true; 806543#L506-1 assume !false; 806541#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 806538#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 806536#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 806534#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 806532#L511 assume 0 != eval_~tmp~0#1; 806529#L516-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 806526#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 806524#L516 havoc eval_~tmp_ndt_1~0#1; 806522#L530-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 806519#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 806517#L530 havoc eval_~tmp_ndt_2~0#1; 806515#L544-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 806511#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 806509#L544 havoc eval_~tmp_ndt_3~0#1; 806506#L558-1 assume !(0 == ~t3_st~0); 806502#L572-1 assume !(0 == ~t4_st~0); 806498#L586-1 assume !(0 == ~t5_st~0); 806499#L506 [2024-11-17 08:52:25,618 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:25,619 INFO L85 PathProgramCache]: Analyzing trace with hash 1524792931, now seen corresponding path program 3 times [2024-11-17 08:52:25,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:25,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841330756] [2024-11-17 08:52:25,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:25,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:25,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:25,627 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:25,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:25,644 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:25,644 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:25,644 INFO L85 PathProgramCache]: Analyzing trace with hash 290118423, now seen corresponding path program 1 times [2024-11-17 08:52:25,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:25,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990087067] [2024-11-17 08:52:25,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:25,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:25,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:25,648 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:25,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:25,652 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:25,652 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:25,652 INFO L85 PathProgramCache]: Analyzing trace with hash 178236789, now seen corresponding path program 1 times [2024-11-17 08:52:25,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:25,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099422200] [2024-11-17 08:52:25,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:25,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:25,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:25,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:25,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:25,692 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099422200] [2024-11-17 08:52:25,693 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099422200] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:25,693 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:25,693 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:25,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981531232] [2024-11-17 08:52:25,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:25,770 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:25,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:25,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:25,770 INFO L87 Difference]: Start difference. First operand 80420 states and 109007 transitions. cyclomatic complexity: 28683 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:26,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:26,158 INFO L93 Difference]: Finished difference Result 150132 states and 202596 transitions. [2024-11-17 08:52:26,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 150132 states and 202596 transitions. [2024-11-17 08:52:27,334 INFO L131 ngComponentsAnalysis]: Automaton has 152 accepting balls. 139820 [2024-11-17 08:52:27,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 150132 states to 150132 states and 202596 transitions. [2024-11-17 08:52:27,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 150132 [2024-11-17 08:52:27,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 150132 [2024-11-17 08:52:27,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150132 states and 202596 transitions. [2024-11-17 08:52:27,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:27,923 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150132 states and 202596 transitions. [2024-11-17 08:52:28,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150132 states and 202596 transitions. [2024-11-17 08:52:29,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150132 to 146676. [2024-11-17 08:52:29,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146676 states, 146676 states have (on average 1.3524502986173608) internal successors, (198372), 146675 states have internal predecessors, (198372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146676 states to 146676 states and 198372 transitions. [2024-11-17 08:52:29,864 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146676 states and 198372 transitions. [2024-11-17 08:52:29,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:29,864 INFO L425 stractBuchiCegarLoop]: Abstraction has 146676 states and 198372 transitions. [2024-11-17 08:52:29,865 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:52:29,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146676 states and 198372 transitions. [2024-11-17 08:52:30,963 INFO L131 ngComponentsAnalysis]: Automaton has 152 accepting balls. 136364 [2024-11-17 08:52:30,963 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:30,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:30,964 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:30,964 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:30,964 INFO L745 eck$LassoCheckResult]: Stem: 1027381#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1026700#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1026701#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1027082#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1027098#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1027099#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1027117#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1026683#L441 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1026684#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1026914#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1026915#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1026948#L611-1 assume !(0 == ~M_E~0); 1027237#L616-1 assume !(0 == ~T1_E~0); 1027238#L621-1 assume !(0 == ~T2_E~0); 1026761#L626-1 assume !(0 == ~T3_E~0); 1026762#L631-1 assume !(0 == ~T4_E~0); 1026953#L636-1 assume !(0 == ~T5_E~0); 1026814#L641-1 assume !(0 == ~E_M~0); 1026815#L646-1 assume !(0 == ~E_1~0); 1026971#L651-1 assume !(0 == ~E_2~0); 1027309#L656-1 assume !(0 == ~E_3~0); 1027208#L661-1 assume !(0 == ~E_4~0); 1027209#L666-1 assume !(0 == ~E_5~0); 1027200#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1026966#L304-8 assume !(1 == ~m_pc~0); 1026967#L314-8 is_master_triggered_~__retres1~0#1 := 0; 1027361#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1026702#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1026673#L755-8 assume !(0 != activate_threads_~tmp~1#1); 1026674#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1026804#L323-8 assume !(1 == ~t1_pc~0); 1026904#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1027102#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1027097#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1027094#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 1027095#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1027012#L342-8 assume !(1 == ~t2_pc~0); 1026828#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1026829#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1027127#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1027171#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 1027074#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1027075#L361-8 assume !(1 == ~t3_pc~0); 1027129#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 1027313#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1026665#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1026666#L779-8 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1027376#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1048843#L380-8 assume !(1 == ~t4_pc~0); 1048842#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1048841#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1048840#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1048839#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 1048838#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1048837#L399-8 assume !(1 == ~t5_pc~0); 1048836#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 1048835#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1048834#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1048833#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 1048832#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1048831#L679-1 assume !(1 == ~M_E~0); 1048830#L684-1 assume !(1 == ~T1_E~0); 1048829#L689-1 assume !(1 == ~T2_E~0); 1048828#L694-1 assume !(1 == ~T3_E~0); 1048827#L699-1 assume !(1 == ~T4_E~0); 1048826#L704-1 assume !(1 == ~T5_E~0); 1048825#L709-1 assume !(1 == ~E_M~0); 1048824#L714-1 assume !(1 == ~E_1~0); 1048823#L719-1 assume !(1 == ~E_2~0); 1048822#L724-1 assume !(1 == ~E_3~0); 1048821#L729-1 assume !(1 == ~E_4~0); 1048820#L734-1 assume !(1 == ~E_5~0); 1026882#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 1026883#L940 assume true; 1060924#L940-1 assume !false; 1048753#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1048750#L506 [2024-11-17 08:52:30,965 INFO L747 eck$LassoCheckResult]: Loop: 1048750#L506 assume true; 1048747#L506-1 assume !false; 1048745#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1048741#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1048738#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1048735#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1048732#L511 assume 0 != eval_~tmp~0#1; 1048730#L516-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1048727#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1048726#L516 havoc eval_~tmp_ndt_1~0#1; 1048724#L530-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1048721#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1048720#L530 havoc eval_~tmp_ndt_2~0#1; 1048716#L544-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1048717#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1048637#L544 havoc eval_~tmp_ndt_3~0#1; 1046309#L558-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1046306#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 1046307#L558 havoc eval_~tmp_ndt_4~0#1; 1048767#L572-1 assume !(0 == ~t4_st~0); 1048755#L586-1 assume !(0 == ~t5_st~0); 1048750#L506 [2024-11-17 08:52:30,965 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:30,965 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163717, now seen corresponding path program 1 times [2024-11-17 08:52:30,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:30,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123261374] [2024-11-17 08:52:30,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:30,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:30,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:30,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:30,991 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:30,991 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123261374] [2024-11-17 08:52:30,991 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123261374] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:30,991 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:30,991 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:30,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834162660] [2024-11-17 08:52:30,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:30,992 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:30,992 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:30,992 INFO L85 PathProgramCache]: Analyzing trace with hash -367022569, now seen corresponding path program 1 times [2024-11-17 08:52:30,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:30,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063676521] [2024-11-17 08:52:30,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:30,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:30,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:30,996 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:30,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:30,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:31,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:31,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:31,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:31,076 INFO L87 Difference]: Start difference. First operand 146676 states and 198372 transitions. cyclomatic complexity: 51848 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:31,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:31,276 INFO L93 Difference]: Finished difference Result 97420 states and 131283 transitions. [2024-11-17 08:52:31,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97420 states and 131283 transitions. [2024-11-17 08:52:31,588 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 95437 [2024-11-17 08:52:31,796 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97420 states to 97420 states and 131283 transitions. [2024-11-17 08:52:31,796 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97420 [2024-11-17 08:52:31,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97420 [2024-11-17 08:52:31,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97420 states and 131283 transitions. [2024-11-17 08:52:31,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:31,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97420 states and 131283 transitions. [2024-11-17 08:52:31,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97420 states and 131283 transitions. [2024-11-17 08:52:33,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97420 to 97420. [2024-11-17 08:52:33,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97420 states, 97420 states have (on average 1.3475980291521248) internal successors, (131283), 97419 states have internal predecessors, (131283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:33,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97420 states to 97420 states and 131283 transitions. [2024-11-17 08:52:33,332 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97420 states and 131283 transitions. [2024-11-17 08:52:33,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:33,333 INFO L425 stractBuchiCegarLoop]: Abstraction has 97420 states and 131283 transitions. [2024-11-17 08:52:33,333 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:52:33,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97420 states and 131283 transitions. [2024-11-17 08:52:33,552 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 95437 [2024-11-17 08:52:33,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:33,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:33,553 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:33,553 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:33,553 INFO L745 eck$LassoCheckResult]: Stem: 1271444#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1270804#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1270805#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1271171#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1271185#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1271186#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1271208#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1270785#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1270786#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1271008#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1271009#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1271040#L611-1 assume !(0 == ~M_E~0); 1271314#L616-1 assume !(0 == ~T1_E~0); 1271315#L621-1 assume !(0 == ~T2_E~0); 1270864#L626-1 assume !(0 == ~T3_E~0); 1270865#L631-1 assume !(0 == ~T4_E~0); 1271050#L636-1 assume !(0 == ~T5_E~0); 1270911#L641-1 assume !(0 == ~E_M~0); 1270912#L646-1 assume !(0 == ~E_1~0); 1271063#L651-1 assume !(0 == ~E_2~0); 1271380#L656-1 assume !(0 == ~E_3~0); 1271285#L661-1 assume !(0 == ~E_4~0); 1271286#L666-1 assume !(0 == ~E_5~0); 1271277#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1271061#L304-8 assume !(1 == ~m_pc~0); 1271062#L314-8 is_master_triggered_~__retres1~0#1 := 0; 1271430#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1270803#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1270779#L755-8 assume !(0 != activate_threads_~tmp~1#1); 1270780#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1270902#L323-8 assume !(1 == ~t1_pc~0); 1271001#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1271189#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1271184#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1271181#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 1271182#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1271105#L342-8 assume !(1 == ~t2_pc~0); 1270927#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1270928#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1271214#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1271256#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 1271167#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1271168#L361-8 assume !(1 == ~t3_pc~0); 1271217#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 1271386#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1270767#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1270768#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 1271360#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1270874#L380-8 assume !(1 == ~t4_pc~0); 1270875#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1271035#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1271083#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1270840#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 1270841#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1271404#L399-8 assume !(1 == ~t5_pc~0); 1270932#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 1270933#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1270916#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1270820#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 1270821#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1271138#L679-1 assume !(1 == ~M_E~0); 1270947#L684-1 assume !(1 == ~T1_E~0); 1270948#L689-1 assume !(1 == ~T2_E~0); 1271164#L694-1 assume !(1 == ~T3_E~0); 1271162#L699-1 assume !(1 == ~T4_E~0); 1271163#L704-1 assume !(1 == ~T5_E~0); 1271121#L709-1 assume !(1 == ~E_M~0); 1271057#L714-1 assume !(1 == ~E_1~0); 1271058#L719-1 assume !(1 == ~E_2~0); 1271275#L724-1 assume !(1 == ~E_3~0); 1270852#L729-1 assume !(1 == ~E_4~0); 1270853#L734-1 assume !(1 == ~E_5~0); 1270981#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 1270982#L940 assume true; 1286622#L940-1 assume !false; 1286554#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1286552#L506 [2024-11-17 08:52:33,553 INFO L747 eck$LassoCheckResult]: Loop: 1286552#L506 assume true; 1286550#L506-1 assume !false; 1286548#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1286545#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1286543#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1286541#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1286539#L511 assume 0 != eval_~tmp~0#1; 1286536#L516-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1286533#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1286531#L516 havoc eval_~tmp_ndt_1~0#1; 1286529#L530-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1286527#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1286525#L530 havoc eval_~tmp_ndt_2~0#1; 1286524#L544-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1286523#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1286521#L544 havoc eval_~tmp_ndt_3~0#1; 1286518#L558-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1286515#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 1286516#L558 havoc eval_~tmp_ndt_4~0#1; 1286562#L572-1 assume !(0 == ~t4_st~0); 1286556#L586-1 assume !(0 == ~t5_st~0); 1286552#L506 [2024-11-17 08:52:33,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:33,554 INFO L85 PathProgramCache]: Analyzing trace with hash 1524792931, now seen corresponding path program 4 times [2024-11-17 08:52:33,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:33,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047341557] [2024-11-17 08:52:33,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:33,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:33,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:33,564 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:33,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:33,576 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:33,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:33,577 INFO L85 PathProgramCache]: Analyzing trace with hash -367022569, now seen corresponding path program 2 times [2024-11-17 08:52:33,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:33,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107249549] [2024-11-17 08:52:33,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:33,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:33,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:33,581 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:33,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:33,583 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:33,584 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:33,584 INFO L85 PathProgramCache]: Analyzing trace with hash -511090443, now seen corresponding path program 1 times [2024-11-17 08:52:33,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:33,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934676405] [2024-11-17 08:52:33,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:33,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:33,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:33,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:33,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:33,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1934676405] [2024-11-17 08:52:33,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1934676405] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:33,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:33,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:33,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005291537] [2024-11-17 08:52:33,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:33,693 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:33,694 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:33,694 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:33,694 INFO L87 Difference]: Start difference. First operand 97420 states and 131283 transitions. cyclomatic complexity: 33959 Second operand has 3 states, 3 states have (on average 32.333333333333336) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:34,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:34,640 INFO L93 Difference]: Finished difference Result 125141 states and 167283 transitions. [2024-11-17 08:52:34,640 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125141 states and 167283 transitions. [2024-11-17 08:52:35,174 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 122450 [2024-11-17 08:52:35,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125141 states to 125141 states and 167283 transitions. [2024-11-17 08:52:35,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125141 [2024-11-17 08:52:35,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125141 [2024-11-17 08:52:35,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125141 states and 167283 transitions. [2024-11-17 08:52:35,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:35,701 INFO L218 hiAutomatonCegarLoop]: Abstraction has 125141 states and 167283 transitions. [2024-11-17 08:52:35,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125141 states and 167283 transitions. [2024-11-17 08:52:37,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125141 to 122105. [2024-11-17 08:52:37,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122105 states, 122105 states have (on average 1.3408050448384587) internal successors, (163719), 122104 states have internal predecessors, (163719), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:37,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122105 states to 122105 states and 163719 transitions. [2024-11-17 08:52:37,518 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122105 states and 163719 transitions. [2024-11-17 08:52:37,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:37,519 INFO L425 stractBuchiCegarLoop]: Abstraction has 122105 states and 163719 transitions. [2024-11-17 08:52:37,519 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:52:37,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122105 states and 163719 transitions. [2024-11-17 08:52:37,818 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 119414 [2024-11-17 08:52:37,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:37,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:37,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:37,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:37,819 INFO L745 eck$LassoCheckResult]: Stem: 1494096#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1493372#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1493373#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1493749#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1493766#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1493767#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1493786#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1493355#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1493356#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1493582#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1493583#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1493616#L611-1 assume !(0 == ~M_E~0); 1493919#L616-1 assume !(0 == ~T1_E~0); 1493920#L621-1 assume !(0 == ~T2_E~0); 1493432#L626-1 assume !(0 == ~T3_E~0); 1493433#L631-1 assume !(0 == ~T4_E~0); 1493623#L636-1 assume !(0 == ~T5_E~0); 1493485#L641-1 assume !(0 == ~E_M~0); 1493486#L646-1 assume !(0 == ~E_1~0); 1493638#L651-1 assume !(0 == ~E_2~0); 1494002#L656-1 assume !(0 == ~E_3~0); 1493887#L661-1 assume !(0 == ~E_4~0); 1493888#L666-1 assume !(0 == ~E_5~0); 1493878#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1493635#L304-8 assume !(1 == ~m_pc~0); 1493636#L314-8 is_master_triggered_~__retres1~0#1 := 0; 1494073#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1493371#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1493345#L755-8 assume !(0 != activate_threads_~tmp~1#1); 1493346#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1493476#L323-8 assume !(1 == ~t1_pc~0); 1493576#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1493770#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1493765#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1493762#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 1493763#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1493682#L342-8 assume !(1 == ~t2_pc~0); 1493498#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1493499#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1493797#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1493846#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 1493742#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1493743#L361-8 assume !(1 == ~t3_pc~0); 1493800#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 1494013#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1493337#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1493338#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 1493972#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1493444#L380-8 assume !(1 == ~t4_pc~0); 1493445#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1493610#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1493659#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1493409#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 1493410#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1494037#L399-8 assume !(1 == ~t5_pc~0); 1493503#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 1493504#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1493489#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1493391#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 1493392#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1493712#L679-1 assume !(1 == ~M_E~0); 1493521#L684-1 assume !(1 == ~T1_E~0); 1493522#L689-1 assume !(1 == ~T2_E~0); 1493739#L694-1 assume !(1 == ~T3_E~0); 1493735#L699-1 assume !(1 == ~T4_E~0); 1493736#L704-1 assume !(1 == ~T5_E~0); 1493695#L709-1 assume !(1 == ~E_M~0); 1493625#L714-1 assume !(1 == ~E_1~0); 1493626#L719-1 assume !(1 == ~E_2~0); 1493872#L724-1 assume !(1 == ~E_3~0); 1493423#L729-1 assume !(1 == ~E_4~0); 1493424#L734-1 assume !(1 == ~E_5~0); 1493553#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 1493554#L940 assume true; 1510758#L940-1 assume !false; 1510751#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1510749#L506 [2024-11-17 08:52:37,819 INFO L747 eck$LassoCheckResult]: Loop: 1510749#L506 assume true; 1510747#L506-1 assume !false; 1510745#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1510741#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1510739#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1510737#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1510735#L511 assume 0 != eval_~tmp~0#1; 1510731#L516-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1510727#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1510725#L516 havoc eval_~tmp_ndt_1~0#1; 1510723#L530-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1510719#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1510717#L530 havoc eval_~tmp_ndt_2~0#1; 1510715#L544-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1510711#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1510709#L544 havoc eval_~tmp_ndt_3~0#1; 1510707#L558-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1510703#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 1510701#L558 havoc eval_~tmp_ndt_4~0#1; 1510699#L572-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1510696#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 1510697#L572 havoc eval_~tmp_ndt_5~0#1; 1510753#L586-1 assume !(0 == ~t5_st~0); 1510749#L506 [2024-11-17 08:52:37,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:37,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1524792931, now seen corresponding path program 5 times [2024-11-17 08:52:37,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:37,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347106606] [2024-11-17 08:52:37,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:37,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:37,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:37,829 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:37,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:37,841 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:37,842 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:37,842 INFO L85 PathProgramCache]: Analyzing trace with hash -521295465, now seen corresponding path program 1 times [2024-11-17 08:52:37,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:37,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584441725] [2024-11-17 08:52:37,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:37,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:37,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:37,845 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:37,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:37,848 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:37,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:37,848 INFO L85 PathProgramCache]: Analyzing trace with hash -1531568907, now seen corresponding path program 1 times [2024-11-17 08:52:37,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:37,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541100078] [2024-11-17 08:52:37,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:37,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:37,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:37,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:37,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:37,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541100078] [2024-11-17 08:52:37,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541100078] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:37,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:37,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:37,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204122879] [2024-11-17 08:52:37,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:37,960 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:37,960 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:37,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:37,961 INFO L87 Difference]: Start difference. First operand 122105 states and 163719 transitions. cyclomatic complexity: 41710 Second operand has 3 states, 2 states have (on average 49.5) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:39,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:39,186 INFO L93 Difference]: Finished difference Result 158622 states and 210782 transitions. [2024-11-17 08:52:39,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158622 states and 210782 transitions. [2024-11-17 08:52:39,749 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 155109 [2024-11-17 08:52:40,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158622 states to 158622 states and 210782 transitions. [2024-11-17 08:52:40,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 158622 [2024-11-17 08:52:40,230 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 158622 [2024-11-17 08:52:40,230 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158622 states and 210782 transitions. [2024-11-17 08:52:40,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:40,316 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158622 states and 210782 transitions. [2024-11-17 08:52:40,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158622 states and 210782 transitions. [2024-11-17 08:52:42,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158622 to 156762. [2024-11-17 08:52:42,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156762 states, 156762 states have (on average 1.3327336982176803) internal successors, (208922), 156761 states have internal predecessors, (208922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:43,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156762 states to 156762 states and 208922 transitions. [2024-11-17 08:52:43,197 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156762 states and 208922 transitions. [2024-11-17 08:52:43,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:43,198 INFO L425 stractBuchiCegarLoop]: Abstraction has 156762 states and 208922 transitions. [2024-11-17 08:52:43,198 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-17 08:52:43,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156762 states and 208922 transitions. [2024-11-17 08:52:43,637 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 153249 [2024-11-17 08:52:43,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:43,637 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:43,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:43,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:43,638 INFO L745 eck$LassoCheckResult]: Stem: 1774763#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1774106#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1774107#L903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1774470#L419-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1774486#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1774487#L431 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1774506#L436 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1774090#L441 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1774091#L446 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1774316#L451 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1774317#L457 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1774349#L611-1 assume !(0 == ~M_E~0); 1774620#L616-1 assume !(0 == ~T1_E~0); 1774621#L621-1 assume !(0 == ~T2_E~0); 1774167#L626-1 assume !(0 == ~T3_E~0); 1774168#L631-1 assume !(0 == ~T4_E~0); 1774356#L636-1 assume !(0 == ~T5_E~0); 1774219#L641-1 assume !(0 == ~E_M~0); 1774220#L646-1 assume !(0 == ~E_1~0); 1774371#L651-1 assume !(0 == ~E_2~0); 1774694#L656-1 assume !(0 == ~E_3~0); 1774594#L661-1 assume !(0 == ~E_4~0); 1774595#L666-1 assume !(0 == ~E_5~0); 1774583#L672-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1774369#L304-8 assume !(1 == ~m_pc~0); 1774370#L314-8 is_master_triggered_~__retres1~0#1 := 0; 1774743#L307-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1774108#L316-8 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1774080#L755-8 assume !(0 != activate_threads_~tmp~1#1); 1774081#L761-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1774210#L323-8 assume !(1 == ~t1_pc~0); 1774308#L333-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1774489#L326-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1774485#L335-8 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1774481#L763-8 assume !(0 != activate_threads_~tmp___0~0#1); 1774482#L769-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1774412#L342-8 assume !(1 == ~t2_pc~0); 1774232#L352-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1774233#L345-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1774517#L354-8 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1774557#L771-8 assume !(0 != activate_threads_~tmp___1~0#1); 1774465#L777-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1774466#L361-8 assume !(1 == ~t3_pc~0); 1774519#L371-8 is_transmit3_triggered_~__retres1~3#1 := 0; 1774698#L364-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1774072#L373-8 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1774073#L779-8 assume !(0 != activate_threads_~tmp___2~0#1); 1774677#L785-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1774179#L380-8 assume !(1 == ~t4_pc~0); 1774180#L390-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1774342#L383-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1774390#L392-8 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1774146#L787-8 assume !(0 != activate_threads_~tmp___3~0#1); 1774147#L793-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1774719#L399-8 assume !(1 == ~t5_pc~0); 1774239#L409-8 is_transmit5_triggered_~__retres1~5#1 := 0; 1774240#L402-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1774223#L411-8 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1774126#L795-8 assume !(0 != activate_threads_~tmp___4~0#1); 1774127#L801-8 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1774440#L679-1 assume !(1 == ~M_E~0); 1774256#L684-1 assume !(1 == ~T1_E~0); 1774257#L689-1 assume !(1 == ~T2_E~0); 1774463#L694-1 assume !(1 == ~T3_E~0); 1774460#L699-1 assume !(1 == ~T4_E~0); 1774461#L704-1 assume !(1 == ~T5_E~0); 1774424#L709-1 assume !(1 == ~E_M~0); 1774360#L714-1 assume !(1 == ~E_1~0); 1774361#L719-1 assume !(1 == ~E_2~0); 1774579#L724-1 assume !(1 == ~E_3~0); 1774158#L729-1 assume !(1 == ~E_4~0); 1774159#L734-1 assume !(1 == ~E_5~0); 1774286#L740-1 assume true;assume { :end_inline_reset_delta_events } true; 1774287#L940 assume true; 1792533#L940-1 assume !false; 1792532#start_simulation_while_7_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1792530#L506 [2024-11-17 08:52:43,638 INFO L747 eck$LassoCheckResult]: Loop: 1792530#L506 assume true; 1792528#L506-1 assume !false; 1792526#eval_while_6_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1792522#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1792520#L486-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1792518#L497-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1792516#L511 assume 0 != eval_~tmp~0#1; 1792512#L516-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1792508#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1792506#L516 havoc eval_~tmp_ndt_1~0#1; 1792504#L530-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1792500#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1792499#L530 havoc eval_~tmp_ndt_2~0#1; 1792498#L544-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1792496#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1792495#L544 havoc eval_~tmp_ndt_3~0#1; 1792494#L558-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1792492#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 1792491#L558 havoc eval_~tmp_ndt_4~0#1; 1792490#L572-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1792488#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 1792487#L572 havoc eval_~tmp_ndt_5~0#1; 1792486#L586-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 1792484#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 1792485#L586 havoc eval_~tmp_ndt_6~0#1; 1792530#L506 [2024-11-17 08:52:43,638 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1524792931, now seen corresponding path program 6 times [2024-11-17 08:52:43,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523365955] [2024-11-17 08:52:43,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:43,649 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:43,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:43,664 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:43,664 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1546243223, now seen corresponding path program 1 times [2024-11-17 08:52:43,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1070141021] [2024-11-17 08:52:43,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:43,669 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:43,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:43,672 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:43,672 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,673 INFO L85 PathProgramCache]: Analyzing trace with hash 1336074357, now seen corresponding path program 1 times [2024-11-17 08:52:43,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,673 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725114869] [2024-11-17 08:52:43,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:43,682 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:43,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:43,702 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:45,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:45,150 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:45,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:45,480 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.11 08:52:45 BoogieIcfgContainer [2024-11-17 08:52:45,481 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-17 08:52:45,481 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-17 08:52:45,481 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-17 08:52:45,482 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-17 08:52:45,482 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:05" (3/4) ... [2024-11-17 08:52:45,484 INFO L140 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-17 08:52:45,579 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-17 08:52:45,579 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-17 08:52:45,580 INFO L158 Benchmark]: Toolchain (without parser) took 42487.67ms. Allocated memory was 153.1MB in the beginning and 15.0GB in the end (delta: 14.9GB). Free memory was 94.3MB in the beginning and 10.9GB in the end (delta: -10.8GB). Peak memory consumption was 4.1GB. Max. memory is 16.1GB. [2024-11-17 08:52:45,580 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 92.3MB. Free memory is still 45.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-17 08:52:45,581 INFO L158 Benchmark]: CACSL2BoogieTranslator took 429.23ms. Allocated memory is still 153.1MB. Free memory was 93.9MB in the beginning and 116.3MB in the end (delta: -22.4MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2024-11-17 08:52:45,581 INFO L158 Benchmark]: Boogie Procedure Inliner took 80.91ms. Allocated memory is still 153.1MB. Free memory was 116.3MB in the beginning and 111.4MB in the end (delta: 4.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-17 08:52:45,581 INFO L158 Benchmark]: Boogie Preprocessor took 98.43ms. Allocated memory is still 153.1MB. Free memory was 111.4MB in the beginning and 106.5MB in the end (delta: 4.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-17 08:52:45,581 INFO L158 Benchmark]: IcfgBuilder took 1472.66ms. Allocated memory is still 153.1MB. Free memory was 106.5MB in the beginning and 91.6MB in the end (delta: 14.8MB). Peak memory consumption was 58.8MB. Max. memory is 16.1GB. [2024-11-17 08:52:45,582 INFO L158 Benchmark]: BuchiAutomizer took 40303.07ms. Allocated memory was 153.1MB in the beginning and 15.0GB in the end (delta: 14.9GB). Free memory was 91.6MB in the beginning and 10.9GB in the end (delta: -10.8GB). Peak memory consumption was 4.1GB. Max. memory is 16.1GB. [2024-11-17 08:52:45,582 INFO L158 Benchmark]: Witness Printer took 98.25ms. Allocated memory is still 15.0GB. Free memory was 10.9GB in the beginning and 10.9GB in the end (delta: 14.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-11-17 08:52:45,583 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 92.3MB. Free memory is still 45.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 429.23ms. Allocated memory is still 153.1MB. Free memory was 93.9MB in the beginning and 116.3MB in the end (delta: -22.4MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 80.91ms. Allocated memory is still 153.1MB. Free memory was 116.3MB in the beginning and 111.4MB in the end (delta: 4.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 98.43ms. Allocated memory is still 153.1MB. Free memory was 111.4MB in the beginning and 106.5MB in the end (delta: 4.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * IcfgBuilder took 1472.66ms. Allocated memory is still 153.1MB. Free memory was 106.5MB in the beginning and 91.6MB in the end (delta: 14.8MB). Peak memory consumption was 58.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 40303.07ms. Allocated memory was 153.1MB in the beginning and 15.0GB in the end (delta: 14.9GB). Free memory was 91.6MB in the beginning and 10.9GB in the end (delta: -10.8GB). Peak memory consumption was 4.1GB. Max. memory is 16.1GB. * Witness Printer took 98.25ms. Allocated memory is still 15.0GB. Free memory was 10.9GB in the beginning and 10.9GB in the end (delta: 14.7MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (22 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.22 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 156762 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 39.9s and 23 iterations. TraceHistogramMax:1. Analysis of lassos took 5.2s. Construction of modules took 0.9s. Büchi inclusion checks took 30.3s. Highest rank in rank-based complementation 0. Minimization of det autom 22. Minimization of nondet autom 0. Automata minimization 15.2s AutomataMinimizationTime, 22 MinimizatonAttempts, 36738 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 8.9s Buchi closure took 0.9s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 15312 SdHoareTripleChecker+Valid, 1.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 15312 mSDsluCounter, 34178 SdHoareTripleChecker+Invalid, 1.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 14826 mSDsCounter, 237 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 517 IncrementalHoareTripleChecker+Invalid, 754 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 237 mSolverCounterUnsat, 19352 mSDtfsCounter, 517 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 506]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 506]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-17 08:52:45,619 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)