./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:52:02,470 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:52:02,541 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:52:02,546 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:52:02,549 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:52:02,549 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:52:02,575 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:52:02,576 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:52:02,577 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:52:02,577 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:52:02,578 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:52:02,578 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:52:02,579 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:52:02,582 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:52:02,582 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:52:02,583 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:52:02,583 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:52:02,583 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:52:02,583 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:52:02,584 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:52:02,584 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:52:02,585 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:52:02,585 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:52:02,585 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:52:02,588 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:52:02,588 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:52:02,589 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:52:02,589 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:52:02,589 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:52:02,589 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:52:02,590 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:52:02,590 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:52:02,590 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:52:02,590 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:52:02,591 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:52:02,591 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:52:02,592 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:52:02,592 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:52:02,593 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:52:02,593 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:52:02,594 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2024-11-17 08:52:02,854 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:52:02,881 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:52:02,884 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:52:02,886 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:52:02,886 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:52:02,888 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2024-11-17 08:52:04,343 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:52:04,552 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:52:04,553 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2024-11-17 08:52:04,567 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1a2991e38/5691de760d304584b5bb266d0e0c44c3/FLAG695de348f [2024-11-17 08:52:04,580 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1a2991e38/5691de760d304584b5bb266d0e0c44c3 [2024-11-17 08:52:04,583 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:52:04,584 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:52:04,585 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:04,585 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:52:04,590 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:52:04,591 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:04" (1/1) ... [2024-11-17 08:52:04,592 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@196a80ec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:04, skipping insertion in model container [2024-11-17 08:52:04,593 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:04" (1/1) ... [2024-11-17 08:52:04,636 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:52:04,975 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:04,995 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:52:05,051 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:05,080 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:52:05,081 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05 WrapperNode [2024-11-17 08:52:05,081 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:05,082 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:05,082 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:52:05,082 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:52:05,089 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,104 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,181 INFO L138 Inliner]: procedures = 40, calls = 51, calls flagged for inlining = 46, calls inlined = 116, statements flattened = 1670 [2024-11-17 08:52:05,182 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:05,183 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:52:05,183 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:52:05,183 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:52:05,193 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,194 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,204 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,245 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:52:05,249 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,249 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,274 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,279 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,286 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,294 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,302 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:52:05,303 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:52:05,304 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:52:05,304 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:52:05,305 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (1/1) ... [2024-11-17 08:52:05,310 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:05,320 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:05,337 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:05,341 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:52:05,392 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:52:05,393 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:52:05,393 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:52:05,393 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:52:05,477 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:52:05,479 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:06,791 INFO L? ?]: Removed 322 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:06,792 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:06,830 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:06,831 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:06,831 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:06 BoogieIcfgContainer [2024-11-17 08:52:06,832 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:06,833 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:06,833 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:06,839 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:06,840 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:06,841 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:52:04" (1/3) ... [2024-11-17 08:52:06,842 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@47a65072 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:06, skipping insertion in model container [2024-11-17 08:52:06,842 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:06,842 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:05" (2/3) ... [2024-11-17 08:52:06,842 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@47a65072 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:06, skipping insertion in model container [2024-11-17 08:52:06,842 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:06,842 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:06" (3/3) ... [2024-11-17 08:52:06,844 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2024-11-17 08:52:06,922 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:06,923 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:06,923 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:06,923 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:06,923 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:06,923 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:06,924 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:06,924 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:06,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 736 states, 735 states have (on average 1.4952380952380953) internal successors, (1099), 735 states have internal predecessors, (1099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 640 [2024-11-17 08:52:07,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,021 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,022 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:07,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 736 states, 735 states have (on average 1.4952380952380953) internal successors, (1099), 735 states have internal predecessors, (1099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 640 [2024-11-17 08:52:07,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,062 INFO L745 eck$LassoCheckResult]: Stem: 714#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 39#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 524#L1028true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337#L480-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 550#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 712#L492true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 719#L497true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 56#L502true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 565#L507true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 186#L512true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 657#L517true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 646#L523true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 500#L696-1true assume !(0 == ~M_E~0); 566#L701-1true assume !(0 == ~T1_E~0); 597#L706-1true assume !(0 == ~T2_E~0); 314#L711-1true assume !(0 == ~T3_E~0); 139#L716-1true assume !(0 == ~T4_E~0); 618#L721-1true assume !(0 == ~T5_E~0); 279#L726-1true assume !(0 == ~T6_E~0); 494#L731-1true assume !(0 == ~E_M~0); 252#L736-1true assume !(0 == ~E_1~0); 320#L741-1true assume !(0 == ~E_2~0); 654#L746-1true assume !(0 == ~E_3~0); 173#L751-1true assume !(0 == ~E_4~0); 236#L756-1true assume !(0 == ~E_5~0); 136#L761-1true assume !(0 == ~E_6~0); 619#L767-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 302#L346-9true assume 1 == ~m_pc~0; 46#L347-9true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 146#L349-9true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78#L358-9true assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 182#L861-9true assume !(0 != activate_threads_~tmp~1#1); 120#L867-9true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 425#L365-9true assume 1 == ~t1_pc~0; 581#L366-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 218#L368-9true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12#L377-9true assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 397#L869-9true assume !(0 != activate_threads_~tmp___0~0#1); 504#L875-9true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 304#L384-9true assume 1 == ~t2_pc~0; 225#L385-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 664#L387-9true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 643#L396-9true assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 97#L877-9true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 459#L883-9true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18#L403-9true assume 1 == ~t3_pc~0; 532#L404-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 347#L406-9true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 701#L415-9true assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 487#L885-9true assume !(0 != activate_threads_~tmp___2~0#1); 586#L891-9true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84#L422-9true assume 1 == ~t4_pc~0; 190#L423-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9#L425-9true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 547#L434-9true assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207#L893-9true assume !(0 != activate_threads_~tmp___3~0#1); 189#L899-9true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 633#L441-9true assume 1 == ~t5_pc~0; 647#L442-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 464#L444-9true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 728#L453-9true assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 533#L901-9true assume !(0 != activate_threads_~tmp___4~0#1); 541#L907-9true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50#L460-9true assume 1 == ~t6_pc~0; 674#L461-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 219#L463-9true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100#L472-9true assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 675#L909-9true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 684#L915-9true assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 704#L774-1true assume !(1 == ~M_E~0); 456#L779-1true assume !(1 == ~T1_E~0); 213#L784-1true assume !(1 == ~T2_E~0); 620#L789-1true assume !(1 == ~T3_E~0); 66#L794-1true assume !(1 == ~T4_E~0); 695#L799-1true assume !(1 == ~T5_E~0); 629#L804-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 689#L809-1true assume !(1 == ~E_M~0); 274#L814-1true assume !(1 == ~E_1~0); 14#L819-1true assume !(1 == ~E_2~0); 328#L824-1true assume !(1 == ~E_3~0); 681#L829-1true assume !(1 == ~E_4~0); 444#L834-1true assume !(1 == ~E_5~0); 129#L839-1true assume !(1 == ~E_6~0); 558#L845-1true assume true;assume { :end_inline_reset_delta_events } true; 21#L1065true [2024-11-17 08:52:07,067 INFO L747 eck$LassoCheckResult]: Loop: 21#L1065true assume true; 185#L1065-1true assume !false; 276#start_simulation_while_8_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 256#L577true assume !true; 644#L585true assume true; 275#L689true assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 419#L480true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 227#L696true assume 0 == ~M_E~0;~M_E~0 := 1; 722#L701true assume 0 == ~T1_E~0;~T1_E~0 := 1; 706#L706true assume 0 == ~T2_E~0;~T2_E~0 := 1; 222#L711true assume 0 == ~T3_E~0;~T3_E~0 := 1; 62#L716true assume 0 == ~T4_E~0;~T4_E~0 := 1; 95#L721true assume 0 == ~T5_E~0;~T5_E~0 := 1; 666#L726true assume !(0 == ~T6_E~0); 488#L731true assume 0 == ~E_M~0;~E_M~0 := 1; 210#L736true assume 0 == ~E_1~0;~E_1~0 := 1; 152#L741true assume 0 == ~E_2~0;~E_2~0 := 1; 472#L746true assume 0 == ~E_3~0;~E_3~0 := 1; 34#L751true assume 0 == ~E_4~0;~E_4~0 := 1; 461#L756true assume 0 == ~E_5~0;~E_5~0 := 1; 484#L761true assume 0 == ~E_6~0;~E_6~0 := 1; 697#L767true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 381#L346-1true assume 1 == ~m_pc~0; 721#L347-1true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 204#L349-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 616#L358-1true assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24#L861-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 349#L867-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 356#L365-1true assume 1 == ~t1_pc~0; 553#L366-1true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 691#L368-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 551#L377-1true assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 153#L869-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 512#L875-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42#L384-1true assume !(1 == ~t2_pc~0); 610#L394-1true is_transmit2_triggered_~__retres1~2#1 := 0; 470#L387-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 380#L396-1true assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 733#L877-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 403#L883-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 680#L403-1true assume 1 == ~t3_pc~0; 708#L404-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 142#L406-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 563#L415-1true assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 727#L885-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 413#L891-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 445#L422-1true assume 1 == ~t4_pc~0; 627#L423-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94#L425-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 514#L434-1true assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 630#L893-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 679#L899-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 157#L441-1true assume 1 == ~t5_pc~0; 214#L442-1true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 174#L444-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 209#L453-1true assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 101#L901-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 125#L907-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 636#L460-1true assume 1 == ~t6_pc~0; 233#L461-1true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 339#L463-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 493#L472-1true assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 392#L909-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 463#L915-1true assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 287#L774true assume 1 == ~M_E~0;~M_E~0 := 2; 540#L779true assume 1 == ~T1_E~0;~T1_E~0 := 2; 322#L784true assume 1 == ~T2_E~0;~T2_E~0 := 2; 454#L789true assume 1 == ~T3_E~0;~T3_E~0 := 2; 301#L794true assume 1 == ~T4_E~0;~T4_E~0 := 2; 518#L799true assume 1 == ~T5_E~0;~T5_E~0 := 2; 358#L804true assume 1 == ~T6_E~0;~T6_E~0 := 2; 331#L809true assume 1 == ~E_M~0;~E_M~0 := 2; 476#L814true assume 1 == ~E_1~0;~E_1~0 := 2; 611#L819true assume 1 == ~E_2~0;~E_2~0 := 2; 300#L824true assume 1 == ~E_3~0;~E_3~0 := 2; 544#L829true assume 1 == ~E_4~0;~E_4~0 := 2; 138#L834true assume 1 == ~E_5~0;~E_5~0 := 2; 393#L839true assume 1 == ~E_6~0;~E_6~0 := 2; 513#L845true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 465#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 243#L556-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 281#L568-1true assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 31#L1084true assume !(0 == start_simulation_~tmp~3#1); 242#L1095true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 409#L530true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 718#L556true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 345#L568true assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 176#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 705#L1041true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81#L1047true assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 181#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 21#L1065true [2024-11-17 08:52:07,077 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,081 INFO L85 PathProgramCache]: Analyzing trace with hash 1000952746, now seen corresponding path program 1 times [2024-11-17 08:52:07,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899592998] [2024-11-17 08:52:07,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899592998] [2024-11-17 08:52:07,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899592998] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,386 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:07,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785778914] [2024-11-17 08:52:07,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,398 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:07,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,400 INFO L85 PathProgramCache]: Analyzing trace with hash 469975940, now seen corresponding path program 1 times [2024-11-17 08:52:07,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787929602] [2024-11-17 08:52:07,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787929602] [2024-11-17 08:52:07,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [787929602] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:07,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178643300] [2024-11-17 08:52:07,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,459 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:07,492 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:07,495 INFO L87 Difference]: Start difference. First operand has 736 states, 735 states have (on average 1.4952380952380953) internal successors, (1099), 735 states have internal predecessors, (1099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,555 INFO L93 Difference]: Finished difference Result 725 states and 1067 transitions. [2024-11-17 08:52:07,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 725 states and 1067 transitions. [2024-11-17 08:52:07,562 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:07,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 725 states to 718 states and 1060 transitions. [2024-11-17 08:52:07,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 718 [2024-11-17 08:52:07,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 718 [2024-11-17 08:52:07,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 718 states and 1060 transitions. [2024-11-17 08:52:07,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,585 INFO L218 hiAutomatonCegarLoop]: Abstraction has 718 states and 1060 transitions. [2024-11-17 08:52:07,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states and 1060 transitions. [2024-11-17 08:52:07,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 718. [2024-11-17 08:52:07,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 718 states, 718 states have (on average 1.4763231197771587) internal successors, (1060), 717 states have internal predecessors, (1060), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 1060 transitions. [2024-11-17 08:52:07,648 INFO L240 hiAutomatonCegarLoop]: Abstraction has 718 states and 1060 transitions. [2024-11-17 08:52:07,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:07,653 INFO L425 stractBuchiCegarLoop]: Abstraction has 718 states and 1060 transitions. [2024-11-17 08:52:07,653 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:07,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 718 states and 1060 transitions. [2024-11-17 08:52:07,658 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:07,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:07,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:07,660 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,660 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:07,661 INFO L745 eck$LassoCheckResult]: Stem: 2187#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1550#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1551#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1997#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1998#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 2148#L492 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 2186#L497 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1586#L502 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1587#L507 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1813#L512 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1814#L517 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2177#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2128#L696-1 assume !(0 == ~M_E~0); 2129#L701-1 assume !(0 == ~T1_E~0); 2154#L706-1 assume !(0 == ~T2_E~0); 1969#L711-1 assume !(0 == ~T3_E~0); 1745#L716-1 assume !(0 == ~T4_E~0); 1746#L721-1 assume !(0 == ~T5_E~0); 1932#L726-1 assume !(0 == ~T6_E~0); 1933#L731-1 assume !(0 == ~E_M~0); 1897#L736-1 assume !(0 == ~E_1~0); 1898#L741-1 assume !(0 == ~E_2~0); 1976#L746-1 assume !(0 == ~E_3~0); 1800#L751-1 assume !(0 == ~E_4~0); 1801#L756-1 assume !(0 == ~E_5~0); 1736#L761-1 assume !(0 == ~E_6~0); 1737#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1959#L346-9 assume 1 == ~m_pc~0; 1563#L347-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1564#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1630#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1631#L861-9 assume !(0 != activate_threads_~tmp~1#1); 1706#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1707#L365-9 assume 1 == ~t1_pc~0; 2079#L366-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1856#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1492#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1493#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 2060#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1960#L384-9 assume 1 == ~t2_pc~0; 1861#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1637#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2175#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1668#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1669#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1504#L403-9 assume 1 == ~t3_pc~0; 1505#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2007#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2008#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2119#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 2120#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1640#L422-9 assume 1 == ~t4_pc~0; 1641#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1485#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1486#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1844#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 1818#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1819#L441-9 assume 1 == ~t5_pc~0; 2173#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2101#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2102#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2142#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 2143#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1572#L460-9 assume 1 == ~t6_pc~0; 1573#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1857#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1673#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1674#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2180#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2182#L774-1 assume !(1 == ~M_E~0); 2098#L779-1 assume !(1 == ~T1_E~0); 1850#L784-1 assume !(1 == ~T2_E~0); 1851#L789-1 assume !(1 == ~T3_E~0); 1607#L794-1 assume !(1 == ~T4_E~0); 1608#L799-1 assume !(1 == ~T5_E~0); 2170#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2171#L809-1 assume !(1 == ~E_M~0); 1926#L814-1 assume !(1 == ~E_1~0); 1500#L819-1 assume !(1 == ~E_2~0); 1501#L824-1 assume !(1 == ~E_3~0); 1986#L829-1 assume !(1 == ~E_4~0); 2092#L834-1 assume !(1 == ~E_5~0); 1722#L839-1 assume !(1 == ~E_6~0); 1723#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 1512#L1065 [2024-11-17 08:52:07,661 INFO L747 eck$LassoCheckResult]: Loop: 1512#L1065 assume true; 1513#L1065-1 assume !false; 1812#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1904#L577 assume true; 1595#L577-1 assume !false; 1596#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1792#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1503#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1536#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2058#L582 assume !(0 != eval_~tmp~0#1); 2176#L585 assume true; 1927#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1928#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1865#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 1866#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2184#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1860#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1600#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1601#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1663#L726 assume !(0 == ~T6_E~0); 2121#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 1849#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 1763#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 1764#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 1541#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 1542#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 2100#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 2117#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2045#L346-1 assume !(1 == ~m_pc~0); 1548#L356-1 is_master_triggered_~__retres1~0#1 := 0; 1549#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1838#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1519#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1520#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2011#L365-1 assume 1 == ~t1_pc~0; 2020#L366-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1931#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2147#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1765#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1766#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1554#L384-1 assume 1 == ~t2_pc~0; 1555#L385-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1982#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2043#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2044#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2064#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2065#L403-1 assume 1 == ~t3_pc~0; 2181#L404-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1747#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1748#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2153#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2072#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2073#L422-1 assume !(1 == ~t4_pc~0); 1648#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1649#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1662#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2133#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2169#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1768#L441-1 assume 1 == ~t5_pc~0; 1769#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1796#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1797#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1671#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1672#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1713#L460-1 assume !(1 == ~t6_pc~0); 1873#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1872#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1999#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2055#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2056#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1940#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 1941#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1977#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1978#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1955#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1956#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2022#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1987#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 1988#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 2109#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 1953#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 1954#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 1738#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 1739#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 2057#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2103#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1605#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1883#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1526#L1084 assume !(0 == start_simulation_~tmp~3#1); 1528#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1882#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1581#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2005#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1802#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1803#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1634#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1635#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1512#L1065 [2024-11-17 08:52:07,662 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1572203979, now seen corresponding path program 1 times [2024-11-17 08:52:07,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781077963] [2024-11-17 08:52:07,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,774 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781077963] [2024-11-17 08:52:07,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781077963] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:07,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121903508] [2024-11-17 08:52:07,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,775 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:07,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:07,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1235976335, now seen corresponding path program 1 times [2024-11-17 08:52:07,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:07,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1263086437] [2024-11-17 08:52:07,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:07,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:07,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:07,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:07,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:07,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1263086437] [2024-11-17 08:52:07,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1263086437] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:07,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:07,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:07,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779925464] [2024-11-17 08:52:07,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:07,951 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:07,951 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:07,952 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:07,952 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:07,952 INFO L87 Difference]: Start difference. First operand 718 states and 1060 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:07,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:07,980 INFO L93 Difference]: Finished difference Result 718 states and 1059 transitions. [2024-11-17 08:52:07,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 718 states and 1059 transitions. [2024-11-17 08:52:07,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:07,990 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 718 states to 718 states and 1059 transitions. [2024-11-17 08:52:07,991 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 718 [2024-11-17 08:52:07,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 718 [2024-11-17 08:52:07,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 718 states and 1059 transitions. [2024-11-17 08:52:07,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:07,994 INFO L218 hiAutomatonCegarLoop]: Abstraction has 718 states and 1059 transitions. [2024-11-17 08:52:07,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states and 1059 transitions. [2024-11-17 08:52:08,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 718. [2024-11-17 08:52:08,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 718 states, 718 states have (on average 1.4749303621169916) internal successors, (1059), 717 states have internal predecessors, (1059), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 1059 transitions. [2024-11-17 08:52:08,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 718 states and 1059 transitions. [2024-11-17 08:52:08,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,010 INFO L425 stractBuchiCegarLoop]: Abstraction has 718 states and 1059 transitions. [2024-11-17 08:52:08,011 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:08,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 718 states and 1059 transitions. [2024-11-17 08:52:08,014 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,016 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,019 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,019 INFO L745 eck$LassoCheckResult]: Stem: 3632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2993#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2994#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3442#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3443#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3592#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3631#L497 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3031#L502 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3032#L507 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3258#L512 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3259#L517 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3622#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3573#L696-1 assume !(0 == ~M_E~0); 3574#L701-1 assume !(0 == ~T1_E~0); 3599#L706-1 assume !(0 == ~T2_E~0); 3414#L711-1 assume !(0 == ~T3_E~0); 3185#L716-1 assume !(0 == ~T4_E~0); 3186#L721-1 assume !(0 == ~T5_E~0); 3375#L726-1 assume !(0 == ~T6_E~0); 3376#L731-1 assume !(0 == ~E_M~0); 3342#L736-1 assume !(0 == ~E_1~0); 3343#L741-1 assume !(0 == ~E_2~0); 3421#L746-1 assume !(0 == ~E_3~0); 3241#L751-1 assume !(0 == ~E_4~0); 3242#L756-1 assume !(0 == ~E_5~0); 3179#L761-1 assume !(0 == ~E_6~0); 3180#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3402#L346-9 assume 1 == ~m_pc~0; 3008#L347-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3009#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3073#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3074#L861-9 assume !(0 != activate_threads_~tmp~1#1); 3151#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3152#L365-9 assume 1 == ~t1_pc~0; 3524#L366-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3301#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2937#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2938#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 3505#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3405#L384-9 assume 1 == ~t2_pc~0; 3306#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3082#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3620#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3112#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3113#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2949#L403-9 assume 1 == ~t3_pc~0; 2950#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3452#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3453#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3564#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 3565#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3085#L422-9 assume 1 == ~t4_pc~0; 3086#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2930#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2931#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3289#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 3263#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3264#L441-9 assume 1 == ~t5_pc~0; 3618#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3546#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3547#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3587#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 3588#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3017#L460-9 assume 1 == ~t6_pc~0; 3018#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3302#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3116#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3117#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3625#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3627#L774-1 assume !(1 == ~M_E~0); 3543#L779-1 assume !(1 == ~T1_E~0); 3295#L784-1 assume !(1 == ~T2_E~0); 3296#L789-1 assume !(1 == ~T3_E~0); 3052#L794-1 assume !(1 == ~T4_E~0); 3053#L799-1 assume !(1 == ~T5_E~0); 3614#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3615#L809-1 assume !(1 == ~E_M~0); 3371#L814-1 assume !(1 == ~E_1~0); 2941#L819-1 assume !(1 == ~E_2~0); 2942#L824-1 assume !(1 == ~E_3~0); 3430#L829-1 assume !(1 == ~E_4~0); 3537#L834-1 assume !(1 == ~E_5~0); 3166#L839-1 assume !(1 == ~E_6~0); 3167#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 2957#L1065 [2024-11-17 08:52:08,021 INFO L747 eck$LassoCheckResult]: Loop: 2957#L1065 assume true; 2958#L1065-1 assume !false; 3257#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3349#L577 assume true; 3040#L577-1 assume !false; 3041#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3237#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2948#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2981#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3503#L582 assume !(0 != eval_~tmp~0#1); 3621#L585 assume true; 3372#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3373#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3310#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 3311#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3629#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3304#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3045#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3046#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3108#L726 assume !(0 == ~T6_E~0); 3566#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 3294#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 3208#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 3209#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 2982#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 2983#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 3545#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 3562#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3490#L346-1 assume 1 == ~m_pc~0; 3491#L347-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2998#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3286#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2964#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2965#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3456#L365-1 assume !(1 == ~t1_pc~0); 3377#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 3378#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3593#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3210#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3211#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2999#L384-1 assume 1 == ~t2_pc~0; 3000#L385-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3427#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3488#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3489#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3509#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3510#L403-1 assume 1 == ~t3_pc~0; 3626#L404-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3192#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3193#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3598#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3517#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3518#L422-1 assume 1 == ~t4_pc~0; 3538#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3094#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3107#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3578#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3616#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3215#L441-1 assume 1 == ~t5_pc~0; 3216#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3243#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3244#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3118#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3119#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3160#L460-1 assume 1 == ~t6_pc~0; 3316#L461-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3317#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3444#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3500#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3501#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3385#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 3386#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3422#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3423#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3400#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3401#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3467#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3433#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 3434#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 3555#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 3398#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 3399#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 3183#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 3184#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 3502#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3548#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3050#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3328#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2975#L1084 assume !(0 == start_simulation_~tmp~3#1); 2977#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3327#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3026#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3450#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3247#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3248#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3079#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3080#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 2957#L1065 [2024-11-17 08:52:08,022 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1452084106, now seen corresponding path program 1 times [2024-11-17 08:52:08,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293572344] [2024-11-17 08:52:08,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293572344] [2024-11-17 08:52:08,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1293572344] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:08,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306827706] [2024-11-17 08:52:08,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,088 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,089 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1186095531, now seen corresponding path program 1 times [2024-11-17 08:52:08,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1674431165] [2024-11-17 08:52:08,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1674431165] [2024-11-17 08:52:08,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1674431165] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660888371] [2024-11-17 08:52:08,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,185 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,185 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:08,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:08,186 INFO L87 Difference]: Start difference. First operand 718 states and 1059 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,200 INFO L93 Difference]: Finished difference Result 718 states and 1058 transitions. [2024-11-17 08:52:08,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 718 states and 1058 transitions. [2024-11-17 08:52:08,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 718 states to 718 states and 1058 transitions. [2024-11-17 08:52:08,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 718 [2024-11-17 08:52:08,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 718 [2024-11-17 08:52:08,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 718 states and 1058 transitions. [2024-11-17 08:52:08,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,210 INFO L218 hiAutomatonCegarLoop]: Abstraction has 718 states and 1058 transitions. [2024-11-17 08:52:08,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states and 1058 transitions. [2024-11-17 08:52:08,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 718. [2024-11-17 08:52:08,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 718 states, 718 states have (on average 1.4735376044568245) internal successors, (1058), 717 states have internal predecessors, (1058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 1058 transitions. [2024-11-17 08:52:08,221 INFO L240 hiAutomatonCegarLoop]: Abstraction has 718 states and 1058 transitions. [2024-11-17 08:52:08,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,223 INFO L425 stractBuchiCegarLoop]: Abstraction has 718 states and 1058 transitions. [2024-11-17 08:52:08,223 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:08,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 718 states and 1058 transitions. [2024-11-17 08:52:08,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,228 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,228 INFO L745 eck$LassoCheckResult]: Stem: 5077#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4438#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4439#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4887#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4888#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5037#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5076#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4476#L502 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4477#L507 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4703#L512 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4704#L517 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5067#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5018#L696-1 assume !(0 == ~M_E~0); 5019#L701-1 assume !(0 == ~T1_E~0); 5044#L706-1 assume !(0 == ~T2_E~0); 4859#L711-1 assume !(0 == ~T3_E~0); 4633#L716-1 assume !(0 == ~T4_E~0); 4634#L721-1 assume !(0 == ~T5_E~0); 4820#L726-1 assume !(0 == ~T6_E~0); 4821#L731-1 assume !(0 == ~E_M~0); 4787#L736-1 assume !(0 == ~E_1~0); 4788#L741-1 assume !(0 == ~E_2~0); 4866#L746-1 assume !(0 == ~E_3~0); 4690#L751-1 assume !(0 == ~E_4~0); 4691#L756-1 assume !(0 == ~E_5~0); 4624#L761-1 assume !(0 == ~E_6~0); 4625#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4849#L346-9 assume 1 == ~m_pc~0; 4453#L347-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4454#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4518#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4519#L861-9 assume !(0 != activate_threads_~tmp~1#1); 4596#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4597#L365-9 assume 1 == ~t1_pc~0; 4969#L366-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4746#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4382#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4383#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 4950#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4850#L384-9 assume 1 == ~t2_pc~0; 4751#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4527#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5065#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4558#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4559#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4394#L403-9 assume 1 == ~t3_pc~0; 4395#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4897#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4898#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5009#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 5010#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4530#L422-9 assume 1 == ~t4_pc~0; 4531#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4375#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4376#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4734#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 4708#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4709#L441-9 assume 1 == ~t5_pc~0; 5063#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4991#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4992#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5032#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 5033#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4462#L460-9 assume 1 == ~t6_pc~0; 4463#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4747#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4563#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4564#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5070#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5072#L774-1 assume !(1 == ~M_E~0); 4988#L779-1 assume !(1 == ~T1_E~0); 4740#L784-1 assume !(1 == ~T2_E~0); 4741#L789-1 assume !(1 == ~T3_E~0); 4497#L794-1 assume !(1 == ~T4_E~0); 4498#L799-1 assume !(1 == ~T5_E~0); 5060#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5061#L809-1 assume !(1 == ~E_M~0); 4816#L814-1 assume !(1 == ~E_1~0); 4390#L819-1 assume !(1 == ~E_2~0); 4391#L824-1 assume !(1 == ~E_3~0); 4876#L829-1 assume !(1 == ~E_4~0); 4982#L834-1 assume !(1 == ~E_5~0); 4612#L839-1 assume !(1 == ~E_6~0); 4613#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 4402#L1065 [2024-11-17 08:52:08,228 INFO L747 eck$LassoCheckResult]: Loop: 4402#L1065 assume true; 4403#L1065-1 assume !false; 4702#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4794#L577 assume true; 4485#L577-1 assume !false; 4486#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4682#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4393#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4426#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4948#L582 assume !(0 != eval_~tmp~0#1); 5066#L585 assume true; 4817#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4818#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4755#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 4756#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5074#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4749#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4490#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4491#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4553#L726 assume !(0 == ~T6_E~0); 5011#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 4739#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 4653#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 4654#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 4429#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 4430#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 4990#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 5007#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4935#L346-1 assume 1 == ~m_pc~0; 4936#L347-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4443#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4731#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4411#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4412#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4901#L365-1 assume !(1 == ~t1_pc~0); 4822#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 4823#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5038#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4655#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4656#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4446#L384-1 assume !(1 == ~t2_pc~0); 4448#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 4872#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4933#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4934#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4954#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4955#L403-1 assume !(1 == ~t3_pc~0); 4723#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 4637#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4638#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5043#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4962#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4963#L422-1 assume 1 == ~t4_pc~0; 4983#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4539#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4552#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5023#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5059#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4658#L441-1 assume 1 == ~t5_pc~0; 4659#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4686#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4687#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4561#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4562#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4601#L460-1 assume 1 == ~t6_pc~0; 4760#L461-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4761#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4889#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4945#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4946#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4830#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 4831#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4867#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4868#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4845#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4846#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4912#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4877#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 4878#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 4999#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 4842#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 4843#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 4628#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 4629#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 4947#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4993#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4493#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4773#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4416#L1084 assume !(0 == start_simulation_~tmp~3#1); 4418#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4772#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4471#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4895#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4692#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4693#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4524#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4525#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4402#L1065 [2024-11-17 08:52:08,229 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,229 INFO L85 PathProgramCache]: Analyzing trace with hash 1032567275, now seen corresponding path program 1 times [2024-11-17 08:52:08,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405407877] [2024-11-17 08:52:08,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405407877] [2024-11-17 08:52:08,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405407877] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:08,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091828932] [2024-11-17 08:52:08,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,274 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,275 INFO L85 PathProgramCache]: Analyzing trace with hash -904817039, now seen corresponding path program 1 times [2024-11-17 08:52:08,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472707349] [2024-11-17 08:52:08,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,353 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472707349] [2024-11-17 08:52:08,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [472707349] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031243137] [2024-11-17 08:52:08,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,355 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:08,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:08,358 INFO L87 Difference]: Start difference. First operand 718 states and 1058 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,373 INFO L93 Difference]: Finished difference Result 718 states and 1057 transitions. [2024-11-17 08:52:08,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 718 states and 1057 transitions. [2024-11-17 08:52:08,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,382 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 718 states to 718 states and 1057 transitions. [2024-11-17 08:52:08,382 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 718 [2024-11-17 08:52:08,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 718 [2024-11-17 08:52:08,383 INFO L73 IsDeterministic]: Start isDeterministic. Operand 718 states and 1057 transitions. [2024-11-17 08:52:08,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,384 INFO L218 hiAutomatonCegarLoop]: Abstraction has 718 states and 1057 transitions. [2024-11-17 08:52:08,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states and 1057 transitions. [2024-11-17 08:52:08,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 718. [2024-11-17 08:52:08,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 718 states, 718 states have (on average 1.4721448467966574) internal successors, (1057), 717 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 1057 transitions. [2024-11-17 08:52:08,394 INFO L240 hiAutomatonCegarLoop]: Abstraction has 718 states and 1057 transitions. [2024-11-17 08:52:08,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,396 INFO L425 stractBuchiCegarLoop]: Abstraction has 718 states and 1057 transitions. [2024-11-17 08:52:08,396 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:08,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 718 states and 1057 transitions. [2024-11-17 08:52:08,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,403 INFO L745 eck$LassoCheckResult]: Stem: 6522#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5887#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5888#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6332#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6333#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 6483#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6521#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5921#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5922#L507 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6148#L512 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6149#L517 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6512#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6463#L696-1 assume !(0 == ~M_E~0); 6464#L701-1 assume !(0 == ~T1_E~0); 6489#L706-1 assume !(0 == ~T2_E~0); 6305#L711-1 assume !(0 == ~T3_E~0); 6080#L716-1 assume !(0 == ~T4_E~0); 6081#L721-1 assume !(0 == ~T5_E~0); 6267#L726-1 assume !(0 == ~T6_E~0); 6268#L731-1 assume !(0 == ~E_M~0); 6234#L736-1 assume !(0 == ~E_1~0); 6235#L741-1 assume !(0 == ~E_2~0); 6311#L746-1 assume !(0 == ~E_3~0); 6135#L751-1 assume !(0 == ~E_4~0); 6136#L756-1 assume !(0 == ~E_5~0); 6071#L761-1 assume !(0 == ~E_6~0); 6072#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6294#L346-9 assume 1 == ~m_pc~0; 5898#L347-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5899#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5965#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5966#L861-9 assume !(0 != activate_threads_~tmp~1#1); 6041#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6042#L365-9 assume 1 == ~t1_pc~0; 6414#L366-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6191#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5827#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5828#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 6395#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6295#L384-9 assume 1 == ~t2_pc~0; 6196#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5972#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6510#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6002#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6003#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5839#L403-9 assume 1 == ~t3_pc~0; 5840#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6342#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6343#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6454#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 6455#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5975#L422-9 assume 1 == ~t4_pc~0; 5976#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5820#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5821#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6179#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 6153#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6154#L441-9 assume 1 == ~t5_pc~0; 6508#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6436#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6437#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6477#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 6478#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5907#L460-9 assume 1 == ~t6_pc~0; 5908#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6192#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6006#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6007#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6515#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6517#L774-1 assume !(1 == ~M_E~0); 6433#L779-1 assume !(1 == ~T1_E~0); 6185#L784-1 assume !(1 == ~T2_E~0); 6186#L789-1 assume !(1 == ~T3_E~0); 5942#L794-1 assume !(1 == ~T4_E~0); 5943#L799-1 assume !(1 == ~T5_E~0); 6504#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6505#L809-1 assume !(1 == ~E_M~0); 6261#L814-1 assume !(1 == ~E_1~0); 5831#L819-1 assume !(1 == ~E_2~0); 5832#L824-1 assume !(1 == ~E_3~0); 6320#L829-1 assume !(1 == ~E_4~0); 6427#L834-1 assume !(1 == ~E_5~0); 6056#L839-1 assume !(1 == ~E_6~0); 6057#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 5847#L1065 [2024-11-17 08:52:08,404 INFO L747 eck$LassoCheckResult]: Loop: 5847#L1065 assume true; 5848#L1065-1 assume !false; 6147#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6239#L577 assume true; 5930#L577-1 assume !false; 5931#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6127#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5838#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5871#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6393#L582 assume !(0 != eval_~tmp~0#1); 6511#L585 assume true; 6262#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6263#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6200#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 6201#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6519#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6194#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5935#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5936#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5998#L726 assume !(0 == ~T6_E~0); 6456#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 6184#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 6098#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 6099#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 5872#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 5873#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 6435#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 6452#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6380#L346-1 assume 1 == ~m_pc~0; 6381#L347-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5886#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6176#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5854#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5855#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6346#L365-1 assume 1 == ~t1_pc~0; 6355#L366-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6266#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6482#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6100#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6101#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5889#L384-1 assume 1 == ~t2_pc~0; 5890#L385-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6317#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6378#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6379#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6399#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6400#L403-1 assume 1 == ~t3_pc~0; 6516#L404-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6082#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6083#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6488#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6407#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6408#L422-1 assume 1 == ~t4_pc~0; 6428#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5984#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5997#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6468#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6506#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6105#L441-1 assume 1 == ~t5_pc~0; 6106#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6131#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6132#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6008#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6009#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6050#L460-1 assume !(1 == ~t6_pc~0); 6208#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 6207#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6334#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6390#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6391#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6275#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 6276#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6312#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6313#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6290#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6291#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6357#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6323#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 6324#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 6445#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 6288#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 6289#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 6073#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 6074#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 6392#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6438#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5940#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6218#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5865#L1084 assume !(0 == start_simulation_~tmp~3#1); 5867#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6217#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5916#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6340#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6137#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6138#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5969#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5970#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 5847#L1065 [2024-11-17 08:52:08,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,406 INFO L85 PathProgramCache]: Analyzing trace with hash 1019034474, now seen corresponding path program 1 times [2024-11-17 08:52:08,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616015427] [2024-11-17 08:52:08,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,450 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616015427] [2024-11-17 08:52:08,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616015427] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,451 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:08,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722831952] [2024-11-17 08:52:08,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,452 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,453 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,453 INFO L85 PathProgramCache]: Analyzing trace with hash -384370453, now seen corresponding path program 1 times [2024-11-17 08:52:08,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216337463] [2024-11-17 08:52:08,454 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216337463] [2024-11-17 08:52:08,539 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216337463] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,539 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,539 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267686642] [2024-11-17 08:52:08,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,540 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,541 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:08,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:08,542 INFO L87 Difference]: Start difference. First operand 718 states and 1057 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,555 INFO L93 Difference]: Finished difference Result 718 states and 1056 transitions. [2024-11-17 08:52:08,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 718 states and 1056 transitions. [2024-11-17 08:52:08,560 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 718 states to 718 states and 1056 transitions. [2024-11-17 08:52:08,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 718 [2024-11-17 08:52:08,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 718 [2024-11-17 08:52:08,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 718 states and 1056 transitions. [2024-11-17 08:52:08,566 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,566 INFO L218 hiAutomatonCegarLoop]: Abstraction has 718 states and 1056 transitions. [2024-11-17 08:52:08,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states and 1056 transitions. [2024-11-17 08:52:08,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 718. [2024-11-17 08:52:08,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 718 states, 718 states have (on average 1.4707520891364902) internal successors, (1056), 717 states have internal predecessors, (1056), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 1056 transitions. [2024-11-17 08:52:08,576 INFO L240 hiAutomatonCegarLoop]: Abstraction has 718 states and 1056 transitions. [2024-11-17 08:52:08,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,579 INFO L425 stractBuchiCegarLoop]: Abstraction has 718 states and 1056 transitions. [2024-11-17 08:52:08,579 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:08,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 718 states and 1056 transitions. [2024-11-17 08:52:08,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,584 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,584 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,584 INFO L745 eck$LassoCheckResult]: Stem: 7967#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7328#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7329#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7777#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7778#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7927#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7966#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7366#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7367#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7593#L512 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7594#L517 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7957#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7908#L696-1 assume !(0 == ~M_E~0); 7909#L701-1 assume !(0 == ~T1_E~0); 7934#L706-1 assume !(0 == ~T2_E~0); 7749#L711-1 assume !(0 == ~T3_E~0); 7523#L716-1 assume !(0 == ~T4_E~0); 7524#L721-1 assume !(0 == ~T5_E~0); 7710#L726-1 assume !(0 == ~T6_E~0); 7711#L731-1 assume !(0 == ~E_M~0); 7677#L736-1 assume !(0 == ~E_1~0); 7678#L741-1 assume !(0 == ~E_2~0); 7756#L746-1 assume !(0 == ~E_3~0); 7578#L751-1 assume !(0 == ~E_4~0); 7579#L756-1 assume !(0 == ~E_5~0); 7514#L761-1 assume !(0 == ~E_6~0); 7515#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7737#L346-9 assume 1 == ~m_pc~0; 7343#L347-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7344#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7408#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7409#L861-9 assume !(0 != activate_threads_~tmp~1#1); 7486#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7487#L365-9 assume 1 == ~t1_pc~0; 7859#L366-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7636#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7272#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7273#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 7840#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7740#L384-9 assume 1 == ~t2_pc~0; 7641#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7417#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7955#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7448#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7449#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7284#L403-9 assume 1 == ~t3_pc~0; 7285#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7787#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7788#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7899#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 7900#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7420#L422-9 assume 1 == ~t4_pc~0; 7421#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7265#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7266#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7624#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 7598#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7599#L441-9 assume 1 == ~t5_pc~0; 7953#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7881#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7882#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7922#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 7923#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7352#L460-9 assume 1 == ~t6_pc~0; 7353#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7637#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7451#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7452#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7960#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7962#L774-1 assume !(1 == ~M_E~0); 7878#L779-1 assume !(1 == ~T1_E~0); 7630#L784-1 assume !(1 == ~T2_E~0); 7631#L789-1 assume !(1 == ~T3_E~0); 7387#L794-1 assume !(1 == ~T4_E~0); 7388#L799-1 assume !(1 == ~T5_E~0); 7949#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7950#L809-1 assume !(1 == ~E_M~0); 7706#L814-1 assume !(1 == ~E_1~0); 7280#L819-1 assume !(1 == ~E_2~0); 7281#L824-1 assume !(1 == ~E_3~0); 7765#L829-1 assume !(1 == ~E_4~0); 7872#L834-1 assume !(1 == ~E_5~0); 7502#L839-1 assume !(1 == ~E_6~0); 7503#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 7292#L1065 [2024-11-17 08:52:08,585 INFO L747 eck$LassoCheckResult]: Loop: 7292#L1065 assume true; 7293#L1065-1 assume !false; 7592#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7684#L577 assume true; 7375#L577-1 assume !false; 7376#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7572#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7283#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7316#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7838#L582 assume !(0 != eval_~tmp~0#1); 7956#L585 assume true; 7707#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7708#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7645#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 7646#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7964#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7639#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7380#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7381#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7443#L726 assume !(0 == ~T6_E~0); 7901#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 7629#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 7543#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 7544#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 7317#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 7318#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 7880#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 7897#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7825#L346-1 assume 1 == ~m_pc~0; 7826#L347-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7333#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7621#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7301#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7302#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7791#L365-1 assume !(1 == ~t1_pc~0); 7712#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 7713#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7928#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7545#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7546#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7334#L384-1 assume 1 == ~t2_pc~0; 7335#L385-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7762#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7823#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7824#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7844#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7845#L403-1 assume 1 == ~t3_pc~0; 7961#L404-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7527#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7528#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7933#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7852#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7853#L422-1 assume 1 == ~t4_pc~0; 7873#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7429#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7442#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7913#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7951#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7550#L441-1 assume !(1 == ~t5_pc~0); 7552#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 7580#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7581#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7453#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7454#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7495#L460-1 assume 1 == ~t6_pc~0; 7651#L461-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7652#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7779#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7835#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7836#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7720#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 7721#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7757#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7758#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7735#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7736#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7802#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7768#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 7769#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 7890#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 7733#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 7734#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 7518#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 7519#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 7837#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7884#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7383#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7663#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7310#L1084 assume !(0 == start_simulation_~tmp~3#1); 7312#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7660#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7361#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7785#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7582#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7583#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7414#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7415#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7292#L1065 [2024-11-17 08:52:08,586 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,586 INFO L85 PathProgramCache]: Analyzing trace with hash -89780725, now seen corresponding path program 1 times [2024-11-17 08:52:08,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,586 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91716920] [2024-11-17 08:52:08,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91716920] [2024-11-17 08:52:08,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91716920] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,624 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,625 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:08,625 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254824949] [2024-11-17 08:52:08,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,627 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,628 INFO L85 PathProgramCache]: Analyzing trace with hash 1292771246, now seen corresponding path program 1 times [2024-11-17 08:52:08,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186485487] [2024-11-17 08:52:08,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,691 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186485487] [2024-11-17 08:52:08,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186485487] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,692 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301151323] [2024-11-17 08:52:08,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,693 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,693 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,693 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:08,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:08,694 INFO L87 Difference]: Start difference. First operand 718 states and 1056 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,711 INFO L93 Difference]: Finished difference Result 718 states and 1055 transitions. [2024-11-17 08:52:08,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 718 states and 1055 transitions. [2024-11-17 08:52:08,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 718 states to 718 states and 1055 transitions. [2024-11-17 08:52:08,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 718 [2024-11-17 08:52:08,719 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 718 [2024-11-17 08:52:08,719 INFO L73 IsDeterministic]: Start isDeterministic. Operand 718 states and 1055 transitions. [2024-11-17 08:52:08,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,720 INFO L218 hiAutomatonCegarLoop]: Abstraction has 718 states and 1055 transitions. [2024-11-17 08:52:08,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states and 1055 transitions. [2024-11-17 08:52:08,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 718. [2024-11-17 08:52:08,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 718 states, 718 states have (on average 1.4693593314763231) internal successors, (1055), 717 states have internal predecessors, (1055), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 1055 transitions. [2024-11-17 08:52:08,730 INFO L240 hiAutomatonCegarLoop]: Abstraction has 718 states and 1055 transitions. [2024-11-17 08:52:08,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,732 INFO L425 stractBuchiCegarLoop]: Abstraction has 718 states and 1055 transitions. [2024-11-17 08:52:08,733 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:52:08,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 718 states and 1055 transitions. [2024-11-17 08:52:08,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,736 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,737 INFO L745 eck$LassoCheckResult]: Stem: 9412#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8775#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8776#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9222#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9223#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 9373#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9411#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8811#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8812#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9038#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9039#L517 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9402#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9353#L696-1 assume !(0 == ~M_E~0); 9354#L701-1 assume !(0 == ~T1_E~0); 9379#L706-1 assume !(0 == ~T2_E~0); 9194#L711-1 assume !(0 == ~T3_E~0); 8970#L716-1 assume !(0 == ~T4_E~0); 8971#L721-1 assume !(0 == ~T5_E~0); 9157#L726-1 assume !(0 == ~T6_E~0); 9158#L731-1 assume !(0 == ~E_M~0); 9124#L736-1 assume !(0 == ~E_1~0); 9125#L741-1 assume !(0 == ~E_2~0); 9201#L746-1 assume !(0 == ~E_3~0); 9025#L751-1 assume !(0 == ~E_4~0); 9026#L756-1 assume !(0 == ~E_5~0); 8961#L761-1 assume !(0 == ~E_6~0); 8962#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9184#L346-9 assume 1 == ~m_pc~0; 8788#L347-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8789#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8855#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8856#L861-9 assume !(0 != activate_threads_~tmp~1#1); 8931#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8932#L365-9 assume 1 == ~t1_pc~0; 9304#L366-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9081#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8717#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8718#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 9285#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9185#L384-9 assume 1 == ~t2_pc~0; 9086#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8862#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9400#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8893#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8894#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8729#L403-9 assume 1 == ~t3_pc~0; 8730#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9232#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9233#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9344#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 9345#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8865#L422-9 assume 1 == ~t4_pc~0; 8866#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8710#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8711#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9069#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 9043#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9044#L441-9 assume 1 == ~t5_pc~0; 9398#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9326#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9327#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9367#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 9368#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8797#L460-9 assume 1 == ~t6_pc~0; 8798#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9082#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8898#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8899#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9405#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9407#L774-1 assume !(1 == ~M_E~0); 9323#L779-1 assume !(1 == ~T1_E~0); 9075#L784-1 assume !(1 == ~T2_E~0); 9076#L789-1 assume !(1 == ~T3_E~0); 8832#L794-1 assume !(1 == ~T4_E~0); 8833#L799-1 assume !(1 == ~T5_E~0); 9395#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9396#L809-1 assume !(1 == ~E_M~0); 9151#L814-1 assume !(1 == ~E_1~0); 8725#L819-1 assume !(1 == ~E_2~0); 8726#L824-1 assume !(1 == ~E_3~0); 9211#L829-1 assume !(1 == ~E_4~0); 9317#L834-1 assume !(1 == ~E_5~0); 8947#L839-1 assume !(1 == ~E_6~0); 8948#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 8737#L1065 [2024-11-17 08:52:08,738 INFO L747 eck$LassoCheckResult]: Loop: 8737#L1065 assume true; 8738#L1065-1 assume !false; 9037#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9129#L577 assume true; 8820#L577-1 assume !false; 8821#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9017#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8728#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8761#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9283#L582 assume !(0 != eval_~tmp~0#1); 9401#L585 assume true; 9152#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9153#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9090#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 9091#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9409#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9085#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8825#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8826#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8888#L726 assume !(0 == ~T6_E~0); 9346#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 9071#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 8988#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 8989#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 8762#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 8763#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 9325#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 9342#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9270#L346-1 assume !(1 == ~m_pc~0); 8773#L356-1 is_master_triggered_~__retres1~0#1 := 0; 8774#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9063#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8744#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8745#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9236#L365-1 assume !(1 == ~t1_pc~0); 9155#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 9156#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9372#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8990#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8991#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8779#L384-1 assume 1 == ~t2_pc~0; 8780#L385-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9207#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9268#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9269#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9289#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9290#L403-1 assume !(1 == ~t3_pc~0); 9058#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 8972#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8973#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9378#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9297#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9298#L422-1 assume 1 == ~t4_pc~0; 9318#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8874#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8887#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9358#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9394#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8993#L441-1 assume 1 == ~t5_pc~0; 8994#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9021#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9022#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8896#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8897#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8938#L460-1 assume 1 == ~t6_pc~0; 9096#L461-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9097#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9224#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9280#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9281#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9165#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 9166#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9202#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9203#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9180#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9181#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9247#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9213#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 9214#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 9334#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 9178#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 9179#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 8963#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 8964#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 9282#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9328#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8830#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9108#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8753#L1084 assume !(0 == start_simulation_~tmp~3#1); 8755#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9107#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8806#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9230#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9027#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9028#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8859#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8860#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 8737#L1065 [2024-11-17 08:52:08,740 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,740 INFO L85 PathProgramCache]: Analyzing trace with hash -956832950, now seen corresponding path program 1 times [2024-11-17 08:52:08,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212112372] [2024-11-17 08:52:08,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,772 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,772 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212112372] [2024-11-17 08:52:08,773 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212112372] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,773 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,773 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:08,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139509657] [2024-11-17 08:52:08,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,774 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,774 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,774 INFO L85 PathProgramCache]: Analyzing trace with hash 1600113137, now seen corresponding path program 1 times [2024-11-17 08:52:08,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371931192] [2024-11-17 08:52:08,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,831 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371931192] [2024-11-17 08:52:08,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1371931192] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,831 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,831 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:08,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858997403] [2024-11-17 08:52:08,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,833 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:08,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:08,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:08,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:08,833 INFO L87 Difference]: Start difference. First operand 718 states and 1055 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:08,846 INFO L93 Difference]: Finished difference Result 718 states and 1054 transitions. [2024-11-17 08:52:08,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 718 states and 1054 transitions. [2024-11-17 08:52:08,850 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 718 states to 718 states and 1054 transitions. [2024-11-17 08:52:08,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 718 [2024-11-17 08:52:08,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 718 [2024-11-17 08:52:08,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 718 states and 1054 transitions. [2024-11-17 08:52:08,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:08,855 INFO L218 hiAutomatonCegarLoop]: Abstraction has 718 states and 1054 transitions. [2024-11-17 08:52:08,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 718 states and 1054 transitions. [2024-11-17 08:52:08,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 718 to 718. [2024-11-17 08:52:08,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 718 states, 718 states have (on average 1.467966573816156) internal successors, (1054), 717 states have internal predecessors, (1054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:08,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 1054 transitions. [2024-11-17 08:52:08,866 INFO L240 hiAutomatonCegarLoop]: Abstraction has 718 states and 1054 transitions. [2024-11-17 08:52:08,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:08,868 INFO L425 stractBuchiCegarLoop]: Abstraction has 718 states and 1054 transitions. [2024-11-17 08:52:08,868 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:52:08,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 718 states and 1054 transitions. [2024-11-17 08:52:08,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 627 [2024-11-17 08:52:08,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:08,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:08,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:08,872 INFO L745 eck$LassoCheckResult]: Stem: 10857#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10218#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10219#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10667#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10668#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 10817#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10856#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10256#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10257#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10483#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10484#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10847#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10798#L696-1 assume !(0 == ~M_E~0); 10799#L701-1 assume !(0 == ~T1_E~0); 10824#L706-1 assume !(0 == ~T2_E~0); 10639#L711-1 assume !(0 == ~T3_E~0); 10410#L716-1 assume !(0 == ~T4_E~0); 10411#L721-1 assume !(0 == ~T5_E~0); 10600#L726-1 assume !(0 == ~T6_E~0); 10601#L731-1 assume !(0 == ~E_M~0); 10567#L736-1 assume !(0 == ~E_1~0); 10568#L741-1 assume !(0 == ~E_2~0); 10646#L746-1 assume !(0 == ~E_3~0); 10466#L751-1 assume !(0 == ~E_4~0); 10467#L756-1 assume !(0 == ~E_5~0); 10404#L761-1 assume !(0 == ~E_6~0); 10405#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10627#L346-9 assume 1 == ~m_pc~0; 10233#L347-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10234#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10298#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10299#L861-9 assume !(0 != activate_threads_~tmp~1#1); 10376#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10377#L365-9 assume 1 == ~t1_pc~0; 10749#L366-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10526#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10162#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10163#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 10730#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10630#L384-9 assume 1 == ~t2_pc~0; 10531#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10307#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10845#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10337#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10338#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10174#L403-9 assume 1 == ~t3_pc~0; 10175#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10677#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10678#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10789#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 10790#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10310#L422-9 assume 1 == ~t4_pc~0; 10311#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10155#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10156#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10514#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 10488#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10489#L441-9 assume 1 == ~t5_pc~0; 10843#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10771#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10772#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10812#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 10813#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10242#L460-9 assume 1 == ~t6_pc~0; 10243#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10527#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10341#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10342#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10850#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10852#L774-1 assume !(1 == ~M_E~0); 10768#L779-1 assume !(1 == ~T1_E~0); 10520#L784-1 assume !(1 == ~T2_E~0); 10521#L789-1 assume !(1 == ~T3_E~0); 10277#L794-1 assume !(1 == ~T4_E~0); 10278#L799-1 assume !(1 == ~T5_E~0); 10839#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10840#L809-1 assume !(1 == ~E_M~0); 10596#L814-1 assume !(1 == ~E_1~0); 10166#L819-1 assume !(1 == ~E_2~0); 10167#L824-1 assume !(1 == ~E_3~0); 10655#L829-1 assume !(1 == ~E_4~0); 10762#L834-1 assume !(1 == ~E_5~0); 10391#L839-1 assume !(1 == ~E_6~0); 10392#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 10182#L1065 [2024-11-17 08:52:08,873 INFO L747 eck$LassoCheckResult]: Loop: 10182#L1065 assume true; 10183#L1065-1 assume !false; 10482#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10574#L577 assume true; 10265#L577-1 assume !false; 10266#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10462#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10173#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10206#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10728#L582 assume !(0 != eval_~tmp~0#1); 10846#L585 assume true; 10597#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10598#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10535#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 10536#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10854#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10529#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10270#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10271#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10333#L726 assume !(0 == ~T6_E~0); 10791#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 10519#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 10433#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 10434#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 10207#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 10208#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 10770#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 10787#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10715#L346-1 assume 1 == ~m_pc~0; 10716#L347-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10223#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10511#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10189#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10190#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10681#L365-1 assume 1 == ~t1_pc~0; 10690#L366-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10603#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10818#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10435#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10436#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10224#L384-1 assume 1 == ~t2_pc~0; 10225#L385-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10652#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10713#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10714#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10734#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10735#L403-1 assume 1 == ~t3_pc~0; 10851#L404-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10417#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10418#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10823#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10742#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10743#L422-1 assume 1 == ~t4_pc~0; 10763#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10319#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10332#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10803#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10841#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10440#L441-1 assume 1 == ~t5_pc~0; 10441#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10468#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10469#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10343#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10344#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10385#L460-1 assume 1 == ~t6_pc~0; 10541#L461-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10542#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10669#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10725#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10726#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10610#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 10611#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10647#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10648#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10625#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10626#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10692#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10658#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 10659#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 10780#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 10623#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 10624#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 10408#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 10409#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 10727#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10773#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10275#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10553#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10200#L1084 assume !(0 == start_simulation_~tmp~3#1); 10202#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10552#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10251#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10675#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10472#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10473#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10304#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10305#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 10182#L1065 [2024-11-17 08:52:08,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1400444373, now seen corresponding path program 1 times [2024-11-17 08:52:08,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [662228387] [2024-11-17 08:52:08,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:08,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:08,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:08,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [662228387] [2024-11-17 08:52:08,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [662228387] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:08,922 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:08,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:08,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664842847] [2024-11-17 08:52:08,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:08,923 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:08,923 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:08,923 INFO L85 PathProgramCache]: Analyzing trace with hash 2074066088, now seen corresponding path program 1 times [2024-11-17 08:52:08,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:08,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085404024] [2024-11-17 08:52:08,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:08,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:08,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,014 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085404024] [2024-11-17 08:52:09,014 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085404024] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,014 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:09,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985377958] [2024-11-17 08:52:09,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,017 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:09,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:09,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:09,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:09,018 INFO L87 Difference]: Start difference. First operand 718 states and 1054 transitions. cyclomatic complexity: 337 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:09,117 INFO L93 Difference]: Finished difference Result 1326 states and 1924 transitions. [2024-11-17 08:52:09,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1326 states and 1924 transitions. [2024-11-17 08:52:09,124 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1234 [2024-11-17 08:52:09,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1326 states to 1326 states and 1924 transitions. [2024-11-17 08:52:09,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1326 [2024-11-17 08:52:09,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1326 [2024-11-17 08:52:09,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1326 states and 1924 transitions. [2024-11-17 08:52:09,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:09,132 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1326 states and 1924 transitions. [2024-11-17 08:52:09,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1326 states and 1924 transitions. [2024-11-17 08:52:09,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1326 to 1278. [2024-11-17 08:52:09,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4530516431924883) internal successors, (1857), 1277 states have internal predecessors, (1857), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1857 transitions. [2024-11-17 08:52:09,155 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1278 states and 1857 transitions. [2024-11-17 08:52:09,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:09,157 INFO L425 stractBuchiCegarLoop]: Abstraction has 1278 states and 1857 transitions. [2024-11-17 08:52:09,157 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:52:09,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1857 transitions. [2024-11-17 08:52:09,163 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1186 [2024-11-17 08:52:09,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:09,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:09,165 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,166 INFO L745 eck$LassoCheckResult]: Stem: 12948#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 12271#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12272#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12728#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12729#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 12897#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12947#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12306#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12307#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12536#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12537#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12930#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12873#L696-1 assume !(0 == ~M_E~0); 12874#L701-1 assume !(0 == ~T1_E~0); 12904#L706-1 assume !(0 == ~T2_E~0); 12700#L711-1 assume !(0 == ~T3_E~0); 12460#L716-1 assume !(0 == ~T4_E~0); 12461#L721-1 assume !(0 == ~T5_E~0); 12658#L726-1 assume !(0 == ~T6_E~0); 12659#L731-1 assume !(0 == ~E_M~0); 12626#L736-1 assume !(0 == ~E_1~0); 12627#L741-1 assume !(0 == ~E_2~0); 12707#L746-1 assume !(0 == ~E_3~0); 12518#L751-1 assume !(0 == ~E_4~0); 12519#L756-1 assume !(0 == ~E_5~0); 12454#L761-1 assume !(0 == ~E_6~0); 12455#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12687#L346-9 assume !(1 == ~m_pc~0); 12688#L356-9 is_master_triggered_~__retres1~0#1 := 0; 12474#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12347#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12348#L861-9 assume !(0 != activate_threads_~tmp~1#1); 12425#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12426#L365-9 assume 1 == ~t1_pc~0; 12819#L366-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12582#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12215#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12216#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 12796#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12691#L384-9 assume 1 == ~t2_pc~0; 12588#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12356#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12928#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12386#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12387#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12227#L403-9 assume 1 == ~t3_pc~0; 12228#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12739#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12740#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12864#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 12865#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12359#L422-9 assume 1 == ~t4_pc~0; 12360#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12208#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12209#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12569#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 12541#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12542#L441-9 assume 1 == ~t5_pc~0; 12926#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12844#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12845#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12892#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 12893#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12292#L460-9 assume 1 == ~t6_pc~0; 12293#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12583#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12390#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12391#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12934#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12936#L774-1 assume !(1 == ~M_E~0); 12841#L779-1 assume !(1 == ~T1_E~0); 12575#L784-1 assume !(1 == ~T2_E~0); 12576#L789-1 assume !(1 == ~T3_E~0); 12326#L794-1 assume !(1 == ~T4_E~0); 12327#L799-1 assume !(1 == ~T5_E~0); 12922#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12923#L809-1 assume !(1 == ~E_M~0); 12654#L814-1 assume !(1 == ~E_1~0); 12219#L819-1 assume !(1 == ~E_2~0); 12220#L824-1 assume !(1 == ~E_3~0); 12716#L829-1 assume !(1 == ~E_4~0); 12834#L834-1 assume !(1 == ~E_5~0); 12440#L839-1 assume !(1 == ~E_6~0); 12441#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 12900#L1065 [2024-11-17 08:52:09,166 INFO L747 eck$LassoCheckResult]: Loop: 12900#L1065 assume true; 13304#L1065-1 assume !false; 13303#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12805#L577 assume true; 13288#L577-1 assume !false; 13013#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12514#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12226#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12259#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12794#L582 assume !(0 != eval_~tmp~0#1); 12950#L585 assume true; 13195#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13193#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13191#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 13189#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13187#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13184#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13182#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13180#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13178#L726 assume !(0 == ~T6_E~0); 13176#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 13174#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 13171#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 13169#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 13012#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 12983#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 12974#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 12940#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12781#L346-1 assume !(1 == ~m_pc~0); 12782#L356-1 is_master_triggered_~__retres1~0#1 := 0; 13159#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13158#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13157#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13156#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13155#L365-1 assume !(1 == ~t1_pc~0); 13152#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 13150#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13148#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13146#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13144#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13142#L384-1 assume !(1 == ~t2_pc~0); 13139#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 13136#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13134#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13132#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13130#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13128#L403-1 assume !(1 == ~t3_pc~0); 13125#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 13124#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13123#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13122#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13121#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13120#L422-1 assume !(1 == ~t4_pc~0); 13116#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 13114#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13112#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13110#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13108#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13106#L441-1 assume !(1 == ~t5_pc~0); 13102#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 12520#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12521#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12392#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12393#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12434#L460-1 assume 1 == ~t6_pc~0; 12598#L461-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12599#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12730#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12791#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12792#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12668#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 12669#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12708#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12709#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12685#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12686#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12755#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12719#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 12720#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 12855#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 12683#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 12684#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 12458#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 12459#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 12793#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12846#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12324#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12610#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 12253#L1084 assume !(0 == start_simulation_~tmp~3#1); 12255#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 13320#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13317#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 13315#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 13313#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13311#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13309#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13307#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 12900#L1065 [2024-11-17 08:52:09,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,167 INFO L85 PathProgramCache]: Analyzing trace with hash -810660498, now seen corresponding path program 1 times [2024-11-17 08:52:09,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838652536] [2024-11-17 08:52:09,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [838652536] [2024-11-17 08:52:09,217 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [838652536] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,217 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,217 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:09,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1123815622] [2024-11-17 08:52:09,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,217 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:09,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,218 INFO L85 PathProgramCache]: Analyzing trace with hash -1649747206, now seen corresponding path program 1 times [2024-11-17 08:52:09,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161178609] [2024-11-17 08:52:09,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,278 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161178609] [2024-11-17 08:52:09,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161178609] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:09,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025219383] [2024-11-17 08:52:09,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,279 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:09,279 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:09,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:09,279 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:09,280 INFO L87 Difference]: Start difference. First operand 1278 states and 1857 transitions. cyclomatic complexity: 581 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:09,356 INFO L93 Difference]: Finished difference Result 2345 states and 3382 transitions. [2024-11-17 08:52:09,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2345 states and 3382 transitions. [2024-11-17 08:52:09,370 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2248 [2024-11-17 08:52:09,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2345 states to 2345 states and 3382 transitions. [2024-11-17 08:52:09,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2345 [2024-11-17 08:52:09,383 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2345 [2024-11-17 08:52:09,383 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2345 states and 3382 transitions. [2024-11-17 08:52:09,386 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:09,386 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2345 states and 3382 transitions. [2024-11-17 08:52:09,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2345 states and 3382 transitions. [2024-11-17 08:52:09,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2345 to 2337. [2024-11-17 08:52:09,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2337 states, 2337 states have (on average 1.4437312794180572) internal successors, (3374), 2336 states have internal predecessors, (3374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2337 states to 2337 states and 3374 transitions. [2024-11-17 08:52:09,422 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2337 states and 3374 transitions. [2024-11-17 08:52:09,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:09,425 INFO L425 stractBuchiCegarLoop]: Abstraction has 2337 states and 3374 transitions. [2024-11-17 08:52:09,425 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:52:09,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2337 states and 3374 transitions. [2024-11-17 08:52:09,436 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2240 [2024-11-17 08:52:09,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:09,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:09,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,439 INFO L745 eck$LassoCheckResult]: Stem: 16604#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 15903#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15904#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16372#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16373#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 16540#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16601#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15938#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15939#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16171#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16172#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16585#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16516#L696-1 assume !(0 == ~M_E~0); 16517#L701-1 assume !(0 == ~T1_E~0); 16548#L706-1 assume !(0 == ~T2_E~0); 16340#L711-1 assume !(0 == ~T3_E~0); 16091#L716-1 assume !(0 == ~T4_E~0); 16092#L721-1 assume !(0 == ~T5_E~0); 16297#L726-1 assume !(0 == ~T6_E~0); 16298#L731-1 assume !(0 == ~E_M~0); 16265#L736-1 assume !(0 == ~E_1~0); 16266#L741-1 assume !(0 == ~E_2~0); 16347#L746-1 assume !(0 == ~E_3~0); 16151#L751-1 assume !(0 == ~E_4~0); 16152#L756-1 assume !(0 == ~E_5~0); 16085#L761-1 assume !(0 == ~E_6~0); 16086#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16326#L346-9 assume !(1 == ~m_pc~0); 16327#L356-9 is_master_triggered_~__retres1~0#1 := 0; 16107#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15980#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15981#L861-9 assume !(0 != activate_threads_~tmp~1#1); 16058#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16059#L365-9 assume !(1 == ~t1_pc~0); 16269#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 16218#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15847#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15848#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 16437#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16330#L384-9 assume 1 == ~t2_pc~0; 16224#L385-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15989#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16583#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16019#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16020#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15859#L403-9 assume 1 == ~t3_pc~0; 15860#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16382#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16383#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16507#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 16508#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15992#L422-9 assume 1 == ~t4_pc~0; 15993#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15840#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15841#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16206#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 16176#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16177#L441-9 assume 1 == ~t5_pc~0; 16576#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16487#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16488#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16534#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 16535#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15924#L460-9 assume 1 == ~t6_pc~0; 15925#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16219#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16023#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16024#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16591#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16593#L774-1 assume !(1 == ~M_E~0); 16482#L779-1 assume !(1 == ~T1_E~0); 16212#L784-1 assume !(1 == ~T2_E~0); 16213#L789-1 assume !(1 == ~T3_E~0); 15959#L794-1 assume !(1 == ~T4_E~0); 15960#L799-1 assume !(1 == ~T5_E~0); 16570#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16571#L809-1 assume !(1 == ~E_M~0); 16293#L814-1 assume !(1 == ~E_1~0); 15851#L819-1 assume !(1 == ~E_2~0); 15852#L824-1 assume !(1 == ~E_3~0); 16360#L829-1 assume !(1 == ~E_4~0); 16474#L834-1 assume !(1 == ~E_5~0); 16073#L839-1 assume !(1 == ~E_6~0); 16074#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 16544#L1065 [2024-11-17 08:52:09,439 INFO L747 eck$LassoCheckResult]: Loop: 16544#L1065 assume true; 16946#L1065-1 assume !false; 16688#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16680#L577 assume true; 16675#L577-1 assume !false; 16673#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 16665#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16663#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 16655#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16653#L582 assume !(0 != eval_~tmp~0#1); 16654#L585 assume true; 17112#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17111#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17110#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 17109#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17108#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17107#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17106#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17105#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17104#L726 assume !(0 == ~T6_E~0); 17103#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 17102#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 17101#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 17100#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 17099#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 17098#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 17097#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 17096#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17095#L346-1 assume !(1 == ~m_pc~0); 17094#L356-1 is_master_triggered_~__retres1~0#1 := 0; 17093#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17092#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17090#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17088#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17086#L365-1 assume !(1 == ~t1_pc~0); 17084#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 17082#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17080#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17078#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17076#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17074#L384-1 assume 1 == ~t2_pc~0; 17072#L385-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17069#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17067#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17065#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17062#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17060#L403-1 assume !(1 == ~t3_pc~0); 17057#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 17055#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17053#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17051#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17048#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17046#L422-1 assume !(1 == ~t4_pc~0); 17043#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 17041#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17039#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17037#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17034#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17032#L441-1 assume !(1 == ~t5_pc~0); 17029#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 17027#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17025#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17023#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17020#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17018#L460-1 assume !(1 == ~t6_pc~0); 17015#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 17013#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17011#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17009#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17006#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17004#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 17002#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17000#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16998#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16996#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16994#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16992#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16990#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 16988#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 16986#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 16984#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 16982#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 16980#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 16978#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 16976#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 16970#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16966#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 16964#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16961#L1084 assume !(0 == start_simulation_~tmp~3#1); 16960#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 16954#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16952#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 16951#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16950#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16949#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16948#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16947#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 16544#L1065 [2024-11-17 08:52:09,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,440 INFO L85 PathProgramCache]: Analyzing trace with hash 803610353, now seen corresponding path program 1 times [2024-11-17 08:52:09,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895679270] [2024-11-17 08:52:09,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895679270] [2024-11-17 08:52:09,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895679270] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:09,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454831562] [2024-11-17 08:52:09,487 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,488 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:09,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,488 INFO L85 PathProgramCache]: Analyzing trace with hash -403000326, now seen corresponding path program 1 times [2024-11-17 08:52:09,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782534675] [2024-11-17 08:52:09,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782534675] [2024-11-17 08:52:09,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782534675] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:09,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612003733] [2024-11-17 08:52:09,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,583 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:09,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:09,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:09,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:09,583 INFO L87 Difference]: Start difference. First operand 2337 states and 3374 transitions. cyclomatic complexity: 1041 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:09,680 INFO L93 Difference]: Finished difference Result 4348 states and 6239 transitions. [2024-11-17 08:52:09,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4348 states and 6239 transitions. [2024-11-17 08:52:09,714 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4236 [2024-11-17 08:52:09,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4348 states to 4348 states and 6239 transitions. [2024-11-17 08:52:09,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4348 [2024-11-17 08:52:09,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4348 [2024-11-17 08:52:09,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4348 states and 6239 transitions. [2024-11-17 08:52:09,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:09,752 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4348 states and 6239 transitions. [2024-11-17 08:52:09,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4348 states and 6239 transitions. [2024-11-17 08:52:09,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4348 to 4332. [2024-11-17 08:52:09,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4332 states, 4332 states have (on average 1.4365189289012004) internal successors, (6223), 4331 states have internal predecessors, (6223), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:09,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4332 states to 4332 states and 6223 transitions. [2024-11-17 08:52:09,836 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4332 states and 6223 transitions. [2024-11-17 08:52:09,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:09,838 INFO L425 stractBuchiCegarLoop]: Abstraction has 4332 states and 6223 transitions. [2024-11-17 08:52:09,838 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:52:09,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4332 states and 6223 transitions. [2024-11-17 08:52:09,855 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4220 [2024-11-17 08:52:09,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:09,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:09,856 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,856 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:09,857 INFO L745 eck$LassoCheckResult]: Stem: 23297#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 22596#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 22597#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23055#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23056#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 23232#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23296#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22631#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22632#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22862#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22863#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23276#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23205#L696-1 assume !(0 == ~M_E~0); 23206#L701-1 assume !(0 == ~T1_E~0); 23242#L706-1 assume !(0 == ~T2_E~0); 23028#L711-1 assume !(0 == ~T3_E~0); 22784#L716-1 assume !(0 == ~T4_E~0); 22785#L721-1 assume !(0 == ~T5_E~0); 22982#L726-1 assume !(0 == ~T6_E~0); 22983#L731-1 assume !(0 == ~E_M~0); 22950#L736-1 assume !(0 == ~E_1~0); 22951#L741-1 assume !(0 == ~E_2~0); 23034#L746-1 assume !(0 == ~E_3~0); 22843#L751-1 assume !(0 == ~E_4~0); 22844#L756-1 assume !(0 == ~E_5~0); 22778#L761-1 assume !(0 == ~E_6~0); 22779#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23014#L346-9 assume !(1 == ~m_pc~0); 23015#L356-9 is_master_triggered_~__retres1~0#1 := 0; 22799#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22672#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22673#L861-9 assume !(0 != activate_threads_~tmp~1#1); 22749#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22750#L365-9 assume !(1 == ~t1_pc~0); 22954#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 22907#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22541#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22542#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 23123#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23018#L384-9 assume !(1 == ~t2_pc~0); 22680#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 22681#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23273#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22710#L877-9 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22711#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22553#L403-9 assume 1 == ~t3_pc~0; 22554#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23065#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23066#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23196#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 23197#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22684#L422-9 assume 1 == ~t4_pc~0; 22685#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22534#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22535#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22895#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 22867#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22868#L441-9 assume 1 == ~t5_pc~0; 23266#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23171#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23172#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23222#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 23223#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22617#L460-9 assume 1 == ~t6_pc~0; 22618#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22908#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22714#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22715#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23281#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23285#L774-1 assume !(1 == ~M_E~0); 23165#L779-1 assume !(1 == ~T1_E~0); 22901#L784-1 assume !(1 == ~T2_E~0); 22902#L789-1 assume !(1 == ~T3_E~0); 22651#L794-1 assume !(1 == ~T4_E~0); 22652#L799-1 assume !(1 == ~T5_E~0); 23262#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23263#L809-1 assume !(1 == ~E_M~0); 22978#L814-1 assume !(1 == ~E_1~0); 22545#L819-1 assume !(1 == ~E_2~0); 22546#L824-1 assume !(1 == ~E_3~0); 23043#L829-1 assume !(1 == ~E_4~0); 23159#L834-1 assume !(1 == ~E_5~0); 22764#L839-1 assume !(1 == ~E_6~0); 22765#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 22560#L1065 [2024-11-17 08:52:09,857 INFO L747 eck$LassoCheckResult]: Loop: 22560#L1065 assume true; 22561#L1065-1 assume !false; 22861#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22957#L577 assume true; 22639#L577-1 assume !false; 22640#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22839#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22552#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22584#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23120#L582 assume !(0 != eval_~tmp~0#1); 23307#L585 assume true; 26661#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26660#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26659#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 26658#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26657#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26656#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26655#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26654#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26653#L726 assume !(0 == ~T6_E~0); 26652#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 26651#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 26650#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 26649#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 26648#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 26647#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 26646#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 26645#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26643#L346-1 assume !(1 == ~m_pc~0); 26641#L356-1 is_master_triggered_~__retres1~0#1 := 0; 26639#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26637#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26635#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26633#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26631#L365-1 assume !(1 == ~t1_pc~0); 26629#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 26627#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26625#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26623#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26621#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26619#L384-1 assume !(1 == ~t2_pc~0); 26618#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 26617#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26615#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26613#L877-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26611#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26609#L403-1 assume !(1 == ~t3_pc~0); 26605#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 26603#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26601#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26599#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26597#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26595#L422-1 assume 1 == ~t4_pc~0; 26592#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26589#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26587#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26585#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26583#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26581#L441-1 assume !(1 == ~t5_pc~0); 26577#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 26575#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26573#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26571#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26569#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26567#L460-1 assume !(1 == ~t6_pc~0); 26563#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 26561#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26560#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26559#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26558#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26557#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 26556#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26555#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26554#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26553#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23215#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23079#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23047#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 23048#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 23183#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 23010#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 23011#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 22782#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 22783#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 23119#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23173#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22649#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22935#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 22578#L1084 assume !(0 == start_simulation_~tmp~3#1); 22580#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22934#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22626#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23063#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 22849#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22850#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22678#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 22679#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 22560#L1065 [2024-11-17 08:52:09,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,858 INFO L85 PathProgramCache]: Analyzing trace with hash 1152257716, now seen corresponding path program 1 times [2024-11-17 08:52:09,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,858 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498055675] [2024-11-17 08:52:09,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498055675] [2024-11-17 08:52:09,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498055675] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:09,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938918514] [2024-11-17 08:52:09,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,926 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:09,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:09,927 INFO L85 PathProgramCache]: Analyzing trace with hash -161863814, now seen corresponding path program 1 times [2024-11-17 08:52:09,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:09,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409556640] [2024-11-17 08:52:09,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:09,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:09,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:09,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:09,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:09,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [409556640] [2024-11-17 08:52:09,979 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [409556640] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:09,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:09,980 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:09,980 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458140693] [2024-11-17 08:52:09,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:09,980 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:09,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:09,983 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:09,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:09,983 INFO L87 Difference]: Start difference. First operand 4332 states and 6223 transitions. cyclomatic complexity: 1899 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:10,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:10,197 INFO L93 Difference]: Finished difference Result 4428 states and 6290 transitions. [2024-11-17 08:52:10,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4428 states and 6290 transitions. [2024-11-17 08:52:10,223 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4316 [2024-11-17 08:52:10,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4428 states to 4428 states and 6290 transitions. [2024-11-17 08:52:10,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4428 [2024-11-17 08:52:10,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4428 [2024-11-17 08:52:10,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4428 states and 6290 transitions. [2024-11-17 08:52:10,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:10,254 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4428 states and 6290 transitions. [2024-11-17 08:52:10,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4428 states and 6290 transitions. [2024-11-17 08:52:10,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4428 to 4428. [2024-11-17 08:52:10,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4428 states, 4428 states have (on average 1.420505871725384) internal successors, (6290), 4427 states have internal predecessors, (6290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:10,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4428 states to 4428 states and 6290 transitions. [2024-11-17 08:52:10,389 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4428 states and 6290 transitions. [2024-11-17 08:52:10,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:10,390 INFO L425 stractBuchiCegarLoop]: Abstraction has 4428 states and 6290 transitions. [2024-11-17 08:52:10,390 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:52:10,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4428 states and 6290 transitions. [2024-11-17 08:52:10,407 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4316 [2024-11-17 08:52:10,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:10,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:10,408 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:10,408 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:10,409 INFO L745 eck$LassoCheckResult]: Stem: 32072#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 31367#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 31368#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31822#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31823#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 31997#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32071#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31402#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31403#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31631#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31632#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32052#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31973#L696-1 assume !(0 == ~M_E~0); 31974#L701-1 assume !(0 == ~T1_E~0); 32009#L706-1 assume !(0 == ~T2_E~0); 31794#L711-1 assume !(0 == ~T3_E~0); 31555#L716-1 assume !(0 == ~T4_E~0); 31556#L721-1 assume !(0 == ~T5_E~0); 31750#L726-1 assume !(0 == ~T6_E~0); 31751#L731-1 assume !(0 == ~E_M~0); 31718#L736-1 assume !(0 == ~E_1~0); 31719#L741-1 assume !(0 == ~E_2~0); 31801#L746-1 assume !(0 == ~E_3~0); 31613#L751-1 assume !(0 == ~E_4~0); 31614#L756-1 assume !(0 == ~E_5~0); 31549#L761-1 assume !(0 == ~E_6~0); 31550#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31779#L346-9 assume !(1 == ~m_pc~0); 31780#L356-9 is_master_triggered_~__retres1~0#1 := 0; 31570#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31442#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31443#L861-9 assume !(0 != activate_threads_~tmp~1#1); 31520#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31521#L365-9 assume !(1 == ~t1_pc~0); 31722#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 31676#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31312#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31313#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 31890#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31783#L384-9 assume !(1 == ~t2_pc~0); 31450#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 31451#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32049#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31481#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 31482#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31324#L403-9 assume 1 == ~t3_pc~0; 31325#L404-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31832#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31833#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31964#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 31965#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31454#L422-9 assume 1 == ~t4_pc~0; 31455#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31305#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31306#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31664#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 31636#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31637#L441-9 assume 1 == ~t5_pc~0; 32045#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31941#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31942#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31990#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 31991#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31388#L460-9 assume 1 == ~t6_pc~0; 31389#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31677#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31485#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31486#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32057#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32060#L774-1 assume !(1 == ~M_E~0); 31933#L779-1 assume !(1 == ~T1_E~0); 31670#L784-1 assume !(1 == ~T2_E~0); 31671#L789-1 assume !(1 == ~T3_E~0); 31422#L794-1 assume !(1 == ~T4_E~0); 31423#L799-1 assume !(1 == ~T5_E~0); 32040#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32041#L809-1 assume !(1 == ~E_M~0); 31746#L814-1 assume !(1 == ~E_1~0); 31316#L819-1 assume !(1 == ~E_2~0); 31317#L824-1 assume !(1 == ~E_3~0); 31810#L829-1 assume !(1 == ~E_4~0); 31927#L834-1 assume !(1 == ~E_5~0); 31535#L839-1 assume !(1 == ~E_6~0); 31536#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 32005#L1065 [2024-11-17 08:52:10,409 INFO L747 eck$LassoCheckResult]: Loop: 32005#L1065 assume true; 33152#L1065-1 assume !false; 32959#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32957#L577 assume true; 32956#L577-1 assume !false; 32955#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 32948#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 32947#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32946#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32945#L582 assume !(0 != eval_~tmp~0#1); 32050#L585 assume true; 31747#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31748#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35641#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 35638#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35636#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35634#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35631#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35629#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35627#L726 assume !(0 == ~T6_E~0); 35625#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 35623#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 35621#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 35620#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 35617#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 35616#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 35615#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 35614#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35613#L346-1 assume !(1 == ~m_pc~0); 35612#L356-1 is_master_triggered_~__retres1~0#1 := 0; 35611#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35609#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31338#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31339#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31847#L365-1 assume !(1 == ~t1_pc~0); 31752#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 31753#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32063#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 35580#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35579#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35578#L384-1 assume !(1 == ~t2_pc~0); 35577#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 35340#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35339#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35338#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 35337#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35336#L403-1 assume !(1 == ~t3_pc~0); 35334#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 35333#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35332#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35331#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35330#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35329#L422-1 assume 1 == ~t4_pc~0; 35328#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35326#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35324#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35322#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35320#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35318#L441-1 assume !(1 == ~t5_pc~0); 35315#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 35313#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35311#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35310#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35309#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35308#L460-1 assume !(1 == ~t6_pc~0); 35306#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 35303#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35302#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35301#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35300#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35299#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 35298#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35296#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35294#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35292#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35290#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35288#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35286#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 35284#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 35282#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 35280#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 35278#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 35276#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 35274#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 35272#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 35262#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 35258#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 35255#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 35184#L1084 assume !(0 == start_simulation_~tmp~3#1); 35182#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 33170#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 33166#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 33164#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 33162#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33160#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33158#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 33155#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 32005#L1065 [2024-11-17 08:52:10,409 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:10,409 INFO L85 PathProgramCache]: Analyzing trace with hash -783402571, now seen corresponding path program 1 times [2024-11-17 08:52:10,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:10,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [94222625] [2024-11-17 08:52:10,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:10,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:10,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:10,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:10,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:10,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [94222625] [2024-11-17 08:52:10,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [94222625] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:10,446 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:10,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:10,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958170486] [2024-11-17 08:52:10,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:10,446 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:10,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:10,447 INFO L85 PathProgramCache]: Analyzing trace with hash -2087397125, now seen corresponding path program 1 times [2024-11-17 08:52:10,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:10,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622592701] [2024-11-17 08:52:10,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:10,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:10,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:10,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:10,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:10,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622592701] [2024-11-17 08:52:10,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622592701] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:10,498 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:10,498 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:10,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1333624573] [2024-11-17 08:52:10,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:10,498 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:10,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:10,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:10,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:10,499 INFO L87 Difference]: Start difference. First operand 4428 states and 6290 transitions. cyclomatic complexity: 1870 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:10,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:10,599 INFO L93 Difference]: Finished difference Result 8291 states and 11719 transitions. [2024-11-17 08:52:10,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8291 states and 11719 transitions. [2024-11-17 08:52:10,644 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8140 [2024-11-17 08:52:10,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8291 states to 8291 states and 11719 transitions. [2024-11-17 08:52:10,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8291 [2024-11-17 08:52:10,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8291 [2024-11-17 08:52:10,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8291 states and 11719 transitions. [2024-11-17 08:52:10,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:10,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8291 states and 11719 transitions. [2024-11-17 08:52:10,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8291 states and 11719 transitions. [2024-11-17 08:52:10,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8291 to 8259. [2024-11-17 08:52:10,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8259 states, 8259 states have (on average 1.4150623562174598) internal successors, (11687), 8258 states have internal predecessors, (11687), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:10,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8259 states to 8259 states and 11687 transitions. [2024-11-17 08:52:10,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8259 states and 11687 transitions. [2024-11-17 08:52:10,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:10,950 INFO L425 stractBuchiCegarLoop]: Abstraction has 8259 states and 11687 transitions. [2024-11-17 08:52:10,950 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:52:10,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8259 states and 11687 transitions. [2024-11-17 08:52:10,983 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8108 [2024-11-17 08:52:10,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:10,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:10,984 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:10,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:10,985 INFO L745 eck$LassoCheckResult]: Stem: 44805#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 44094#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 44095#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44557#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44558#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 44737#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44804#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44128#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44129#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44358#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44359#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44784#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44710#L696-1 assume !(0 == ~M_E~0); 44711#L701-1 assume !(0 == ~T1_E~0); 44744#L706-1 assume !(0 == ~T2_E~0); 44524#L711-1 assume !(0 == ~T3_E~0); 44279#L716-1 assume !(0 == ~T4_E~0); 44280#L721-1 assume !(0 == ~T5_E~0); 44480#L726-1 assume !(0 == ~T6_E~0); 44481#L731-1 assume !(0 == ~E_M~0); 44446#L736-1 assume !(0 == ~E_1~0); 44447#L741-1 assume !(0 == ~E_2~0); 44530#L746-1 assume !(0 == ~E_3~0); 44340#L751-1 assume !(0 == ~E_4~0); 44341#L756-1 assume !(0 == ~E_5~0); 44273#L761-1 assume !(0 == ~E_6~0); 44274#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44510#L346-9 assume !(1 == ~m_pc~0); 44511#L356-9 is_master_triggered_~__retres1~0#1 := 0; 44294#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44170#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44171#L861-9 assume !(0 != activate_threads_~tmp~1#1); 44247#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44248#L365-9 assume !(1 == ~t1_pc~0); 44450#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 44405#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44040#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44041#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 44624#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44514#L384-9 assume !(1 == ~t2_pc~0); 44178#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 44179#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44782#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44208#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 44209#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44052#L403-9 assume !(1 == ~t3_pc~0); 44053#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 44568#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44569#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44700#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 44701#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44182#L422-9 assume 1 == ~t4_pc~0; 44183#L423-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44033#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44034#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44393#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 44363#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44364#L441-9 assume 1 == ~t5_pc~0; 44776#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44676#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44677#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44726#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 44727#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44114#L460-9 assume 1 == ~t6_pc~0; 44115#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44406#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44212#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44213#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44792#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44793#L774-1 assume !(1 == ~M_E~0); 44669#L779-1 assume !(1 == ~T1_E~0); 44399#L784-1 assume !(1 == ~T2_E~0); 44400#L789-1 assume !(1 == ~T3_E~0); 44148#L794-1 assume !(1 == ~T4_E~0); 44149#L799-1 assume !(1 == ~T5_E~0); 44772#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44773#L809-1 assume !(1 == ~E_M~0); 44476#L814-1 assume !(1 == ~E_1~0); 44044#L819-1 assume !(1 == ~E_2~0); 44045#L824-1 assume !(1 == ~E_3~0); 44543#L829-1 assume !(1 == ~E_4~0); 44662#L834-1 assume !(1 == ~E_5~0); 44261#L839-1 assume !(1 == ~E_6~0); 44262#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 44058#L1065 [2024-11-17 08:52:10,985 INFO L747 eck$LassoCheckResult]: Loop: 44058#L1065 assume true; 44059#L1065-1 assume !false; 44357#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44453#L577 assume true; 44136#L577-1 assume !false; 44137#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 44336#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 44051#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 44082#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 44622#L582 assume !(0 != eval_~tmp~0#1); 44783#L585 assume true; 44477#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44478#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44413#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 44414#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44795#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44408#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44141#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44142#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44204#L726 assume !(0 == ~T6_E~0); 44702#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 44395#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 44304#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 44305#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 44083#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 44084#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 51897#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 51896#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51895#L346-1 assume !(1 == ~m_pc~0); 51891#L356-1 is_master_triggered_~__retres1~0#1 := 0; 51890#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51889#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51888#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51887#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51886#L365-1 assume !(1 == ~t1_pc~0); 51885#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 51884#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51883#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 51882#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51881#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51880#L384-1 assume !(1 == ~t2_pc~0); 51879#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 44684#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44604#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44605#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 44631#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44632#L403-1 assume !(1 == ~t3_pc~0); 44380#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 44286#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44287#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44743#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44639#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44640#L422-1 assume 1 == ~t4_pc~0; 44663#L423-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44192#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44203#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44714#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44774#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44314#L441-1 assume 1 == ~t5_pc~0; 44315#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44342#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44343#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44214#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44215#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44255#L460-1 assume 1 == ~t6_pc~0; 44419#L461-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44420#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44559#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44619#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44620#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44490#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 44491#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44531#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44532#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44508#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44509#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44582#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44546#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 44547#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 44688#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 44506#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 44507#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 44277#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 44278#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 44621#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 44678#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 44146#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 44431#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 44076#L1084 assume !(0 == start_simulation_~tmp~3#1); 44078#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 44430#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 44123#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 44566#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 44346#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44347#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44176#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 44177#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 44058#L1065 [2024-11-17 08:52:10,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:10,986 INFO L85 PathProgramCache]: Analyzing trace with hash -676726856, now seen corresponding path program 1 times [2024-11-17 08:52:10,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:10,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523193946] [2024-11-17 08:52:10,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:10,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:10,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:11,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:11,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:11,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523193946] [2024-11-17 08:52:11,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1523193946] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:11,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:11,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:11,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393797390] [2024-11-17 08:52:11,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:11,108 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:11,108 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:11,109 INFO L85 PathProgramCache]: Analyzing trace with hash 264363701, now seen corresponding path program 1 times [2024-11-17 08:52:11,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:11,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264921602] [2024-11-17 08:52:11,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:11,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:11,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:11,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:11,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:11,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264921602] [2024-11-17 08:52:11,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264921602] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:11,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:11,165 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:11,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695871188] [2024-11-17 08:52:11,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:11,166 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:11,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:11,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:11,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:11,167 INFO L87 Difference]: Start difference. First operand 8259 states and 11687 transitions. cyclomatic complexity: 3444 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:11,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:11,273 INFO L93 Difference]: Finished difference Result 15478 states and 21804 transitions. [2024-11-17 08:52:11,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15478 states and 21804 transitions. [2024-11-17 08:52:11,425 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 15248 [2024-11-17 08:52:11,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15478 states to 15478 states and 21804 transitions. [2024-11-17 08:52:11,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15478 [2024-11-17 08:52:11,515 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15478 [2024-11-17 08:52:11,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15478 states and 21804 transitions. [2024-11-17 08:52:11,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:11,537 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15478 states and 21804 transitions. [2024-11-17 08:52:11,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15478 states and 21804 transitions. [2024-11-17 08:52:11,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15478 to 15414. [2024-11-17 08:52:11,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15414 states, 15414 states have (on average 1.410406124302582) internal successors, (21740), 15413 states have internal predecessors, (21740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:11,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15414 states to 15414 states and 21740 transitions. [2024-11-17 08:52:11,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15414 states and 21740 transitions. [2024-11-17 08:52:11,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:11,961 INFO L425 stractBuchiCegarLoop]: Abstraction has 15414 states and 21740 transitions. [2024-11-17 08:52:11,961 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:52:11,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15414 states and 21740 transitions. [2024-11-17 08:52:12,011 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 15184 [2024-11-17 08:52:12,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:12,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:12,012 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:12,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:12,013 INFO L745 eck$LassoCheckResult]: Stem: 68596#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 67839#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 67840#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68318#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68319#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 68508#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68595#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67873#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67874#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68109#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68110#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68564#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68481#L696-1 assume !(0 == ~M_E~0); 68482#L701-1 assume !(0 == ~T1_E~0); 68521#L706-1 assume !(0 == ~T2_E~0); 68288#L711-1 assume !(0 == ~T3_E~0); 68030#L716-1 assume !(0 == ~T4_E~0); 68031#L721-1 assume !(0 == ~T5_E~0); 68239#L726-1 assume !(0 == ~T6_E~0); 68240#L731-1 assume !(0 == ~E_M~0); 68203#L736-1 assume !(0 == ~E_1~0); 68204#L741-1 assume !(0 == ~E_2~0); 68295#L746-1 assume !(0 == ~E_3~0); 68095#L751-1 assume !(0 == ~E_4~0); 68096#L756-1 assume !(0 == ~E_5~0); 68021#L761-1 assume !(0 == ~E_6~0); 68022#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68273#L346-9 assume !(1 == ~m_pc~0); 68274#L356-9 is_master_triggered_~__retres1~0#1 := 0; 68042#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67914#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67915#L861-9 assume !(0 != activate_threads_~tmp~1#1); 67993#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67994#L365-9 assume !(1 == ~t1_pc~0); 68207#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 68155#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67785#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67786#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 68392#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68277#L384-9 assume !(1 == ~t2_pc~0); 67922#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 67923#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68562#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67953#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 67954#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67797#L403-9 assume !(1 == ~t3_pc~0); 67798#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 68329#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68330#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68469#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 68470#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67926#L422-9 assume !(1 == ~t4_pc~0); 67927#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 67778#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67779#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68143#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 68114#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68115#L441-9 assume 1 == ~t5_pc~0; 68558#L442-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 68444#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68445#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 68500#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 68501#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67859#L460-9 assume 1 == ~t6_pc~0; 67860#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68156#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67958#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67959#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 68576#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68582#L774-1 assume !(1 == ~M_E~0); 68438#L779-1 assume !(1 == ~T1_E~0); 68149#L784-1 assume !(1 == ~T2_E~0); 68150#L789-1 assume !(1 == ~T3_E~0); 67893#L794-1 assume !(1 == ~T4_E~0); 67894#L799-1 assume !(1 == ~T5_E~0); 68555#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68556#L809-1 assume !(1 == ~E_M~0); 68234#L814-1 assume !(1 == ~E_1~0); 67793#L819-1 assume !(1 == ~E_2~0); 67794#L824-1 assume !(1 == ~E_3~0); 68308#L829-1 assume !(1 == ~E_4~0); 68431#L834-1 assume !(1 == ~E_5~0); 68009#L839-1 assume !(1 == ~E_6~0); 68010#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 68516#L1065 [2024-11-17 08:52:12,013 INFO L747 eck$LassoCheckResult]: Loop: 68516#L1065 assume true; 76899#L1065-1 assume !false; 76838#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76835#L577 assume true; 76833#L577-1 assume !false; 76831#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 76813#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 76811#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 76809#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 76806#L582 assume !(0 != eval_~tmp~0#1); 76807#L585 assume true; 77124#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77122#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77120#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 77118#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77116#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77114#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77112#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77110#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77108#L726 assume !(0 == ~T6_E~0); 77106#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 77104#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 77102#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 77100#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 77098#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 77096#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 77094#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 77091#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77089#L346-1 assume !(1 == ~m_pc~0); 77087#L356-1 is_master_triggered_~__retres1~0#1 := 0; 77085#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77083#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77081#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77078#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77076#L365-1 assume !(1 == ~t1_pc~0); 77074#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 77072#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77070#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77067#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77065#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77063#L384-1 assume !(1 == ~t2_pc~0); 77061#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 77059#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77058#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77055#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 77054#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77053#L403-1 assume !(1 == ~t3_pc~0); 77052#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 77051#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77050#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 77049#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77048#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77047#L422-1 assume !(1 == ~t4_pc~0); 77045#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 77043#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77041#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77039#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77037#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77035#L441-1 assume 1 == ~t5_pc~0; 77033#L442-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77030#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77028#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 77026#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77024#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77022#L460-1 assume !(1 == ~t6_pc~0); 77019#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 77017#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77015#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77013#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77011#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77009#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 77007#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77005#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77003#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77001#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76999#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76997#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76995#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 76993#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 76991#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 76989#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 76987#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 76985#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 76983#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 76980#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 76968#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 76964#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 76962#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 76929#L1084 assume !(0 == start_simulation_~tmp~3#1); 76927#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 76915#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 76912#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 76910#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 76908#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76906#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76904#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 76902#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 68516#L1065 [2024-11-17 08:52:12,014 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,014 INFO L85 PathProgramCache]: Analyzing trace with hash 1159803899, now seen corresponding path program 1 times [2024-11-17 08:52:12,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1224057734] [2024-11-17 08:52:12,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:12,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:12,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:12,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1224057734] [2024-11-17 08:52:12,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1224057734] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:12,049 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:12,049 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:12,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885554055] [2024-11-17 08:52:12,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:12,050 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:12,050 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:12,050 INFO L85 PathProgramCache]: Analyzing trace with hash -1845425477, now seen corresponding path program 1 times [2024-11-17 08:52:12,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:12,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118636649] [2024-11-17 08:52:12,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:12,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:12,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:12,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:12,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:12,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118636649] [2024-11-17 08:52:12,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1118636649] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:12,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:12,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:12,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270408082] [2024-11-17 08:52:12,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:12,105 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:12,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:12,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:12,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:12,106 INFO L87 Difference]: Start difference. First operand 15414 states and 21740 transitions. cyclomatic complexity: 6358 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:12,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:12,366 INFO L93 Difference]: Finished difference Result 28901 states and 40633 transitions. [2024-11-17 08:52:12,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28901 states and 40633 transitions. [2024-11-17 08:52:12,500 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 28464 [2024-11-17 08:52:12,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28901 states to 28901 states and 40633 transitions. [2024-11-17 08:52:12,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28901 [2024-11-17 08:52:12,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28901 [2024-11-17 08:52:12,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28901 states and 40633 transitions. [2024-11-17 08:52:12,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:12,669 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28901 states and 40633 transitions. [2024-11-17 08:52:12,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28901 states and 40633 transitions. [2024-11-17 08:52:13,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28901 to 28773. [2024-11-17 08:52:13,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28773 states, 28773 states have (on average 1.4077433705209745) internal successors, (40505), 28772 states have internal predecessors, (40505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:13,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28773 states to 28773 states and 40505 transitions. [2024-11-17 08:52:13,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28773 states and 40505 transitions. [2024-11-17 08:52:13,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:13,319 INFO L425 stractBuchiCegarLoop]: Abstraction has 28773 states and 40505 transitions. [2024-11-17 08:52:13,319 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:52:13,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28773 states and 40505 transitions. [2024-11-17 08:52:13,422 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 28336 [2024-11-17 08:52:13,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:13,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:13,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:13,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:13,425 INFO L745 eck$LassoCheckResult]: Stem: 112909#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 112161#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 112162#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112632#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112633#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 112826#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112908#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112195#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112196#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112425#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112426#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 112884#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112800#L696-1 assume !(0 == ~M_E~0); 112801#L701-1 assume !(0 == ~T1_E~0); 112843#L706-1 assume !(0 == ~T2_E~0); 112598#L711-1 assume !(0 == ~T3_E~0); 112348#L716-1 assume !(0 == ~T4_E~0); 112349#L721-1 assume !(0 == ~T5_E~0); 112551#L726-1 assume !(0 == ~T6_E~0); 112552#L731-1 assume !(0 == ~E_M~0); 112517#L736-1 assume !(0 == ~E_1~0); 112518#L741-1 assume !(0 == ~E_2~0); 112605#L746-1 assume !(0 == ~E_3~0); 112407#L751-1 assume !(0 == ~E_4~0); 112408#L756-1 assume !(0 == ~E_5~0); 112342#L761-1 assume !(0 == ~E_6~0); 112343#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112583#L346-9 assume !(1 == ~m_pc~0); 112584#L356-9 is_master_triggered_~__retres1~0#1 := 0; 112362#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112236#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112237#L861-9 assume !(0 != activate_threads_~tmp~1#1); 112314#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112315#L365-9 assume !(1 == ~t1_pc~0); 112521#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 112474#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112108#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112109#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 112708#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112587#L384-9 assume !(1 == ~t2_pc~0); 112244#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 112245#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112882#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 112274#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 112275#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112120#L403-9 assume !(1 == ~t3_pc~0); 112121#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 112642#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112643#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 112790#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 112791#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112248#L422-9 assume !(1 == ~t4_pc~0); 112249#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 112102#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112103#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112458#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 112430#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112431#L441-9 assume !(1 == ~t5_pc~0); 112878#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 112768#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112769#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112816#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 112817#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112181#L460-9 assume 1 == ~t6_pc~0; 112182#L461-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 112475#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112280#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112281#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 112893#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112897#L774-1 assume !(1 == ~M_E~0); 112762#L779-1 assume !(1 == ~T1_E~0); 112465#L784-1 assume !(1 == ~T2_E~0); 112466#L789-1 assume !(1 == ~T3_E~0); 112216#L794-1 assume !(1 == ~T4_E~0); 112217#L799-1 assume !(1 == ~T5_E~0); 112874#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 112875#L809-1 assume !(1 == ~E_M~0); 112547#L814-1 assume !(1 == ~E_1~0); 112112#L819-1 assume !(1 == ~E_2~0); 112113#L824-1 assume !(1 == ~E_3~0); 112617#L829-1 assume !(1 == ~E_4~0); 112753#L834-1 assume !(1 == ~E_5~0); 112328#L839-1 assume !(1 == ~E_6~0); 112329#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 112837#L1065 [2024-11-17 08:52:13,425 INFO L747 eck$LassoCheckResult]: Loop: 112837#L1065 assume true; 126787#L1065-1 assume !false; 126768#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 126765#L577 assume true; 126763#L577-1 assume !false; 126761#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 126746#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 126744#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 126742#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 126739#L582 assume !(0 != eval_~tmp~0#1); 126740#L585 assume true; 127001#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 126999#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 126997#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 126995#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 126993#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 126991#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 126989#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 126987#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 126985#L726 assume !(0 == ~T6_E~0); 126983#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 126981#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 126979#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 126977#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 126975#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 126973#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 126971#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 126969#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126966#L346-1 assume !(1 == ~m_pc~0); 126964#L356-1 is_master_triggered_~__retres1~0#1 := 0; 126962#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126960#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126958#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 126955#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126953#L365-1 assume !(1 == ~t1_pc~0); 126951#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 126949#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126947#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 126946#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 126943#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126942#L384-1 assume !(1 == ~t2_pc~0); 126941#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 126940#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126939#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 126938#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 126937#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126936#L403-1 assume !(1 == ~t3_pc~0); 126935#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 126933#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126931#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 126929#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 126927#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126925#L422-1 assume !(1 == ~t4_pc~0); 126923#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 126921#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126919#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 126917#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126915#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126913#L441-1 assume !(1 == ~t5_pc~0); 126911#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 126909#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126907#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126905#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 126903#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 126901#L460-1 assume 1 == ~t6_pc~0; 126899#L461-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 126896#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 126894#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126892#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 126890#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126888#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 126886#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 126884#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 126882#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 126880#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126878#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 126876#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 126874#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 126872#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 126870#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 126868#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 126866#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 126864#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 126862#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 126860#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 126849#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 126845#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 126843#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 126818#L1084 assume !(0 == start_simulation_~tmp~3#1); 126816#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 126804#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 126801#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 126799#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 126796#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 126794#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 126792#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 126790#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 112837#L1065 [2024-11-17 08:52:13,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:13,426 INFO L85 PathProgramCache]: Analyzing trace with hash 2059378302, now seen corresponding path program 1 times [2024-11-17 08:52:13,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:13,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193567014] [2024-11-17 08:52:13,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:13,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:13,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:13,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:13,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:13,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193567014] [2024-11-17 08:52:13,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [193567014] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:13,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:13,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:13,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188763787] [2024-11-17 08:52:13,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:13,489 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:13,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:13,490 INFO L85 PathProgramCache]: Analyzing trace with hash 719686779, now seen corresponding path program 1 times [2024-11-17 08:52:13,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:13,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251622549] [2024-11-17 08:52:13,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:13,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:13,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:13,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:13,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:13,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251622549] [2024-11-17 08:52:13,666 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251622549] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:13,666 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:13,666 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:13,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913123144] [2024-11-17 08:52:13,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:13,666 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:13,666 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:13,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:13,667 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:13,667 INFO L87 Difference]: Start difference. First operand 28773 states and 40505 transitions. cyclomatic complexity: 11796 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:14,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:14,083 INFO L93 Difference]: Finished difference Result 65860 states and 92358 transitions. [2024-11-17 08:52:14,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65860 states and 92358 transitions. [2024-11-17 08:52:14,660 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 64560 [2024-11-17 08:52:15,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65860 states to 65860 states and 92358 transitions. [2024-11-17 08:52:15,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65860 [2024-11-17 08:52:15,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65860 [2024-11-17 08:52:15,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65860 states and 92358 transitions. [2024-11-17 08:52:15,173 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:15,173 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65860 states and 92358 transitions. [2024-11-17 08:52:15,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65860 states and 92358 transitions. [2024-11-17 08:52:15,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65860 to 53588. [2024-11-17 08:52:16,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53588 states, 53588 states have (on average 1.4066955288497425) internal successors, (75382), 53587 states have internal predecessors, (75382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:16,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53588 states to 53588 states and 75382 transitions. [2024-11-17 08:52:16,312 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53588 states and 75382 transitions. [2024-11-17 08:52:16,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:16,313 INFO L425 stractBuchiCegarLoop]: Abstraction has 53588 states and 75382 transitions. [2024-11-17 08:52:16,313 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:52:16,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53588 states and 75382 transitions. [2024-11-17 08:52:16,476 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 52800 [2024-11-17 08:52:16,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:16,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:16,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:16,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:16,479 INFO L745 eck$LassoCheckResult]: Stem: 207595#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 206806#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 206807#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 207287#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 207288#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 207484#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 207594#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 206839#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 206840#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 207074#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 207075#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 207553#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 207457#L696-1 assume !(0 == ~M_E~0); 207458#L701-1 assume !(0 == ~T1_E~0); 207501#L706-1 assume !(0 == ~T2_E~0); 207252#L711-1 assume !(0 == ~T3_E~0); 206990#L716-1 assume !(0 == ~T4_E~0); 206991#L721-1 assume !(0 == ~T5_E~0); 207203#L726-1 assume !(0 == ~T6_E~0); 207204#L731-1 assume !(0 == ~E_M~0); 207165#L736-1 assume !(0 == ~E_1~0); 207166#L741-1 assume !(0 == ~E_2~0); 207258#L746-1 assume !(0 == ~E_3~0); 207053#L751-1 assume !(0 == ~E_4~0); 207054#L756-1 assume !(0 == ~E_5~0); 206984#L761-1 assume !(0 == ~E_6~0); 206985#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 207236#L346-9 assume !(1 == ~m_pc~0); 207237#L356-9 is_master_triggered_~__retres1~0#1 := 0; 207006#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206879#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 206880#L861-9 assume !(0 != activate_threads_~tmp~1#1); 206956#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 206957#L365-9 assume !(1 == ~t1_pc~0); 207169#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 207122#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206753#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 206754#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 207367#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 207240#L384-9 assume !(1 == ~t2_pc~0); 206887#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 206888#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207550#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 206917#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 206918#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206765#L403-9 assume !(1 == ~t3_pc~0); 206766#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 207300#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 207301#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 207444#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 207445#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206891#L422-9 assume !(1 == ~t4_pc~0); 206892#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 206747#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206748#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 207110#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 207079#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 207080#L441-9 assume !(1 == ~t5_pc~0); 207545#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 207422#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 207423#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 207473#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 207474#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 206826#L460-9 assume !(1 == ~t6_pc~0); 206827#L470-9 is_transmit6_triggered_~__retres1~6#1 := 0; 207123#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 206922#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 206923#L909-9 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 207569#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 207572#L774-1 assume !(1 == ~M_E~0); 207418#L779-1 assume !(1 == ~T1_E~0); 207116#L784-1 assume !(1 == ~T2_E~0); 207117#L789-1 assume !(1 == ~T3_E~0); 206859#L794-1 assume !(1 == ~T4_E~0); 206860#L799-1 assume !(1 == ~T5_E~0); 207541#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 207542#L809-1 assume !(1 == ~E_M~0); 207198#L814-1 assume !(1 == ~E_1~0); 206757#L819-1 assume !(1 == ~E_2~0); 206758#L824-1 assume !(1 == ~E_3~0); 207272#L829-1 assume !(1 == ~E_4~0); 207411#L834-1 assume !(1 == ~E_5~0); 206970#L839-1 assume !(1 == ~E_6~0); 206971#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 207494#L1065 [2024-11-17 08:52:16,479 INFO L747 eck$LassoCheckResult]: Loop: 207494#L1065 assume true; 240570#L1065-1 assume !false; 240543#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 240540#L577 assume true; 240538#L577-1 assume !false; 240536#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 240519#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 240517#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 240515#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 240512#L582 assume !(0 != eval_~tmp~0#1); 240513#L585 assume true; 240754#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 240753#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 240752#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 240749#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 240744#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 240742#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 240740#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 240738#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 240737#L726 assume !(0 == ~T6_E~0); 240736#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 240735#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 240734#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 240733#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 240732#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 240724#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 240722#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 240720#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 240717#L346-1 assume !(1 == ~m_pc~0); 240713#L356-1 is_master_triggered_~__retres1~0#1 := 0; 240712#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 240710#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 240706#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 240705#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 240704#L365-1 assume !(1 == ~t1_pc~0); 240703#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 240702#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 240700#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 240698#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 240696#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 240694#L384-1 assume !(1 == ~t2_pc~0); 240692#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 240690#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 240688#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 240686#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 240684#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 240682#L403-1 assume !(1 == ~t3_pc~0); 240680#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 240678#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 240676#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 240674#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 240672#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 240670#L422-1 assume !(1 == ~t4_pc~0); 240668#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 240666#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 240664#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 240662#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 240660#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 240658#L441-1 assume !(1 == ~t5_pc~0); 240656#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 240654#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 240652#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 240650#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 240648#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 240646#L460-1 assume !(1 == ~t6_pc~0); 212048#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 240643#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 240641#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 240639#L909-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 240637#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 240635#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 240633#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 240631#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 240629#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 240628#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 240626#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 240624#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 240622#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 240620#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 240618#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 240616#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 240614#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 240612#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 240610#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 240608#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 240598#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 240594#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 240592#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 240588#L1084 assume !(0 == start_simulation_~tmp~3#1); 240587#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 240581#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 240579#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 240577#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 240576#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 240575#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 240574#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 240572#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 207494#L1065 [2024-11-17 08:52:16,479 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:16,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1206589631, now seen corresponding path program 1 times [2024-11-17 08:52:16,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:16,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152502156] [2024-11-17 08:52:16,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:16,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:16,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:16,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:16,714 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:16,714 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1152502156] [2024-11-17 08:52:16,714 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1152502156] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:16,715 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:16,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:16,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343352015] [2024-11-17 08:52:16,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:16,715 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:16,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:16,716 INFO L85 PathProgramCache]: Analyzing trace with hash -1738749762, now seen corresponding path program 1 times [2024-11-17 08:52:16,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:16,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916688843] [2024-11-17 08:52:16,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:16,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:16,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:16,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:16,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:16,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916688843] [2024-11-17 08:52:16,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916688843] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:16,771 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:16,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:16,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896591269] [2024-11-17 08:52:16,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:16,771 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:16,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:16,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:16,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:16,772 INFO L87 Difference]: Start difference. First operand 53588 states and 75382 transitions. cyclomatic complexity: 21858 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:17,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:17,122 INFO L93 Difference]: Finished difference Result 54740 states and 76213 transitions. [2024-11-17 08:52:17,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54740 states and 76213 transitions. [2024-11-17 08:52:17,596 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 53952 [2024-11-17 08:52:17,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54740 states to 54740 states and 76213 transitions. [2024-11-17 08:52:17,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54740 [2024-11-17 08:52:17,850 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54740 [2024-11-17 08:52:17,850 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54740 states and 76213 transitions. [2024-11-17 08:52:17,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:17,932 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54740 states and 76213 transitions. [2024-11-17 08:52:17,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54740 states and 76213 transitions. [2024-11-17 08:52:18,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54740 to 54740. [2024-11-17 08:52:18,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54740 states, 54740 states have (on average 1.3922725611983924) internal successors, (76213), 54739 states have internal predecessors, (76213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:19,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54740 states to 54740 states and 76213 transitions. [2024-11-17 08:52:19,154 INFO L240 hiAutomatonCegarLoop]: Abstraction has 54740 states and 76213 transitions. [2024-11-17 08:52:19,155 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:19,156 INFO L425 stractBuchiCegarLoop]: Abstraction has 54740 states and 76213 transitions. [2024-11-17 08:52:19,156 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:52:19,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54740 states and 76213 transitions. [2024-11-17 08:52:19,298 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 53952 [2024-11-17 08:52:19,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:19,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:19,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:19,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:19,301 INFO L745 eck$LassoCheckResult]: Stem: 315897#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 315150#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 315151#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 315618#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 315619#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 315826#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 315895#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 315180#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 315181#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 315411#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 315412#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 315870#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 315795#L696-1 assume !(0 == ~M_E~0); 315796#L701-1 assume !(0 == ~T1_E~0); 315835#L706-1 assume !(0 == ~T2_E~0); 315592#L711-1 assume !(0 == ~T3_E~0); 315335#L716-1 assume !(0 == ~T4_E~0); 315336#L721-1 assume !(0 == ~T5_E~0); 315545#L726-1 assume !(0 == ~T6_E~0); 315546#L731-1 assume !(0 == ~E_M~0); 315506#L736-1 assume !(0 == ~E_1~0); 315507#L741-1 assume !(0 == ~E_2~0); 315598#L746-1 assume !(0 == ~E_3~0); 315393#L751-1 assume !(0 == ~E_4~0); 315394#L756-1 assume !(0 == ~E_5~0); 315326#L761-1 assume !(0 == ~E_6~0); 315327#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 315579#L346-9 assume !(1 == ~m_pc~0); 315580#L356-9 is_master_triggered_~__retres1~0#1 := 0; 315347#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 315223#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 315224#L861-9 assume !(0 != activate_threads_~tmp~1#1); 315296#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 315297#L365-9 assume !(1 == ~t1_pc~0); 315508#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 315459#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 315092#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315093#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 315700#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 315581#L384-9 assume !(1 == ~t2_pc~0); 315229#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 315230#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 315869#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 315259#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 315260#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 315104#L403-9 assume !(1 == ~t3_pc~0); 315105#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 315632#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 315633#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 315784#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 315785#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 315233#L422-9 assume !(1 == ~t4_pc~0); 315234#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 315086#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 315087#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 315443#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 315416#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 315417#L441-9 assume !(1 == ~t5_pc~0); 315866#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 315760#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 315761#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 315819#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 315820#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 315167#L460-9 assume !(1 == ~t6_pc~0); 315168#L470-9 is_transmit6_triggered_~__retres1~6#1 := 0; 315460#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 315264#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 315265#L909-9 assume !(0 != activate_threads_~tmp___5~0#1); 315879#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 315882#L774-1 assume !(1 == ~M_E~0); 315757#L779-1 assume !(1 == ~T1_E~0); 315449#L784-1 assume !(1 == ~T2_E~0); 315450#L789-1 assume !(1 == ~T3_E~0); 315200#L794-1 assume !(1 == ~T4_E~0); 315201#L799-1 assume !(1 == ~T5_E~0); 315863#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 315864#L809-1 assume !(1 == ~E_M~0); 315538#L814-1 assume !(1 == ~E_1~0); 315100#L819-1 assume !(1 == ~E_2~0); 315101#L824-1 assume !(1 == ~E_3~0); 315608#L829-1 assume !(1 == ~E_4~0); 315748#L834-1 assume !(1 == ~E_5~0); 315312#L839-1 assume !(1 == ~E_6~0); 315313#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 315831#L1065 [2024-11-17 08:52:19,301 INFO L747 eck$LassoCheckResult]: Loop: 315831#L1065 assume true; 321157#L1065-1 assume !false; 321125#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 321122#L577 assume true; 321120#L577-1 assume !false; 321118#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 320963#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 320961#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 320959#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 320956#L582 assume !(0 != eval_~tmp~0#1); 320957#L585 assume true; 338584#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 338582#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 338580#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 338578#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 338576#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 338574#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 338572#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 338570#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 338568#L726 assume !(0 == ~T6_E~0); 338566#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 338564#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 338562#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 338560#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 338558#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 338556#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 338554#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 338552#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 338550#L346-1 assume !(1 == ~m_pc~0); 338548#L356-1 is_master_triggered_~__retres1~0#1 := 0; 338546#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 338544#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 338542#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 338540#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 338538#L365-1 assume !(1 == ~t1_pc~0); 338536#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 338534#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 338532#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 338530#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 338528#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 338526#L384-1 assume !(1 == ~t2_pc~0); 338524#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 338522#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 338520#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 338518#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 338517#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 338514#L403-1 assume !(1 == ~t3_pc~0); 338490#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 338485#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 338479#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 338473#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 338467#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 338460#L422-1 assume !(1 == ~t4_pc~0); 338454#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 338448#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 338442#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 338436#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 338433#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 338431#L441-1 assume !(1 == ~t5_pc~0); 338429#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 338427#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 338425#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 338422#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 338419#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 321240#L460-1 assume !(1 == ~t6_pc~0); 321238#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 321236#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 321234#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 321232#L909-1 assume !(0 != activate_threads_~tmp___5~0#1); 321229#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 321227#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 321225#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 321223#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 321221#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 321219#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 321217#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 321215#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 321213#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 321211#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 321209#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 321207#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 321205#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 321203#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 321201#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 321199#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 321189#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 321185#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 321183#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 321177#L1084 assume !(0 == start_simulation_~tmp~3#1); 321176#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 321170#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 321167#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 321166#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 321164#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 321163#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 321162#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 321160#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 315831#L1065 [2024-11-17 08:52:19,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:19,302 INFO L85 PathProgramCache]: Analyzing trace with hash 146720066, now seen corresponding path program 1 times [2024-11-17 08:52:19,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:19,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159214277] [2024-11-17 08:52:19,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:19,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:19,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:19,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:19,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:19,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159214277] [2024-11-17 08:52:19,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159214277] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:19,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:19,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:19,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558476439] [2024-11-17 08:52:19,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:19,355 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:19,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:19,355 INFO L85 PathProgramCache]: Analyzing trace with hash -1045648065, now seen corresponding path program 1 times [2024-11-17 08:52:19,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:19,356 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520213234] [2024-11-17 08:52:19,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:19,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:19,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:19,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:19,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:19,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520213234] [2024-11-17 08:52:19,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520213234] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:19,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:19,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:19,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180912466] [2024-11-17 08:52:19,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:19,404 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:19,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:19,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:19,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:19,405 INFO L87 Difference]: Start difference. First operand 54740 states and 76213 transitions. cyclomatic complexity: 21537 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:19,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:19,809 INFO L93 Difference]: Finished difference Result 109396 states and 151845 transitions. [2024-11-17 08:52:19,810 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109396 states and 151845 transitions. [2024-11-17 08:52:20,613 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 107776 [2024-11-17 08:52:20,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109396 states to 109396 states and 151845 transitions. [2024-11-17 08:52:20,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109396 [2024-11-17 08:52:21,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109396 [2024-11-17 08:52:21,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109396 states and 151845 transitions. [2024-11-17 08:52:21,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:21,114 INFO L218 hiAutomatonCegarLoop]: Abstraction has 109396 states and 151845 transitions. [2024-11-17 08:52:21,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109396 states and 151845 transitions. [2024-11-17 08:52:22,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109396 to 109396. [2024-11-17 08:52:22,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109396 states, 109396 states have (on average 1.388030640974076) internal successors, (151845), 109395 states have internal predecessors, (151845), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:22,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109396 states to 109396 states and 151845 transitions. [2024-11-17 08:52:22,961 INFO L240 hiAutomatonCegarLoop]: Abstraction has 109396 states and 151845 transitions. [2024-11-17 08:52:22,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:22,961 INFO L425 stractBuchiCegarLoop]: Abstraction has 109396 states and 151845 transitions. [2024-11-17 08:52:22,961 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:52:22,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109396 states and 151845 transitions. [2024-11-17 08:52:23,257 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 107776 [2024-11-17 08:52:23,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:23,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:23,258 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:23,258 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:23,259 INFO L745 eck$LassoCheckResult]: Stem: 480161#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 479294#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 479295#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 479789#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 479790#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 480024#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 480160#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 479328#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 479329#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 479564#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 479565#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 480113#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 479979#L696-1 assume 0 == ~M_E~0;~M_E~0 := 1; 479980#L701-1 assume !(0 == ~T1_E~0); 480041#L706-1 assume !(0 == ~T2_E~0); 479758#L711-1 assume !(0 == ~T3_E~0); 479759#L716-1 assume !(0 == ~T4_E~0); 480080#L721-1 assume !(0 == ~T5_E~0); 480081#L726-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 479705#L731-1 assume !(0 == ~E_M~0); 480242#L736-1 assume !(0 == ~E_1~0); 480241#L741-1 assume !(0 == ~E_2~0); 480240#L746-1 assume !(0 == ~E_3~0); 480239#L751-1 assume !(0 == ~E_4~0); 480238#L756-1 assume !(0 == ~E_5~0); 480237#L761-1 assume !(0 == ~E_6~0); 480236#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 480235#L346-9 assume !(1 == ~m_pc~0); 480234#L356-9 is_master_triggered_~__retres1~0#1 := 0; 480233#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 480232#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 480231#L861-9 assume !(0 != activate_threads_~tmp~1#1); 480230#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 480229#L365-9 assume !(1 == ~t1_pc~0); 480228#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 480227#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 480226#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 480225#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 480224#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 480223#L384-9 assume !(1 == ~t2_pc~0); 480222#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 480221#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 480220#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 480219#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 480218#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 480217#L403-9 assume !(1 == ~t3_pc~0); 480216#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 480215#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 480214#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 480213#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 480212#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 480211#L422-9 assume !(1 == ~t4_pc~0); 480210#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 480209#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 480208#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 480207#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 480206#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 480205#L441-9 assume !(1 == ~t5_pc~0); 480204#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 480203#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 480202#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 480201#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 480200#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 480199#L460-9 assume !(1 == ~t6_pc~0); 480198#L470-9 is_transmit6_triggered_~__retres1~6#1 := 0; 480197#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 480196#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 480195#L909-9 assume !(0 != activate_threads_~tmp___5~0#1); 480194#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 480193#L774-1 assume !(1 == ~M_E~0); 480192#L779-1 assume !(1 == ~T1_E~0); 480191#L784-1 assume !(1 == ~T2_E~0); 480190#L789-1 assume !(1 == ~T3_E~0); 480189#L794-1 assume !(1 == ~T4_E~0); 480188#L799-1 assume !(1 == ~T5_E~0); 480187#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 480095#L809-1 assume !(1 == ~E_M~0); 479700#L814-1 assume !(1 == ~E_1~0); 479245#L819-1 assume !(1 == ~E_2~0); 479246#L824-1 assume !(1 == ~E_3~0); 479777#L829-1 assume !(1 == ~E_4~0); 479929#L834-1 assume !(1 == ~E_5~0); 479460#L839-1 assume !(1 == ~E_6~0); 479461#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 480032#L1065 [2024-11-17 08:52:23,259 INFO L747 eck$LassoCheckResult]: Loop: 480032#L1065 assume true; 506874#L1065-1 assume !false; 506869#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 506867#L577 assume true; 506865#L577-1 assume !false; 506863#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 506847#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 506845#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 506843#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 506840#L582 assume !(0 != eval_~tmp~0#1); 506841#L585 assume true; 587688#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 585603#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 585484#L696 assume 0 == ~M_E~0;~M_E~0 := 1; 578177#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 585477#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 578161#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 578160#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 578159#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 578158#L726 assume 0 == ~T6_E~0;~T6_E~0 := 1; 578154#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 578152#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 578150#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 578148#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 578146#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 578144#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 578142#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 578140#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 578138#L346-1 assume !(1 == ~m_pc~0); 578136#L356-1 is_master_triggered_~__retres1~0#1 := 0; 578134#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 578132#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 578130#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 578128#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 578126#L365-1 assume !(1 == ~t1_pc~0); 578124#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 578122#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 578120#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 578118#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 578116#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 578114#L384-1 assume !(1 == ~t2_pc~0); 578112#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 578110#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 578108#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 578106#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 578104#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 578102#L403-1 assume !(1 == ~t3_pc~0); 578100#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 578098#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 578096#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 578094#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 578092#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 578090#L422-1 assume !(1 == ~t4_pc~0); 578088#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 578086#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 578084#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 578082#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 578080#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 578078#L441-1 assume !(1 == ~t5_pc~0); 578076#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 578074#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 578072#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 578070#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 578068#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 506959#L460-1 assume !(1 == ~t6_pc~0); 506955#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 506954#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 506953#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 506952#L909-1 assume !(0 != activate_threads_~tmp___5~0#1); 506950#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 506948#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 506946#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 506944#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 506942#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 506940#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 506938#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 506927#L804 assume 1 == ~T6_E~0;~T6_E~0 := 2; 506925#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 506923#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 506921#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 506919#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 506917#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 506915#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 506913#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 506911#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 506901#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 506897#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 506895#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 506892#L1084 assume !(0 == start_simulation_~tmp~3#1); 506891#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 506885#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 506883#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 506881#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 506880#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 506878#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 506877#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 506875#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 480032#L1065 [2024-11-17 08:52:23,260 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:23,260 INFO L85 PathProgramCache]: Analyzing trace with hash 474253380, now seen corresponding path program 1 times [2024-11-17 08:52:23,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:23,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700771794] [2024-11-17 08:52:23,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:23,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:23,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:23,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:23,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:23,300 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700771794] [2024-11-17 08:52:23,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700771794] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:23,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:23,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:23,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318915355] [2024-11-17 08:52:23,301 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:23,301 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:23,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:23,302 INFO L85 PathProgramCache]: Analyzing trace with hash -1465164896, now seen corresponding path program 1 times [2024-11-17 08:52:23,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:23,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724587799] [2024-11-17 08:52:23,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:23,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:23,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:23,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:23,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:23,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724587799] [2024-11-17 08:52:23,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724587799] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:23,356 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:23,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:23,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889217024] [2024-11-17 08:52:23,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:23,357 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:23,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:23,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:23,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:23,358 INFO L87 Difference]: Start difference. First operand 109396 states and 151845 transitions. cyclomatic complexity: 42577 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:24,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:24,509 INFO L93 Difference]: Finished difference Result 165653 states and 230412 transitions. [2024-11-17 08:52:24,509 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 165653 states and 230412 transitions. [2024-11-17 08:52:25,100 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 163392 [2024-11-17 08:52:25,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 165653 states to 165653 states and 230412 transitions. [2024-11-17 08:52:25,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 165653 [2024-11-17 08:52:25,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 165653 [2024-11-17 08:52:25,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 165653 states and 230412 transitions. [2024-11-17 08:52:25,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:25,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 165653 states and 230412 transitions. [2024-11-17 08:52:25,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165653 states and 230412 transitions. [2024-11-17 08:52:27,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165653 to 119245. [2024-11-17 08:52:27,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119245 states, 119245 states have (on average 1.3954211916642207) internal successors, (166397), 119244 states have internal predecessors, (166397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:27,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119245 states to 119245 states and 166397 transitions. [2024-11-17 08:52:27,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 119245 states and 166397 transitions. [2024-11-17 08:52:27,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:27,910 INFO L425 stractBuchiCegarLoop]: Abstraction has 119245 states and 166397 transitions. [2024-11-17 08:52:27,910 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:52:27,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 119245 states and 166397 transitions. [2024-11-17 08:52:28,160 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 117696 [2024-11-17 08:52:28,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:28,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:28,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:28,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:28,162 INFO L745 eck$LassoCheckResult]: Stem: 755147#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 754353#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 754354#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 754833#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 754834#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 755034#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 755146#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 754386#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 754387#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 754624#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 754625#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 755102#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 754999#L696-1 assume !(0 == ~M_E~0); 755000#L701-1 assume !(0 == ~T1_E~0); 755047#L706-1 assume !(0 == ~T2_E~0); 754803#L711-1 assume !(0 == ~T3_E~0); 754543#L716-1 assume !(0 == ~T4_E~0); 754544#L721-1 assume !(0 == ~T5_E~0); 754754#L726-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 754755#L731-1 assume !(0 == ~E_M~0); 755184#L736-1 assume !(0 == ~E_1~0); 754809#L741-1 assume !(0 == ~E_2~0); 754810#L746-1 assume !(0 == ~E_3~0); 754603#L751-1 assume !(0 == ~E_4~0); 754604#L756-1 assume !(0 == ~E_5~0); 754694#L761-1 assume !(0 == ~E_6~0); 755077#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 755078#L346-9 assume !(1 == ~m_pc~0); 755182#L356-9 is_master_triggered_~__retres1~0#1 := 0; 754557#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 754558#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 754619#L861-9 assume !(0 != activate_threads_~tmp~1#1); 754507#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 754508#L365-9 assume !(1 == ~t1_pc~0); 754723#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 754672#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 754673#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 755177#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 755176#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 754792#L384-9 assume !(1 == ~t2_pc~0); 754793#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 755111#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 755112#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 754466#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 754467#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 754967#L403-9 assume !(1 == ~t3_pc~0); 755065#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 755066#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 755139#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 754990#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 754991#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 754439#L422-9 assume !(1 == ~t4_pc~0); 754440#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 754293#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 754294#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 755173#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 754629#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 754630#L441-9 assume !(1 == ~t5_pc~0); 755163#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 754969#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 754970#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 755022#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 755023#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 754373#L460-9 assume !(1 == ~t6_pc~0); 754374#L470-9 is_transmit6_triggered_~__retres1~6#1 := 0; 755171#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 755170#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 755120#L909-9 assume !(0 != activate_threads_~tmp___5~0#1); 755121#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 755141#L774-1 assume !(1 == ~M_E~0); 754962#L779-1 assume !(1 == ~T1_E~0); 754664#L784-1 assume !(1 == ~T2_E~0); 754665#L789-1 assume !(1 == ~T3_E~0); 755167#L794-1 assume !(1 == ~T4_E~0); 755134#L799-1 assume !(1 == ~T5_E~0); 755135#L804-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 755087#L809-1 assume !(1 == ~E_M~0); 754750#L814-1 assume !(1 == ~E_1~0); 754304#L819-1 assume !(1 == ~E_2~0); 754305#L824-1 assume !(1 == ~E_3~0); 754821#L829-1 assume !(1 == ~E_4~0); 754956#L834-1 assume !(1 == ~E_5~0); 754523#L839-1 assume !(1 == ~E_6~0); 754524#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 755039#L1065 [2024-11-17 08:52:28,163 INFO L747 eck$LassoCheckResult]: Loop: 755039#L1065 assume true; 768550#L1065-1 assume !false; 768548#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 768485#L577 assume true; 768545#L577-1 assume !false; 768543#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 768529#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 768527#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 768525#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 768522#L582 assume !(0 != eval_~tmp~0#1); 768523#L585 assume true; 777216#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 777213#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 777211#L696 assume !(0 == ~M_E~0); 777209#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 777207#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 777205#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 777202#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 777198#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 777196#L726 assume !(0 == ~T6_E~0); 777197#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 780102#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 780097#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 780093#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 780089#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 780085#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 780080#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 780076#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 780072#L346-1 assume !(1 == ~m_pc~0); 780068#L356-1 is_master_triggered_~__retres1~0#1 := 0; 780064#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 780059#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 780056#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 780052#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 780048#L365-1 assume !(1 == ~t1_pc~0); 780043#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 780038#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 780031#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 780026#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 780020#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 780013#L384-1 assume !(1 == ~t2_pc~0); 780007#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 780001#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 779933#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 779927#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 779921#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 779915#L403-1 assume !(1 == ~t3_pc~0); 779909#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 779886#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 779881#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 779876#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 779863#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 779857#L422-1 assume !(1 == ~t4_pc~0); 779740#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 779739#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 779738#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 779736#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 779734#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 779732#L441-1 assume !(1 == ~t5_pc~0); 779730#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 779728#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 779726#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 779724#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 779722#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 772278#L460-1 assume !(1 == ~t6_pc~0); 772276#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 772274#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 772273#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 772272#L909-1 assume !(0 != activate_threads_~tmp___5~0#1); 772271#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 772270#L774 assume !(1 == ~M_E~0); 762773#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 772269#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 772261#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 772259#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 772257#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 772255#L804 assume !(1 == ~T6_E~0); 772252#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 772250#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 772248#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 772246#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 772244#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 772243#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 772242#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 772241#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 772234#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 772231#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 772230#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 764660#L1084 assume !(0 == start_simulation_~tmp~3#1); 764661#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 768566#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 768563#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 768561#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 768559#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 768557#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 768555#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 768553#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 755039#L1065 [2024-11-17 08:52:28,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:28,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1634779869, now seen corresponding path program 1 times [2024-11-17 08:52:28,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:28,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974961327] [2024-11-17 08:52:28,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:28,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:28,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:28,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:28,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:28,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1974961327] [2024-11-17 08:52:28,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1974961327] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:28,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:28,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:28,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686688532] [2024-11-17 08:52:28,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:28,211 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:28,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:28,212 INFO L85 PathProgramCache]: Analyzing trace with hash 1335235040, now seen corresponding path program 1 times [2024-11-17 08:52:28,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:28,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089850091] [2024-11-17 08:52:28,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:28,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:28,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:28,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:28,255 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:28,255 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089850091] [2024-11-17 08:52:28,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089850091] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:28,255 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:28,256 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:28,256 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463258029] [2024-11-17 08:52:28,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:28,256 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:28,257 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:28,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:28,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:28,258 INFO L87 Difference]: Start difference. First operand 119245 states and 166397 transitions. cyclomatic complexity: 47216 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:28,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:28,712 INFO L93 Difference]: Finished difference Result 149332 states and 206897 transitions. [2024-11-17 08:52:28,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 149332 states and 206897 transitions. [2024-11-17 08:52:29,843 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 147136 [2024-11-17 08:52:30,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 149332 states to 149332 states and 206897 transitions. [2024-11-17 08:52:30,197 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149332 [2024-11-17 08:52:30,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149332 [2024-11-17 08:52:30,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 149332 states and 206897 transitions. [2024-11-17 08:52:30,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:30,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 149332 states and 206897 transitions. [2024-11-17 08:52:30,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149332 states and 206897 transitions. [2024-11-17 08:52:31,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149332 to 102932. [2024-11-17 08:52:31,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102932 states, 102932 states have (on average 1.3895095791396261) internal successors, (143025), 102931 states have internal predecessors, (143025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:32,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102932 states to 102932 states and 143025 transitions. [2024-11-17 08:52:32,022 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102932 states and 143025 transitions. [2024-11-17 08:52:32,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:32,023 INFO L425 stractBuchiCegarLoop]: Abstraction has 102932 states and 143025 transitions. [2024-11-17 08:52:32,023 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:52:32,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102932 states and 143025 transitions. [2024-11-17 08:52:32,291 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 101440 [2024-11-17 08:52:32,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:32,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:32,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:32,292 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:32,293 INFO L745 eck$LassoCheckResult]: Stem: 1023736#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1022943#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1022944#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1023424#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1023425#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1023640#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1023735#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1022977#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1022978#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1023212#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1023213#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1023697#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1023608#L696-1 assume !(0 == ~M_E~0); 1023609#L701-1 assume !(0 == ~T1_E~0); 1023653#L706-1 assume !(0 == ~T2_E~0); 1023392#L711-1 assume !(0 == ~T3_E~0); 1023132#L716-1 assume !(0 == ~T4_E~0); 1023133#L721-1 assume !(0 == ~T5_E~0); 1023344#L726-1 assume !(0 == ~T6_E~0); 1023345#L731-1 assume !(0 == ~E_M~0); 1023308#L736-1 assume !(0 == ~E_1~0); 1023309#L741-1 assume !(0 == ~E_2~0); 1023399#L746-1 assume !(0 == ~E_3~0); 1023195#L751-1 assume !(0 == ~E_4~0); 1023196#L756-1 assume !(0 == ~E_5~0); 1023126#L761-1 assume !(0 == ~E_6~0); 1023127#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1023378#L346-9 assume !(1 == ~m_pc~0); 1023379#L356-9 is_master_triggered_~__retres1~0#1 := 0; 1023147#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1023018#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1023019#L861-9 assume !(0 != activate_threads_~tmp~1#1); 1023096#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1023097#L365-9 assume !(1 == ~t1_pc~0); 1023312#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 1023263#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1022889#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1022890#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 1023507#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1023382#L384-9 assume !(1 == ~t2_pc~0); 1023026#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 1023027#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1023695#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1023056#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 1023057#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1022901#L403-9 assume !(1 == ~t3_pc~0); 1022902#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 1023436#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1023437#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1023595#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 1023596#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1023030#L422-9 assume !(1 == ~t4_pc~0); 1023031#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 1022882#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1022883#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1023246#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 1023217#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1023218#L441-9 assume !(1 == ~t5_pc~0); 1023691#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 1023570#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1023571#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1023628#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 1023629#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1022964#L460-9 assume !(1 == ~t6_pc~0); 1022965#L470-9 is_transmit6_triggered_~__retres1~6#1 := 0; 1023264#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1023060#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1023061#L909-9 assume !(0 != activate_threads_~tmp___5~0#1); 1023709#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1023713#L774-1 assume !(1 == ~M_E~0); 1023566#L779-1 assume !(1 == ~T1_E~0); 1023253#L784-1 assume !(1 == ~T2_E~0); 1023254#L789-1 assume !(1 == ~T3_E~0); 1022998#L794-1 assume !(1 == ~T4_E~0); 1022999#L799-1 assume !(1 == ~T5_E~0); 1023687#L804-1 assume !(1 == ~T6_E~0); 1023688#L809-1 assume !(1 == ~E_M~0); 1023340#L814-1 assume !(1 == ~E_1~0); 1022893#L819-1 assume !(1 == ~E_2~0); 1022894#L824-1 assume !(1 == ~E_3~0); 1023408#L829-1 assume !(1 == ~E_4~0); 1023559#L834-1 assume !(1 == ~E_5~0); 1023111#L839-1 assume !(1 == ~E_6~0); 1023112#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 1023648#L1065 [2024-11-17 08:52:32,293 INFO L747 eck$LassoCheckResult]: Loop: 1023648#L1065 assume true; 1048764#L1065-1 assume !false; 1048742#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1048740#L577 assume true; 1048739#L577-1 assume !false; 1048738#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1048731#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1048730#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1048728#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1048726#L582 assume !(0 != eval_~tmp~0#1); 1048727#L585 assume true; 1060240#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1060238#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1060236#L696 assume !(0 == ~M_E~0); 1060234#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1060232#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1060230#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1060228#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1060226#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1060224#L726 assume !(0 == ~T6_E~0); 1060222#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 1060220#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 1060218#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 1060216#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 1060214#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 1060212#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 1060210#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 1060208#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1060205#L346-1 assume !(1 == ~m_pc~0); 1060203#L356-1 is_master_triggered_~__retres1~0#1 := 0; 1060201#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1060199#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1060197#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1060195#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1060192#L365-1 assume !(1 == ~t1_pc~0); 1060190#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1060188#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1060186#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1060184#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1060181#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1060178#L384-1 assume !(1 == ~t2_pc~0); 1060176#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1060174#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1060172#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1060169#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 1060167#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1060164#L403-1 assume !(1 == ~t3_pc~0); 1060162#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1060160#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1060158#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1060156#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1060155#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1060152#L422-1 assume !(1 == ~t4_pc~0); 1060151#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1060150#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1060149#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1060148#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1060147#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1060146#L441-1 assume !(1 == ~t5_pc~0); 1060145#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1060144#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1060143#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1060142#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1060141#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1060140#L460-1 assume !(1 == ~t6_pc~0); 1052415#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1060138#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1060136#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1060134#L909-1 assume !(0 != activate_threads_~tmp___5~0#1); 1060132#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1060130#L774 assume !(1 == ~M_E~0); 1040305#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1060127#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1060125#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1060123#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1060120#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1060118#L804 assume !(1 == ~T6_E~0); 1060116#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 1060114#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 1060112#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 1060110#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 1060108#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 1060106#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 1060104#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 1060102#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1060092#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1060088#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1060086#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1040282#L1084 assume !(0 == start_simulation_~tmp~3#1); 1040283#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1048783#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1048780#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1048777#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1048774#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1048772#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1048770#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1048768#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1023648#L1065 [2024-11-17 08:52:32,293 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:32,293 INFO L85 PathProgramCache]: Analyzing trace with hash -1660734397, now seen corresponding path program 1 times [2024-11-17 08:52:32,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:32,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462902543] [2024-11-17 08:52:32,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:32,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:32,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:32,306 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:32,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:32,348 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:32,349 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:32,349 INFO L85 PathProgramCache]: Analyzing trace with hash 1335235040, now seen corresponding path program 2 times [2024-11-17 08:52:32,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:32,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1045980909] [2024-11-17 08:52:32,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:32,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:32,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:32,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:32,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:32,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1045980909] [2024-11-17 08:52:32,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1045980909] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:32,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:32,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:32,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879634765] [2024-11-17 08:52:32,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:32,397 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:32,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:32,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:32,398 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:32,399 INFO L87 Difference]: Start difference. First operand 102932 states and 143025 transitions. cyclomatic complexity: 40157 Second operand has 5 states, 5 states have (on average 19.4) internal successors, (97), 5 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:33,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:33,405 INFO L93 Difference]: Finished difference Result 104724 states and 144817 transitions. [2024-11-17 08:52:33,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104724 states and 144817 transitions. [2024-11-17 08:52:33,795 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 103232 [2024-11-17 08:52:34,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104724 states to 104724 states and 144817 transitions. [2024-11-17 08:52:34,048 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 104724 [2024-11-17 08:52:34,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 104724 [2024-11-17 08:52:34,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104724 states and 144817 transitions. [2024-11-17 08:52:34,172 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:34,173 INFO L218 hiAutomatonCegarLoop]: Abstraction has 104724 states and 144817 transitions. [2024-11-17 08:52:34,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104724 states and 144817 transitions. [2024-11-17 08:52:35,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104724 to 103700. [2024-11-17 08:52:35,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103700 states, 103700 states have (on average 1.3866248794599807) internal successors, (143793), 103699 states have internal predecessors, (143793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:35,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103700 states to 103700 states and 143793 transitions. [2024-11-17 08:52:35,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103700 states and 143793 transitions. [2024-11-17 08:52:35,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:35,697 INFO L425 stractBuchiCegarLoop]: Abstraction has 103700 states and 143793 transitions. [2024-11-17 08:52:35,697 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:52:35,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103700 states and 143793 transitions. [2024-11-17 08:52:35,967 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 102208 [2024-11-17 08:52:35,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:35,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:35,968 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:35,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:35,969 INFO L745 eck$LassoCheckResult]: Stem: 1231421#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1230608#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1230609#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1231107#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1231108#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1231310#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1231418#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1230641#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1230642#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1230881#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1230882#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1231377#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1231280#L696-1 assume !(0 == ~M_E~0); 1231281#L701-1 assume !(0 == ~T1_E~0); 1231324#L706-1 assume !(0 == ~T2_E~0); 1231074#L711-1 assume !(0 == ~T3_E~0); 1230797#L716-1 assume !(0 == ~T4_E~0); 1230798#L721-1 assume !(0 == ~T5_E~0); 1231017#L726-1 assume !(0 == ~T6_E~0); 1231018#L731-1 assume !(0 == ~E_M~0); 1230979#L736-1 assume !(0 == ~E_1~0); 1230980#L741-1 assume !(0 == ~E_2~0); 1231080#L746-1 assume !(0 == ~E_3~0); 1230859#L751-1 assume !(0 == ~E_4~0); 1230860#L756-1 assume !(0 == ~E_5~0); 1230791#L761-1 assume !(0 == ~E_6~0); 1230792#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1231056#L346-9 assume !(1 == ~m_pc~0); 1231057#L356-9 is_master_triggered_~__retres1~0#1 := 0; 1230812#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1230684#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1230685#L861-9 assume !(0 != activate_threads_~tmp~1#1); 1230762#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1230763#L365-9 assume !(1 == ~t1_pc~0); 1230983#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 1230933#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1230553#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1230554#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 1231186#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1231060#L384-9 assume !(1 == ~t2_pc~0); 1230692#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 1230693#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1231375#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1230722#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 1230723#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1230566#L403-9 assume !(1 == ~t3_pc~0); 1230567#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 1231119#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1231120#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1231268#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 1231269#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1230696#L422-9 assume !(1 == ~t4_pc~0); 1230697#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 1230546#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1230547#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1230918#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 1230886#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1230887#L441-9 assume !(1 == ~t5_pc~0); 1231372#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 1231241#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1231242#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1231299#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 1231300#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1230628#L460-9 assume !(1 == ~t6_pc~0); 1230629#L470-9 is_transmit6_triggered_~__retres1~6#1 := 0; 1230934#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1230727#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1230728#L909-9 assume !(0 != activate_threads_~tmp___5~0#1); 1231390#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1231394#L774-1 assume !(1 == ~M_E~0); 1231238#L779-1 assume !(1 == ~T1_E~0); 1230925#L784-1 assume !(1 == ~T2_E~0); 1230926#L789-1 assume !(1 == ~T3_E~0); 1230662#L794-1 assume !(1 == ~T4_E~0); 1230663#L799-1 assume !(1 == ~T5_E~0); 1231367#L804-1 assume !(1 == ~T6_E~0); 1231368#L809-1 assume !(1 == ~E_M~0); 1231013#L814-1 assume !(1 == ~E_1~0); 1230557#L819-1 assume !(1 == ~E_2~0); 1230558#L824-1 assume !(1 == ~E_3~0); 1231093#L829-1 assume !(1 == ~E_4~0); 1231230#L834-1 assume !(1 == ~E_5~0); 1230778#L839-1 assume !(1 == ~E_6~0); 1230779#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 1231317#L1065 [2024-11-17 08:52:35,969 INFO L747 eck$LassoCheckResult]: Loop: 1231317#L1065 assume true; 1254924#L1065-1 assume !false; 1254923#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1254114#L577 assume true; 1254922#L577-1 assume !false; 1254921#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1254920#L530-2 assume !(0 == ~m_st~0); 1254919#L534-2 assume !(0 == ~t1_st~0); 1254918#L538-2 assume !(0 == ~t2_st~0); 1254917#L542-2 assume !(0 == ~t3_st~0); 1254916#L546-2 assume !(0 == ~t4_st~0); 1254915#L550-2 assume !(0 == ~t5_st~0); 1254913#L554-2 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1254912#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1254911#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1254910#L582 assume !(0 != eval_~tmp~0#1); 1254909#L585 assume true; 1254907#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1254905#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1254903#L696 assume !(0 == ~M_E~0); 1254901#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1254899#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1254897#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1254895#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1254893#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1254891#L726 assume !(0 == ~T6_E~0); 1254889#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 1254887#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 1254885#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 1254883#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 1254881#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 1254879#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 1254877#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 1254875#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1254873#L346-1 assume !(1 == ~m_pc~0); 1254871#L356-1 is_master_triggered_~__retres1~0#1 := 0; 1254869#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1254867#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1254865#L861-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1254863#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1254861#L365-1 assume !(1 == ~t1_pc~0); 1254859#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1254857#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1254855#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1254853#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1254851#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1254849#L384-1 assume !(1 == ~t2_pc~0); 1254847#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1254845#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1254843#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1254841#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 1254839#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1254837#L403-1 assume !(1 == ~t3_pc~0); 1254835#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1254833#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1254831#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1254829#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1254827#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1254825#L422-1 assume !(1 == ~t4_pc~0); 1254823#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1254821#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1254819#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1254817#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1254815#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1254813#L441-1 assume !(1 == ~t5_pc~0); 1254811#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1254809#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1254807#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1254805#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1254803#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1254801#L460-1 assume !(1 == ~t6_pc~0); 1254257#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1254799#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1254797#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1254795#L909-1 assume !(0 != activate_threads_~tmp___5~0#1); 1254793#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1254791#L774 assume !(1 == ~M_E~0); 1254788#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1254787#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1254786#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1254785#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1254784#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1254783#L804 assume !(1 == ~T6_E~0); 1254782#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 1254781#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 1254780#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 1254779#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 1254778#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 1254777#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 1254776#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 1254775#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1254770#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1254764#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1254619#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1254617#L1084 assume !(0 == start_simulation_~tmp~3#1); 1254618#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1254986#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1254979#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1254929#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1254928#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1254927#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1254926#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1254925#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1231317#L1065 [2024-11-17 08:52:35,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:35,970 INFO L85 PathProgramCache]: Analyzing trace with hash -1660734397, now seen corresponding path program 2 times [2024-11-17 08:52:35,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:35,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947219486] [2024-11-17 08:52:35,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:35,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:35,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:35,980 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:35,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:36,000 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:36,001 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:36,001 INFO L85 PathProgramCache]: Analyzing trace with hash 18681527, now seen corresponding path program 1 times [2024-11-17 08:52:36,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:36,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233976426] [2024-11-17 08:52:36,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:36,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:36,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:36,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:36,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:36,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233976426] [2024-11-17 08:52:36,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233976426] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:36,071 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:36,071 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:36,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672133651] [2024-11-17 08:52:36,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:36,072 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:36,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:36,072 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:36,072 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:36,073 INFO L87 Difference]: Start difference. First operand 103700 states and 143793 transitions. cyclomatic complexity: 40157 Second operand has 5 states, 5 states have (on average 20.6) internal successors, (103), 5 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:37,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:37,281 INFO L93 Difference]: Finished difference Result 105812 states and 145328 transitions. [2024-11-17 08:52:37,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105812 states and 145328 transitions. [2024-11-17 08:52:37,737 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 104320 [2024-11-17 08:52:38,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105812 states to 105812 states and 145328 transitions. [2024-11-17 08:52:38,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 105812 [2024-11-17 08:52:38,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 105812 [2024-11-17 08:52:38,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105812 states and 145328 transitions. [2024-11-17 08:52:38,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:38,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 105812 states and 145328 transitions. [2024-11-17 08:52:38,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105812 states and 145328 transitions. [2024-11-17 08:52:39,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105812 to 105812. [2024-11-17 08:52:39,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105812 states, 105812 states have (on average 1.3734548066381884) internal successors, (145328), 105811 states have internal predecessors, (145328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:39,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105812 states to 105812 states and 145328 transitions. [2024-11-17 08:52:39,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 105812 states and 145328 transitions. [2024-11-17 08:52:39,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:39,810 INFO L425 stractBuchiCegarLoop]: Abstraction has 105812 states and 145328 transitions. [2024-11-17 08:52:39,810 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:52:39,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105812 states and 145328 transitions. [2024-11-17 08:52:40,077 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 104320 [2024-11-17 08:52:40,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:40,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:40,078 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:40,078 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:40,079 INFO L745 eck$LassoCheckResult]: Stem: 1440876#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1440128#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1440129#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1440600#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1440601#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1440790#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1440875#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1440162#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1440163#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1440390#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1440391#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1440848#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1440764#L696-1 assume !(0 == ~M_E~0); 1440765#L701-1 assume !(0 == ~T1_E~0); 1440802#L706-1 assume !(0 == ~T2_E~0); 1440569#L711-1 assume !(0 == ~T3_E~0); 1440313#L716-1 assume !(0 == ~T4_E~0); 1440314#L721-1 assume !(0 == ~T5_E~0); 1440520#L726-1 assume !(0 == ~T6_E~0); 1440521#L731-1 assume !(0 == ~E_M~0); 1440485#L736-1 assume !(0 == ~E_1~0); 1440486#L741-1 assume !(0 == ~E_2~0); 1440576#L746-1 assume !(0 == ~E_3~0); 1440371#L751-1 assume !(0 == ~E_4~0); 1440372#L756-1 assume !(0 == ~E_5~0); 1440307#L761-1 assume !(0 == ~E_6~0); 1440308#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1440555#L346-9 assume !(1 == ~m_pc~0); 1440556#L356-9 is_master_triggered_~__retres1~0#1 := 0; 1440327#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1440204#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1440205#L861-9 assume !(0 != activate_threads_~tmp~1#1); 1440280#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1440281#L365-9 assume !(1 == ~t1_pc~0); 1440489#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 1440439#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1440073#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1440074#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 1440679#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1440559#L384-9 assume !(1 == ~t2_pc~0); 1440212#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 1440213#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1440846#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1440242#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 1440243#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1440086#L403-9 assume !(1 == ~t3_pc~0); 1440087#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 1440611#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1440612#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1440754#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 1440755#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1440216#L422-9 assume !(1 == ~t4_pc~0); 1440217#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 1440066#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1440067#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1440422#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 1440396#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1440397#L441-9 assume !(1 == ~t5_pc~0); 1440844#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 1440733#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1440734#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1440782#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 1440783#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1440149#L460-9 assume !(1 == ~t6_pc~0); 1440150#L470-9 is_transmit6_triggered_~__retres1~6#1 := 0; 1440440#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1440246#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1440247#L909-9 assume !(0 != activate_threads_~tmp___5~0#1); 1440856#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1440864#L774-1 assume !(1 == ~M_E~0); 1440730#L779-1 assume !(1 == ~T1_E~0); 1440430#L784-1 assume !(1 == ~T2_E~0); 1440431#L789-1 assume !(1 == ~T3_E~0); 1440184#L794-1 assume !(1 == ~T4_E~0); 1440185#L799-1 assume !(1 == ~T5_E~0); 1440840#L804-1 assume !(1 == ~T6_E~0); 1440841#L809-1 assume !(1 == ~E_M~0); 1440516#L814-1 assume !(1 == ~E_1~0); 1440077#L819-1 assume !(1 == ~E_2~0); 1440078#L824-1 assume !(1 == ~E_3~0); 1440585#L829-1 assume !(1 == ~E_4~0); 1440724#L834-1 assume !(1 == ~E_5~0); 1440294#L839-1 assume !(1 == ~E_6~0); 1440295#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 1440798#L1065 [2024-11-17 08:52:40,079 INFO L747 eck$LassoCheckResult]: Loop: 1440798#L1065 assume true; 1449796#L1065-1 assume !false; 1449794#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1449751#L577 assume true; 1449789#L577-1 assume !false; 1449787#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1449779#L530-2 assume !(0 == ~m_st~0); 1449780#L534-2 assume !(0 == ~t1_st~0); 1449781#L538-2 assume !(0 == ~t2_st~0); 1449784#L542-2 assume !(0 == ~t3_st~0); 1449785#L546-2 assume !(0 == ~t4_st~0); 1449786#L550-2 assume !(0 == ~t5_st~0); 1449782#L554-2 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1449783#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1454639#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1454637#L582 assume !(0 != eval_~tmp~0#1); 1454635#L585 assume true; 1454633#L689 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1454631#L480 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1454629#L696 assume !(0 == ~M_E~0); 1454627#L701 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1454625#L706 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1454623#L711 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1454622#L716 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1454620#L721 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1454618#L726 assume !(0 == ~T6_E~0); 1454616#L731 assume 0 == ~E_M~0;~E_M~0 := 1; 1454614#L736 assume 0 == ~E_1~0;~E_1~0 := 1; 1454611#L741 assume 0 == ~E_2~0;~E_2~0 := 1; 1454609#L746 assume 0 == ~E_3~0;~E_3~0 := 1; 1454607#L751 assume 0 == ~E_4~0;~E_4~0 := 1; 1454605#L756 assume 0 == ~E_5~0;~E_5~0 := 1; 1454603#L761 assume 0 == ~E_6~0;~E_6~0 := 1; 1454600#L767 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1454596#L346-1 assume !(1 == ~m_pc~0); 1454593#L356-1 is_master_triggered_~__retres1~0#1 := 0; 1454590#L349-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1454587#L358-1 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1454586#L861-1 assume !(0 != activate_threads_~tmp~1#1); 1454584#L867-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1454582#L365-1 assume !(1 == ~t1_pc~0); 1454580#L375-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1454578#L368-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1454576#L377-1 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1454574#L869-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1454571#L875-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1454569#L384-1 assume !(1 == ~t2_pc~0); 1454567#L394-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1454565#L387-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1454563#L396-1 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1454560#L877-1 assume !(0 != activate_threads_~tmp___1~0#1); 1454557#L883-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1454556#L403-1 assume !(1 == ~t3_pc~0); 1454555#L413-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1454554#L406-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1454553#L415-1 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1454552#L885-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1454551#L891-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1454550#L422-1 assume !(1 == ~t4_pc~0); 1454548#L432-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1454546#L425-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1454544#L434-1 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1454542#L893-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1454540#L899-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1454538#L441-1 assume !(1 == ~t5_pc~0); 1454536#L451-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1454534#L444-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1454532#L453-1 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1454530#L901-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1454528#L907-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1451603#L460-1 assume !(1 == ~t6_pc~0); 1451601#L470-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1451599#L463-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1451596#L472-1 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1451594#L909-1 assume !(0 != activate_threads_~tmp___5~0#1); 1451592#L915-1 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1451589#L774 assume !(1 == ~M_E~0); 1451585#L779 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1451583#L784 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1451581#L789 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1451579#L794 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1451577#L799 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1451575#L804 assume !(1 == ~T6_E~0); 1451573#L809 assume 1 == ~E_M~0;~E_M~0 := 2; 1451571#L814 assume 1 == ~E_1~0;~E_1~0 := 2; 1451569#L819 assume 1 == ~E_2~0;~E_2~0 := 2; 1451567#L824 assume 1 == ~E_3~0;~E_3~0 := 2; 1451565#L829 assume 1 == ~E_4~0;~E_4~0 := 2; 1451562#L834 assume 1 == ~E_5~0;~E_5~0 := 2; 1451560#L839 assume 1 == ~E_6~0;~E_6~0 := 2; 1451558#L845 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1451540#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1451537#L556-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1451536#L568-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1449845#L1084 assume !(0 == start_simulation_~tmp~3#1); 1449843#L1095 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1449812#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1449809#L556 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1449807#L568 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1449805#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1449803#L1041 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1449801#L1047 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1449799#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1440798#L1065 [2024-11-17 08:52:40,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:40,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1660734397, now seen corresponding path program 3 times [2024-11-17 08:52:40,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:40,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951626619] [2024-11-17 08:52:40,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:40,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:40,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:40,091 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:40,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:40,109 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:40,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:40,110 INFO L85 PathProgramCache]: Analyzing trace with hash 1323075256, now seen corresponding path program 1 times [2024-11-17 08:52:40,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:40,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685575789] [2024-11-17 08:52:40,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:40,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:40,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:40,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:40,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:40,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685575789] [2024-11-17 08:52:40,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685575789] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:40,141 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:40,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:40,142 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234610241] [2024-11-17 08:52:40,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:40,142 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:40,142 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:40,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:40,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:40,143 INFO L87 Difference]: Start difference. First operand 105812 states and 145328 transitions. cyclomatic complexity: 39580 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:41,369 INFO L93 Difference]: Finished difference Result 167479 states and 225747 transitions. [2024-11-17 08:52:41,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167479 states and 225747 transitions. [2024-11-17 08:52:41,926 INFO L131 ngComponentsAnalysis]: Automaton has 97 accepting balls. 165246 [2024-11-17 08:52:42,247 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167479 states to 167479 states and 225747 transitions. [2024-11-17 08:52:42,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 167479 [2024-11-17 08:52:42,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 167479 [2024-11-17 08:52:42,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 167479 states and 225747 transitions. [2024-11-17 08:52:42,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:42,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 167479 states and 225747 transitions. [2024-11-17 08:52:42,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167479 states and 225747 transitions. [2024-11-17 08:52:44,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167479 to 161847. [2024-11-17 08:52:44,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 161847 states, 161847 states have (on average 1.35131945602946) internal successors, (218707), 161846 states have internal predecessors, (218707), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:45,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161847 states to 161847 states and 218707 transitions. [2024-11-17 08:52:45,194 INFO L240 hiAutomatonCegarLoop]: Abstraction has 161847 states and 218707 transitions. [2024-11-17 08:52:45,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:45,195 INFO L425 stractBuchiCegarLoop]: Abstraction has 161847 states and 218707 transitions. [2024-11-17 08:52:45,196 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-17 08:52:45,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 161847 states and 218707 transitions. [2024-11-17 08:52:45,620 INFO L131 ngComponentsAnalysis]: Automaton has 97 accepting balls. 159614 [2024-11-17 08:52:45,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:45,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:45,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:45,622 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:45,622 INFO L745 eck$LassoCheckResult]: Stem: 1714222#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1713428#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1713429#L1028 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1713904#L480-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1713905#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1714125#L492 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1714220#L497 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1713458#L502 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1713459#L507 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1713692#L512 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1713693#L517 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1714185#L523 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1714096#L696-1 assume !(0 == ~M_E~0); 1714097#L701-1 assume !(0 == ~T1_E~0); 1714135#L706-1 assume !(0 == ~T2_E~0); 1713870#L711-1 assume !(0 == ~T3_E~0); 1713615#L716-1 assume !(0 == ~T4_E~0); 1713616#L721-1 assume !(0 == ~T5_E~0); 1713825#L726-1 assume !(0 == ~T6_E~0); 1713826#L731-1 assume !(0 == ~E_M~0); 1713789#L736-1 assume !(0 == ~E_1~0); 1713790#L741-1 assume !(0 == ~E_2~0); 1713877#L746-1 assume !(0 == ~E_3~0); 1713676#L751-1 assume !(0 == ~E_4~0); 1713677#L756-1 assume !(0 == ~E_5~0); 1713606#L761-1 assume !(0 == ~E_6~0); 1713607#L767-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1713856#L346-9 assume !(1 == ~m_pc~0); 1713857#L356-9 is_master_triggered_~__retres1~0#1 := 0; 1713627#L349-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1713502#L358-9 assume true;activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1713503#L861-9 assume !(0 != activate_threads_~tmp~1#1); 1713577#L867-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1713578#L365-9 assume !(1 == ~t1_pc~0); 1713791#L375-9 is_transmit1_triggered_~__retres1~1#1 := 0; 1713742#L368-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1713370#L377-9 assume true;activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1713371#L869-9 assume !(0 != activate_threads_~tmp___0~0#1); 1713989#L875-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1713859#L384-9 assume !(1 == ~t2_pc~0); 1713508#L394-9 is_transmit2_triggered_~__retres1~2#1 := 0; 1713509#L387-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1714183#L396-9 assume true;activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1713538#L877-9 assume !(0 != activate_threads_~tmp___1~0#1); 1713539#L883-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1713383#L403-9 assume !(1 == ~t3_pc~0); 1713384#L413-9 is_transmit3_triggered_~__retres1~3#1 := 0; 1713918#L406-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1713919#L415-9 assume true;activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1714083#L885-9 assume !(0 != activate_threads_~tmp___2~0#1); 1714084#L891-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1713512#L422-9 assume !(1 == ~t4_pc~0); 1713513#L432-9 is_transmit4_triggered_~__retres1~4#1 := 0; 1713363#L425-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1713364#L434-9 assume true;activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1713727#L893-9 assume !(0 != activate_threads_~tmp___3~0#1); 1713697#L899-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1713698#L441-9 assume !(1 == ~t5_pc~0); 1714175#L451-9 is_transmit5_triggered_~__retres1~5#1 := 0; 1714057#L444-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1714058#L453-9 assume true;activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1714113#L901-9 assume !(0 != activate_threads_~tmp___4~0#1); 1714114#L907-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1713445#L460-9 assume !(1 == ~t6_pc~0); 1713446#L470-9 is_transmit6_triggered_~__retres1~6#1 := 0; 1713743#L463-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1713543#L472-9 assume true;activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1713544#L909-9 assume !(0 != activate_threads_~tmp___5~0#1); 1714198#L915-9 assume true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1714204#L774-1 assume !(1 == ~M_E~0); 1714051#L779-1 assume !(1 == ~T1_E~0); 1713734#L784-1 assume !(1 == ~T2_E~0); 1713735#L789-1 assume !(1 == ~T3_E~0); 1713479#L794-1 assume !(1 == ~T4_E~0); 1713480#L799-1 assume !(1 == ~T5_E~0); 1714171#L804-1 assume !(1 == ~T6_E~0); 1714172#L809-1 assume !(1 == ~E_M~0); 1713820#L814-1 assume !(1 == ~E_1~0); 1713378#L819-1 assume !(1 == ~E_2~0); 1713379#L824-1 assume !(1 == ~E_3~0); 1713890#L829-1 assume !(1 == ~E_4~0); 1714042#L834-1 assume !(1 == ~E_5~0); 1713593#L839-1 assume !(1 == ~E_6~0); 1713594#L845-1 assume true;assume { :end_inline_reset_delta_events } true; 1714131#L1065 assume true; 1732230#L1065-1 assume !false; 1732225#start_simulation_while_8_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1732222#L577 [2024-11-17 08:52:45,623 INFO L747 eck$LassoCheckResult]: Loop: 1732222#L577 assume true; 1732220#L577-1 assume !false; 1732218#eval_while_7_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1732215#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1732213#L556-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1732211#L568-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1732209#L582 assume 0 != eval_~tmp~0#1; 1732206#L587-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1732203#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 1732201#L587 havoc eval_~tmp_ndt_1~0#1; 1732194#L601-1 assume !(0 == ~t1_st~0); 1732187#L615-1 assume !(0 == ~t2_st~0); 1732178#L629-1 assume !(0 == ~t3_st~0); 1732171#L643-1 assume !(0 == ~t4_st~0); 1732168#L657-1 assume !(0 == ~t5_st~0); 1732169#L671-1 assume !(0 == ~t6_st~0); 1732222#L577 [2024-11-17 08:52:45,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:45,623 INFO L85 PathProgramCache]: Analyzing trace with hash -1208981592, now seen corresponding path program 1 times [2024-11-17 08:52:45,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:45,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795646829] [2024-11-17 08:52:45,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:45,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:45,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:45,636 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:45,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:45,658 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:45,658 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:45,659 INFO L85 PathProgramCache]: Analyzing trace with hash 1559011581, now seen corresponding path program 1 times [2024-11-17 08:52:45,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:45,659 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436025659] [2024-11-17 08:52:45,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:45,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:45,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:45,663 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:45,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:45,667 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:45,668 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:45,668 INFO L85 PathProgramCache]: Analyzing trace with hash 738122404, now seen corresponding path program 1 times [2024-11-17 08:52:45,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:45,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813376506] [2024-11-17 08:52:45,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:45,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:45,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:45,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:45,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:45,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1813376506] [2024-11-17 08:52:45,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1813376506] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:45,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:45,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:45,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802409226] [2024-11-17 08:52:45,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:45,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:45,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:45,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:45,820 INFO L87 Difference]: Start difference. First operand 161847 states and 218707 transitions. cyclomatic complexity: 56957 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:46,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:46,373 INFO L93 Difference]: Finished difference Result 190414 states and 252942 transitions. [2024-11-17 08:52:46,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190414 states and 252942 transitions. [2024-11-17 08:52:47,951 INFO L131 ngComponentsAnalysis]: Automaton has 98 accepting balls. 187827 [2024-11-17 08:52:48,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190414 states to 190414 states and 252942 transitions. [2024-11-17 08:52:48,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 190414 [2024-11-17 08:52:48,373 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 190414 [2024-11-17 08:52:48,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 190414 states and 252942 transitions. [2024-11-17 08:52:48,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:48,450 INFO L218 hiAutomatonCegarLoop]: Abstraction has 190414 states and 252942 transitions. [2024-11-17 08:52:48,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190414 states and 252942 transitions. [2024-11-17 08:52:50,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190414 to 181342. [2024-11-17 08:52:50,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 181342 states, 181342 states have (on average 1.333689933936981) internal successors, (241854), 181341 states have internal predecessors, (241854), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:50,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 181342 states to 181342 states and 241854 transitions. [2024-11-17 08:52:50,425 INFO L240 hiAutomatonCegarLoop]: Abstraction has 181342 states and 241854 transitions. [2024-11-17 08:52:50,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:50,426 INFO L425 stractBuchiCegarLoop]: Abstraction has 181342 states and 241854 transitions. [2024-11-17 08:52:50,426 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-17 08:52:50,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 181342 states and 241854 transitions.