./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:52:22,782 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:52:22,852 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:52:22,859 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:52:22,862 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:52:22,863 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:52:22,914 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:52:22,915 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:52:22,916 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:52:22,917 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:52:22,918 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:52:22,919 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:52:22,919 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:52:22,919 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:52:22,920 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:52:22,920 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:52:22,920 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:52:22,920 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:52:22,921 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:52:22,921 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:52:22,921 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:52:22,925 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:52:22,926 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:52:22,926 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:52:22,926 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:52:22,926 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:52:22,926 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:52:22,927 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:52:22,927 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:52:22,927 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:52:22,927 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:52:22,927 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:52:22,928 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:52:22,928 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:52:22,928 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:52:22,928 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:52:22,929 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:52:22,929 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:52:22,933 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:52:22,933 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:52:22,934 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2024-11-17 08:52:23,189 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:52:23,215 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:52:23,219 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:52:23,220 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:52:23,224 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:52:23,225 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2024-11-17 08:52:24,639 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:52:24,844 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:52:24,845 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2024-11-17 08:52:24,860 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a88b8b6e9/ff91146c51f2465baef98ac8409b940e/FLAG0fc1e181a [2024-11-17 08:52:25,224 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a88b8b6e9/ff91146c51f2465baef98ac8409b940e [2024-11-17 08:52:25,226 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:52:25,228 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:52:25,231 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:25,231 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:52:25,237 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:52:25,238 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,239 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1ee61d85 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25, skipping insertion in model container [2024-11-17 08:52:25,239 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,278 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:52:25,596 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:25,620 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:52:25,671 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:25,696 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:52:25,696 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25 WrapperNode [2024-11-17 08:52:25,696 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:25,697 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:25,697 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:52:25,697 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:52:25,703 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,713 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,775 INFO L138 Inliner]: procedures = 42, calls = 54, calls flagged for inlining = 49, calls inlined = 137, statements flattened = 2010 [2024-11-17 08:52:25,775 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:25,776 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:52:25,776 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:52:25,776 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:52:25,791 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,791 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,802 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,837 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:52:25,837 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,837 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,864 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,872 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,879 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,886 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,900 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:52:25,902 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:52:25,902 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:52:25,902 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:52:25,903 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (1/1) ... [2024-11-17 08:52:25,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:25,924 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:25,943 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:25,949 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:52:26,024 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:52:26,024 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:52:26,024 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:52:26,024 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:52:26,165 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:52:26,167 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:27,716 INFO L? ?]: Removed 396 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:27,717 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:27,767 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:27,769 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:27,769 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:27 BoogieIcfgContainer [2024-11-17 08:52:27,769 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:27,771 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:27,771 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:27,775 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:27,775 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:27,776 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:52:25" (1/3) ... [2024-11-17 08:52:27,777 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@58288b65 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:27, skipping insertion in model container [2024-11-17 08:52:27,777 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:27,777 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:25" (2/3) ... [2024-11-17 08:52:27,777 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@58288b65 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:27, skipping insertion in model container [2024-11-17 08:52:27,777 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:27,778 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:27" (3/3) ... [2024-11-17 08:52:27,779 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2024-11-17 08:52:27,851 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:27,852 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:27,852 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:27,852 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:27,852 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:27,852 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:27,852 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:27,852 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:27,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 890 states, 889 states have (on average 1.4926884139482566) internal successors, (1327), 889 states have internal predecessors, (1327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:27,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 782 [2024-11-17 08:52:27,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:27,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:27,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:27,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:27,943 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:27,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 890 states, 889 states have (on average 1.4926884139482566) internal successors, (1327), 889 states have internal predecessors, (1327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:27,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 782 [2024-11-17 08:52:27,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:27,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:27,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:27,972 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:27,981 INFO L745 eck$LassoCheckResult]: Stem: 431#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 48#L1153true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 275#L541-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 836#L548true assume 1 == ~m_i~0;~m_st~0 := 0; 169#L553true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 319#L558true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 610#L563true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 659#L568true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 697#L573true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 822#L578true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 75#L583true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 567#L589true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9#L781-1true assume !(0 == ~M_E~0); 881#L786-1true assume !(0 == ~T1_E~0); 20#L791-1true assume !(0 == ~T2_E~0); 383#L796-1true assume !(0 == ~T3_E~0); 359#L801-1true assume !(0 == ~T4_E~0); 387#L806-1true assume !(0 == ~T5_E~0); 805#L811-1true assume !(0 == ~T6_E~0); 144#L816-1true assume 0 == ~T7_E~0;~T7_E~0 := 1; 661#L821-1true assume !(0 == ~E_M~0); 38#L826-1true assume !(0 == ~E_1~0); 354#L831-1true assume !(0 == ~E_2~0); 226#L836-1true assume !(0 == ~E_3~0); 530#L841-1true assume !(0 == ~E_4~0); 117#L846-1true assume !(0 == ~E_5~0); 830#L851-1true assume !(0 == ~E_6~0); 129#L856-1true assume 0 == ~E_7~0;~E_7~0 := 1; 217#L862-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 592#L388-10true assume 1 == ~m_pc~0; 703#L389-10true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 664#L391-10true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 795#L400-10true assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 419#L967-10true assume !(0 != activate_threads_~tmp~1#1); 557#L973-10true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122#L407-10true assume !(1 == ~t1_pc~0); 46#L417-10true is_transmit1_triggered_~__retres1~1#1 := 0; 779#L410-10true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41#L419-10true assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 352#L975-10true assume !(0 != activate_threads_~tmp___0~0#1); 19#L981-10true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 322#L426-10true assume 1 == ~t2_pc~0; 565#L427-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 512#L429-10true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 407#L438-10true assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14#L983-10true assume !(0 != activate_threads_~tmp___1~0#1); 200#L989-10true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 757#L445-10true assume 1 == ~t3_pc~0; 264#L446-10true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 307#L448-10true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 630#L457-10true assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 760#L991-10true assume !(0 != activate_threads_~tmp___2~0#1); 796#L997-10true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 720#L464-10true assume 1 == ~t4_pc~0; 142#L465-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 450#L467-10true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 576#L476-10true assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 240#L999-10true assume !(0 != activate_threads_~tmp___3~0#1); 548#L1005-10true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 848#L483-10true assume !(1 == ~t5_pc~0); 149#L493-10true is_transmit5_triggered_~__retres1~5#1 := 0; 384#L486-10true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180#L495-10true assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 321#L1007-10true assume !(0 != activate_threads_~tmp___4~0#1); 276#L1013-10true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 451#L502-10true assume 1 == ~t6_pc~0; 203#L503-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2#L505-10true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 869#L514-10true assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 489#L1015-10true assume !(0 != activate_threads_~tmp___5~0#1); 680#L1021-10true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 602#L521-10true assume 1 == ~t7_pc~0; 64#L522-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 286#L524-10true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 854#L533-10true assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98#L1023-10true assume !(0 != activate_threads_~tmp___6~0#1); 167#L1029-10true assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103#L869-1true assume !(1 == ~M_E~0); 773#L874-1true assume !(1 == ~T1_E~0); 711#L879-1true assume !(1 == ~T2_E~0); 272#L884-1true assume !(1 == ~T3_E~0); 7#L889-1true assume !(1 == ~T4_E~0); 147#L894-1true assume !(1 == ~T5_E~0); 865#L899-1true assume !(1 == ~T6_E~0); 437#L904-1true assume !(1 == ~T7_E~0); 242#L909-1true assume !(1 == ~E_M~0); 369#L914-1true assume !(1 == ~E_1~0); 393#L919-1true assume !(1 == ~E_2~0); 201#L924-1true assume !(1 == ~E_3~0); 94#L929-1true assume !(1 == ~E_4~0); 734#L934-1true assume !(1 == ~E_5~0); 232#L939-1true assume !(1 == ~E_6~0); 577#L944-1true assume !(1 == ~E_7~0); 53#L950-1true assume true;assume { :end_inline_reset_delta_events } true; 304#L1190true [2024-11-17 08:52:27,987 INFO L747 eck$LassoCheckResult]: Loop: 304#L1190true assume true; 145#L1190-1true assume !false; 429#start_simulation_while_9_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 216#L648true assume !true; 295#L656true assume true; 176#L774true assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 730#L541true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 527#L781true assume 0 == ~M_E~0;~M_E~0 := 1; 459#L786true assume 0 == ~T1_E~0;~T1_E~0 := 1; 245#L791true assume 0 == ~T2_E~0;~T2_E~0 := 1; 287#L796true assume !(0 == ~T3_E~0); 653#L801true assume 0 == ~T4_E~0;~T4_E~0 := 1; 161#L806true assume 0 == ~T5_E~0;~T5_E~0 := 1; 721#L811true assume 0 == ~T6_E~0;~T6_E~0 := 1; 386#L816true assume 0 == ~T7_E~0;~T7_E~0 := 1; 551#L821true assume 0 == ~E_M~0;~E_M~0 := 1; 257#L826true assume 0 == ~E_1~0;~E_1~0 := 1; 405#L831true assume 0 == ~E_2~0;~E_2~0 := 1; 668#L836true assume !(0 == ~E_3~0); 170#L841true assume 0 == ~E_4~0;~E_4~0 := 1; 126#L846true assume 0 == ~E_5~0;~E_5~0 := 1; 851#L851true assume 0 == ~E_6~0;~E_6~0 := 1; 556#L856true assume 0 == ~E_7~0;~E_7~0 := 1; 282#L862true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 413#L388-1true assume !(1 == ~m_pc~0); 686#L398-1true is_master_triggered_~__retres1~0#1 := 0; 777#L391-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160#L400-1true assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 326#L967-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 502#L973-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74#L407-1true assume !(1 == ~t1_pc~0); 430#L417-1true is_transmit1_triggered_~__retres1~1#1 := 0; 313#L410-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 316#L419-1true assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 750#L975-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 473#L981-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 732#L426-1true assume 1 == ~t2_pc~0; 501#L427-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 607#L429-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 591#L438-1true assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 299#L983-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 225#L989-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 361#L445-1true assume 1 == ~t3_pc~0; 850#L446-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 533#L448-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 797#L457-1true assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 151#L991-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 294#L997-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25#L464-1true assume 1 == ~t4_pc~0; 555#L465-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 128#L467-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33#L476-1true assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 164#L999-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 844#L1005-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 737#L483-1true assume !(1 == ~t5_pc~0); 221#L493-1true is_transmit5_triggered_~__retres1~5#1 := 0; 549#L486-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78#L495-1true assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 289#L1007-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100#L1013-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 91#L502-1true assume !(1 == ~t6_pc~0); 72#L512-1true is_transmit6_triggered_~__retres1~6#1 := 0; 495#L505-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 248#L514-1true assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 727#L1015-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 818#L1021-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 397#L521-1true assume 1 == ~t7_pc~0; 458#L522-1true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 480#L524-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 861#L533-1true assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 115#L1023-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 134#L1029-1true assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 486#L869true assume 1 == ~M_E~0;~M_E~0 := 2; 171#L874true assume 1 == ~T1_E~0;~T1_E~0 := 2; 519#L879true assume 1 == ~T2_E~0;~T2_E~0 := 2; 338#L884true assume 1 == ~T3_E~0;~T3_E~0 := 2; 228#L889true assume 1 == ~T4_E~0;~T4_E~0 := 2; 471#L894true assume 1 == ~T5_E~0;~T5_E~0 := 2; 819#L899true assume 1 == ~T6_E~0;~T6_E~0 := 2; 334#L904true assume 1 == ~T7_E~0;~T7_E~0 := 2; 701#L909true assume 1 == ~E_M~0;~E_M~0 := 2; 728#L914true assume 1 == ~E_1~0;~E_1~0 := 2; 173#L919true assume 1 == ~E_2~0;~E_2~0 := 2; 174#L924true assume 1 == ~E_3~0;~E_3~0 := 2; 166#L929true assume 1 == ~E_4~0;~E_4~0 := 2; 293#L934true assume 1 == ~E_5~0;~E_5~0 := 2; 784#L939true assume 1 == ~E_6~0;~E_6~0 := 2; 563#L944true assume 1 == ~E_7~0;~E_7~0 := 2; 251#L950true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 633#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 490#L626-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 260#L639-1true assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 821#L1209true assume !(0 == start_simulation_~tmp~3#1); 111#L1220true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 820#L596true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 162#L626true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 815#L639true assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 641#L1164true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73#L1166true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 172#L1172true assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 140#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 304#L1190true [2024-11-17 08:52:27,996 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:27,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1812237002, now seen corresponding path program 1 times [2024-11-17 08:52:28,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:28,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439760525] [2024-11-17 08:52:28,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:28,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:28,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:28,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:28,331 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:28,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439760525] [2024-11-17 08:52:28,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439760525] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:28,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:28,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:28,334 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737711449] [2024-11-17 08:52:28,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:28,339 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:28,341 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:28,341 INFO L85 PathProgramCache]: Analyzing trace with hash -1233262324, now seen corresponding path program 1 times [2024-11-17 08:52:28,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:28,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1176024527] [2024-11-17 08:52:28,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:28,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:28,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:28,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:28,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:28,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1176024527] [2024-11-17 08:52:28,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1176024527] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:28,408 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:28,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:28,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1978296502] [2024-11-17 08:52:28,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:28,409 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:28,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:28,443 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:28,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:28,447 INFO L87 Difference]: Start difference. First operand has 890 states, 889 states have (on average 1.4926884139482566) internal successors, (1327), 889 states have internal predecessors, (1327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:28,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:28,517 INFO L93 Difference]: Finished difference Result 878 states and 1292 transitions. [2024-11-17 08:52:28,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 878 states and 1292 transitions. [2024-11-17 08:52:28,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:28,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 878 states to 871 states and 1285 transitions. [2024-11-17 08:52:28,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 871 [2024-11-17 08:52:28,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 871 [2024-11-17 08:52:28,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 871 states and 1285 transitions. [2024-11-17 08:52:28,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:28,554 INFO L218 hiAutomatonCegarLoop]: Abstraction has 871 states and 1285 transitions. [2024-11-17 08:52:28,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 871 states and 1285 transitions. [2024-11-17 08:52:28,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 871 to 871. [2024-11-17 08:52:28,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 871 states, 871 states have (on average 1.4753157290470724) internal successors, (1285), 870 states have internal predecessors, (1285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:28,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1285 transitions. [2024-11-17 08:52:28,652 INFO L240 hiAutomatonCegarLoop]: Abstraction has 871 states and 1285 transitions. [2024-11-17 08:52:28,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:28,665 INFO L425 stractBuchiCegarLoop]: Abstraction has 871 states and 1285 transitions. [2024-11-17 08:52:28,665 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:28,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 871 states and 1285 transitions. [2024-11-17 08:52:28,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:28,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:28,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:28,672 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:28,673 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:28,673 INFO L745 eck$LassoCheckResult]: Stem: 2453#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1814#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1815#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1879#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2266#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2106#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2107#L558 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2324#L563 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2575#L568 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2607#L573 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2617#L578 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1936#L583 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1937#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1793#L781-1 assume !(0 == ~M_E~0); 1794#L786-1 assume !(0 == ~T1_E~0); 1818#L791-1 assume !(0 == ~T2_E~0); 1819#L796-1 assume !(0 == ~T3_E~0); 2374#L801-1 assume !(0 == ~T4_E~0); 2375#L806-1 assume !(0 == ~T5_E~0); 2408#L811-1 assume !(0 == ~T6_E~0); 2070#L816-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2071#L821-1 assume !(0 == ~E_M~0); 1858#L826-1 assume !(0 == ~E_1~0); 1859#L831-1 assume !(0 == ~E_2~0); 2189#L836-1 assume !(0 == ~E_3~0); 2190#L841-1 assume !(0 == ~E_4~0); 2019#L846-1 assume !(0 == ~E_5~0); 2020#L851-1 assume !(0 == ~E_6~0); 2043#L856-1 assume 0 == ~E_7~0;~E_7~0 := 1; 2044#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2178#L388-10 assume 1 == ~m_pc~0; 2563#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1833#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2609#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2439#L967-10 assume !(0 != activate_threads_~tmp~1#1); 2440#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2030#L407-10 assume !(1 == ~t1_pc~0); 1875#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 1876#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1864#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1865#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 1816#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1817#L426-10 assume 1 == ~t2_pc~0; 2328#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2288#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2428#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1806#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 1807#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2153#L445-10 assume 1 == ~t3_pc~0; 2252#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2253#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2308#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2591#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 2633#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2625#L464-10 assume 1 == ~t4_pc~0; 2066#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2067#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2472#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2212#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 2213#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2549#L483-10 assume !(1 == ~t5_pc~0); 2081#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 2082#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2120#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2121#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 2267#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2268#L502-10 assume 1 == ~t6_pc~0; 2157#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1777#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1778#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2505#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 2506#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2568#L521-10 assume 1 == ~t7_pc~0; 1916#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1850#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2285#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1983#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 1984#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1993#L869-1 assume !(1 == ~M_E~0); 1994#L874-1 assume !(1 == ~T1_E~0); 2623#L879-1 assume !(1 == ~T2_E~0); 2262#L884-1 assume !(1 == ~T3_E~0); 1788#L889-1 assume !(1 == ~T4_E~0); 1789#L894-1 assume !(1 == ~T5_E~0); 2077#L899-1 assume !(1 == ~T6_E~0); 2457#L904-1 assume !(1 == ~T7_E~0); 2215#L909-1 assume !(1 == ~E_M~0); 2216#L914-1 assume !(1 == ~E_1~0); 2387#L919-1 assume !(1 == ~E_2~0); 2154#L924-1 assume !(1 == ~E_3~0); 1974#L929-1 assume !(1 == ~E_4~0); 1975#L934-1 assume !(1 == ~E_5~0); 2200#L939-1 assume !(1 == ~E_6~0); 2201#L944-1 assume !(1 == ~E_7~0); 1888#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 1889#L1190 [2024-11-17 08:52:28,674 INFO L747 eck$LassoCheckResult]: Loop: 1889#L1190 assume true; 2072#L1190-1 assume !false; 2073#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2076#L648 assume true; 2177#L648-1 assume !false; 2260#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2261#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1960#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2258#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2239#L653 assume !(0 != eval_~tmp~0#1); 2241#L656 assume true; 2115#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2116#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2529#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 2479#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2220#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2221#L796 assume !(0 == ~T3_E~0); 2286#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2098#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2099#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2406#L816 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2407#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 2243#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 2244#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 2426#L836 assume !(0 == ~E_3~0); 2108#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 2038#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 2039#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 2551#L856 assume 0 == ~E_7~0;~E_7~0 := 1; 2279#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2280#L388-1 assume 1 == ~m_pc~0; 2397#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2398#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2096#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2097#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2333#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1933#L407-1 assume 1 == ~t1_pc~0; 1934#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2118#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2316#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2322#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2491#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2492#L426-1 assume !(1 == ~t2_pc~0); 2209#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 2210#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2562#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2302#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2187#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2188#L445-1 assume !(1 == ~t3_pc~0); 1810#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1811#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2533#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2085#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2086#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1829#L464-1 assume 1 == ~t4_pc~0; 1830#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2042#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1847#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1848#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2101#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2629#L483-1 assume 1 == ~t5_pc~0; 2630#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2183#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1942#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1943#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1988#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1968#L502-1 assume 1 == ~t6_pc~0; 1969#L503-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1930#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2224#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2225#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2628#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2418#L521-1 assume !(1 == ~t7_pc~0); 2194#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 2195#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2497#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2015#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2016#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2053#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 2109#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2110#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2349#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2192#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2193#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2489#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2342#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2343#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 2618#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 2111#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 2112#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 2104#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 2105#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 2295#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 2554#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 2231#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2232#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1804#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2246#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2247#L1209 assume !(0 == start_simulation_~tmp~3#1); 2007#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2008#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1902#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2100#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2595#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1931#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1932#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2063#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1889#L1190 [2024-11-17 08:52:28,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:28,675 INFO L85 PathProgramCache]: Analyzing trace with hash 873705387, now seen corresponding path program 1 times [2024-11-17 08:52:28,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:28,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176399737] [2024-11-17 08:52:28,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:28,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:28,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:28,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:28,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:28,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176399737] [2024-11-17 08:52:28,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [176399737] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:28,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:28,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:28,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126560240] [2024-11-17 08:52:28,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:28,804 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:28,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:28,805 INFO L85 PathProgramCache]: Analyzing trace with hash -1645159536, now seen corresponding path program 1 times [2024-11-17 08:52:28,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:28,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428032381] [2024-11-17 08:52:28,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:28,806 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:28,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:28,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:28,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:28,922 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [428032381] [2024-11-17 08:52:28,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [428032381] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:28,922 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:28,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:28,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942652778] [2024-11-17 08:52:28,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:28,923 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:28,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:28,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:28,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:28,926 INFO L87 Difference]: Start difference. First operand 871 states and 1285 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:28,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:28,945 INFO L93 Difference]: Finished difference Result 871 states and 1284 transitions. [2024-11-17 08:52:28,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 871 states and 1284 transitions. [2024-11-17 08:52:28,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:28,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 871 states to 871 states and 1284 transitions. [2024-11-17 08:52:28,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 871 [2024-11-17 08:52:28,956 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 871 [2024-11-17 08:52:28,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 871 states and 1284 transitions. [2024-11-17 08:52:28,958 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:28,958 INFO L218 hiAutomatonCegarLoop]: Abstraction has 871 states and 1284 transitions. [2024-11-17 08:52:28,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 871 states and 1284 transitions. [2024-11-17 08:52:28,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 871 to 871. [2024-11-17 08:52:28,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 871 states, 871 states have (on average 1.4741676234213548) internal successors, (1284), 870 states have internal predecessors, (1284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:28,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1284 transitions. [2024-11-17 08:52:28,977 INFO L240 hiAutomatonCegarLoop]: Abstraction has 871 states and 1284 transitions. [2024-11-17 08:52:28,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:28,979 INFO L425 stractBuchiCegarLoop]: Abstraction has 871 states and 1284 transitions. [2024-11-17 08:52:28,979 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:28,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 871 states and 1284 transitions. [2024-11-17 08:52:28,983 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:28,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:28,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:28,985 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:28,985 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:28,986 INFO L745 eck$LassoCheckResult]: Stem: 4204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3565#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3566#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3630#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4017#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 3857#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3858#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4075#L563 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4326#L568 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4358#L573 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4368#L578 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3687#L583 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3688#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3544#L781-1 assume !(0 == ~M_E~0); 3545#L786-1 assume !(0 == ~T1_E~0); 3569#L791-1 assume !(0 == ~T2_E~0); 3570#L796-1 assume !(0 == ~T3_E~0); 4125#L801-1 assume !(0 == ~T4_E~0); 4126#L806-1 assume !(0 == ~T5_E~0); 4159#L811-1 assume !(0 == ~T6_E~0); 3821#L816-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3822#L821-1 assume !(0 == ~E_M~0); 3609#L826-1 assume !(0 == ~E_1~0); 3610#L831-1 assume !(0 == ~E_2~0); 3940#L836-1 assume !(0 == ~E_3~0); 3941#L841-1 assume !(0 == ~E_4~0); 3770#L846-1 assume !(0 == ~E_5~0); 3771#L851-1 assume !(0 == ~E_6~0); 3794#L856-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3795#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3929#L388-10 assume 1 == ~m_pc~0; 4314#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3584#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4360#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4190#L967-10 assume !(0 != activate_threads_~tmp~1#1); 4191#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3781#L407-10 assume !(1 == ~t1_pc~0); 3626#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 3627#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3615#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3616#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 3567#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3568#L426-10 assume 1 == ~t2_pc~0; 4079#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4039#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4179#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3557#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 3558#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3904#L445-10 assume 1 == ~t3_pc~0; 4003#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4004#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4059#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4342#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 4384#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4376#L464-10 assume 1 == ~t4_pc~0; 3817#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3818#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4223#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3963#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 3964#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4300#L483-10 assume !(1 == ~t5_pc~0); 3832#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 3833#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3871#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3872#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 4018#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4019#L502-10 assume 1 == ~t6_pc~0; 3908#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3528#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3529#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4256#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 4257#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4319#L521-10 assume 1 == ~t7_pc~0; 3667#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3601#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4036#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3734#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 3735#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3744#L869-1 assume !(1 == ~M_E~0); 3745#L874-1 assume !(1 == ~T1_E~0); 4374#L879-1 assume !(1 == ~T2_E~0); 4013#L884-1 assume !(1 == ~T3_E~0); 3539#L889-1 assume !(1 == ~T4_E~0); 3540#L894-1 assume !(1 == ~T5_E~0); 3828#L899-1 assume !(1 == ~T6_E~0); 4208#L904-1 assume !(1 == ~T7_E~0); 3966#L909-1 assume !(1 == ~E_M~0); 3967#L914-1 assume !(1 == ~E_1~0); 4138#L919-1 assume !(1 == ~E_2~0); 3905#L924-1 assume !(1 == ~E_3~0); 3725#L929-1 assume !(1 == ~E_4~0); 3726#L934-1 assume !(1 == ~E_5~0); 3951#L939-1 assume !(1 == ~E_6~0); 3952#L944-1 assume !(1 == ~E_7~0); 3639#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 3640#L1190 [2024-11-17 08:52:28,986 INFO L747 eck$LassoCheckResult]: Loop: 3640#L1190 assume true; 3823#L1190-1 assume !false; 3824#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3827#L648 assume true; 3928#L648-1 assume !false; 4011#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4012#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3711#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4009#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3990#L653 assume !(0 != eval_~tmp~0#1); 3992#L656 assume true; 3866#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3867#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4280#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 4230#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3971#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3972#L796 assume !(0 == ~T3_E~0); 4037#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3849#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3850#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4157#L816 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4158#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 3994#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 3995#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 4177#L836 assume !(0 == ~E_3~0); 3859#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 3789#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 3790#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 4302#L856 assume 0 == ~E_7~0;~E_7~0 := 1; 4030#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4031#L388-1 assume 1 == ~m_pc~0; 4148#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4149#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3847#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3848#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4084#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3684#L407-1 assume 1 == ~t1_pc~0; 3685#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3869#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4067#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4073#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4242#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4243#L426-1 assume 1 == ~t2_pc~0; 4262#L427-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3961#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4313#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4053#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3938#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3939#L445-1 assume 1 == ~t3_pc~0; 4128#L446-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3562#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4284#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3836#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3837#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3580#L464-1 assume 1 == ~t4_pc~0; 3581#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3793#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3598#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3599#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3852#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4380#L483-1 assume 1 == ~t5_pc~0; 4381#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3934#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3693#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3694#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3739#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3719#L502-1 assume !(1 == ~t6_pc~0); 3680#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 3681#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3975#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3976#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4379#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4169#L521-1 assume !(1 == ~t7_pc~0); 3945#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 3946#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4248#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3766#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3767#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3804#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 3860#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3861#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4100#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3943#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3944#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4240#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4093#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4094#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 4369#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 3862#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 3863#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 3855#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 3856#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 4046#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 4305#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 3982#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3983#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3555#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3997#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 3998#L1209 assume !(0 == start_simulation_~tmp~3#1); 3758#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3759#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3653#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3851#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 4346#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3682#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3683#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 3814#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 3640#L1190 [2024-11-17 08:52:28,987 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:28,987 INFO L85 PathProgramCache]: Analyzing trace with hash 1259072170, now seen corresponding path program 1 times [2024-11-17 08:52:28,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:28,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47260742] [2024-11-17 08:52:28,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:28,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47260742] [2024-11-17 08:52:29,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [47260742] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,036 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:29,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393512126] [2024-11-17 08:52:29,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,037 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:29,037 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,038 INFO L85 PathProgramCache]: Analyzing trace with hash 880547341, now seen corresponding path program 1 times [2024-11-17 08:52:29,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803151494] [2024-11-17 08:52:29,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803151494] [2024-11-17 08:52:29,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803151494] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:29,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308408697] [2024-11-17 08:52:29,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,162 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:29,163 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:29,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:29,163 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:29,163 INFO L87 Difference]: Start difference. First operand 871 states and 1284 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:29,183 INFO L93 Difference]: Finished difference Result 871 states and 1283 transitions. [2024-11-17 08:52:29,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 871 states and 1283 transitions. [2024-11-17 08:52:29,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 871 states to 871 states and 1283 transitions. [2024-11-17 08:52:29,193 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 871 [2024-11-17 08:52:29,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 871 [2024-11-17 08:52:29,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 871 states and 1283 transitions. [2024-11-17 08:52:29,195 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:29,195 INFO L218 hiAutomatonCegarLoop]: Abstraction has 871 states and 1283 transitions. [2024-11-17 08:52:29,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 871 states and 1283 transitions. [2024-11-17 08:52:29,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 871 to 871. [2024-11-17 08:52:29,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 871 states, 871 states have (on average 1.4730195177956371) internal successors, (1283), 870 states have internal predecessors, (1283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1283 transitions. [2024-11-17 08:52:29,210 INFO L240 hiAutomatonCegarLoop]: Abstraction has 871 states and 1283 transitions. [2024-11-17 08:52:29,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:29,212 INFO L425 stractBuchiCegarLoop]: Abstraction has 871 states and 1283 transitions. [2024-11-17 08:52:29,212 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:29,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 871 states and 1283 transitions. [2024-11-17 08:52:29,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:29,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:29,219 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,219 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,221 INFO L745 eck$LassoCheckResult]: Stem: 5955#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5316#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5317#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5381#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5768#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5608#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5609#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5826#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6077#L568 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6109#L573 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6119#L578 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5438#L583 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5439#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5295#L781-1 assume !(0 == ~M_E~0); 5296#L786-1 assume !(0 == ~T1_E~0); 5320#L791-1 assume !(0 == ~T2_E~0); 5321#L796-1 assume !(0 == ~T3_E~0); 5876#L801-1 assume !(0 == ~T4_E~0); 5877#L806-1 assume !(0 == ~T5_E~0); 5910#L811-1 assume !(0 == ~T6_E~0); 5572#L816-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5573#L821-1 assume !(0 == ~E_M~0); 5360#L826-1 assume !(0 == ~E_1~0); 5361#L831-1 assume !(0 == ~E_2~0); 5691#L836-1 assume !(0 == ~E_3~0); 5692#L841-1 assume !(0 == ~E_4~0); 5521#L846-1 assume !(0 == ~E_5~0); 5522#L851-1 assume !(0 == ~E_6~0); 5545#L856-1 assume 0 == ~E_7~0;~E_7~0 := 1; 5546#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5680#L388-10 assume 1 == ~m_pc~0; 6065#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5335#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6111#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5941#L967-10 assume !(0 != activate_threads_~tmp~1#1); 5942#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5532#L407-10 assume !(1 == ~t1_pc~0); 5377#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 5378#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5366#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5367#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 5318#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5319#L426-10 assume 1 == ~t2_pc~0; 5830#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5790#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5930#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5308#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 5309#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5655#L445-10 assume 1 == ~t3_pc~0; 5754#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5755#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5810#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6093#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 6135#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6127#L464-10 assume 1 == ~t4_pc~0; 5568#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5569#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5974#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5714#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 5715#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6051#L483-10 assume !(1 == ~t5_pc~0); 5583#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 5584#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5622#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5623#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 5769#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5770#L502-10 assume 1 == ~t6_pc~0; 5659#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5279#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5280#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6007#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 6008#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6070#L521-10 assume 1 == ~t7_pc~0; 5418#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5352#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5787#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5485#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 5486#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5495#L869-1 assume !(1 == ~M_E~0); 5496#L874-1 assume !(1 == ~T1_E~0); 6125#L879-1 assume !(1 == ~T2_E~0); 5764#L884-1 assume !(1 == ~T3_E~0); 5290#L889-1 assume !(1 == ~T4_E~0); 5291#L894-1 assume !(1 == ~T5_E~0); 5579#L899-1 assume !(1 == ~T6_E~0); 5959#L904-1 assume !(1 == ~T7_E~0); 5717#L909-1 assume !(1 == ~E_M~0); 5718#L914-1 assume !(1 == ~E_1~0); 5889#L919-1 assume !(1 == ~E_2~0); 5656#L924-1 assume !(1 == ~E_3~0); 5476#L929-1 assume !(1 == ~E_4~0); 5477#L934-1 assume !(1 == ~E_5~0); 5702#L939-1 assume !(1 == ~E_6~0); 5703#L944-1 assume !(1 == ~E_7~0); 5390#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 5391#L1190 [2024-11-17 08:52:29,221 INFO L747 eck$LassoCheckResult]: Loop: 5391#L1190 assume true; 5574#L1190-1 assume !false; 5575#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5578#L648 assume true; 5679#L648-1 assume !false; 5762#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5763#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5462#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5760#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5741#L653 assume !(0 != eval_~tmp~0#1); 5743#L656 assume true; 5617#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5618#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6031#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 5981#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5722#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5723#L796 assume !(0 == ~T3_E~0); 5788#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5600#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5601#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5908#L816 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5909#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 5745#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 5746#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 5928#L836 assume !(0 == ~E_3~0); 5610#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 5540#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 5541#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 6053#L856 assume 0 == ~E_7~0;~E_7~0 := 1; 5781#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5782#L388-1 assume 1 == ~m_pc~0; 5899#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5900#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5598#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5599#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5835#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5435#L407-1 assume 1 == ~t1_pc~0; 5436#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5620#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5818#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5824#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5993#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5994#L426-1 assume 1 == ~t2_pc~0; 6013#L427-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5712#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6064#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5804#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5689#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5690#L445-1 assume !(1 == ~t3_pc~0); 5312#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 5313#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6035#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5587#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5588#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5331#L464-1 assume 1 == ~t4_pc~0; 5332#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5544#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5349#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5350#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5603#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6131#L483-1 assume 1 == ~t5_pc~0; 6132#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5685#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5444#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5445#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5490#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5470#L502-1 assume !(1 == ~t6_pc~0); 5431#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 5432#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5726#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5727#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6130#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5920#L521-1 assume !(1 == ~t7_pc~0); 5696#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 5697#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5999#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5517#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5518#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5555#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 5611#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5612#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5851#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5694#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5695#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5991#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5844#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5845#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 6120#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 5613#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 5614#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 5606#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 5607#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 5797#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 6056#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 5733#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5734#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5306#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5748#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5749#L1209 assume !(0 == start_simulation_~tmp~3#1); 5509#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5510#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5404#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5602#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6097#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5433#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5434#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5565#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5391#L1190 [2024-11-17 08:52:29,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,222 INFO L85 PathProgramCache]: Analyzing trace with hash -391064629, now seen corresponding path program 1 times [2024-11-17 08:52:29,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617465210] [2024-11-17 08:52:29,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,285 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617465210] [2024-11-17 08:52:29,285 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617465210] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,285 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:29,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445090348] [2024-11-17 08:52:29,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,286 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:29,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,287 INFO L85 PathProgramCache]: Analyzing trace with hash 727168144, now seen corresponding path program 1 times [2024-11-17 08:52:29,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359519837] [2024-11-17 08:52:29,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [359519837] [2024-11-17 08:52:29,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [359519837] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,383 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,383 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:29,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175390270] [2024-11-17 08:52:29,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,384 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:29,384 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:29,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:29,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:29,385 INFO L87 Difference]: Start difference. First operand 871 states and 1283 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:29,401 INFO L93 Difference]: Finished difference Result 871 states and 1282 transitions. [2024-11-17 08:52:29,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 871 states and 1282 transitions. [2024-11-17 08:52:29,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 871 states to 871 states and 1282 transitions. [2024-11-17 08:52:29,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 871 [2024-11-17 08:52:29,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 871 [2024-11-17 08:52:29,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 871 states and 1282 transitions. [2024-11-17 08:52:29,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:29,413 INFO L218 hiAutomatonCegarLoop]: Abstraction has 871 states and 1282 transitions. [2024-11-17 08:52:29,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 871 states and 1282 transitions. [2024-11-17 08:52:29,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 871 to 871. [2024-11-17 08:52:29,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 871 states, 871 states have (on average 1.4718714121699197) internal successors, (1282), 870 states have internal predecessors, (1282), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1282 transitions. [2024-11-17 08:52:29,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 871 states and 1282 transitions. [2024-11-17 08:52:29,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:29,432 INFO L425 stractBuchiCegarLoop]: Abstraction has 871 states and 1282 transitions. [2024-11-17 08:52:29,432 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:29,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 871 states and 1282 transitions. [2024-11-17 08:52:29,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:29,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:29,440 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,440 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,441 INFO L745 eck$LassoCheckResult]: Stem: 7706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7067#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7068#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7132#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7519#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 7359#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7360#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7577#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7828#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7860#L573 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7870#L578 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7189#L583 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7190#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7046#L781-1 assume !(0 == ~M_E~0); 7047#L786-1 assume !(0 == ~T1_E~0); 7071#L791-1 assume !(0 == ~T2_E~0); 7072#L796-1 assume !(0 == ~T3_E~0); 7627#L801-1 assume !(0 == ~T4_E~0); 7628#L806-1 assume !(0 == ~T5_E~0); 7661#L811-1 assume !(0 == ~T6_E~0); 7323#L816-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7324#L821-1 assume !(0 == ~E_M~0); 7111#L826-1 assume !(0 == ~E_1~0); 7112#L831-1 assume !(0 == ~E_2~0); 7442#L836-1 assume !(0 == ~E_3~0); 7443#L841-1 assume !(0 == ~E_4~0); 7272#L846-1 assume !(0 == ~E_5~0); 7273#L851-1 assume !(0 == ~E_6~0); 7296#L856-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7297#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7431#L388-10 assume 1 == ~m_pc~0; 7816#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7086#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7862#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7692#L967-10 assume !(0 != activate_threads_~tmp~1#1); 7693#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7283#L407-10 assume !(1 == ~t1_pc~0); 7128#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 7129#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7117#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7118#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 7069#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7070#L426-10 assume 1 == ~t2_pc~0; 7581#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7541#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7681#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7059#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 7060#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7406#L445-10 assume 1 == ~t3_pc~0; 7505#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7506#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7561#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7844#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 7886#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7878#L464-10 assume 1 == ~t4_pc~0; 7319#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7320#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7725#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7465#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 7466#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7802#L483-10 assume !(1 == ~t5_pc~0); 7334#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 7335#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7373#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7374#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 7520#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7521#L502-10 assume 1 == ~t6_pc~0; 7410#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7030#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7031#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7758#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 7759#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7821#L521-10 assume 1 == ~t7_pc~0; 7169#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7103#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7538#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7236#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 7237#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7246#L869-1 assume !(1 == ~M_E~0); 7247#L874-1 assume !(1 == ~T1_E~0); 7876#L879-1 assume !(1 == ~T2_E~0); 7515#L884-1 assume !(1 == ~T3_E~0); 7041#L889-1 assume !(1 == ~T4_E~0); 7042#L894-1 assume !(1 == ~T5_E~0); 7330#L899-1 assume !(1 == ~T6_E~0); 7710#L904-1 assume !(1 == ~T7_E~0); 7468#L909-1 assume !(1 == ~E_M~0); 7469#L914-1 assume !(1 == ~E_1~0); 7640#L919-1 assume !(1 == ~E_2~0); 7407#L924-1 assume !(1 == ~E_3~0); 7227#L929-1 assume !(1 == ~E_4~0); 7228#L934-1 assume !(1 == ~E_5~0); 7453#L939-1 assume !(1 == ~E_6~0); 7454#L944-1 assume !(1 == ~E_7~0); 7141#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 7142#L1190 [2024-11-17 08:52:29,444 INFO L747 eck$LassoCheckResult]: Loop: 7142#L1190 assume true; 7325#L1190-1 assume !false; 7326#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7329#L648 assume true; 7430#L648-1 assume !false; 7513#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7514#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7213#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7511#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7492#L653 assume !(0 != eval_~tmp~0#1); 7494#L656 assume true; 7368#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7369#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7782#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 7732#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7473#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7474#L796 assume !(0 == ~T3_E~0); 7539#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7351#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7352#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7659#L816 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7660#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 7496#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 7497#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 7679#L836 assume !(0 == ~E_3~0); 7361#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 7291#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 7292#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 7804#L856 assume 0 == ~E_7~0;~E_7~0 := 1; 7532#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7533#L388-1 assume 1 == ~m_pc~0; 7650#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7651#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7349#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7350#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7586#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7186#L407-1 assume 1 == ~t1_pc~0; 7187#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7371#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7569#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7575#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7744#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7745#L426-1 assume 1 == ~t2_pc~0; 7764#L427-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7463#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7815#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7555#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7440#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7441#L445-1 assume !(1 == ~t3_pc~0); 7063#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 7064#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7786#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7338#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7339#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7082#L464-1 assume 1 == ~t4_pc~0; 7083#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7295#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7100#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7101#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7354#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7882#L483-1 assume 1 == ~t5_pc~0; 7883#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7436#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7195#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7196#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7241#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7221#L502-1 assume 1 == ~t6_pc~0; 7222#L503-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7183#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7477#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7478#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7881#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7671#L521-1 assume !(1 == ~t7_pc~0); 7447#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 7448#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7750#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7268#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7269#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7306#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 7362#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7363#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7602#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7445#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7446#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7742#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7595#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7596#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 7871#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 7364#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 7365#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 7357#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 7358#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 7548#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 7807#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 7484#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7485#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7057#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7499#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7500#L1209 assume !(0 == start_simulation_~tmp~3#1); 7260#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 7261#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7155#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7353#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 7848#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7184#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7185#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 7316#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 7142#L1190 [2024-11-17 08:52:29,445 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,445 INFO L85 PathProgramCache]: Analyzing trace with hash 2049557130, now seen corresponding path program 1 times [2024-11-17 08:52:29,445 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132520426] [2024-11-17 08:52:29,445 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2132520426] [2024-11-17 08:52:29,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2132520426] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,490 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,490 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:29,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589925286] [2024-11-17 08:52:29,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,490 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:29,491 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,491 INFO L85 PathProgramCache]: Analyzing trace with hash 1291021133, now seen corresponding path program 1 times [2024-11-17 08:52:29,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1370125419] [2024-11-17 08:52:29,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,564 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1370125419] [2024-11-17 08:52:29,564 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1370125419] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,564 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:29,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417531125] [2024-11-17 08:52:29,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,566 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:29,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:29,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:29,567 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:29,567 INFO L87 Difference]: Start difference. First operand 871 states and 1282 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:29,583 INFO L93 Difference]: Finished difference Result 871 states and 1281 transitions. [2024-11-17 08:52:29,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 871 states and 1281 transitions. [2024-11-17 08:52:29,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 871 states to 871 states and 1281 transitions. [2024-11-17 08:52:29,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 871 [2024-11-17 08:52:29,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 871 [2024-11-17 08:52:29,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 871 states and 1281 transitions. [2024-11-17 08:52:29,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:29,595 INFO L218 hiAutomatonCegarLoop]: Abstraction has 871 states and 1281 transitions. [2024-11-17 08:52:29,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 871 states and 1281 transitions. [2024-11-17 08:52:29,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 871 to 871. [2024-11-17 08:52:29,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 871 states, 871 states have (on average 1.470723306544202) internal successors, (1281), 870 states have internal predecessors, (1281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1281 transitions. [2024-11-17 08:52:29,609 INFO L240 hiAutomatonCegarLoop]: Abstraction has 871 states and 1281 transitions. [2024-11-17 08:52:29,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:29,611 INFO L425 stractBuchiCegarLoop]: Abstraction has 871 states and 1281 transitions. [2024-11-17 08:52:29,612 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:29,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 871 states and 1281 transitions. [2024-11-17 08:52:29,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:29,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:29,617 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,617 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,619 INFO L745 eck$LassoCheckResult]: Stem: 9457#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8818#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8819#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8883#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9270#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 9110#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9111#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9328#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9579#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9611#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9621#L578 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8942#L583 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8943#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8797#L781-1 assume !(0 == ~M_E~0); 8798#L786-1 assume !(0 == ~T1_E~0); 8822#L791-1 assume !(0 == ~T2_E~0); 8823#L796-1 assume !(0 == ~T3_E~0); 9379#L801-1 assume !(0 == ~T4_E~0); 9380#L806-1 assume !(0 == ~T5_E~0); 9412#L811-1 assume !(0 == ~T6_E~0); 9074#L816-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9075#L821-1 assume !(0 == ~E_M~0); 8862#L826-1 assume !(0 == ~E_1~0); 8863#L831-1 assume !(0 == ~E_2~0); 9193#L836-1 assume !(0 == ~E_3~0); 9194#L841-1 assume !(0 == ~E_4~0); 9025#L846-1 assume !(0 == ~E_5~0); 9026#L851-1 assume !(0 == ~E_6~0); 9047#L856-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9048#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9182#L388-10 assume 1 == ~m_pc~0; 9568#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8839#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9613#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9443#L967-10 assume !(0 != activate_threads_~tmp~1#1); 9444#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9034#L407-10 assume !(1 == ~t1_pc~0); 8881#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 8882#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8871#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8872#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 8820#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8821#L426-10 assume 1 == ~t2_pc~0; 9332#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9292#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9432#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8812#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 8813#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9157#L445-10 assume 1 == ~t3_pc~0; 9257#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9258#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9312#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9595#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 9637#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9630#L464-10 assume 1 == ~t4_pc~0; 9070#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9071#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9476#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9216#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 9217#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9553#L483-10 assume !(1 == ~t5_pc~0); 9085#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 9086#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9124#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9125#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 9271#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9272#L502-10 assume 1 == ~t6_pc~0; 9161#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8781#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8782#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9509#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 9510#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9572#L521-10 assume 1 == ~t7_pc~0; 8920#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8854#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9289#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8990#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 8991#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8999#L869-1 assume !(1 == ~M_E~0); 9000#L874-1 assume !(1 == ~T1_E~0); 9628#L879-1 assume !(1 == ~T2_E~0); 9266#L884-1 assume !(1 == ~T3_E~0); 8792#L889-1 assume !(1 == ~T4_E~0); 8793#L894-1 assume !(1 == ~T5_E~0); 9084#L899-1 assume !(1 == ~T6_E~0); 9461#L904-1 assume !(1 == ~T7_E~0); 9221#L909-1 assume !(1 == ~E_M~0); 9222#L914-1 assume !(1 == ~E_1~0); 9391#L919-1 assume !(1 == ~E_2~0); 9158#L924-1 assume !(1 == ~E_3~0); 8978#L929-1 assume !(1 == ~E_4~0); 8979#L934-1 assume !(1 == ~E_5~0); 9205#L939-1 assume !(1 == ~E_6~0); 9206#L944-1 assume !(1 == ~E_7~0); 8892#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 8893#L1190 [2024-11-17 08:52:29,619 INFO L747 eck$LassoCheckResult]: Loop: 8893#L1190 assume true; 9076#L1190-1 assume !false; 9077#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9080#L648 assume true; 9181#L648-1 assume !false; 9264#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9265#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8964#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9262#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9243#L653 assume !(0 != eval_~tmp~0#1); 9245#L656 assume true; 9119#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9120#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9533#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 9483#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9224#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9225#L796 assume !(0 == ~T3_E~0); 9290#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9103#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9104#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9410#L816 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9411#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 9247#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 9248#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 9430#L836 assume !(0 == ~E_3~0); 9112#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 9042#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 9043#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 9555#L856 assume 0 == ~E_7~0;~E_7~0 := 1; 9283#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9284#L388-1 assume 1 == ~m_pc~0; 9401#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9402#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9100#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9101#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9337#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8937#L407-1 assume 1 == ~t1_pc~0; 8938#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9122#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9320#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9326#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9495#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9496#L426-1 assume 1 == ~t2_pc~0; 9515#L427-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9214#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9566#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9306#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9191#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9192#L445-1 assume 1 == ~t3_pc~0; 9381#L446-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8815#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9537#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9089#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9090#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8833#L464-1 assume 1 == ~t4_pc~0; 8834#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9046#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8851#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8852#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9105#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9633#L483-1 assume 1 == ~t5_pc~0; 9634#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9187#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8946#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8947#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8992#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8972#L502-1 assume !(1 == ~t6_pc~0); 8933#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 8934#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9227#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9228#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9632#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9422#L521-1 assume !(1 == ~t7_pc~0); 9198#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 9199#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9501#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9019#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9020#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9057#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 9113#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9114#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9353#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9196#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9197#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9493#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9346#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9347#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 9622#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 9115#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 9116#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 9108#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 9109#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 9299#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 9558#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 9235#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9236#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8808#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9250#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9251#L1209 assume !(0 == start_simulation_~tmp~3#1); 9011#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9012#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8906#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9102#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 9599#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8935#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8936#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9065#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8893#L1190 [2024-11-17 08:52:29,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,620 INFO L85 PathProgramCache]: Analyzing trace with hash 881360875, now seen corresponding path program 1 times [2024-11-17 08:52:29,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518034598] [2024-11-17 08:52:29,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518034598] [2024-11-17 08:52:29,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518034598] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,665 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:29,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208010054] [2024-11-17 08:52:29,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,665 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:29,666 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,666 INFO L85 PathProgramCache]: Analyzing trace with hash 880547341, now seen corresponding path program 2 times [2024-11-17 08:52:29,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381132597] [2024-11-17 08:52:29,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381132597] [2024-11-17 08:52:29,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381132597] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:29,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515655399] [2024-11-17 08:52:29,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,738 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:29,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:29,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:29,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:29,740 INFO L87 Difference]: Start difference. First operand 871 states and 1281 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:29,756 INFO L93 Difference]: Finished difference Result 871 states and 1280 transitions. [2024-11-17 08:52:29,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 871 states and 1280 transitions. [2024-11-17 08:52:29,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 871 states to 871 states and 1280 transitions. [2024-11-17 08:52:29,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 871 [2024-11-17 08:52:29,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 871 [2024-11-17 08:52:29,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 871 states and 1280 transitions. [2024-11-17 08:52:29,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:29,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 871 states and 1280 transitions. [2024-11-17 08:52:29,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 871 states and 1280 transitions. [2024-11-17 08:52:29,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 871 to 871. [2024-11-17 08:52:29,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 871 states, 871 states have (on average 1.4695752009184846) internal successors, (1280), 870 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1280 transitions. [2024-11-17 08:52:29,782 INFO L240 hiAutomatonCegarLoop]: Abstraction has 871 states and 1280 transitions. [2024-11-17 08:52:29,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:29,786 INFO L425 stractBuchiCegarLoop]: Abstraction has 871 states and 1280 transitions. [2024-11-17 08:52:29,786 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:52:29,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 871 states and 1280 transitions. [2024-11-17 08:52:29,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,791 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:29,791 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:29,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,794 INFO L745 eck$LassoCheckResult]: Stem: 11208#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10569#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10570#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10634#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11021#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 10861#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10862#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11079#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11330#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11362#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11372#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10691#L583 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10692#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10548#L781-1 assume !(0 == ~M_E~0); 10549#L786-1 assume !(0 == ~T1_E~0); 10573#L791-1 assume !(0 == ~T2_E~0); 10574#L796-1 assume !(0 == ~T3_E~0); 11130#L801-1 assume !(0 == ~T4_E~0); 11131#L806-1 assume !(0 == ~T5_E~0); 11163#L811-1 assume !(0 == ~T6_E~0); 10825#L816-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10826#L821-1 assume !(0 == ~E_M~0); 10613#L826-1 assume !(0 == ~E_1~0); 10614#L831-1 assume !(0 == ~E_2~0); 10944#L836-1 assume !(0 == ~E_3~0); 10945#L841-1 assume !(0 == ~E_4~0); 10776#L846-1 assume !(0 == ~E_5~0); 10777#L851-1 assume !(0 == ~E_6~0); 10798#L856-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10799#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10933#L388-10 assume 1 == ~m_pc~0; 11319#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10588#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11364#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11194#L967-10 assume !(0 != activate_threads_~tmp~1#1); 11195#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10785#L407-10 assume !(1 == ~t1_pc~0); 10632#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 10633#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10619#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10620#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 10571#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10572#L426-10 assume 1 == ~t2_pc~0; 11083#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11043#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11183#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10561#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 10562#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10908#L445-10 assume 1 == ~t3_pc~0; 11007#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11008#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11063#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11346#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 11388#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11381#L464-10 assume 1 == ~t4_pc~0; 10821#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10822#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11227#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10967#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 10968#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11304#L483-10 assume !(1 == ~t5_pc~0); 10836#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 10837#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10875#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10876#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 11022#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11023#L502-10 assume 1 == ~t6_pc~0; 10912#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10532#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10533#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11260#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 11261#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11323#L521-10 assume 1 == ~t7_pc~0; 10671#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10605#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11040#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10741#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 10742#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10750#L869-1 assume !(1 == ~M_E~0); 10751#L874-1 assume !(1 == ~T1_E~0); 11379#L879-1 assume !(1 == ~T2_E~0); 11017#L884-1 assume !(1 == ~T3_E~0); 10543#L889-1 assume !(1 == ~T4_E~0); 10544#L894-1 assume !(1 == ~T5_E~0); 10832#L899-1 assume !(1 == ~T6_E~0); 11212#L904-1 assume !(1 == ~T7_E~0); 10970#L909-1 assume !(1 == ~E_M~0); 10971#L914-1 assume !(1 == ~E_1~0); 11142#L919-1 assume !(1 == ~E_2~0); 10909#L924-1 assume !(1 == ~E_3~0); 10729#L929-1 assume !(1 == ~E_4~0); 10730#L934-1 assume !(1 == ~E_5~0); 10956#L939-1 assume !(1 == ~E_6~0); 10957#L944-1 assume !(1 == ~E_7~0); 10643#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 10644#L1190 [2024-11-17 08:52:29,794 INFO L747 eck$LassoCheckResult]: Loop: 10644#L1190 assume true; 10827#L1190-1 assume !false; 10828#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10831#L648 assume true; 10932#L648-1 assume !false; 11015#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11016#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10715#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11013#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10994#L653 assume !(0 != eval_~tmp~0#1); 10996#L656 assume true; 10870#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10871#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11284#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 11234#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10975#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10976#L796 assume !(0 == ~T3_E~0); 11041#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10854#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10855#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11161#L816 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11162#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 10998#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 10999#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 11181#L836 assume !(0 == ~E_3~0); 10863#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 10795#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 10796#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 11306#L856 assume 0 == ~E_7~0;~E_7~0 := 1; 11034#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11035#L388-1 assume 1 == ~m_pc~0; 11152#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11153#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10851#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10852#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11088#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10688#L407-1 assume 1 == ~t1_pc~0; 10689#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10874#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11071#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11077#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11246#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11247#L426-1 assume 1 == ~t2_pc~0; 11266#L427-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10965#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11317#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11057#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10942#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10943#L445-1 assume !(1 == ~t3_pc~0); 10565#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 10566#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11288#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10840#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10841#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10584#L464-1 assume 1 == ~t4_pc~0; 10585#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10797#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10602#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10603#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10856#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11384#L483-1 assume 1 == ~t5_pc~0; 11385#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10938#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10697#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10698#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10743#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10723#L502-1 assume 1 == ~t6_pc~0; 10724#L503-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10685#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10978#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10979#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11383#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11173#L521-1 assume !(1 == ~t7_pc~0); 10949#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 10950#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11252#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10770#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10771#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10808#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 10864#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10865#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11104#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10947#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10948#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11244#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11095#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11096#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 11373#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 10866#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 10867#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 10859#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 10860#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 11050#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 11309#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 10986#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10987#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10559#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11000#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11001#L1209 assume !(0 == start_simulation_~tmp~3#1); 10762#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 10763#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10655#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10853#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11350#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10686#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10687#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 10816#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 10644#L1190 [2024-11-17 08:52:29,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,796 INFO L85 PathProgramCache]: Analyzing trace with hash 2090603114, now seen corresponding path program 1 times [2024-11-17 08:52:29,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520487936] [2024-11-17 08:52:29,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,835 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520487936] [2024-11-17 08:52:29,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520487936] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,835 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,835 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:29,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52432079] [2024-11-17 08:52:29,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,836 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:29,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,836 INFO L85 PathProgramCache]: Analyzing trace with hash 1291021133, now seen corresponding path program 2 times [2024-11-17 08:52:29,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734358727] [2024-11-17 08:52:29,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:29,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:29,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:29,929 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:29,930 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734358727] [2024-11-17 08:52:29,930 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734358727] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:29,930 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:29,930 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:29,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519155940] [2024-11-17 08:52:29,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:29,931 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:29,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:29,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:29,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:29,932 INFO L87 Difference]: Start difference. First operand 871 states and 1280 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:29,951 INFO L93 Difference]: Finished difference Result 871 states and 1279 transitions. [2024-11-17 08:52:29,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 871 states and 1279 transitions. [2024-11-17 08:52:29,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 871 states to 871 states and 1279 transitions. [2024-11-17 08:52:29,961 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 871 [2024-11-17 08:52:29,962 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 871 [2024-11-17 08:52:29,962 INFO L73 IsDeterministic]: Start isDeterministic. Operand 871 states and 1279 transitions. [2024-11-17 08:52:29,963 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:29,963 INFO L218 hiAutomatonCegarLoop]: Abstraction has 871 states and 1279 transitions. [2024-11-17 08:52:29,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 871 states and 1279 transitions. [2024-11-17 08:52:29,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 871 to 871. [2024-11-17 08:52:29,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 871 states, 871 states have (on average 1.468427095292767) internal successors, (1279), 870 states have internal predecessors, (1279), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:29,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 871 states to 871 states and 1279 transitions. [2024-11-17 08:52:29,980 INFO L240 hiAutomatonCegarLoop]: Abstraction has 871 states and 1279 transitions. [2024-11-17 08:52:29,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:29,983 INFO L425 stractBuchiCegarLoop]: Abstraction has 871 states and 1279 transitions. [2024-11-17 08:52:29,983 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:52:29,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 871 states and 1279 transitions. [2024-11-17 08:52:29,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 768 [2024-11-17 08:52:29,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:29,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:29,989 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,989 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:29,989 INFO L745 eck$LassoCheckResult]: Stem: 12959#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12320#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12321#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12385#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12772#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12612#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12613#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12830#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13081#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13113#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13123#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12442#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12443#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12299#L781-1 assume !(0 == ~M_E~0); 12300#L786-1 assume !(0 == ~T1_E~0); 12324#L791-1 assume !(0 == ~T2_E~0); 12325#L796-1 assume !(0 == ~T3_E~0); 12880#L801-1 assume !(0 == ~T4_E~0); 12881#L806-1 assume !(0 == ~T5_E~0); 12914#L811-1 assume !(0 == ~T6_E~0); 12576#L816-1 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12577#L821-1 assume !(0 == ~E_M~0); 12364#L826-1 assume !(0 == ~E_1~0); 12365#L831-1 assume !(0 == ~E_2~0); 12695#L836-1 assume !(0 == ~E_3~0); 12696#L841-1 assume !(0 == ~E_4~0); 12525#L846-1 assume !(0 == ~E_5~0); 12526#L851-1 assume !(0 == ~E_6~0); 12549#L856-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12550#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12684#L388-10 assume 1 == ~m_pc~0; 13069#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12339#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13115#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12945#L967-10 assume !(0 != activate_threads_~tmp~1#1); 12946#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12536#L407-10 assume !(1 == ~t1_pc~0); 12381#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 12382#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12370#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12371#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 12322#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12323#L426-10 assume 1 == ~t2_pc~0; 12834#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12794#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12934#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12312#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 12313#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12659#L445-10 assume 1 == ~t3_pc~0; 12758#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12759#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12814#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13097#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 13139#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13131#L464-10 assume 1 == ~t4_pc~0; 12572#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12573#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12978#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12718#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 12719#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13055#L483-10 assume !(1 == ~t5_pc~0); 12587#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 12588#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12626#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12627#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 12773#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12774#L502-10 assume 1 == ~t6_pc~0; 12663#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12283#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12284#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13011#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 13012#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13074#L521-10 assume 1 == ~t7_pc~0; 12422#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12356#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12791#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12489#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 12490#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12499#L869-1 assume !(1 == ~M_E~0); 12500#L874-1 assume !(1 == ~T1_E~0); 13129#L879-1 assume !(1 == ~T2_E~0); 12768#L884-1 assume !(1 == ~T3_E~0); 12294#L889-1 assume !(1 == ~T4_E~0); 12295#L894-1 assume !(1 == ~T5_E~0); 12583#L899-1 assume !(1 == ~T6_E~0); 12963#L904-1 assume !(1 == ~T7_E~0); 12721#L909-1 assume !(1 == ~E_M~0); 12722#L914-1 assume !(1 == ~E_1~0); 12893#L919-1 assume !(1 == ~E_2~0); 12660#L924-1 assume !(1 == ~E_3~0); 12480#L929-1 assume !(1 == ~E_4~0); 12481#L934-1 assume !(1 == ~E_5~0); 12706#L939-1 assume !(1 == ~E_6~0); 12707#L944-1 assume !(1 == ~E_7~0); 12394#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 12395#L1190 [2024-11-17 08:52:29,990 INFO L747 eck$LassoCheckResult]: Loop: 12395#L1190 assume true; 12578#L1190-1 assume !false; 12579#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12582#L648 assume true; 12683#L648-1 assume !false; 12766#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12767#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 12466#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12764#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12745#L653 assume !(0 != eval_~tmp~0#1); 12747#L656 assume true; 12621#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12622#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13035#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 12985#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12726#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12727#L796 assume !(0 == ~T3_E~0); 12792#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12604#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12605#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12912#L816 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12913#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 12749#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 12750#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 12932#L836 assume !(0 == ~E_3~0); 12614#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 12544#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 12545#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 13057#L856 assume 0 == ~E_7~0;~E_7~0 := 1; 12785#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12786#L388-1 assume 1 == ~m_pc~0; 12903#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12904#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12602#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12603#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12839#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12439#L407-1 assume 1 == ~t1_pc~0; 12440#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12624#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12822#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12828#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12997#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12998#L426-1 assume 1 == ~t2_pc~0; 13017#L427-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12716#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13068#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12808#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12693#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12694#L445-1 assume 1 == ~t3_pc~0; 12883#L446-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12317#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13039#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12591#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12592#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12335#L464-1 assume 1 == ~t4_pc~0; 12336#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12548#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12353#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12354#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12607#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13135#L483-1 assume 1 == ~t5_pc~0; 13136#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12689#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12448#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12449#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12494#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12474#L502-1 assume !(1 == ~t6_pc~0); 12435#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 12436#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12730#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12731#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13134#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12924#L521-1 assume !(1 == ~t7_pc~0); 12700#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 12701#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13003#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12521#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12522#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12559#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 12615#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12616#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12855#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12698#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12699#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12995#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12848#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12849#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 13124#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 12617#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 12618#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 12610#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 12611#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 12801#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 13060#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 12737#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12738#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 12310#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12752#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12753#L1209 assume !(0 == start_simulation_~tmp~3#1); 12513#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12514#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 12408#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12606#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13101#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12437#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12438#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 12569#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 12395#L1190 [2024-11-17 08:52:29,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:29,991 INFO L85 PathProgramCache]: Analyzing trace with hash 882684939, now seen corresponding path program 1 times [2024-11-17 08:52:29,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:29,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553902027] [2024-11-17 08:52:29,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:29,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:30,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:30,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:30,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:30,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553902027] [2024-11-17 08:52:30,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553902027] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:30,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:30,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:30,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847204353] [2024-11-17 08:52:30,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:30,080 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:30,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:30,081 INFO L85 PathProgramCache]: Analyzing trace with hash 880547341, now seen corresponding path program 3 times [2024-11-17 08:52:30,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:30,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684142057] [2024-11-17 08:52:30,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:30,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:30,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:30,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:30,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:30,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684142057] [2024-11-17 08:52:30,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684142057] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:30,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:30,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:30,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732562245] [2024-11-17 08:52:30,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:30,150 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:30,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:30,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:30,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:30,151 INFO L87 Difference]: Start difference. First operand 871 states and 1279 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:30,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:30,260 INFO L93 Difference]: Finished difference Result 1581 states and 2310 transitions. [2024-11-17 08:52:30,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1581 states and 2310 transitions. [2024-11-17 08:52:30,269 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1462 [2024-11-17 08:52:30,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1581 states to 1581 states and 2310 transitions. [2024-11-17 08:52:30,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1581 [2024-11-17 08:52:30,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1581 [2024-11-17 08:52:30,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1581 states and 2310 transitions. [2024-11-17 08:52:30,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:30,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1581 states and 2310 transitions. [2024-11-17 08:52:30,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1581 states and 2310 transitions. [2024-11-17 08:52:30,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1581 to 1581. [2024-11-17 08:52:30,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1581 states, 1581 states have (on average 1.4611005692599621) internal successors, (2310), 1580 states have internal predecessors, (2310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:30,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1581 states to 1581 states and 2310 transitions. [2024-11-17 08:52:30,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1581 states and 2310 transitions. [2024-11-17 08:52:30,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:30,309 INFO L425 stractBuchiCegarLoop]: Abstraction has 1581 states and 2310 transitions. [2024-11-17 08:52:30,310 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:52:30,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1581 states and 2310 transitions. [2024-11-17 08:52:30,316 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1462 [2024-11-17 08:52:30,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:30,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:30,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:30,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:30,318 INFO L745 eck$LassoCheckResult]: Stem: 15436#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 14784#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14785#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14849#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15243#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 15078#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15079#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15304#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15572#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15612#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15631#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14906#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14907#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14763#L781-1 assume !(0 == ~M_E~0); 14764#L786-1 assume !(0 == ~T1_E~0); 14788#L791-1 assume !(0 == ~T2_E~0); 14789#L796-1 assume !(0 == ~T3_E~0); 15356#L801-1 assume !(0 == ~T4_E~0); 15357#L806-1 assume !(0 == ~T5_E~0); 15390#L811-1 assume !(0 == ~T6_E~0); 15042#L816-1 assume !(0 == ~T7_E~0); 15043#L821-1 assume !(0 == ~E_M~0); 14828#L826-1 assume !(0 == ~E_1~0); 14829#L831-1 assume !(0 == ~E_2~0); 15162#L836-1 assume !(0 == ~E_3~0); 15163#L841-1 assume !(0 == ~E_4~0); 14991#L846-1 assume !(0 == ~E_5~0); 14992#L851-1 assume !(0 == ~E_6~0); 15015#L856-1 assume 0 == ~E_7~0;~E_7~0 := 1; 15016#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15151#L388-10 assume 1 == ~m_pc~0; 15560#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14803#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15614#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15422#L967-10 assume !(0 != activate_threads_~tmp~1#1); 15423#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15002#L407-10 assume !(1 == ~t1_pc~0); 14845#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 14846#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14834#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14835#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 14786#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14787#L426-10 assume 1 == ~t2_pc~0; 15308#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15265#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15411#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14776#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 14777#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15126#L445-10 assume 1 == ~t3_pc~0; 15227#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15228#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15287#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15589#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 15656#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15642#L464-10 assume 1 == ~t4_pc~0; 15038#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15039#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15456#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15187#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 15188#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15539#L483-10 assume !(1 == ~t5_pc~0); 15053#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 15054#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15092#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15093#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 15244#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15245#L502-10 assume 1 == ~t6_pc~0; 15130#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14747#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14748#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15491#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 15492#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15565#L521-10 assume 1 == ~t7_pc~0; 14886#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14820#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15262#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14953#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 14954#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14963#L869-1 assume 1 == ~M_E~0;~M_E~0 := 2; 14964#L874-1 assume !(1 == ~T1_E~0); 15639#L879-1 assume !(1 == ~T2_E~0); 15238#L884-1 assume !(1 == ~T3_E~0); 14758#L889-1 assume !(1 == ~T4_E~0); 14759#L894-1 assume !(1 == ~T5_E~0); 15049#L899-1 assume !(1 == ~T6_E~0); 15678#L904-1 assume !(1 == ~T7_E~0); 15441#L909-1 assume !(1 == ~E_M~0); 15748#L914-1 assume !(1 == ~E_1~0); 15746#L919-1 assume !(1 == ~E_2~0); 15745#L924-1 assume !(1 == ~E_3~0); 15744#L929-1 assume !(1 == ~E_4~0); 15742#L934-1 assume !(1 == ~E_5~0); 15740#L939-1 assume !(1 == ~E_6~0); 15552#L944-1 assume !(1 == ~E_7~0); 14858#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 14859#L1190 [2024-11-17 08:52:30,318 INFO L747 eck$LassoCheckResult]: Loop: 14859#L1190 assume true; 15699#L1190-1 assume !false; 15695#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15694#L648 assume true; 15693#L648-1 assume !false; 15236#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15237#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14930#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15234#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15331#L653 assume !(0 != eval_~tmp~0#1); 15273#L656 assume true; 15087#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15088#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15646#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 15464#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15195#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15196#L796 assume !(0 == ~T3_E~0); 15263#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15070#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15071#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15388#L816 assume !(0 == ~T7_E~0); 15389#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 15218#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 15219#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 15409#L836 assume !(0 == ~E_3~0); 15080#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 15010#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 15011#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 15541#L856 assume 0 == ~E_7~0;~E_7~0 := 1; 15256#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15257#L388-1 assume 1 == ~m_pc~0; 15379#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15380#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15068#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15069#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15313#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14903#L407-1 assume 1 == ~t1_pc~0; 14904#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15090#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15296#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15302#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15476#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15477#L426-1 assume 1 == ~t2_pc~0; 15498#L427-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15184#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15559#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15280#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15160#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15161#L445-1 assume !(1 == ~t3_pc~0); 14780#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 14781#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15523#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15057#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15058#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14799#L464-1 assume 1 == ~t4_pc~0; 14800#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15014#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14817#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14818#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15073#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15647#L483-1 assume 1 == ~t5_pc~0; 15648#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15156#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14912#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14913#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14958#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14938#L502-1 assume !(1 == ~t6_pc~0); 14899#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 14900#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15199#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15200#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15645#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15400#L521-1 assume !(1 == ~t7_pc~0); 15401#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 16262#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16261#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16260#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16259#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16258#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 15488#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16257#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16256#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16255#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16254#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16253#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16252#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15323#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 16251#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 16250#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 16249#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 16248#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 16247#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 16246#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 15548#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 15549#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15591#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14774#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15221#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15222#L1209 assume !(0 == start_simulation_~tmp~3#1); 14979#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14980#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14872#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15072#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15598#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14901#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14902#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15035#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 14859#L1190 [2024-11-17 08:52:30,319 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:30,319 INFO L85 PathProgramCache]: Analyzing trace with hash 396427467, now seen corresponding path program 1 times [2024-11-17 08:52:30,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:30,319 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852415516] [2024-11-17 08:52:30,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:30,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:30,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:30,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:30,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:30,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852415516] [2024-11-17 08:52:30,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852415516] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:30,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:30,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:30,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140732705] [2024-11-17 08:52:30,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:30,385 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:30,386 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:30,386 INFO L85 PathProgramCache]: Analyzing trace with hash -1713453615, now seen corresponding path program 1 times [2024-11-17 08:52:30,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:30,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135291389] [2024-11-17 08:52:30,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:30,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:30,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:30,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:30,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:30,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135291389] [2024-11-17 08:52:30,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135291389] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:30,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:30,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:30,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [856734037] [2024-11-17 08:52:30,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:30,445 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:30,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:30,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:30,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:30,446 INFO L87 Difference]: Start difference. First operand 1581 states and 2310 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:30,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:30,629 INFO L93 Difference]: Finished difference Result 2865 states and 4167 transitions. [2024-11-17 08:52:30,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2865 states and 4167 transitions. [2024-11-17 08:52:30,649 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2734 [2024-11-17 08:52:30,662 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2865 states to 2865 states and 4167 transitions. [2024-11-17 08:52:30,662 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2865 [2024-11-17 08:52:30,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2865 [2024-11-17 08:52:30,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2865 states and 4167 transitions. [2024-11-17 08:52:30,667 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:30,667 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2865 states and 4167 transitions. [2024-11-17 08:52:30,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2865 states and 4167 transitions. [2024-11-17 08:52:30,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2865 to 2863. [2024-11-17 08:52:30,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2863 states, 2863 states have (on average 1.4547677261613692) internal successors, (4165), 2862 states have internal predecessors, (4165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:30,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2863 states to 2863 states and 4165 transitions. [2024-11-17 08:52:30,716 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2863 states and 4165 transitions. [2024-11-17 08:52:30,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:30,718 INFO L425 stractBuchiCegarLoop]: Abstraction has 2863 states and 4165 transitions. [2024-11-17 08:52:30,718 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:52:30,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2863 states and 4165 transitions. [2024-11-17 08:52:30,730 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2734 [2024-11-17 08:52:30,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:30,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:30,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:30,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:30,732 INFO L745 eck$LassoCheckResult]: Stem: 19906#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 19242#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19243#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19307#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19703#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 19538#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19539#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19766#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20043#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20079#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20090#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19366#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19367#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19221#L781-1 assume !(0 == ~M_E~0); 19222#L786-1 assume !(0 == ~T1_E~0); 19249#L791-1 assume !(0 == ~T2_E~0); 19250#L796-1 assume !(0 == ~T3_E~0); 19818#L801-1 assume !(0 == ~T4_E~0); 19819#L806-1 assume !(0 == ~T5_E~0); 19853#L811-1 assume !(0 == ~T6_E~0); 19503#L816-1 assume !(0 == ~T7_E~0); 19504#L821-1 assume !(0 == ~E_M~0); 19286#L826-1 assume !(0 == ~E_1~0); 19287#L831-1 assume !(0 == ~E_2~0); 19621#L836-1 assume !(0 == ~E_3~0); 19622#L841-1 assume !(0 == ~E_4~0); 19451#L846-1 assume !(0 == ~E_5~0); 19452#L851-1 assume !(0 == ~E_6~0); 19473#L856-1 assume !(0 == ~E_7~0); 19474#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19610#L388-10 assume 1 == ~m_pc~0; 20031#L389-10 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19263#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20081#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19891#L967-10 assume !(0 != activate_threads_~tmp~1#1); 19892#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19460#L407-10 assume !(1 == ~t1_pc~0); 19305#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 19306#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19295#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19296#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 19244#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19245#L426-10 assume 1 == ~t2_pc~0; 19770#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19725#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19879#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19234#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 19235#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19585#L445-10 assume 1 == ~t3_pc~0; 19687#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19688#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19749#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20061#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 20114#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20099#L464-10 assume 1 == ~t4_pc~0; 19497#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19498#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19927#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19646#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 19647#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20013#L483-10 assume !(1 == ~t5_pc~0); 19512#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 19513#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19552#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19553#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 19704#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19705#L502-10 assume 1 == ~t6_pc~0; 19589#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19205#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19206#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19963#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 19964#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20036#L521-10 assume 1 == ~t7_pc~0; 19344#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19278#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19722#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19412#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 19413#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19422#L869-1 assume 1 == ~M_E~0;~M_E~0 := 2; 19423#L874-1 assume !(1 == ~T1_E~0); 20119#L879-1 assume !(1 == ~T2_E~0); 19698#L884-1 assume !(1 == ~T3_E~0); 19699#L889-1 assume !(1 == ~T4_E~0); 20262#L894-1 assume !(1 == ~T5_E~0); 20136#L899-1 assume !(1 == ~T6_E~0); 19911#L904-1 assume !(1 == ~T7_E~0); 19912#L909-1 assume !(1 == ~E_M~0); 19831#L914-1 assume !(1 == ~E_1~0); 19832#L919-1 assume !(1 == ~E_2~0); 20223#L924-1 assume !(1 == ~E_3~0); 20221#L929-1 assume !(1 == ~E_4~0); 20108#L934-1 assume !(1 == ~E_5~0); 19633#L939-1 assume !(1 == ~E_6~0); 19634#L944-1 assume !(1 == ~E_7~0); 20176#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 20168#L1190 [2024-11-17 08:52:30,733 INFO L747 eck$LassoCheckResult]: Loop: 20168#L1190 assume true; 20162#L1190-1 assume !false; 20158#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20157#L648 assume true; 20156#L648-1 assume !false; 20155#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20151#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20146#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20145#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20143#L653 assume !(0 != eval_~tmp~0#1); 20142#L656 assume true; 20141#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20140#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20138#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 20139#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22067#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22066#L796 assume !(0 == ~T3_E~0); 22065#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22064#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22063#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22062#L816 assume !(0 == ~T7_E~0); 22061#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 22060#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 22059#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 22058#L836 assume !(0 == ~E_3~0); 22057#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 22056#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 22055#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 22054#L856 assume !(0 == ~E_7~0); 22053#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22052#L388-1 assume 1 == ~m_pc~0; 22050#L389-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22049#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22048#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22047#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22046#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22045#L407-1 assume !(1 == ~t1_pc~0); 22043#L417-1 is_transmit1_triggered_~__retres1~1#1 := 0; 22042#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22041#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22040#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22039#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22038#L426-1 assume !(1 == ~t2_pc~0); 22036#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 22035#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22034#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22033#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22032#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22031#L445-1 assume 1 == ~t3_pc~0; 20132#L446-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19239#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19996#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19516#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19517#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19257#L464-1 assume 1 == ~t4_pc~0; 19258#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19472#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19275#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19276#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19533#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20109#L483-1 assume 1 == ~t5_pc~0; 20110#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19615#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19370#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19371#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19417#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19396#L502-1 assume 1 == ~t6_pc~0; 19397#L503-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22011#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19659#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19660#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20104#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19869#L521-1 assume !(1 == ~t7_pc~0); 19626#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 19627#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19953#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22004#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19483#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19484#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 19960#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19984#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19791#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19624#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19625#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19945#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19784#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19785#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 20091#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 19543#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 19544#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 19536#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 19537#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 20122#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 20123#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 20271#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20268#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20261#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20260#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 20259#L1209 assume !(0 == start_simulation_~tmp~3#1); 19642#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20226#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20222#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20220#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 20203#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20201#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20184#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20175#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 20168#L1190 [2024-11-17 08:52:30,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:30,733 INFO L85 PathProgramCache]: Analyzing trace with hash -211649396, now seen corresponding path program 1 times [2024-11-17 08:52:30,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:30,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303364975] [2024-11-17 08:52:30,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:30,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:30,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:30,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:30,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:30,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303364975] [2024-11-17 08:52:30,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303364975] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:30,780 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:30,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:30,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613561212] [2024-11-17 08:52:30,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:30,783 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:30,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:30,783 INFO L85 PathProgramCache]: Analyzing trace with hash -1909448046, now seen corresponding path program 1 times [2024-11-17 08:52:30,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:30,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379410766] [2024-11-17 08:52:30,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:30,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:30,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:30,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:30,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:30,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1379410766] [2024-11-17 08:52:30,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1379410766] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:30,850 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:30,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:30,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246426068] [2024-11-17 08:52:30,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:30,851 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:30,851 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:30,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:30,851 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:30,852 INFO L87 Difference]: Start difference. First operand 2863 states and 4165 transitions. cyclomatic complexity: 1306 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:30,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:30,978 INFO L93 Difference]: Finished difference Result 5525 states and 7960 transitions. [2024-11-17 08:52:30,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5525 states and 7960 transitions. [2024-11-17 08:52:31,011 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5389 [2024-11-17 08:52:31,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5525 states to 5525 states and 7960 transitions. [2024-11-17 08:52:31,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5525 [2024-11-17 08:52:31,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5525 [2024-11-17 08:52:31,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5525 states and 7960 transitions. [2024-11-17 08:52:31,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:31,055 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5525 states and 7960 transitions. [2024-11-17 08:52:31,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5525 states and 7960 transitions. [2024-11-17 08:52:31,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5525 to 5305. [2024-11-17 08:52:31,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5305 states, 5305 states have (on average 1.4424128180961358) internal successors, (7652), 5304 states have internal predecessors, (7652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:31,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5305 states to 5305 states and 7652 transitions. [2024-11-17 08:52:31,157 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5305 states and 7652 transitions. [2024-11-17 08:52:31,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:31,159 INFO L425 stractBuchiCegarLoop]: Abstraction has 5305 states and 7652 transitions. [2024-11-17 08:52:31,159 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:52:31,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5305 states and 7652 transitions. [2024-11-17 08:52:31,180 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5169 [2024-11-17 08:52:31,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:31,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:31,182 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:31,182 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:31,182 INFO L745 eck$LassoCheckResult]: Stem: 28312#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 27639#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 27640#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27704#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28103#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 27934#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27935#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28164#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28474#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28524#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28539#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27763#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27764#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27618#L781-1 assume !(0 == ~M_E~0); 27619#L786-1 assume !(0 == ~T1_E~0); 27646#L791-1 assume !(0 == ~T2_E~0); 27647#L796-1 assume !(0 == ~T3_E~0); 28221#L801-1 assume !(0 == ~T4_E~0); 28222#L806-1 assume !(0 == ~T5_E~0); 28255#L811-1 assume !(0 == ~T6_E~0); 27899#L816-1 assume !(0 == ~T7_E~0); 27900#L821-1 assume !(0 == ~E_M~0); 27683#L826-1 assume !(0 == ~E_1~0); 27684#L831-1 assume !(0 == ~E_2~0); 28023#L836-1 assume !(0 == ~E_3~0); 28024#L841-1 assume !(0 == ~E_4~0); 27849#L846-1 assume !(0 == ~E_5~0); 27850#L851-1 assume !(0 == ~E_6~0); 27870#L856-1 assume !(0 == ~E_7~0); 27871#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28011#L388-10 assume !(1 == ~m_pc~0); 27659#L398-10 is_master_triggered_~__retres1~0#1 := 0; 27660#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28526#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28297#L967-10 assume !(0 != activate_threads_~tmp~1#1); 28298#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27858#L407-10 assume !(1 == ~t1_pc~0); 27702#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 27703#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27692#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27693#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 27641#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27642#L426-10 assume 1 == ~t2_pc~0; 28168#L427-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28125#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28279#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27633#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 27634#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27983#L445-10 assume 1 == ~t3_pc~0; 28090#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28091#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28148#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28494#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 28571#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28552#L464-10 assume 1 == ~t4_pc~0; 27893#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27894#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28333#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28047#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 28048#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28433#L483-10 assume !(1 == ~t5_pc~0); 27908#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 27909#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27949#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27950#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 28104#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28105#L502-10 assume 1 == ~t6_pc~0; 27990#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27602#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27603#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28376#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 28377#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28464#L521-10 assume 1 == ~t7_pc~0; 27741#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27675#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28122#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27812#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 27813#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27821#L869-1 assume 1 == ~M_E~0;~M_E~0 := 2; 27822#L874-1 assume !(1 == ~T1_E~0); 31067#L879-1 assume !(1 == ~T2_E~0); 31066#L884-1 assume !(1 == ~T3_E~0); 31065#L889-1 assume !(1 == ~T4_E~0); 31064#L894-1 assume !(1 == ~T5_E~0); 31063#L899-1 assume !(1 == ~T6_E~0); 28316#L904-1 assume !(1 == ~T7_E~0); 28317#L909-1 assume !(1 == ~E_M~0); 30153#L914-1 assume !(1 == ~E_1~0); 30094#L919-1 assume !(1 == ~E_2~0); 30090#L924-1 assume !(1 == ~E_3~0); 30088#L929-1 assume !(1 == ~E_4~0); 30087#L934-1 assume !(1 == ~E_5~0); 28034#L939-1 assume !(1 == ~E_6~0); 28035#L944-1 assume !(1 == ~E_7~0); 29994#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 29991#L1190 [2024-11-17 08:52:31,183 INFO L747 eck$LassoCheckResult]: Loop: 29991#L1190 assume true; 29989#L1190-1 assume !false; 29918#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29917#L648 assume true; 29916#L648-1 assume !false; 29915#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 29844#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 29789#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 29786#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 29783#L653 assume !(0 != eval_~tmp~0#1); 29784#L656 assume true; 32653#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32650#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32648#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 32646#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32644#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32642#L796 assume !(0 == ~T3_E~0); 32640#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32637#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32636#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32635#L816 assume !(0 == ~T7_E~0); 32634#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 32633#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 32632#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 32631#L836 assume !(0 == ~E_3~0); 32630#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 32628#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 32626#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 32624#L856 assume !(0 == ~E_7~0); 32622#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32620#L388-1 assume !(1 == ~m_pc~0); 32618#L398-1 is_master_triggered_~__retres1~0#1 := 0; 32616#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32613#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32611#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32610#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32609#L407-1 assume 1 == ~t1_pc~0; 32608#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32606#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32605#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32604#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32603#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32602#L426-1 assume !(1 == ~t2_pc~0); 32600#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 32542#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32541#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32532#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32530#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32528#L445-1 assume !(1 == ~t3_pc~0); 32525#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 32523#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32522#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32521#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32520#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32519#L464-1 assume 1 == ~t4_pc~0; 32517#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32508#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32506#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32504#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32502#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32500#L483-1 assume !(1 == ~t5_pc~0); 32497#L493-1 is_transmit5_triggered_~__retres1~5#1 := 0; 32495#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32493#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32491#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32490#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32489#L502-1 assume !(1 == ~t6_pc~0); 32487#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 32486#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32485#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32484#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32483#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32482#L521-1 assume !(1 == ~t7_pc~0); 32478#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 32476#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32473#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32471#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32469#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32467#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 28371#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32464#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32461#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32459#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32457#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32455#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32453#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28185#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 32451#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 32450#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 32388#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 32321#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 32291#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 32285#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 32279#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 31562#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31050#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31044#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31043#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 31042#L1209 assume !(0 == start_simulation_~tmp~3#1); 28042#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30244#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30239#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30187#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 30141#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30139#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30079#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 29993#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 29991#L1190 [2024-11-17 08:52:31,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:31,184 INFO L85 PathProgramCache]: Analyzing trace with hash 1147137231, now seen corresponding path program 1 times [2024-11-17 08:52:31,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:31,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518384535] [2024-11-17 08:52:31,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:31,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:31,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:31,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:31,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:31,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518384535] [2024-11-17 08:52:31,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518384535] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:31,243 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:31,243 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:31,243 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407578275] [2024-11-17 08:52:31,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:31,243 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:31,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:31,245 INFO L85 PathProgramCache]: Analyzing trace with hash 1898989339, now seen corresponding path program 1 times [2024-11-17 08:52:31,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:31,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149121236] [2024-11-17 08:52:31,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:31,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:31,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:31,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:31,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:31,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149121236] [2024-11-17 08:52:31,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149121236] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:31,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:31,329 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:31,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325229854] [2024-11-17 08:52:31,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:31,329 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:31,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:31,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:31,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:31,330 INFO L87 Difference]: Start difference. First operand 5305 states and 7652 transitions. cyclomatic complexity: 2355 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:31,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:31,441 INFO L93 Difference]: Finished difference Result 9947 states and 14256 transitions. [2024-11-17 08:52:31,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9947 states and 14256 transitions. [2024-11-17 08:52:31,488 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9788 [2024-11-17 08:52:31,548 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9947 states to 9947 states and 14256 transitions. [2024-11-17 08:52:31,548 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9947 [2024-11-17 08:52:31,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9947 [2024-11-17 08:52:31,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9947 states and 14256 transitions. [2024-11-17 08:52:31,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:31,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9947 states and 14256 transitions. [2024-11-17 08:52:31,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9947 states and 14256 transitions. [2024-11-17 08:52:31,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9947 to 9915. [2024-11-17 08:52:31,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9915 states, 9915 states have (on average 1.4345940494200706) internal successors, (14224), 9914 states have internal predecessors, (14224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:31,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9915 states to 9915 states and 14224 transitions. [2024-11-17 08:52:31,743 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9915 states and 14224 transitions. [2024-11-17 08:52:31,744 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:31,744 INFO L425 stractBuchiCegarLoop]: Abstraction has 9915 states and 14224 transitions. [2024-11-17 08:52:31,744 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:52:31,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9915 states and 14224 transitions. [2024-11-17 08:52:31,783 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9756 [2024-11-17 08:52:31,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:31,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:31,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:31,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:31,785 INFO L745 eck$LassoCheckResult]: Stem: 43551#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 42900#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 42901#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42965#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43356#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 43193#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43194#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43418#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43703#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43744#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43773#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43022#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43023#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42879#L781-1 assume !(0 == ~M_E~0); 42880#L786-1 assume !(0 == ~T1_E~0); 42904#L791-1 assume !(0 == ~T2_E~0); 42905#L796-1 assume !(0 == ~T3_E~0); 43470#L801-1 assume !(0 == ~T4_E~0); 43471#L806-1 assume !(0 == ~T5_E~0); 43504#L811-1 assume !(0 == ~T6_E~0); 43156#L816-1 assume !(0 == ~T7_E~0); 43157#L821-1 assume !(0 == ~E_M~0); 42944#L826-1 assume !(0 == ~E_1~0); 42945#L831-1 assume !(0 == ~E_2~0); 43276#L836-1 assume !(0 == ~E_3~0); 43277#L841-1 assume !(0 == ~E_4~0); 43105#L846-1 assume !(0 == ~E_5~0); 43106#L851-1 assume !(0 == ~E_6~0); 43128#L856-1 assume !(0 == ~E_7~0); 43129#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43264#L388-10 assume !(1 == ~m_pc~0); 42918#L398-10 is_master_triggered_~__retres1~0#1 := 0; 42919#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43747#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43537#L967-10 assume !(0 != activate_threads_~tmp~1#1); 43538#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43116#L407-10 assume !(1 == ~t1_pc~0); 42961#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 42962#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42950#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42951#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 42902#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42903#L426-10 assume !(1 == ~t2_pc~0); 43377#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 43378#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43525#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42892#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 42893#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43239#L445-10 assume 1 == ~t3_pc~0; 43340#L446-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43341#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43401#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43722#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 43797#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43787#L464-10 assume 1 == ~t4_pc~0; 43152#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43153#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43571#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43300#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 43301#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43655#L483-10 assume !(1 == ~t5_pc~0); 43168#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 43169#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43207#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43208#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 43357#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43358#L502-10 assume 1 == ~t6_pc~0; 43242#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42863#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42864#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43609#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 43610#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43695#L521-10 assume 1 == ~t7_pc~0; 43002#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42936#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43375#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43069#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 43070#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43079#L869-1 assume 1 == ~M_E~0;~M_E~0 := 2; 43080#L874-1 assume !(1 == ~T1_E~0); 43804#L879-1 assume !(1 == ~T2_E~0); 43351#L884-1 assume !(1 == ~T3_E~0); 43352#L889-1 assume !(1 == ~T4_E~0); 43163#L894-1 assume !(1 == ~T5_E~0); 43164#L899-1 assume !(1 == ~T6_E~0); 43555#L904-1 assume !(1 == ~T7_E~0); 43556#L909-1 assume !(1 == ~E_M~0); 48634#L914-1 assume !(1 == ~E_1~0); 48632#L919-1 assume !(1 == ~E_2~0); 48630#L924-1 assume !(1 == ~E_3~0); 48628#L929-1 assume !(1 == ~E_4~0); 48626#L934-1 assume !(1 == ~E_5~0); 48623#L939-1 assume !(1 == ~E_6~0); 43671#L944-1 assume !(1 == ~E_7~0); 43672#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 49808#L1190 [2024-11-17 08:52:31,786 INFO L747 eck$LassoCheckResult]: Loop: 49808#L1190 assume true; 49804#L1190-1 assume !false; 49676#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49674#L648 assume true; 49672#L648-1 assume !false; 49670#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 49519#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 49507#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 49502#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49495#L653 assume !(0 != eval_~tmp~0#1); 49496#L656 assume true; 52607#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43791#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43634#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 43578#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43308#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43309#L796 assume !(0 == ~T3_E~0); 43376#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52602#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52601#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52600#L816 assume !(0 == ~T7_E~0); 52585#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 52584#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 52583#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 43750#L836 assume !(0 == ~E_3~0); 43195#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 43123#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 43124#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 52576#L856 assume !(0 == ~E_7~0); 52575#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52574#L388-1 assume !(1 == ~m_pc~0); 52573#L398-1 is_master_triggered_~__retres1~0#1 := 0; 52572#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52571#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 52570#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52569#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52568#L407-1 assume !(1 == ~t1_pc~0); 52566#L417-1 is_transmit1_triggered_~__retres1~1#1 := 0; 52565#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52564#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52563#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52562#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52561#L426-1 assume !(1 == ~t2_pc~0); 52560#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 52559#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52558#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52556#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52554#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52552#L445-1 assume !(1 == ~t3_pc~0); 52549#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 52547#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52545#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43172#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43173#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42915#L464-1 assume 1 == ~t4_pc~0; 42916#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43127#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42933#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42934#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43188#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43793#L483-1 assume 1 == ~t5_pc~0; 43794#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43270#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43028#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43029#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 43074#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43054#L502-1 assume !(1 == ~t6_pc~0); 43015#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 43016#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43312#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43313#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43790#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43515#L521-1 assume !(1 == ~t7_pc~0); 43281#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 43282#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43599#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43101#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43102#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43138#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 43196#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43197#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52196#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49892#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49889#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49887#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49885#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49881#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 49879#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 49877#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 49874#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 49872#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 49870#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 49868#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 49866#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 48696#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 49858#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 49851#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 49849#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 49847#L1209 assume !(0 == start_simulation_~tmp~3#1); 43296#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 49831#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 49827#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 49825#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 49823#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49820#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49818#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 49812#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 49808#L1190 [2024-11-17 08:52:31,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:31,786 INFO L85 PathProgramCache]: Analyzing trace with hash 1978231186, now seen corresponding path program 1 times [2024-11-17 08:52:31,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:31,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088073261] [2024-11-17 08:52:31,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:31,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:31,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:31,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:31,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:31,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088073261] [2024-11-17 08:52:31,908 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088073261] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:31,908 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:31,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:31,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479339990] [2024-11-17 08:52:31,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:31,910 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:31,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:31,911 INFO L85 PathProgramCache]: Analyzing trace with hash -535810533, now seen corresponding path program 1 times [2024-11-17 08:52:31,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:31,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783338469] [2024-11-17 08:52:31,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:31,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:31,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:31,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:31,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:31,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783338469] [2024-11-17 08:52:31,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783338469] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:31,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:31,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:31,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023989498] [2024-11-17 08:52:31,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:31,969 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:31,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:31,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:31,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:31,970 INFO L87 Difference]: Start difference. First operand 9915 states and 14224 transitions. cyclomatic complexity: 4325 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:32,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:32,107 INFO L93 Difference]: Finished difference Result 18634 states and 26577 transitions. [2024-11-17 08:52:32,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18634 states and 26577 transitions. [2024-11-17 08:52:32,209 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18428 [2024-11-17 08:52:32,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18634 states to 18634 states and 26577 transitions. [2024-11-17 08:52:32,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18634 [2024-11-17 08:52:32,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18634 [2024-11-17 08:52:32,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18634 states and 26577 transitions. [2024-11-17 08:52:32,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:32,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18634 states and 26577 transitions. [2024-11-17 08:52:32,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18634 states and 26577 transitions. [2024-11-17 08:52:32,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18634 to 18570. [2024-11-17 08:52:32,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18570 states, 18570 states have (on average 1.427732902530964) internal successors, (26513), 18569 states have internal predecessors, (26513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:32,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18570 states to 18570 states and 26513 transitions. [2024-11-17 08:52:32,913 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18570 states and 26513 transitions. [2024-11-17 08:52:32,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:32,914 INFO L425 stractBuchiCegarLoop]: Abstraction has 18570 states and 26513 transitions. [2024-11-17 08:52:32,914 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:52:32,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18570 states and 26513 transitions. [2024-11-17 08:52:32,982 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18364 [2024-11-17 08:52:32,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:32,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:32,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:32,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:32,984 INFO L745 eck$LassoCheckResult]: Stem: 72136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 71458#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 71459#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71523#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71924#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 71753#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 71754#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 71990#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72300#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72346#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 72370#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 71582#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 71583#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71437#L781-1 assume !(0 == ~M_E~0); 71438#L786-1 assume !(0 == ~T1_E~0); 71465#L791-1 assume !(0 == ~T2_E~0); 71466#L796-1 assume !(0 == ~T3_E~0); 72049#L801-1 assume !(0 == ~T4_E~0); 72050#L806-1 assume !(0 == ~T5_E~0); 72082#L811-1 assume !(0 == ~T6_E~0); 71719#L816-1 assume !(0 == ~T7_E~0); 71720#L821-1 assume !(0 == ~E_M~0); 71502#L826-1 assume !(0 == ~E_1~0); 71503#L831-1 assume !(0 == ~E_2~0); 71844#L836-1 assume !(0 == ~E_3~0); 71845#L841-1 assume !(0 == ~E_4~0); 71668#L846-1 assume !(0 == ~E_5~0); 71669#L851-1 assume !(0 == ~E_6~0); 71689#L856-1 assume !(0 == ~E_7~0); 71690#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71830#L388-10 assume !(1 == ~m_pc~0); 71476#L398-10 is_master_triggered_~__retres1~0#1 := 0; 71477#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72348#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 72121#L967-10 assume !(0 != activate_threads_~tmp~1#1); 72122#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71677#L407-10 assume !(1 == ~t1_pc~0); 71521#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 71522#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71511#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71512#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 71460#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71461#L426-10 assume !(1 == ~t2_pc~0); 71945#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 71946#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72107#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71452#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 71453#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71802#L445-10 assume !(1 == ~t3_pc~0); 72388#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 71973#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71974#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72321#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 72410#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72390#L464-10 assume 1 == ~t4_pc~0; 71713#L465-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 71714#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72158#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71868#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 71869#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72260#L483-10 assume !(1 == ~t5_pc~0); 71728#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 71729#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71767#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71768#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 71925#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71926#L502-10 assume 1 == ~t6_pc~0; 71805#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 71421#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71422#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72198#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 72199#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72291#L521-10 assume 1 == ~t7_pc~0; 71560#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 71494#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71943#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71631#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 71632#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71640#L869-1 assume 1 == ~M_E~0;~M_E~0 := 2; 71641#L874-1 assume !(1 == ~T1_E~0); 75242#L879-1 assume !(1 == ~T2_E~0); 75240#L884-1 assume !(1 == ~T3_E~0); 75238#L889-1 assume !(1 == ~T4_E~0); 75236#L894-1 assume !(1 == ~T5_E~0); 75233#L899-1 assume !(1 == ~T6_E~0); 75231#L904-1 assume !(1 == ~T7_E~0); 75229#L909-1 assume !(1 == ~E_M~0); 75227#L914-1 assume !(1 == ~E_1~0); 75225#L919-1 assume !(1 == ~E_2~0); 75223#L924-1 assume !(1 == ~E_3~0); 75220#L929-1 assume !(1 == ~E_4~0); 75218#L934-1 assume !(1 == ~E_5~0); 75216#L939-1 assume !(1 == ~E_6~0); 75214#L944-1 assume !(1 == ~E_7~0); 75210#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 75206#L1190 [2024-11-17 08:52:32,984 INFO L747 eck$LassoCheckResult]: Loop: 75206#L1190 assume true; 75204#L1190-1 assume !false; 74925#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74922#L648 assume true; 74920#L648-1 assume !false; 74918#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 74908#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 74902#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 74900#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 74897#L653 assume !(0 != eval_~tmp~0#1); 74898#L656 assume true; 77642#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77641#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77640#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 77639#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77638#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77637#L796 assume !(0 == ~T3_E~0); 77635#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77632#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77630#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77628#L816 assume !(0 == ~T7_E~0); 77626#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 77624#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 77622#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 77619#L836 assume !(0 == ~E_3~0); 77617#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 77615#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 77613#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 77611#L856 assume !(0 == ~E_7~0); 77609#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77607#L388-1 assume !(1 == ~m_pc~0); 77605#L398-1 is_master_triggered_~__retres1~0#1 := 0; 77603#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77601#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77599#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77597#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77595#L407-1 assume 1 == ~t1_pc~0; 77593#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77590#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77588#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77586#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77584#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77583#L426-1 assume !(1 == ~t2_pc~0); 77582#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 77581#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77580#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 77579#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77578#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77577#L445-1 assume !(1 == ~t3_pc~0); 77576#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 77575#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77574#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77573#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77572#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77571#L464-1 assume 1 == ~t4_pc~0; 77569#L465-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77568#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77567#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 77566#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77565#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77564#L483-1 assume 1 == ~t5_pc~0; 76051#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76049#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76048#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76047#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76046#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76043#L502-1 assume !(1 == ~t6_pc~0); 76045#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 76038#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76039#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76034#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76035#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72770#L521-1 assume !(1 == ~t7_pc~0); 72771#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 75886#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75884#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75882#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75880#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75878#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 72756#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 75875#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75873#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75871#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75869#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75867#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 75864#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72740#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 75861#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 75859#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 75857#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 75853#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 75849#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 75477#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 75475#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 75470#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 75448#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 75441#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 75439#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 75391#L1209 assume !(0 == start_simulation_~tmp~3#1); 75389#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 75375#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 75371#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 75369#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 75367#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75365#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75362#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 75209#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 75206#L1190 [2024-11-17 08:52:32,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:32,985 INFO L85 PathProgramCache]: Analyzing trace with hash 2020897941, now seen corresponding path program 1 times [2024-11-17 08:52:32,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:32,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570232240] [2024-11-17 08:52:32,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:32,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:32,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:33,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:33,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:33,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570232240] [2024-11-17 08:52:33,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [570232240] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:33,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:33,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:33,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537660789] [2024-11-17 08:52:33,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:33,102 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:33,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:33,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1856322584, now seen corresponding path program 1 times [2024-11-17 08:52:33,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:33,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816506391] [2024-11-17 08:52:33,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:33,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:33,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:33,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:33,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:33,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816506391] [2024-11-17 08:52:33,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816506391] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:33,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:33,170 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:33,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958879158] [2024-11-17 08:52:33,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:33,171 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:33,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:33,171 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:33,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:33,172 INFO L87 Difference]: Start difference. First operand 18570 states and 26513 transitions. cyclomatic complexity: 7975 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:33,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:33,374 INFO L93 Difference]: Finished difference Result 34941 states and 49650 transitions. [2024-11-17 08:52:33,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34941 states and 49650 transitions. [2024-11-17 08:52:33,740 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 34592 [2024-11-17 08:52:33,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34941 states to 34941 states and 49650 transitions. [2024-11-17 08:52:33,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34941 [2024-11-17 08:52:33,910 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34941 [2024-11-17 08:52:33,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34941 states and 49650 transitions. [2024-11-17 08:52:33,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:33,950 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34941 states and 49650 transitions. [2024-11-17 08:52:33,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34941 states and 49650 transitions. [2024-11-17 08:52:34,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34941 to 34813. [2024-11-17 08:52:34,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34813 states, 34813 states have (on average 1.4225145778875707) internal successors, (49522), 34812 states have internal predecessors, (49522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:34,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34813 states to 34813 states and 49522 transitions. [2024-11-17 08:52:34,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34813 states and 49522 transitions. [2024-11-17 08:52:34,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:34,609 INFO L425 stractBuchiCegarLoop]: Abstraction has 34813 states and 49522 transitions. [2024-11-17 08:52:34,609 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:52:34,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34813 states and 49522 transitions. [2024-11-17 08:52:34,719 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 34464 [2024-11-17 08:52:34,719 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:34,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:34,721 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:34,721 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:34,721 INFO L745 eck$LassoCheckResult]: Stem: 125647#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 124978#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 124979#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 125043#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125441#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 125271#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 125272#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125507#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125792#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 125833#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 125852#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 125100#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 125101#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 124957#L781-1 assume !(0 == ~M_E~0); 124958#L786-1 assume !(0 == ~T1_E~0); 124982#L791-1 assume !(0 == ~T2_E~0); 124983#L796-1 assume !(0 == ~T3_E~0); 125561#L801-1 assume !(0 == ~T4_E~0); 125562#L806-1 assume !(0 == ~T5_E~0); 125595#L811-1 assume !(0 == ~T6_E~0); 125233#L816-1 assume !(0 == ~T7_E~0); 125234#L821-1 assume !(0 == ~E_M~0); 125022#L826-1 assume !(0 == ~E_1~0); 125023#L831-1 assume !(0 == ~E_2~0); 125364#L836-1 assume !(0 == ~E_3~0); 125365#L841-1 assume !(0 == ~E_4~0); 125183#L846-1 assume !(0 == ~E_5~0); 125184#L851-1 assume !(0 == ~E_6~0); 125207#L856-1 assume !(0 == ~E_7~0); 125208#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 125351#L388-10 assume !(1 == ~m_pc~0); 124996#L398-10 is_master_triggered_~__retres1~0#1 := 0; 124997#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 125835#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 125630#L967-10 assume !(0 != activate_threads_~tmp~1#1); 125631#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125194#L407-10 assume !(1 == ~t1_pc~0); 125039#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 125040#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125028#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 125029#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 124980#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 124981#L426-10 assume !(1 == ~t2_pc~0); 125462#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 125463#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 125615#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 124970#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 124971#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 125323#L445-10 assume !(1 == ~t3_pc~0); 125862#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 125487#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125488#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 125812#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 125878#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 125863#L464-10 assume !(1 == ~t4_pc~0); 125764#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 125668#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 125669#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 125389#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 125390#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125752#L483-10 assume !(1 == ~t5_pc~0); 125244#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 125245#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125287#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 125288#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 125442#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125443#L502-10 assume 1 == ~t6_pc~0; 125326#L503-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 124941#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 124942#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 125705#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 125706#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125784#L521-10 assume 1 == ~t7_pc~0; 125080#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 125014#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125460#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 125146#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 125147#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125156#L869-1 assume 1 == ~M_E~0;~M_E~0 := 2; 125157#L874-1 assume !(1 == ~T1_E~0); 125860#L879-1 assume !(1 == ~T2_E~0); 125436#L884-1 assume !(1 == ~T3_E~0); 124952#L889-1 assume !(1 == ~T4_E~0); 124953#L894-1 assume !(1 == ~T5_E~0); 125240#L899-1 assume !(1 == ~T6_E~0); 125651#L904-1 assume !(1 == ~T7_E~0); 125392#L909-1 assume !(1 == ~E_M~0); 125393#L914-1 assume !(1 == ~E_1~0); 125574#L919-1 assume !(1 == ~E_2~0); 125324#L924-1 assume !(1 == ~E_3~0); 125137#L929-1 assume !(1 == ~E_4~0); 125138#L934-1 assume !(1 == ~E_5~0); 125376#L939-1 assume !(1 == ~E_6~0); 125377#L944-1 assume !(1 == ~E_7~0); 125052#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 125053#L1190 [2024-11-17 08:52:34,722 INFO L747 eck$LassoCheckResult]: Loop: 125053#L1190 assume true; 134346#L1190-1 assume !false; 134341#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134339#L648 assume true; 134337#L648-1 assume !false; 134335#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 134328#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 134322#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 134320#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 134317#L653 assume !(0 != eval_~tmp~0#1); 134318#L656 assume true; 134855#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 134853#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 134851#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 134849#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 134847#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134845#L796 assume !(0 == ~T3_E~0); 134843#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134841#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 134839#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 134837#L816 assume !(0 == ~T7_E~0); 134834#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 134831#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 134828#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 134825#L836 assume !(0 == ~E_3~0); 134822#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 134819#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 134816#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 134814#L856 assume !(0 == ~E_7~0); 134804#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134801#L388-1 assume !(1 == ~m_pc~0); 134798#L398-1 is_master_triggered_~__retres1~0#1 := 0; 134794#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134792#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 134789#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 134786#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134783#L407-1 assume !(1 == ~t1_pc~0); 134779#L417-1 is_transmit1_triggered_~__retres1~1#1 := 0; 134775#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134772#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 134769#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 134765#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134762#L426-1 assume !(1 == ~t2_pc~0); 134759#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 134756#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134753#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 134750#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 134747#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134744#L445-1 assume !(1 == ~t3_pc~0); 134741#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 134738#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134735#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 134732#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 134729#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134726#L464-1 assume !(1 == ~t4_pc~0); 134722#L474-1 is_transmit4_triggered_~__retres1~4#1 := 0; 134718#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134714#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134710#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 134706#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134702#L483-1 assume 1 == ~t5_pc~0; 134698#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 134691#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134687#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134683#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 134678#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134674#L502-1 assume 1 == ~t6_pc~0; 134670#L503-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 134664#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134660#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134656#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 134651#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 134647#L521-1 assume !(1 == ~t7_pc~0); 134642#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 134637#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 134632#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 134627#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 134621#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134616#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 133985#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134607#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134602#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 134596#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 134591#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134585#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 134579#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 134571#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 134566#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 134561#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 134556#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 134550#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 134543#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 134536#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 134530#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 133943#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 134448#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 134436#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 134430#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 134423#L1209 assume !(0 == start_simulation_~tmp~3#1); 134417#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 134403#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 134394#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 134386#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 134380#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134375#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134369#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 134361#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 125053#L1190 [2024-11-17 08:52:34,722 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:34,722 INFO L85 PathProgramCache]: Analyzing trace with hash 1457044952, now seen corresponding path program 1 times [2024-11-17 08:52:34,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:34,723 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233441944] [2024-11-17 08:52:34,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:34,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:34,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:34,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:34,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:34,773 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1233441944] [2024-11-17 08:52:34,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1233441944] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:34,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:34,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:34,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [483501526] [2024-11-17 08:52:34,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:34,774 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:34,774 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:34,775 INFO L85 PathProgramCache]: Analyzing trace with hash 859136411, now seen corresponding path program 1 times [2024-11-17 08:52:34,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:34,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607669468] [2024-11-17 08:52:34,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:34,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:34,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:34,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:34,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:34,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607669468] [2024-11-17 08:52:34,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607669468] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:34,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:34,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:34,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864162920] [2024-11-17 08:52:34,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:34,964 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:34,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:34,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:34,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:34,965 INFO L87 Difference]: Start difference. First operand 34813 states and 49522 transitions. cyclomatic complexity: 14773 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:35,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:35,533 INFO L93 Difference]: Finished difference Result 82656 states and 116675 transitions. [2024-11-17 08:52:35,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82656 states and 116675 transitions. [2024-11-17 08:52:36,081 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 81636 [2024-11-17 08:52:36,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82656 states to 82656 states and 116675 transitions. [2024-11-17 08:52:36,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82656 [2024-11-17 08:52:36,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82656 [2024-11-17 08:52:36,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82656 states and 116675 transitions. [2024-11-17 08:52:36,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:36,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82656 states and 116675 transitions. [2024-11-17 08:52:36,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82656 states and 116675 transitions. [2024-11-17 08:52:37,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82656 to 66924. [2024-11-17 08:52:37,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66924 states, 66924 states have (on average 1.4160390891160122) internal successors, (94767), 66923 states have internal predecessors, (94767), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:37,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66924 states to 66924 states and 94767 transitions. [2024-11-17 08:52:37,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66924 states and 94767 transitions. [2024-11-17 08:52:37,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:37,933 INFO L425 stractBuchiCegarLoop]: Abstraction has 66924 states and 94767 transitions. [2024-11-17 08:52:37,933 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:52:37,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66924 states and 94767 transitions. [2024-11-17 08:52:38,157 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 66352 [2024-11-17 08:52:38,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:38,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:38,160 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:38,160 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:38,160 INFO L745 eck$LassoCheckResult]: Stem: 243129#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 242459#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 242460#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 242523#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 242922#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 242753#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 242754#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 242986#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 243294#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 243338#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 243352#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 242581#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 242582#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 242438#L781-1 assume !(0 == ~M_E~0); 242439#L786-1 assume !(0 == ~T1_E~0); 242463#L791-1 assume !(0 == ~T2_E~0); 242464#L796-1 assume !(0 == ~T3_E~0); 243038#L801-1 assume !(0 == ~T4_E~0); 243039#L806-1 assume !(0 == ~T5_E~0); 243075#L811-1 assume !(0 == ~T6_E~0); 242714#L816-1 assume !(0 == ~T7_E~0); 242715#L821-1 assume !(0 == ~E_M~0); 242503#L826-1 assume !(0 == ~E_1~0); 242504#L831-1 assume !(0 == ~E_2~0); 242843#L836-1 assume !(0 == ~E_3~0); 242844#L841-1 assume !(0 == ~E_4~0); 242663#L846-1 assume !(0 == ~E_5~0); 242664#L851-1 assume !(0 == ~E_6~0); 242687#L856-1 assume !(0 == ~E_7~0); 242688#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 242831#L388-10 assume !(1 == ~m_pc~0); 242477#L398-10 is_master_triggered_~__retres1~0#1 := 0; 242478#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 243339#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 243114#L967-10 assume !(0 != activate_threads_~tmp~1#1); 243115#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 242674#L407-10 assume !(1 == ~t1_pc~0); 242519#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 242520#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 242509#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 242510#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 242461#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 242462#L426-10 assume !(1 == ~t2_pc~0); 242943#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 242944#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 243099#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 242451#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 242452#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 242805#L445-10 assume !(1 == ~t3_pc~0); 243365#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 242968#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 242969#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 243315#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 243386#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 243366#L464-10 assume !(1 == ~t4_pc~0); 243263#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 243150#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 243151#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 242867#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 242868#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 243251#L483-10 assume !(1 == ~t5_pc~0); 242725#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 242726#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 242768#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 242769#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 242923#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 242924#L502-10 assume !(1 == ~t6_pc~0); 242742#L512-10 is_transmit6_triggered_~__retres1~6#1 := 0; 242422#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 242423#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 243196#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 243197#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 243287#L521-10 assume 1 == ~t7_pc~0; 242560#L522-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 242495#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 242941#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 242627#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 242628#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 242636#L869-1 assume 1 == ~M_E~0;~M_E~0 := 2; 242637#L874-1 assume !(1 == ~T1_E~0); 243361#L879-1 assume !(1 == ~T2_E~0); 242918#L884-1 assume !(1 == ~T3_E~0); 242433#L889-1 assume !(1 == ~T4_E~0); 242434#L894-1 assume !(1 == ~T5_E~0); 242721#L899-1 assume !(1 == ~T6_E~0); 243137#L904-1 assume !(1 == ~T7_E~0); 242870#L909-1 assume !(1 == ~E_M~0); 242871#L914-1 assume !(1 == ~E_1~0); 243053#L919-1 assume !(1 == ~E_2~0); 255782#L924-1 assume !(1 == ~E_3~0); 255780#L929-1 assume !(1 == ~E_4~0); 255778#L934-1 assume !(1 == ~E_5~0); 255776#L939-1 assume !(1 == ~E_6~0); 255775#L944-1 assume !(1 == ~E_7~0); 255773#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 255771#L1190 [2024-11-17 08:52:38,161 INFO L747 eck$LassoCheckResult]: Loop: 255771#L1190 assume true; 255769#L1190-1 assume !false; 255659#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 255655#L648 assume true; 255653#L648-1 assume !false; 255651#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 255642#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255636#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 255635#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 255632#L653 assume !(0 != eval_~tmp~0#1); 255633#L656 assume true; 256006#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 256004#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 256002#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 256000#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 255997#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 255995#L796 assume !(0 == ~T3_E~0); 255993#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 255991#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 255989#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 255987#L816 assume !(0 == ~T7_E~0); 255985#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 255983#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 255981#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 255979#L836 assume !(0 == ~E_3~0); 255977#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 255975#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 255974#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 255973#L856 assume !(0 == ~E_7~0); 255972#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 255971#L388-1 assume !(1 == ~m_pc~0); 255970#L398-1 is_master_triggered_~__retres1~0#1 := 0; 255969#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 255968#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 255967#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 255964#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 255963#L407-1 assume 1 == ~t1_pc~0; 255961#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 255958#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 255956#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 255954#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 255952#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 255950#L426-1 assume !(1 == ~t2_pc~0); 255948#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 255945#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 255943#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 255941#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 255939#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 255937#L445-1 assume !(1 == ~t3_pc~0); 255935#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 255933#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 255931#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 255929#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 255927#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 255925#L464-1 assume !(1 == ~t4_pc~0); 255923#L474-1 is_transmit4_triggered_~__retres1~4#1 := 0; 255921#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 255919#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 255917#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 255915#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 255913#L483-1 assume 1 == ~t5_pc~0; 255911#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 255908#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255906#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 255904#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 255902#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 255900#L502-1 assume !(1 == ~t6_pc~0); 253652#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 255896#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 255894#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 255892#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 255890#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 255888#L521-1 assume 1 == ~t7_pc~0; 255886#L522-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 255884#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 255882#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 255880#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 255878#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 255876#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 255872#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 255869#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 255867#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 255865#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 255863#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 255861#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 255859#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 255855#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 255853#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 255851#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 255849#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 255847#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 255845#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 255843#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 255841#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 255837#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 255831#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255824#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 255822#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 255818#L1209 assume !(0 == start_simulation_~tmp~3#1); 255817#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 255811#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255808#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 255806#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 255803#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 255799#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 255795#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 255772#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 255771#L1190 [2024-11-17 08:52:38,162 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:38,162 INFO L85 PathProgramCache]: Analyzing trace with hash -1635347557, now seen corresponding path program 1 times [2024-11-17 08:52:38,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:38,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [47773434] [2024-11-17 08:52:38,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:38,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:38,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:38,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:38,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:38,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [47773434] [2024-11-17 08:52:38,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [47773434] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:38,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:38,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:38,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328466240] [2024-11-17 08:52:38,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:38,248 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:38,248 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:38,248 INFO L85 PathProgramCache]: Analyzing trace with hash -1282047656, now seen corresponding path program 1 times [2024-11-17 08:52:38,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:38,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146020073] [2024-11-17 08:52:38,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:38,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:38,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:38,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:38,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:38,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146020073] [2024-11-17 08:52:38,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146020073] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:38,312 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:38,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:38,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789649126] [2024-11-17 08:52:38,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:38,313 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:38,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:38,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:38,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:38,313 INFO L87 Difference]: Start difference. First operand 66924 states and 94767 transitions. cyclomatic complexity: 27907 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:39,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:39,289 INFO L93 Difference]: Finished difference Result 153779 states and 216500 transitions. [2024-11-17 08:52:39,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153779 states and 216500 transitions. [2024-11-17 08:52:40,227 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 151864 [2024-11-17 08:52:40,962 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153779 states to 153779 states and 216500 transitions. [2024-11-17 08:52:40,962 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153779 [2024-11-17 08:52:41,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153779 [2024-11-17 08:52:41,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153779 states and 216500 transitions. [2024-11-17 08:52:41,204 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:41,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 153779 states and 216500 transitions. [2024-11-17 08:52:41,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153779 states and 216500 transitions. [2024-11-17 08:52:42,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153779 to 125147. [2024-11-17 08:52:42,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 125147 states, 125147 states have (on average 1.4127066569714017) internal successors, (176796), 125146 states have internal predecessors, (176796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125147 states to 125147 states and 176796 transitions. [2024-11-17 08:52:42,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 125147 states and 176796 transitions. [2024-11-17 08:52:42,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:42,913 INFO L425 stractBuchiCegarLoop]: Abstraction has 125147 states and 176796 transitions. [2024-11-17 08:52:42,913 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:52:42,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 125147 states and 176796 transitions. [2024-11-17 08:52:43,778 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 124128 [2024-11-17 08:52:43,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:43,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:43,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:43,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:43,780 INFO L745 eck$LassoCheckResult]: Stem: 463840#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 463173#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 463174#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 463235#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 463634#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 463465#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 463466#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 463693#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 463999#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 464041#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 464064#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 463293#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 463294#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 463153#L781-1 assume !(0 == ~M_E~0); 463154#L786-1 assume !(0 == ~T1_E~0); 463177#L791-1 assume !(0 == ~T2_E~0); 463178#L796-1 assume !(0 == ~T3_E~0); 463743#L801-1 assume !(0 == ~T4_E~0); 463744#L806-1 assume !(0 == ~T5_E~0); 463781#L811-1 assume !(0 == ~T6_E~0); 463425#L816-1 assume !(0 == ~T7_E~0); 463426#L821-1 assume !(0 == ~E_M~0); 463215#L826-1 assume !(0 == ~E_1~0); 463216#L831-1 assume !(0 == ~E_2~0); 463555#L836-1 assume !(0 == ~E_3~0); 463556#L841-1 assume !(0 == ~E_4~0); 463374#L846-1 assume !(0 == ~E_5~0); 463375#L851-1 assume !(0 == ~E_6~0); 463398#L856-1 assume !(0 == ~E_7~0); 463399#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 463543#L388-10 assume !(1 == ~m_pc~0); 463190#L398-10 is_master_triggered_~__retres1~0#1 := 0; 463191#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 464042#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 463825#L967-10 assume !(0 != activate_threads_~tmp~1#1); 463826#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 463385#L407-10 assume !(1 == ~t1_pc~0); 463231#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 463232#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 463221#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 463222#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 463175#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 463176#L426-10 assume !(1 == ~t2_pc~0); 463655#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 463656#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 463810#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 463165#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 463166#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 463516#L445-10 assume !(1 == ~t3_pc~0); 464081#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 463676#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 463677#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 464020#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 464098#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 464082#L464-10 assume !(1 == ~t4_pc~0); 463971#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 463860#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 463861#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 463578#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 463579#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 463955#L483-10 assume !(1 == ~t5_pc~0); 463437#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 463438#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 463479#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 463480#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 463635#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 463636#L502-10 assume !(1 == ~t6_pc~0); 463454#L512-10 is_transmit6_triggered_~__retres1~6#1 := 0; 463137#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 463138#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 463906#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 463907#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 463993#L521-10 assume !(1 == ~t7_pc~0); 463206#L531-10 is_transmit7_triggered_~__retres1~7#1 := 0; 463207#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 463653#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 463337#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 463338#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 463347#L869-1 assume 1 == ~M_E~0;~M_E~0 := 2; 463348#L874-1 assume !(1 == ~T1_E~0); 464109#L879-1 assume !(1 == ~T2_E~0); 463629#L884-1 assume !(1 == ~T3_E~0); 463630#L889-1 assume !(1 == ~T4_E~0); 463432#L894-1 assume !(1 == ~T5_E~0); 463433#L899-1 assume !(1 == ~T6_E~0); 463846#L904-1 assume !(1 == ~T7_E~0); 463581#L909-1 assume !(1 == ~E_M~0); 463582#L914-1 assume !(1 == ~E_1~0); 463790#L919-1 assume !(1 == ~E_2~0); 463791#L924-1 assume !(1 == ~E_3~0); 463328#L929-1 assume !(1 == ~E_4~0); 463329#L934-1 assume !(1 == ~E_5~0); 463566#L939-1 assume !(1 == ~E_6~0); 463567#L944-1 assume !(1 == ~E_7~0); 463244#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 463245#L1190 [2024-11-17 08:52:43,781 INFO L747 eck$LassoCheckResult]: Loop: 463245#L1190 assume true; 501783#L1190-1 assume !false; 501733#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 501731#L648 assume true; 501729#L648-1 assume !false; 501727#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 501678#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 501665#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 501659#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 501588#L653 assume !(0 != eval_~tmp~0#1); 501589#L656 assume true; 502045#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 502043#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 502041#L781 assume 0 == ~M_E~0;~M_E~0 := 1; 502038#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 502036#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 502034#L796 assume !(0 == ~T3_E~0); 502032#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 502030#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 502028#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 502027#L816 assume !(0 == ~T7_E~0); 502025#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 502023#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 502021#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 502019#L836 assume !(0 == ~E_3~0); 502017#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 502016#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 502014#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 502012#L856 assume !(0 == ~E_7~0); 502010#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 502008#L388-1 assume !(1 == ~m_pc~0); 502006#L398-1 is_master_triggered_~__retres1~0#1 := 0; 502004#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 502002#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 502000#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 501998#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 501996#L407-1 assume 1 == ~t1_pc~0; 501994#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 501991#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 501990#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 501988#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 501986#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 501984#L426-1 assume !(1 == ~t2_pc~0); 501982#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 501980#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 501978#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 501975#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 501973#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 501972#L445-1 assume !(1 == ~t3_pc~0); 501971#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 501962#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 501960#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 501958#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 501956#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 501954#L464-1 assume !(1 == ~t4_pc~0); 501953#L474-1 is_transmit4_triggered_~__retres1~4#1 := 0; 501952#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 501951#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 501950#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 501949#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 501948#L483-1 assume 1 == ~t5_pc~0; 501947#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 501945#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 501944#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 501943#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 501942#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 501940#L502-1 assume !(1 == ~t6_pc~0); 494008#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 501937#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 501935#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 501933#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 501931#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 501929#L521-1 assume !(1 == ~t7_pc~0); 477917#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 501925#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 501923#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 501921#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 501919#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 501917#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 493054#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 501914#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 501912#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 501910#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 501908#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 501906#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 501904#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 493040#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 501901#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 501899#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 501897#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 501895#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 501893#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 501891#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 501889#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 495215#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 501880#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 501873#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 501871#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 501815#L1209 assume !(0 == start_simulation_~tmp~3#1); 501813#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 501799#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 501795#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 501793#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 501791#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 501790#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501788#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 501786#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 463245#L1190 [2024-11-17 08:52:43,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,782 INFO L85 PathProgramCache]: Analyzing trace with hash -609437794, now seen corresponding path program 1 times [2024-11-17 08:52:43,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217537677] [2024-11-17 08:52:43,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:43,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:43,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:43,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217537677] [2024-11-17 08:52:43,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217537677] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:43,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:43,829 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:43,829 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127977161] [2024-11-17 08:52:43,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:43,829 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:43,830 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,830 INFO L85 PathProgramCache]: Analyzing trace with hash -1607550757, now seen corresponding path program 1 times [2024-11-17 08:52:43,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716637879] [2024-11-17 08:52:43,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:43,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:43,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:43,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716637879] [2024-11-17 08:52:43,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716637879] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:43,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:43,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:43,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473901153] [2024-11-17 08:52:43,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:43,879 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:43,879 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:43,880 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:43,880 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:43,880 INFO L87 Difference]: Start difference. First operand 125147 states and 176796 transitions. cyclomatic complexity: 51713 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:44,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:44,284 INFO L93 Difference]: Finished difference Result 157164 states and 222141 transitions. [2024-11-17 08:52:44,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 157164 states and 222141 transitions. [2024-11-17 08:52:45,422 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 155936 [2024-11-17 08:52:45,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 157164 states to 157164 states and 222141 transitions. [2024-11-17 08:52:45,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 157164 [2024-11-17 08:52:46,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 157164 [2024-11-17 08:52:46,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 157164 states and 222141 transitions. [2024-11-17 08:52:46,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:46,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 157164 states and 222141 transitions. [2024-11-17 08:52:46,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157164 states and 222141 transitions. [2024-11-17 08:52:47,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157164 to 67681. [2024-11-17 08:52:47,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67681 states, 67681 states have (on average 1.4204577355535526) internal successors, (96138), 67680 states have internal predecessors, (96138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67681 states to 67681 states and 96138 transitions. [2024-11-17 08:52:47,427 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67681 states and 96138 transitions. [2024-11-17 08:52:47,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:47,428 INFO L425 stractBuchiCegarLoop]: Abstraction has 67681 states and 96138 transitions. [2024-11-17 08:52:47,428 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:52:47,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67681 states and 96138 transitions. [2024-11-17 08:52:47,596 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67136 [2024-11-17 08:52:47,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:47,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:47,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,599 INFO L745 eck$LassoCheckResult]: Stem: 746179#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 745493#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 745494#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 745556#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 745957#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 745784#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 745785#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 746031#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 746337#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 746383#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 746405#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 745614#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 745615#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 745473#L781-1 assume !(0 == ~M_E~0); 745474#L786-1 assume !(0 == ~T1_E~0); 745497#L791-1 assume !(0 == ~T2_E~0); 745498#L796-1 assume !(0 == ~T3_E~0); 746083#L801-1 assume !(0 == ~T4_E~0); 746084#L806-1 assume !(0 == ~T5_E~0); 746121#L811-1 assume !(0 == ~T6_E~0); 745744#L816-1 assume !(0 == ~T7_E~0); 745745#L821-1 assume !(0 == ~E_M~0); 745536#L826-1 assume !(0 == ~E_1~0); 745537#L831-1 assume !(0 == ~E_2~0); 745875#L836-1 assume !(0 == ~E_3~0); 745876#L841-1 assume !(0 == ~E_4~0); 745695#L846-1 assume !(0 == ~E_5~0); 745696#L851-1 assume !(0 == ~E_6~0); 745719#L856-1 assume !(0 == ~E_7~0); 745720#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 745863#L388-10 assume !(1 == ~m_pc~0); 745511#L398-10 is_master_triggered_~__retres1~0#1 := 0; 745512#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 746387#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 746163#L967-10 assume !(0 != activate_threads_~tmp~1#1); 746164#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 745706#L407-10 assume !(1 == ~t1_pc~0); 745552#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 745553#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 745542#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 745543#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 745495#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 745496#L426-10 assume !(1 == ~t2_pc~0); 745978#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 745979#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 746148#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 745485#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 745486#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 745838#L445-10 assume !(1 == ~t3_pc~0); 746417#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 746009#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 746010#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 746361#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 746434#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 746418#L464-10 assume !(1 == ~t4_pc~0); 746311#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 746197#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 746198#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 745899#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 745900#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 746299#L483-10 assume !(1 == ~t5_pc~0); 745755#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 745756#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 745800#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 745801#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 745958#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 745959#L502-10 assume !(1 == ~t6_pc~0); 745773#L512-10 is_transmit6_triggered_~__retres1~6#1 := 0; 745457#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 745458#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 746239#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 746240#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 746328#L521-10 assume !(1 == ~t7_pc~0); 745527#L531-10 is_transmit7_triggered_~__retres1~7#1 := 0; 745528#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 745976#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 745659#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 745660#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 745668#L869-1 assume !(1 == ~M_E~0); 745669#L874-1 assume !(1 == ~T1_E~0); 746414#L879-1 assume !(1 == ~T2_E~0); 745952#L884-1 assume !(1 == ~T3_E~0); 745468#L889-1 assume !(1 == ~T4_E~0); 745469#L894-1 assume !(1 == ~T5_E~0); 745751#L899-1 assume !(1 == ~T6_E~0); 746183#L904-1 assume !(1 == ~T7_E~0); 745902#L909-1 assume !(1 == ~E_M~0); 745903#L914-1 assume !(1 == ~E_1~0); 746096#L919-1 assume !(1 == ~E_2~0); 745839#L924-1 assume !(1 == ~E_3~0); 745650#L929-1 assume !(1 == ~E_4~0); 745651#L934-1 assume !(1 == ~E_5~0); 745886#L939-1 assume !(1 == ~E_6~0); 745887#L944-1 assume !(1 == ~E_7~0); 745565#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 745566#L1190 [2024-11-17 08:52:47,600 INFO L747 eck$LassoCheckResult]: Loop: 745566#L1190 assume true; 770179#L1190-1 assume !false; 770171#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 770167#L648 assume true; 770163#L648-1 assume !false; 770160#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 770059#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 770049#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 770043#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 770036#L653 assume !(0 != eval_~tmp~0#1); 770037#L656 assume true; 789840#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 789839#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 789838#L781 assume !(0 == ~M_E~0); 789836#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 789834#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 789832#L796 assume !(0 == ~T3_E~0); 789830#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 789828#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 789826#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 789824#L816 assume !(0 == ~T7_E~0); 789822#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 789820#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 789818#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 789816#L836 assume !(0 == ~E_3~0); 789814#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 789812#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 789810#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 789808#L856 assume !(0 == ~E_7~0); 789806#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 789804#L388-1 assume !(1 == ~m_pc~0); 789802#L398-1 is_master_triggered_~__retres1~0#1 := 0; 789800#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 789798#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 789796#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 789794#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 789792#L407-1 assume !(1 == ~t1_pc~0); 789789#L417-1 is_transmit1_triggered_~__retres1~1#1 := 0; 789787#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 789785#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 789782#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 789780#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 789778#L426-1 assume !(1 == ~t2_pc~0); 789776#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 789774#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 789772#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 789770#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 789768#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 789766#L445-1 assume !(1 == ~t3_pc~0); 789764#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 789762#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 789750#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 789739#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 789728#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 789588#L464-1 assume !(1 == ~t4_pc~0); 789377#L474-1 is_transmit4_triggered_~__retres1~4#1 := 0; 789370#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 789369#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 789368#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 789367#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 789366#L483-1 assume 1 == ~t5_pc~0; 789364#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 789361#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 789359#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 789357#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 789355#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 789353#L502-1 assume !(1 == ~t6_pc~0); 773630#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 789350#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 789348#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 789347#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 789346#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 789345#L521-1 assume !(1 == ~t7_pc~0); 764429#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 789342#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 789340#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 789338#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 789336#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 789334#L869 assume !(1 == ~M_E~0); 753740#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 789331#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 789329#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 789328#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 789325#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 789323#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 789321#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 789319#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 789317#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 789315#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 789252#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 789244#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 789238#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 789231#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 789225#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 789219#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 787003#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 774869#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 763655#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 753892#L1209 assume !(0 == start_simulation_~tmp~3#1); 753893#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 770228#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 770220#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 770215#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 770211#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 770206#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 770200#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 770192#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 745566#L1190 [2024-11-17 08:52:47,600 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,601 INFO L85 PathProgramCache]: Analyzing trace with hash 743871903, now seen corresponding path program 1 times [2024-11-17 08:52:47,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679051372] [2024-11-17 08:52:47,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:47,612 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:47,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:47,660 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:47,661 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,661 INFO L85 PathProgramCache]: Analyzing trace with hash 178897662, now seen corresponding path program 1 times [2024-11-17 08:52:47,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1860779134] [2024-11-17 08:52:47,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,720 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1860779134] [2024-11-17 08:52:47,720 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1860779134] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,720 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,720 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:47,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [573204167] [2024-11-17 08:52:47,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,721 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:47,721 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:47,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:47,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:47,722 INFO L87 Difference]: Start difference. First operand 67681 states and 96138 transitions. cyclomatic complexity: 28473 Second operand has 5 states, 5 states have (on average 21.4) internal successors, (107), 5 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:48,476 INFO L93 Difference]: Finished difference Result 68577 states and 97034 transitions. [2024-11-17 08:52:48,476 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68577 states and 97034 transitions. [2024-11-17 08:52:48,757 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 68032 [2024-11-17 08:52:48,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68577 states to 68577 states and 97034 transitions. [2024-11-17 08:52:48,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68577 [2024-11-17 08:52:48,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68577 [2024-11-17 08:52:48,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68577 states and 97034 transitions. [2024-11-17 08:52:49,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:49,039 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68577 states and 97034 transitions. [2024-11-17 08:52:49,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68577 states and 97034 transitions. [2024-11-17 08:52:50,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68577 to 68065. [2024-11-17 08:52:50,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68065 states, 68065 states have (on average 1.4180856534195254) internal successors, (96522), 68064 states have internal predecessors, (96522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:50,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68065 states to 68065 states and 96522 transitions. [2024-11-17 08:52:50,496 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68065 states and 96522 transitions. [2024-11-17 08:52:50,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:50,497 INFO L425 stractBuchiCegarLoop]: Abstraction has 68065 states and 96522 transitions. [2024-11-17 08:52:50,497 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:52:50,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68065 states and 96522 transitions. [2024-11-17 08:52:50,704 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67520 [2024-11-17 08:52:50,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:50,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:50,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:50,706 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:50,706 INFO L745 eck$LassoCheckResult]: Stem: 882446#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 881759#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 881760#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 881822#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 882231#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 882052#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 882053#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 882297#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 882618#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 882667#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 882692#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 881881#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 881882#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 881739#L781-1 assume !(0 == ~M_E~0); 881740#L786-1 assume !(0 == ~T1_E~0); 881763#L791-1 assume !(0 == ~T2_E~0); 881764#L796-1 assume !(0 == ~T3_E~0); 882351#L801-1 assume !(0 == ~T4_E~0); 882352#L806-1 assume !(0 == ~T5_E~0); 882390#L811-1 assume !(0 == ~T6_E~0); 882010#L816-1 assume !(0 == ~T7_E~0); 882011#L821-1 assume !(0 == ~E_M~0); 881802#L826-1 assume !(0 == ~E_1~0); 881803#L831-1 assume !(0 == ~E_2~0); 882146#L836-1 assume !(0 == ~E_3~0); 882147#L841-1 assume !(0 == ~E_4~0); 881960#L846-1 assume !(0 == ~E_5~0); 881961#L851-1 assume !(0 == ~E_6~0); 881983#L856-1 assume !(0 == ~E_7~0); 881984#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 882131#L388-10 assume !(1 == ~m_pc~0); 881777#L398-10 is_master_triggered_~__retres1~0#1 := 0; 881778#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 882668#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 882432#L967-10 assume !(0 != activate_threads_~tmp~1#1); 882433#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 881971#L407-10 assume !(1 == ~t1_pc~0); 881818#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 881819#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 881808#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 881809#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 881761#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 881762#L426-10 assume !(1 == ~t2_pc~0); 882253#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 882254#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 882416#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 881751#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 881752#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 882104#L445-10 assume !(1 == ~t3_pc~0); 882711#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 882276#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 882277#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 882643#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 882729#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 882712#L464-10 assume !(1 == ~t4_pc~0); 882584#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 882467#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 882468#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 882171#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 882172#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 882571#L483-10 assume !(1 == ~t5_pc~0); 882021#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 882022#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 882065#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 882066#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 882232#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 882233#L502-10 assume !(1 == ~t6_pc~0); 882039#L512-10 is_transmit6_triggered_~__retres1~6#1 := 0; 881723#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 881724#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 882507#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 882508#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 882611#L521-10 assume !(1 == ~t7_pc~0); 881793#L531-10 is_transmit7_triggered_~__retres1~7#1 := 0; 881794#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 882251#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 881925#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 881926#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 881934#L869-1 assume !(1 == ~M_E~0); 881935#L874-1 assume !(1 == ~T1_E~0); 882702#L879-1 assume !(1 == ~T2_E~0); 882226#L884-1 assume !(1 == ~T3_E~0); 881734#L889-1 assume !(1 == ~T4_E~0); 881735#L894-1 assume !(1 == ~T5_E~0); 882017#L899-1 assume !(1 == ~T6_E~0); 882452#L904-1 assume !(1 == ~T7_E~0); 882174#L909-1 assume !(1 == ~E_M~0); 882175#L914-1 assume !(1 == ~E_1~0); 882367#L919-1 assume !(1 == ~E_2~0); 882105#L924-1 assume !(1 == ~E_3~0); 881916#L929-1 assume !(1 == ~E_4~0); 881917#L934-1 assume !(1 == ~E_5~0); 882157#L939-1 assume !(1 == ~E_6~0); 882158#L944-1 assume !(1 == ~E_7~0); 881831#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 881832#L1190 [2024-11-17 08:52:50,706 INFO L747 eck$LassoCheckResult]: Loop: 881832#L1190 assume true; 901547#L1190-1 assume !false; 901537#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 901527#L648 assume true; 901523#L648-1 assume !false; 901511#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 899415#L596-2 assume !(0 == ~m_st~0); 899416#L600-2 assume !(0 == ~t1_st~0); 899417#L604-2 assume !(0 == ~t2_st~0); 899418#L608-2 assume !(0 == ~t3_st~0); 899410#L612-2 assume !(0 == ~t4_st~0); 899411#L616-2 assume !(0 == ~t5_st~0); 899412#L620-2 assume !(0 == ~t6_st~0); 899413#L624-2 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 899414#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 903141#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 903132#L653 assume !(0 != eval_~tmp~0#1); 903130#L656 assume true; 903129#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 903127#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 903125#L781 assume !(0 == ~M_E~0); 903123#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 903121#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 903119#L796 assume !(0 == ~T3_E~0); 903117#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 903115#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 903114#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 903113#L816 assume !(0 == ~T7_E~0); 903112#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 903111#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 903110#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 903108#L836 assume !(0 == ~E_3~0); 902815#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 902813#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 902811#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 902809#L856 assume !(0 == ~E_7~0); 902807#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 902804#L388-1 assume !(1 == ~m_pc~0); 902805#L398-1 is_master_triggered_~__retres1~0#1 := 0; 902798#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 902799#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 902792#L967-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 902793#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 902785#L407-1 assume !(1 == ~t1_pc~0); 902787#L417-1 is_transmit1_triggered_~__retres1~1#1 := 0; 902778#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 902779#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 902772#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 902773#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 902766#L426-1 assume !(1 == ~t2_pc~0); 902767#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 902760#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 902761#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 902754#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 902755#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 902748#L445-1 assume !(1 == ~t3_pc~0); 902749#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 902741#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 902742#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 902735#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 902736#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 902729#L464-1 assume !(1 == ~t4_pc~0); 902730#L474-1 is_transmit4_triggered_~__retres1~4#1 := 0; 902723#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 902724#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 902938#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 902936#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 902712#L483-1 assume 1 == ~t5_pc~0; 902713#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 902584#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 902585#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 902576#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 902577#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 902569#L502-1 assume !(1 == ~t6_pc~0); 900894#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 902561#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 902562#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 902551#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 902552#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 902361#L521-1 assume !(1 == ~t7_pc~0); 902359#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 902357#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 902355#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 902353#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 902350#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 902347#L869 assume !(1 == ~M_E~0); 902343#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 902341#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 902339#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 902337#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 902334#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 902332#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 902330#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 902328#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 902326#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 902324#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 902322#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 902320#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 902318#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 902316#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 902314#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 902312#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 902308#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 902301#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 902299#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 902295#L1209 assume !(0 == start_simulation_~tmp~3#1); 902294#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 902284#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 902242#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 901570#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 901567#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 901564#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 901559#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 901555#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 881832#L1190 [2024-11-17 08:52:50,707 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:50,707 INFO L85 PathProgramCache]: Analyzing trace with hash 743871903, now seen corresponding path program 2 times [2024-11-17 08:52:50,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:50,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856747737] [2024-11-17 08:52:50,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:50,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:50,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:50,720 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:50,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:50,748 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:50,749 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:50,749 INFO L85 PathProgramCache]: Analyzing trace with hash 858650450, now seen corresponding path program 1 times [2024-11-17 08:52:50,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:50,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [203018332] [2024-11-17 08:52:50,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:50,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:50,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:50,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:50,824 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:50,824 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [203018332] [2024-11-17 08:52:50,824 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [203018332] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:50,824 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:50,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:50,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654173448] [2024-11-17 08:52:50,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:50,825 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:50,825 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:50,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:50,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:50,826 INFO L87 Difference]: Start difference. First operand 68065 states and 96522 transitions. cyclomatic complexity: 28473 Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:51,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:51,201 INFO L93 Difference]: Finished difference Result 69409 states and 97481 transitions. [2024-11-17 08:52:51,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69409 states and 97481 transitions. [2024-11-17 08:52:51,427 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 68864 [2024-11-17 08:52:51,570 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69409 states to 69409 states and 97481 transitions. [2024-11-17 08:52:51,570 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69409 [2024-11-17 08:52:51,615 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69409 [2024-11-17 08:52:51,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69409 states and 97481 transitions. [2024-11-17 08:52:51,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:51,653 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69409 states and 97481 transitions. [2024-11-17 08:52:51,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69409 states and 97481 transitions. [2024-11-17 08:52:52,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69409 to 69409. [2024-11-17 08:52:52,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69409 states, 69409 states have (on average 1.404443227823481) internal successors, (97481), 69408 states have internal predecessors, (97481), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:52,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69409 states to 69409 states and 97481 transitions. [2024-11-17 08:52:52,897 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69409 states and 97481 transitions. [2024-11-17 08:52:52,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:52,898 INFO L425 stractBuchiCegarLoop]: Abstraction has 69409 states and 97481 transitions. [2024-11-17 08:52:52,898 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:52:52,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69409 states and 97481 transitions. [2024-11-17 08:52:53,064 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 68864 [2024-11-17 08:52:53,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:53,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:53,066 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:53,066 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:53,066 INFO L745 eck$LassoCheckResult]: Stem: 1019914#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1019241#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1019242#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1019305#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1019702#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1019534#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1019535#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1019766#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1020081#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1020133#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1020160#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1019363#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1019364#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1019221#L781-1 assume !(0 == ~M_E~0); 1019222#L786-1 assume !(0 == ~T1_E~0); 1019245#L791-1 assume !(0 == ~T2_E~0); 1019246#L796-1 assume !(0 == ~T3_E~0); 1019818#L801-1 assume !(0 == ~T4_E~0); 1019819#L806-1 assume !(0 == ~T5_E~0); 1019855#L811-1 assume !(0 == ~T6_E~0); 1019495#L816-1 assume !(0 == ~T7_E~0); 1019496#L821-1 assume !(0 == ~E_M~0); 1019284#L826-1 assume !(0 == ~E_1~0); 1019285#L831-1 assume !(0 == ~E_2~0); 1019626#L836-1 assume !(0 == ~E_3~0); 1019627#L841-1 assume !(0 == ~E_4~0); 1019444#L846-1 assume !(0 == ~E_5~0); 1019445#L851-1 assume !(0 == ~E_6~0); 1019467#L856-1 assume !(0 == ~E_7~0); 1019468#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1019611#L388-10 assume !(1 == ~m_pc~0); 1019259#L398-10 is_master_triggered_~__retres1~0#1 := 0; 1019260#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1020136#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1019896#L967-10 assume !(0 != activate_threads_~tmp~1#1); 1019897#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1019455#L407-10 assume !(1 == ~t1_pc~0); 1019301#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 1019302#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1019290#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1019291#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 1019243#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1019244#L426-10 assume !(1 == ~t2_pc~0); 1019723#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 1019724#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1019879#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1019233#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 1019234#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1019585#L445-10 assume !(1 == ~t3_pc~0); 1020175#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 1019747#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1019748#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1020103#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 1020199#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1020176#L464-10 assume !(1 == ~t4_pc~0); 1020046#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 1019936#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1019937#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1019649#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 1019650#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1020038#L483-10 assume !(1 == ~t5_pc~0); 1019506#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 1019507#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1019547#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1019548#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 1019703#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1019704#L502-10 assume !(1 == ~t6_pc~0); 1019523#L512-10 is_transmit6_triggered_~__retres1~6#1 := 0; 1019205#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1019206#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1019985#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 1019986#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1020074#L521-10 assume !(1 == ~t7_pc~0); 1019275#L531-10 is_transmit7_triggered_~__retres1~7#1 := 0; 1019276#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1019721#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1019409#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 1019410#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1019418#L869-1 assume !(1 == ~M_E~0); 1019419#L874-1 assume !(1 == ~T1_E~0); 1020172#L879-1 assume !(1 == ~T2_E~0); 1019698#L884-1 assume !(1 == ~T3_E~0); 1019216#L889-1 assume !(1 == ~T4_E~0); 1019217#L894-1 assume !(1 == ~T5_E~0); 1019502#L899-1 assume !(1 == ~T6_E~0); 1019922#L904-1 assume !(1 == ~T7_E~0); 1019652#L909-1 assume !(1 == ~E_M~0); 1019653#L914-1 assume !(1 == ~E_1~0); 1019831#L919-1 assume !(1 == ~E_2~0); 1019586#L924-1 assume !(1 == ~E_3~0); 1019400#L929-1 assume !(1 == ~E_4~0); 1019401#L934-1 assume !(1 == ~E_5~0); 1019636#L939-1 assume !(1 == ~E_6~0); 1019637#L944-1 assume !(1 == ~E_7~0); 1019314#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 1019315#L1190 [2024-11-17 08:52:53,067 INFO L747 eck$LassoCheckResult]: Loop: 1019315#L1190 assume true; 1037304#L1190-1 assume !false; 1035776#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1035774#L648 assume true; 1035772#L648-1 assume !false; 1035770#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1035734#L596-2 assume !(0 == ~m_st~0); 1035735#L600-2 assume !(0 == ~t1_st~0); 1035736#L604-2 assume !(0 == ~t2_st~0); 1035737#L608-2 assume !(0 == ~t3_st~0); 1035729#L612-2 assume !(0 == ~t4_st~0); 1035730#L616-2 assume !(0 == ~t5_st~0); 1035731#L620-2 assume !(0 == ~t6_st~0); 1035732#L624-2 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1035733#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1035723#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1035724#L653 assume !(0 != eval_~tmp~0#1); 1041601#L656 assume true; 1041598#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1041593#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1041591#L781 assume !(0 == ~M_E~0); 1041589#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1041587#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1041585#L796 assume !(0 == ~T3_E~0); 1041582#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1041580#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1041575#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1041569#L816 assume !(0 == ~T7_E~0); 1041563#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 1041558#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 1041550#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 1041544#L836 assume !(0 == ~E_3~0); 1041538#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 1041532#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 1041525#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 1041518#L856 assume !(0 == ~E_7~0); 1041512#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1041505#L388-1 assume !(1 == ~m_pc~0); 1041499#L398-1 is_master_triggered_~__retres1~0#1 := 0; 1041492#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1041485#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1041479#L967-1 assume !(0 != activate_threads_~tmp~1#1); 1041473#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1041467#L407-1 assume 1 == ~t1_pc~0; 1041461#L408-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1041454#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1041449#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1041435#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1041425#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1041416#L426-1 assume !(1 == ~t2_pc~0); 1041406#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1041160#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1041153#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1041136#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1041133#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1041129#L445-1 assume !(1 == ~t3_pc~0); 1041125#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1041121#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1038329#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1038324#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1038319#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1038313#L464-1 assume !(1 == ~t4_pc~0); 1038308#L474-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1038301#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1038293#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1038286#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1038279#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1038271#L483-1 assume 1 == ~t5_pc~0; 1038265#L484-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1038258#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1038251#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1038241#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1038231#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1038223#L502-1 assume !(1 == ~t6_pc~0); 1036171#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1038210#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1038202#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1038200#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1038198#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1038196#L521-1 assume !(1 == ~t7_pc~0); 1034412#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1038193#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1038191#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1038183#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1038092#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1037731#L869 assume !(1 == ~M_E~0); 1037727#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1037725#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1037723#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1037720#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1037718#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1037716#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1037714#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1037712#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 1037710#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 1037709#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 1037707#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 1037705#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 1037703#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 1037692#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 1037682#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 1037674#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1037578#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1037565#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1037559#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1037553#L1209 assume !(0 == start_simulation_~tmp~3#1); 1037549#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1037321#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1037317#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1037315#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1037313#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1037311#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1037309#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1037307#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1019315#L1190 [2024-11-17 08:52:53,067 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:53,067 INFO L85 PathProgramCache]: Analyzing trace with hash 743871903, now seen corresponding path program 3 times [2024-11-17 08:52:53,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:53,067 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988655009] [2024-11-17 08:52:53,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:53,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:53,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:53,078 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:52:53,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:52:53,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:52:53,108 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:53,108 INFO L85 PathProgramCache]: Analyzing trace with hash -1999705008, now seen corresponding path program 1 times [2024-11-17 08:52:53,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:53,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399824610] [2024-11-17 08:52:53,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:53,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:53,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:53,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:53,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:53,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399824610] [2024-11-17 08:52:53,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399824610] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:53,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:53,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:53,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482800681] [2024-11-17 08:52:53,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:53,148 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:53,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:53,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:53,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:53,149 INFO L87 Difference]: Start difference. First operand 69409 states and 97481 transitions. cyclomatic complexity: 28088 Second operand has 3 states, 3 states have (on average 38.0) internal successors, (114), 3 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:53,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:53,943 INFO L93 Difference]: Finished difference Result 112016 states and 155055 transitions. [2024-11-17 08:52:53,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112016 states and 155055 transitions. [2024-11-17 08:52:54,349 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 111200 [2024-11-17 08:52:54,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112016 states to 112016 states and 155055 transitions. [2024-11-17 08:52:54,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 112016 [2024-11-17 08:52:54,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 112016 [2024-11-17 08:52:54,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 112016 states and 155055 transitions. [2024-11-17 08:52:54,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:54,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 112016 states and 155055 transitions. [2024-11-17 08:52:54,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112016 states and 155055 transitions. [2024-11-17 08:52:56,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112016 to 108912. [2024-11-17 08:52:56,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108912 states, 108912 states have (on average 1.3857701630674306) internal successors, (150927), 108911 states have internal predecessors, (150927), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:56,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108912 states to 108912 states and 150927 transitions. [2024-11-17 08:52:56,354 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108912 states and 150927 transitions. [2024-11-17 08:52:56,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:56,355 INFO L425 stractBuchiCegarLoop]: Abstraction has 108912 states and 150927 transitions. [2024-11-17 08:52:56,355 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:52:56,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108912 states and 150927 transitions. [2024-11-17 08:52:56,691 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 108096 [2024-11-17 08:52:56,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:56,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:56,694 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:56,694 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:56,695 INFO L745 eck$LassoCheckResult]: Stem: 1201373#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1200672#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1200673#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1200734#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1201142#L548 assume !(1 == ~m_i~0);~m_st~0 := 2; 1201760#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1201211#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1201212#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1201618#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1201619#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1201750#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1201751#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1201528#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1201529#L781-1 assume !(0 == ~M_E~0); 1201795#L786-1 assume !(0 == ~T1_E~0); 1201796#L791-1 assume !(0 == ~T2_E~0); 1201305#L796-1 assume !(0 == ~T3_E~0); 1201306#L801-1 assume !(0 == ~T4_E~0); 1201313#L806-1 assume !(0 == ~T5_E~0); 1201314#L811-1 assume !(0 == ~T6_E~0); 1200921#L816-1 assume !(0 == ~T7_E~0); 1200922#L821-1 assume !(0 == ~E_M~0); 1200714#L826-1 assume !(0 == ~E_1~0); 1200715#L831-1 assume !(0 == ~E_2~0); 1201060#L836-1 assume !(0 == ~E_3~0); 1201061#L841-1 assume !(0 == ~E_4~0); 1200870#L846-1 assume !(0 == ~E_5~0); 1200871#L851-1 assume !(0 == ~E_6~0); 1200895#L856-1 assume !(0 == ~E_7~0); 1200896#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1201546#L388-10 assume !(1 == ~m_pc~0); 1201547#L398-10 is_master_triggered_~__retres1~0#1 := 0; 1201624#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1201625#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1201357#L967-10 assume !(0 != activate_threads_~tmp~1#1); 1201358#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1200881#L407-10 assume !(1 == ~t1_pc~0); 1200882#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 1201719#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1201720#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1201260#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 1201261#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1201217#L426-10 assume !(1 == ~t2_pc~0); 1201218#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 1201467#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1201468#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1200664#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 1200665#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1201698#L445-10 assume !(1 == ~t3_pc~0); 1201699#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 1201190#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1201191#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1201702#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 1201703#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1201678#L464-10 assume !(1 == ~t4_pc~0); 1201679#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 1201395#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1201396#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1201086#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 1201087#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1201764#L483-10 assume !(1 == ~t5_pc~0); 1201765#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 1201307#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1201308#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1201215#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 1201216#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1201397#L502-10 assume !(1 == ~t6_pc~0); 1201398#L512-10 is_transmit6_triggered_~__retres1~6#1 := 0; 1200636#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1200637#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1201445#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 1201446#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1201554#L521-10 assume !(1 == ~t7_pc~0); 1201555#L531-10 is_transmit7_triggered_~__retres1~7#1 := 0; 1201162#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1201163#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1200834#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 1200835#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1200843#L869-1 assume !(1 == ~M_E~0); 1200844#L874-1 assume !(1 == ~T1_E~0); 1201667#L879-1 assume !(1 == ~T2_E~0); 1201668#L884-1 assume !(1 == ~T3_E~0); 1200647#L889-1 assume !(1 == ~T4_E~0); 1200648#L894-1 assume !(1 == ~T5_E~0); 1201781#L899-1 assume !(1 == ~T6_E~0); 1201782#L904-1 assume !(1 == ~T7_E~0); 1201089#L909-1 assume !(1 == ~E_M~0); 1201090#L914-1 assume !(1 == ~E_1~0); 1201322#L919-1 assume !(1 == ~E_2~0); 1201323#L924-1 assume !(1 == ~E_3~0); 1200825#L929-1 assume !(1 == ~E_4~0); 1200826#L934-1 assume !(1 == ~E_5~0); 1201072#L939-1 assume !(1 == ~E_6~0); 1201073#L944-1 assume !(1 == ~E_7~0); 1200743#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 1200744#L1190 [2024-11-17 08:52:56,695 INFO L747 eck$LassoCheckResult]: Loop: 1200744#L1190 assume true; 1229576#L1190-1 assume !false; 1229562#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1229560#L648 assume true; 1229558#L648-1 assume !false; 1229556#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1229555#L596-2 assume !(0 == ~m_st~0); 1223326#L600-2 assume !(0 == ~t1_st~0); 1229285#L604-2 assume !(0 == ~t2_st~0); 1229286#L608-2 assume !(0 == ~t3_st~0); 1229280#L612-2 assume !(0 == ~t4_st~0); 1229281#L616-2 assume !(0 == ~t5_st~0); 1229282#L620-2 assume !(0 == ~t6_st~0); 1229283#L624-2 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 1229284#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1236435#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1236433#L653 assume !(0 != eval_~tmp~0#1); 1236431#L656 assume true; 1236430#L774 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1236428#L541 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1236427#L781 assume !(0 == ~M_E~0); 1236426#L786 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1236425#L791 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1236424#L796 assume !(0 == ~T3_E~0); 1236416#L801 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1236414#L806 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1236412#L811 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1236410#L816 assume !(0 == ~T7_E~0); 1236408#L821 assume 0 == ~E_M~0;~E_M~0 := 1; 1236406#L826 assume 0 == ~E_1~0;~E_1~0 := 1; 1236404#L831 assume 0 == ~E_2~0;~E_2~0 := 1; 1236402#L836 assume !(0 == ~E_3~0); 1236400#L841 assume 0 == ~E_4~0;~E_4~0 := 1; 1236399#L846 assume 0 == ~E_5~0;~E_5~0 := 1; 1236397#L851 assume 0 == ~E_6~0;~E_6~0 := 1; 1236392#L856 assume !(0 == ~E_7~0); 1236390#L862 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1236388#L388-1 assume !(1 == ~m_pc~0); 1236386#L398-1 is_master_triggered_~__retres1~0#1 := 0; 1236384#L391-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1236381#L400-1 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1236379#L967-1 assume !(0 != activate_threads_~tmp~1#1); 1236377#L973-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1236375#L407-1 assume !(1 == ~t1_pc~0); 1236372#L417-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1236369#L410-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1236365#L419-1 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1236363#L975-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1236361#L981-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1236359#L426-1 assume !(1 == ~t2_pc~0); 1217761#L436-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1217762#L429-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1217755#L438-1 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1217756#L983-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1217749#L989-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1217750#L445-1 assume !(1 == ~t3_pc~0); 1217743#L455-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1217744#L448-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1217737#L457-1 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1217738#L991-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1217731#L997-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1217732#L464-1 assume !(1 == ~t4_pc~0); 1217725#L474-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1217726#L467-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1217719#L476-1 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1217720#L999-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1217713#L1005-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1217714#L483-1 assume !(1 == ~t5_pc~0); 1232659#L493-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1217704#L486-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1217705#L495-1 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1217697#L1007-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1217698#L1013-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1216322#L502-1 assume !(1 == ~t6_pc~0); 1216317#L512-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1216312#L505-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1216307#L514-1 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1216303#L1015-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1216302#L1021-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1216278#L521-1 assume !(1 == ~t7_pc~0); 1211146#L531-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1216263#L524-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1216260#L533-1 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1216259#L1023-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1216258#L1029-1 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1216256#L869 assume !(1 == ~M_E~0); 1215888#L874 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1216253#L879 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1216251#L884 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1216249#L889 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1216247#L894 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1216245#L899 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1216242#L904 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1216240#L909 assume 1 == ~E_M~0;~E_M~0 := 2; 1216238#L914 assume 1 == ~E_1~0;~E_1~0 := 2; 1216235#L919 assume 1 == ~E_2~0;~E_2~0 := 2; 1216233#L924 assume 1 == ~E_3~0;~E_3~0 := 2; 1216231#L929 assume 1 == ~E_4~0;~E_4~0 := 2; 1216229#L934 assume 1 == ~E_5~0;~E_5~0 := 2; 1216227#L939 assume 1 == ~E_6~0;~E_6~0 := 2; 1216225#L944 assume 1 == ~E_7~0;~E_7~0 := 2; 1216223#L950 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1216222#L596-1 assume !(0 == ~m_st~0); 1216149#L600-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1216140#L626-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1216137#L639-1 assume true;start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1216131#L1209 assume !(0 == start_simulation_~tmp~3#1); 1216132#L1220 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1229600#L596 assume !(0 == ~m_st~0); 1229592#L600 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1229588#L626 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1229587#L639 assume true;stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1229585#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1229583#L1166 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1229581#L1172 assume true;start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1229579#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1200744#L1190 [2024-11-17 08:52:56,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:56,696 INFO L85 PathProgramCache]: Analyzing trace with hash -226419104, now seen corresponding path program 1 times [2024-11-17 08:52:56,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:56,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524165027] [2024-11-17 08:52:56,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:56,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:56,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:56,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:56,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:56,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524165027] [2024-11-17 08:52:56,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524165027] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:56,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:56,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:56,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [895781285] [2024-11-17 08:52:56,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:56,728 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:56,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:56,728 INFO L85 PathProgramCache]: Analyzing trace with hash -295467071, now seen corresponding path program 1 times [2024-11-17 08:52:56,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:56,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018970390] [2024-11-17 08:52:56,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:56,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:56,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:56,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:56,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:56,804 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018970390] [2024-11-17 08:52:56,804 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018970390] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:56,804 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:56,805 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:56,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249209869] [2024-11-17 08:52:56,805 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:56,805 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:56,805 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:56,806 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:56,806 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:56,806 INFO L87 Difference]: Start difference. First operand 108912 states and 150927 transitions. cyclomatic complexity: 42039 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:57,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:57,833 INFO L93 Difference]: Finished difference Result 108820 states and 150795 transitions. [2024-11-17 08:52:57,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108820 states and 150795 transitions. [2024-11-17 08:52:58,223 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 108096 [2024-11-17 08:52:58,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108820 states to 108820 states and 150795 transitions. [2024-11-17 08:52:58,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108820 [2024-11-17 08:52:58,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108820 [2024-11-17 08:52:58,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108820 states and 150795 transitions. [2024-11-17 08:52:58,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:58,549 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108820 states and 150795 transitions. [2024-11-17 08:52:58,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108820 states and 150795 transitions. [2024-11-17 08:52:59,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108820 to 108820. [2024-11-17 08:52:59,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108820 states, 108820 states have (on average 1.3857287263370703) internal successors, (150795), 108819 states have internal predecessors, (150795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108820 states to 108820 states and 150795 transitions. [2024-11-17 08:52:59,979 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108820 states and 150795 transitions. [2024-11-17 08:52:59,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:59,980 INFO L425 stractBuchiCegarLoop]: Abstraction has 108820 states and 150795 transitions. [2024-11-17 08:52:59,980 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:52:59,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108820 states and 150795 transitions. [2024-11-17 08:53:00,264 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 108096 [2024-11-17 08:53:00,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:00,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:00,265 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,265 INFO L745 eck$LassoCheckResult]: Stem: 1419093#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1418413#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1418414#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1418475#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1418882#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1418702#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1418703#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1418949#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1419263#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1419316#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1419344#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1418535#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1418536#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1418393#L781-1 assume !(0 == ~M_E~0); 1418394#L786-1 assume !(0 == ~T1_E~0); 1418420#L791-1 assume !(0 == ~T2_E~0); 1418421#L796-1 assume !(0 == ~T3_E~0); 1419004#L801-1 assume !(0 == ~T4_E~0); 1419005#L806-1 assume !(0 == ~T5_E~0); 1419036#L811-1 assume !(0 == ~T6_E~0); 1418666#L816-1 assume !(0 == ~T7_E~0); 1418667#L821-1 assume !(0 == ~E_M~0); 1418455#L826-1 assume !(0 == ~E_1~0); 1418456#L831-1 assume !(0 == ~E_2~0); 1418797#L836-1 assume !(0 == ~E_3~0); 1418798#L841-1 assume !(0 == ~E_4~0); 1418616#L846-1 assume !(0 == ~E_5~0); 1418617#L851-1 assume !(0 == ~E_6~0); 1418637#L856-1 assume !(0 == ~E_7~0); 1418638#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1418784#L388-10 assume !(1 == ~m_pc~0); 1418432#L398-10 is_master_triggered_~__retres1~0#1 := 0; 1418433#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1419317#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1419076#L967-10 assume !(0 != activate_threads_~tmp~1#1); 1419077#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1418625#L407-10 assume !(1 == ~t1_pc~0); 1418473#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 1418474#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1418463#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1418464#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 1418415#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1418416#L426-10 assume !(1 == ~t2_pc~0); 1418904#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 1418905#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1419062#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1418407#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 1418408#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1418757#L445-10 assume !(1 == ~t3_pc~0); 1419361#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 1418930#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1418931#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1419289#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 1419378#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1419363#L464-10 assume !(1 == ~t4_pc~0); 1419229#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 1419113#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1419114#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1418822#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 1418823#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1419213#L483-10 assume !(1 == ~t5_pc~0); 1418675#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 1418676#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1418721#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1418722#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 1418883#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1418884#L502-10 assume !(1 == ~t6_pc~0); 1418691#L512-10 is_transmit6_triggered_~__retres1~6#1 := 0; 1418377#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1418378#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1419159#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 1419160#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1419256#L521-10 assume !(1 == ~t7_pc~0); 1418446#L531-10 is_transmit7_triggered_~__retres1~7#1 := 0; 1418447#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1418902#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1418580#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 1418581#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1418590#L869-1 assume !(1 == ~M_E~0); 1418591#L874-1 assume !(1 == ~T1_E~0); 1419356#L879-1 assume !(1 == ~T2_E~0); 1418877#L884-1 assume !(1 == ~T3_E~0); 1418388#L889-1 assume !(1 == ~T4_E~0); 1418389#L894-1 assume !(1 == ~T5_E~0); 1418674#L899-1 assume !(1 == ~T6_E~0); 1419099#L904-1 assume !(1 == ~T7_E~0); 1418826#L909-1 assume !(1 == ~E_M~0); 1418827#L914-1 assume !(1 == ~E_1~0); 1419016#L919-1 assume !(1 == ~E_2~0); 1418758#L924-1 assume !(1 == ~E_3~0); 1418569#L929-1 assume !(1 == ~E_4~0); 1418570#L934-1 assume !(1 == ~E_5~0); 1418810#L939-1 assume !(1 == ~E_6~0); 1418811#L944-1 assume !(1 == ~E_7~0); 1418484#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 1418485#L1190 assume true; 1425137#L1190-1 assume !false; 1425126#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1425124#L648 [2024-11-17 08:53:00,266 INFO L747 eck$LassoCheckResult]: Loop: 1425124#L648 assume true; 1425122#L648-1 assume !false; 1425120#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1425117#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1425114#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1425112#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1425084#L653 assume 0 != eval_~tmp~0#1; 1425078#L658-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1425072#L661 assume !(0 != eval_~tmp_ndt_1~0#1); 1425065#L658 havoc eval_~tmp_ndt_1~0#1; 1425059#L672-1 assume !(0 == ~t1_st~0); 1425054#L686-1 assume !(0 == ~t2_st~0); 1425055#L700-1 assume !(0 == ~t3_st~0); 1425243#L714-1 assume !(0 == ~t4_st~0); 1425241#L728-1 assume !(0 == ~t5_st~0); 1425134#L742-1 assume !(0 == ~t6_st~0); 1425127#L756-1 assume !(0 == ~t7_st~0); 1425124#L648 [2024-11-17 08:53:00,266 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,266 INFO L85 PathProgramCache]: Analyzing trace with hash -1341979033, now seen corresponding path program 1 times [2024-11-17 08:53:00,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504683941] [2024-11-17 08:53:00,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:00,277 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:00,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:00,297 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:00,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,298 INFO L85 PathProgramCache]: Analyzing trace with hash -2041266005, now seen corresponding path program 1 times [2024-11-17 08:53:00,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338829490] [2024-11-17 08:53:00,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:00,302 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:00,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:00,307 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:00,307 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,307 INFO L85 PathProgramCache]: Analyzing trace with hash 975082245, now seen corresponding path program 1 times [2024-11-17 08:53:00,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388141845] [2024-11-17 08:53:00,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388141845] [2024-11-17 08:53:00,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388141845] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,346 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:00,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485835559] [2024-11-17 08:53:00,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:00,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:00,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:00,456 INFO L87 Difference]: Start difference. First operand 108820 states and 150795 transitions. cyclomatic complexity: 41999 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:01,769 INFO L93 Difference]: Finished difference Result 205284 states and 281931 transitions. [2024-11-17 08:53:01,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205284 states and 281931 transitions. [2024-11-17 08:53:02,479 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 203936 [2024-11-17 08:53:02,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205284 states to 205284 states and 281931 transitions. [2024-11-17 08:53:02,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 205284 [2024-11-17 08:53:03,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 205284 [2024-11-17 08:53:03,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 205284 states and 281931 transitions. [2024-11-17 08:53:03,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:03,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 205284 states and 281931 transitions. [2024-11-17 08:53:03,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205284 states and 281931 transitions. [2024-11-17 08:53:06,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205284 to 195316. [2024-11-17 08:53:06,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195316 states, 195316 states have (on average 1.3775164349054865) internal successors, (269051), 195315 states have internal predecessors, (269051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195316 states to 195316 states and 269051 transitions. [2024-11-17 08:53:06,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195316 states and 269051 transitions. [2024-11-17 08:53:06,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:06,539 INFO L425 stractBuchiCegarLoop]: Abstraction has 195316 states and 269051 transitions. [2024-11-17 08:53:06,539 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:53:06,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195316 states and 269051 transitions. [2024-11-17 08:53:07,031 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 193968 [2024-11-17 08:53:07,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:07,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:07,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,032 INFO L745 eck$LassoCheckResult]: Stem: 1733226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1732525#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1732526#L1153 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1732587#L541-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1732999#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 1732818#L553 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1732819#L558 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1733071#L563 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1733415#L568 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1733471#L573 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1733506#L578 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1732647#L583 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1732648#L589 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1732505#L781-1 assume !(0 == ~M_E~0); 1732506#L786-1 assume !(0 == ~T1_E~0); 1732532#L791-1 assume !(0 == ~T2_E~0); 1732533#L796-1 assume !(0 == ~T3_E~0); 1733127#L801-1 assume !(0 == ~T4_E~0); 1733128#L806-1 assume !(0 == ~T5_E~0); 1733163#L811-1 assume !(0 == ~T6_E~0); 1732780#L816-1 assume !(0 == ~T7_E~0); 1732781#L821-1 assume !(0 == ~E_M~0); 1732567#L826-1 assume !(0 == ~E_1~0); 1732568#L831-1 assume !(0 == ~E_2~0); 1732916#L836-1 assume !(0 == ~E_3~0); 1732917#L841-1 assume !(0 == ~E_4~0); 1732729#L846-1 assume !(0 == ~E_5~0); 1732730#L851-1 assume !(0 == ~E_6~0); 1732751#L856-1 assume !(0 == ~E_7~0); 1732752#L862-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1732903#L388-10 assume !(1 == ~m_pc~0); 1732544#L398-10 is_master_triggered_~__retres1~0#1 := 0; 1732545#L391-10 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1733472#L400-10 assume true;activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1733209#L967-10 assume !(0 != activate_threads_~tmp~1#1); 1733210#L973-10 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1732738#L407-10 assume !(1 == ~t1_pc~0); 1732585#L417-10 is_transmit1_triggered_~__retres1~1#1 := 0; 1732586#L410-10 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1732575#L419-10 assume true;activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1732576#L975-10 assume !(0 != activate_threads_~tmp___0~0#1); 1732527#L981-10 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1732528#L426-10 assume !(1 == ~t2_pc~0); 1733022#L436-10 is_transmit2_triggered_~__retres1~2#1 := 0; 1733023#L429-10 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1733192#L438-10 assume true;activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1732519#L983-10 assume !(0 != activate_threads_~tmp___1~0#1); 1732520#L989-10 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1732873#L445-10 assume !(1 == ~t3_pc~0); 1733523#L455-10 is_transmit3_triggered_~__retres1~3#1 := 0; 1733052#L448-10 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1733053#L457-10 assume true;activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1733440#L991-10 assume !(0 != activate_threads_~tmp___2~0#1); 1733549#L997-10 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1733527#L464-10 assume !(1 == ~t4_pc~0); 1733382#L474-10 is_transmit4_triggered_~__retres1~4#1 := 0; 1733245#L467-10 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1733246#L476-10 assume true;activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1732944#L999-10 assume !(0 != activate_threads_~tmp___3~0#1); 1732945#L1005-10 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1733361#L483-10 assume !(1 == ~t5_pc~0); 1732789#L493-10 is_transmit5_triggered_~__retres1~5#1 := 0; 1732790#L486-10 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1732834#L495-10 assume true;activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1732835#L1007-10 assume !(0 != activate_threads_~tmp___4~0#1); 1733000#L1013-10 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1733001#L502-10 assume !(1 == ~t6_pc~0); 1732805#L512-10 is_transmit6_triggered_~__retres1~6#1 := 0; 1732489#L505-10 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1732490#L514-10 assume true;activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1733294#L1015-10 assume !(0 != activate_threads_~tmp___5~0#1); 1733295#L1021-10 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1733406#L521-10 assume !(1 == ~t7_pc~0); 1732558#L531-10 is_transmit7_triggered_~__retres1~7#1 := 0; 1732559#L524-10 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1733019#L533-10 assume true;activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1732692#L1023-10 assume !(0 != activate_threads_~tmp___6~0#1); 1732693#L1029-10 assume true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1732702#L869-1 assume !(1 == ~M_E~0); 1732703#L874-1 assume !(1 == ~T1_E~0); 1733520#L879-1 assume !(1 == ~T2_E~0); 1732995#L884-1 assume !(1 == ~T3_E~0); 1732500#L889-1 assume !(1 == ~T4_E~0); 1732501#L894-1 assume !(1 == ~T5_E~0); 1732788#L899-1 assume !(1 == ~T6_E~0); 1733230#L904-1 assume !(1 == ~T7_E~0); 1732948#L909-1 assume !(1 == ~E_M~0); 1732949#L914-1 assume !(1 == ~E_1~0); 1733141#L919-1 assume !(1 == ~E_2~0); 1732874#L924-1 assume !(1 == ~E_3~0); 1732681#L929-1 assume !(1 == ~E_4~0); 1732682#L934-1 assume !(1 == ~E_5~0); 1732929#L939-1 assume !(1 == ~E_6~0); 1732930#L944-1 assume !(1 == ~E_7~0); 1732596#L950-1 assume true;assume { :end_inline_reset_delta_events } true; 1732597#L1190 assume true; 1739833#L1190-1 assume !false; 1739649#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1739647#L648 [2024-11-17 08:53:07,033 INFO L747 eck$LassoCheckResult]: Loop: 1739647#L648 assume true; 1739645#L648-1 assume !false; 1739643#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1739640#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1739638#L626-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1739636#L639-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1739634#L653 assume 0 != eval_~tmp~0#1; 1739631#L658-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1739628#L661 assume !(0 != eval_~tmp_ndt_1~0#1); 1739626#L658 havoc eval_~tmp_ndt_1~0#1; 1739623#L672-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1738623#L675 assume !(0 != eval_~tmp_ndt_2~0#1); 1739622#L672 havoc eval_~tmp_ndt_2~0#1; 1741026#L686-1 assume !(0 == ~t2_st~0); 1741027#L700-1 assume !(0 == ~t3_st~0); 1741577#L714-1 assume !(0 == ~t4_st~0); 1743228#L728-1 assume !(0 == ~t5_st~0); 1739660#L742-1 assume !(0 == ~t6_st~0); 1739650#L756-1 assume !(0 == ~t7_st~0); 1739647#L648 [2024-11-17 08:53:07,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,033 INFO L85 PathProgramCache]: Analyzing trace with hash -1341979033, now seen corresponding path program 2 times [2024-11-17 08:53:07,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623919371] [2024-11-17 08:53:07,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:07,049 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:07,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:07,074 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:07,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,075 INFO L85 PathProgramCache]: Analyzing trace with hash 2051931667, now seen corresponding path program 1 times [2024-11-17 08:53:07,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928900368] [2024-11-17 08:53:07,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:07,080 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:07,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:07,083 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:07,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1659675117, now seen corresponding path program 1 times [2024-11-17 08:53:07,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586604663] [2024-11-17 08:53:07,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,126 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [586604663] [2024-11-17 08:53:07,126 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [586604663] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:07,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435202960] [2024-11-17 08:53:07,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:07,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:07,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:07,213 INFO L87 Difference]: Start difference. First operand 195316 states and 269051 transitions. cyclomatic complexity: 73759 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:08,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:08,687 INFO L93 Difference]: Finished difference Result 235332 states and 321515 transitions. [2024-11-17 08:53:08,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235332 states and 321515 transitions. [2024-11-17 08:53:09,576 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 233920 [2024-11-17 08:53:11,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235332 states to 235332 states and 321515 transitions. [2024-11-17 08:53:11,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 235332 [2024-11-17 08:53:11,152 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 235332 [2024-11-17 08:53:11,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 235332 states and 321515 transitions. [2024-11-17 08:53:11,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:11,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 235332 states and 321515 transitions. [2024-11-17 08:53:11,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235332 states and 321515 transitions.